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clk: renesas: Pass struct cpg_mssr_info to renesas_clk_endisable()

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CPG IP in some specific Renesas SoCs (i.e. new R8A779A0 V3U SoC)
requires a different setting procedure. Make struct cpg_mssr_info
accessible to handle the clock setting in that case.

Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
This commit is contained in:
Hai Pham
2020-05-22 10:39:04 +07:00
committed by Marek Vasut
parent e935409199
commit f7f8d47317
4 changed files with 8 additions and 6 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
drivers/clk/renesas/clk-rcar-gen2.c
View File

@@ -61,14 +61,14 @@ static int gen2_clk_enable(struct clk *clk)
{ {
struct gen2_clk_priv *priv = dev_get_priv(clk->dev); struct gen2_clk_priv *priv = dev_get_priv(clk->dev);
return renesas_clk_endisable(clk, priv->base, true); return renesas_clk_endisable(clk, priv->base, priv->info, true);
} }
static int gen2_clk_disable(struct clk *clk) static int gen2_clk_disable(struct clk *clk)
{ {
struct gen2_clk_priv *priv = dev_get_priv(clk->dev); struct gen2_clk_priv *priv = dev_get_priv(clk->dev);
return renesas_clk_endisable(clk, priv->base, false); return renesas_clk_endisable(clk, priv->base, priv->info, false);
} }
static ulong gen2_clk_get_rate(struct clk *clk) static ulong gen2_clk_get_rate(struct clk *clk)

4
drivers/clk/renesas/clk-rcar-gen3.c
View File

@@ -143,14 +143,14 @@ static int gen3_clk_enable(struct clk *clk)
{ {
struct gen3_clk_priv *priv = dev_get_priv(clk->dev); struct gen3_clk_priv *priv = dev_get_priv(clk->dev);
return renesas_clk_endisable(clk, priv->base, true); return renesas_clk_endisable(clk, priv->base, priv->info, true);
} }
static int gen3_clk_disable(struct clk *clk) static int gen3_clk_disable(struct clk *clk)
{ {
struct gen3_clk_priv *priv = dev_get_priv(clk->dev); struct gen3_clk_priv *priv = dev_get_priv(clk->dev);
return renesas_clk_endisable(clk, priv->base, false); return renesas_clk_endisable(clk, priv->base, priv->info, false);
} }
static u64 gen3_clk_get_rate64(struct clk *clk) static u64 gen3_clk_get_rate64(struct clk *clk)

3
drivers/clk/renesas/renesas-cpg-mssr.c
View File

@@ -132,7 +132,8 @@ int renesas_clk_get_parent(struct clk *clk, struct cpg_mssr_info *info,
return 0; return 0;
} }
int renesas_clk_endisable(struct clk *clk, void __iomem *base, bool enable) int renesas_clk_endisable(struct clk *clk, void __iomem *base,
struct cpg_mssr_info *info, bool enable)
{ {
const unsigned long clkid = clk->id & 0xffff; const unsigned long clkid = clk->id & 0xffff;
const unsigned int reg = clkid / 100; const unsigned int reg = clkid / 100;

3
drivers/clk/renesas/renesas-cpg-mssr.h
View File

@@ -115,7 +115,8 @@ int renesas_clk_get_core(struct clk *clk, struct cpg_mssr_info *info,
const struct cpg_core_clk **core); const struct cpg_core_clk **core);
int renesas_clk_get_parent(struct clk *clk, struct cpg_mssr_info *info, int renesas_clk_get_parent(struct clk *clk, struct cpg_mssr_info *info,
struct clk *parent); struct clk *parent);
int renesas_clk_endisable(struct clk *clk, void __iomem *base, bool enable); int renesas_clk_endisable(struct clk *clk, void __iomem *base,
struct cpg_mssr_info *info, bool enable);
int renesas_clk_remove(void __iomem *base, struct cpg_mssr_info *info); int renesas_clk_remove(void __iomem *base, struct cpg_mssr_info *info);
#endif /* __DRIVERS_CLK_RENESAS_CPG_MSSR__ */ #endif /* __DRIVERS_CLK_RENESAS_CPG_MSSR__ */