Add support for UC100 board
This commit is contained in:
wdenk
parent
8e6b47a89b
commit
f7d1572bf5
@ -2,6 +2,8 @@
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Changes since U-Boot 1.1.1:
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======================================================================
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* Add support for UC100 board
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* Patch by Stefan Roese, 16 Dez 2004:
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- ext2fs support added
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- Tundra universe support added
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2
MAKEALL
2
MAKEALL
@ -51,7 +51,7 @@ LIST_8xx=" \
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FPS850L LANTEC QS850 TQM850L \
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GEN860T lwmon QS860T TQM855L \
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GEN860T_SC MBX quantum TQM860L \
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v37 \
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UC100 v37 \
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"
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#########################################################################
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3
Makefile
3
Makefile
@ -667,6 +667,9 @@ TTTech_config: unconfig
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@echo "#define CONFIG_SHARP_LQ104V7DS01" >>include/config.h
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@./mkconfig -a TQM823L ppc mpc8xx tqm8xx
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UC100_config : unconfig
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@./mkconfig $(@:_config=) ppc mpc8xx uc100
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v37_config: unconfig
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@echo "#define CONFIG_LCD" >include/config.h
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@echo "#define CONFIG_SHARP_LQ084V1DG21" >>include/config.h
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41
board/uc100/Makefile
Normal file
41
board/uc100/Makefile
Normal file
@ -0,0 +1,41 @@
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#
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# (C) Copyright 2000-2003
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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include $(TOPDIR)/config.mk
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LIB = lib$(BOARD).a
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#OBJS = $(BOARD).o flash.o
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OBJS = $(BOARD).o
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$(LIB): .depend $(OBJS)
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$(AR) crv $@ $(OBJS)
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#########################################################################
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.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
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$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
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sinclude .depend
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#########################################################################
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29
board/uc100/config.mk
Normal file
29
board/uc100/config.mk
Normal file
@ -0,0 +1,29 @@
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#
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# (C) Copyright 2000
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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#
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# UC100 boards
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#
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#TEXT_BASE = 0x40000000
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TEXT_BASE = 0x40700000
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140
board/uc100/u-boot.lds
Normal file
140
board/uc100/u-boot.lds
Normal file
@ -0,0 +1,140 @@
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/*
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* (C) Copyright 2000
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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OUTPUT_ARCH(powerpc)
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SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
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/* Do we need any of these for elf?
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__DYNAMIC = 0; */
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SECTIONS
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{
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/* Read-only sections, merged into text segment: */
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. = + SIZEOF_HEADERS;
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.interp : { *(.interp) }
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.hash : { *(.hash) }
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.dynsym : { *(.dynsym) }
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.dynstr : { *(.dynstr) }
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.rel.text : { *(.rel.text) }
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.rela.text : { *(.rela.text) }
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.rel.data : { *(.rel.data) }
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.rela.data : { *(.rela.data) }
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.rel.rodata : { *(.rel.rodata) }
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.rela.rodata : { *(.rela.rodata) }
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.rel.got : { *(.rel.got) }
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.rela.got : { *(.rela.got) }
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.rel.ctors : { *(.rel.ctors) }
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.rela.ctors : { *(.rela.ctors) }
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.rel.dtors : { *(.rel.dtors) }
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.rela.dtors : { *(.rela.dtors) }
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.rel.bss : { *(.rel.bss) }
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.rela.bss : { *(.rela.bss) }
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.rel.plt : { *(.rel.plt) }
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.rela.plt : { *(.rela.plt) }
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.init : { *(.init) }
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.plt : { *(.plt) }
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.text :
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{
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/* WARNING - the following is hand-optimized to fit within */
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/* the sector layout of our flash chips! XXX FIXME XXX */
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cpu/mpc8xx/start.o (.text)
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cpu/mpc8xx/traps.o (.text)
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common/dlmalloc.o (.text)
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lib_ppc/ppcstring.o (.text)
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lib_generic/vsprintf.o (.text)
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lib_generic/crc32.o (.text)
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lib_generic/zlib.o (.text)
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lib_ppc/cache.o (.text)
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lib_ppc/time.o (.text)
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common/environment.o (.text)
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*(.text)
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*(.fixup)
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*(.got1)
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}
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_etext = .;
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PROVIDE (etext = .);
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.rodata :
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{
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*(.rodata)
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*(.rodata1)
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*(.rodata.str1.4)
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}
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.fini : { *(.fini) } =0
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.ctors : { *(.ctors) }
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.dtors : { *(.dtors) }
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/* Read-write section, merged into data segment: */
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. = (. + 0x00FF) & 0xFFFFFF00;
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_erotext = .;
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PROVIDE (erotext = .);
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.reloc :
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{
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*(.got)
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_GOT2_TABLE_ = .;
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*(.got2)
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_FIXUP_TABLE_ = .;
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*(.fixup)
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}
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__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
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__fixup_entries = (. - _FIXUP_TABLE_)>>2;
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.data :
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{
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*(.data)
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*(.data1)
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*(.sdata)
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*(.sdata2)
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*(.dynamic)
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CONSTRUCTORS
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}
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_edata = .;
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PROVIDE (edata = .);
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__u_boot_cmd_start = .;
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.u_boot_cmd : { *(.u_boot_cmd) }
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__u_boot_cmd_end = .;
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__start___ex_table = .;
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__ex_table : { *(__ex_table) }
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__stop___ex_table = .;
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. = ALIGN(256);
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__init_begin = .;
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.text.init : { *(.text.init) }
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.data.init : { *(.data.init) }
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. = ALIGN(256);
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__init_end = .;
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__bss_start = .;
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.bss :
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{
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*(.sbss) *(.scommon)
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*(.dynbss)
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*(.bss)
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*(COMMON)
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}
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_end = . ;
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PROVIDE (end = .);
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}
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134
board/uc100/u-boot.lds.debug
Normal file
134
board/uc100/u-boot.lds.debug
Normal file
@ -0,0 +1,134 @@
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/*
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* (C) Copyright 2000
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
|
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* modify it under the terms of the GNU General Public License as
|
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* published by the Free Software Foundation; either version 2 of
|
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
|
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
|
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*
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* You should have received a copy of the GNU General Public License
|
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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OUTPUT_ARCH(powerpc)
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SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
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/* Do we need any of these for elf?
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__DYNAMIC = 0; */
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SECTIONS
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{
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/* Read-only sections, merged into text segment: */
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. = + SIZEOF_HEADERS;
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||||
.interp : { *(.interp) }
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||||
.hash : { *(.hash) }
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||||
.dynsym : { *(.dynsym) }
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||||
.dynstr : { *(.dynstr) }
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||||
.rel.text : { *(.rel.text) }
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||||
.rela.text : { *(.rela.text) }
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||||
.rel.data : { *(.rel.data) }
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||||
.rela.data : { *(.rela.data) }
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||||
.rel.rodata : { *(.rel.rodata) }
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||||
.rela.rodata : { *(.rela.rodata) }
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||||
.rel.got : { *(.rel.got) }
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||||
.rela.got : { *(.rela.got) }
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||||
.rel.ctors : { *(.rel.ctors) }
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||||
.rela.ctors : { *(.rela.ctors) }
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||||
.rel.dtors : { *(.rel.dtors) }
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||||
.rela.dtors : { *(.rela.dtors) }
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||||
.rel.bss : { *(.rel.bss) }
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||||
.rela.bss : { *(.rela.bss) }
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||||
.rel.plt : { *(.rel.plt) }
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||||
.rela.plt : { *(.rela.plt) }
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||||
.init : { *(.init) }
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||||
.plt : { *(.plt) }
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||||
.text :
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{
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/* WARNING - the following is hand-optimized to fit within */
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/* the sector layout of our flash chips! XXX FIXME XXX */
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cpu/mpc8xx/start.o (.text)
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common/dlmalloc.o (.text)
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lib_generic/vsprintf.o (.text)
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lib_generic/crc32.o (.text)
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||||
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common/environment.o(.text)
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||||
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||||
*(.text)
|
||||
*(.fixup)
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||||
*(.got1)
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||||
}
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||||
_etext = .;
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||||
PROVIDE (etext = .);
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||||
.rodata :
|
||||
{
|
||||
*(.rodata)
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||||
*(.rodata1)
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||||
}
|
||||
.fini : { *(.fini) } =0
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||||
.ctors : { *(.ctors) }
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||||
.dtors : { *(.dtors) }
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||||
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||||
/* Read-write section, merged into data segment: */
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. = (. + 0x0FFF) & 0xFFFFF000;
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_erotext = .;
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||||
PROVIDE (erotext = .);
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||||
.reloc :
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||||
{
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||||
*(.got)
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_GOT2_TABLE_ = .;
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||||
*(.got2)
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||||
_FIXUP_TABLE_ = .;
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||||
*(.fixup)
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||||
}
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||||
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
|
||||
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
|
||||
|
||||
.data :
|
||||
{
|
||||
*(.data)
|
||||
*(.data1)
|
||||
*(.sdata)
|
||||
*(.sdata2)
|
||||
*(.dynamic)
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CONSTRUCTORS
|
||||
}
|
||||
_edata = .;
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||||
PROVIDE (edata = .);
|
||||
|
||||
__u_boot_cmd_start = .;
|
||||
.u_boot_cmd : { *(.u_boot_cmd) }
|
||||
__u_boot_cmd_end = .;
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||||
|
||||
|
||||
__start___ex_table = .;
|
||||
__ex_table : { *(__ex_table) }
|
||||
__stop___ex_table = .;
|
||||
|
||||
. = ALIGN(4096);
|
||||
__init_begin = .;
|
||||
.text.init : { *(.text.init) }
|
||||
.data.init : { *(.data.init) }
|
||||
. = ALIGN(4096);
|
||||
__init_end = .;
|
||||
|
||||
__bss_start = .;
|
||||
.bss :
|
||||
{
|
||||
*(.sbss) *(.scommon)
|
||||
*(.dynbss)
|
||||
*(.bss)
|
||||
*(COMMON)
|
||||
}
|
||||
_end = . ;
|
||||
PROVIDE (end = .);
|
||||
}
|
||||
268
board/uc100/uc100.c
Normal file
268
board/uc100/uc100.c
Normal file
@ -0,0 +1,268 @@
|
||||
/*
|
||||
* (C) Copyright 2000-2004
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#if 0
|
||||
#define DEBUG
|
||||
#endif
|
||||
|
||||
#include <common.h>
|
||||
#include <mpc8xx.h>
|
||||
#include <i2c.h>
|
||||
|
||||
|
||||
/*********************************************************************/
|
||||
/* UPMA Pre Initilization Table by WV (Miron MT48LC16M16A2-7E B) */
|
||||
/*********************************************************************/
|
||||
const uint sdram_init_upm_table[] = {
|
||||
/* SDRAM Initialisation Sequence (offset 0 in UPMA RAM) WV */
|
||||
/* NOP - Precharge - AutoRefr - NOP - NOP */
|
||||
/* NOP - AutoRefr - NOP */
|
||||
/* NOP - NOP - LoadModeR - NOP - Active */
|
||||
/* Position of Single Read */
|
||||
0x0ffffc04, 0x0ff77c04, 0x0ff5fc04, 0x0ffffc04, 0x0ffffc04,
|
||||
0x0ffffc04, 0x0ff5fc04, 0x0ffffc04,
|
||||
|
||||
/* Burst Read. (offset 8 in UPMA RAM) */
|
||||
/* Cycle lent for Initialisation WV */
|
||||
0x0ffffc04, 0x0ffffc34, 0x0f057c34, 0x0ffffc30, 0x1ff7fc05,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
|
||||
|
||||
/* Single Write. (offset 18 in UPMA RAM) */
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
|
||||
|
||||
/* Burst Write. (offset 20 in UPMA RAM) */
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
|
||||
|
||||
/* Refresh (offset 30 in UPMA RAM) */
|
||||
0x0FF77C04, 0x0FFFFC04, 0x0FF5FC84, 0x0FFFFC04, 0x0FFFFC04,
|
||||
0x0FFFFC84, 0x1FFFFC05, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
|
||||
0xFFFFFFFF, 0xFFFFFFFF,
|
||||
|
||||
/* Exception. (offset 3c in UPMA RAM) */
|
||||
0x7FFFFC05, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
|
||||
};
|
||||
|
||||
/*********************************************************************/
|
||||
/* UPMA initilization table. */
|
||||
/*********************************************************************/
|
||||
const uint sdram_upm_table[] = {
|
||||
/* single read. (offset 0 in UPMA RAM) */
|
||||
0x0F07FC04, 0x0FFFFC04, 0x00BDFC04, 0x0FF77C00, 0x1FFFFC05,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, /* 0x05-0x07 new WV */
|
||||
|
||||
/* Burst Read. (offset 8 in UPMA RAM) */
|
||||
0x0F07FC04, 0x0FFFFC04, 0x00BDFC04, 0x00FFFC00, 0x00FFFC00,
|
||||
0x00FFFC00, 0x0FF77C00, 0x1FFFFC05, 0xFFFFFFFF, 0xFFFFFFFF,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
|
||||
|
||||
/* Single Write. (offset 18 in UPMA RAM) */
|
||||
0x0F07FC04, 0x0FFFFC00, 0x00BD7C04, 0x0FFFFC04, 0x0FF77C04,
|
||||
0x1FFFFC05, 0xFFFFFFFF, 0xFFFFFFFF,
|
||||
|
||||
/* Burst Write. (offset 20 in UPMA RAM) */
|
||||
0x0F07FC04, 0x0FFFFC00, 0x00BD7C00, 0x00FFFC00, 0x00FFFC00,
|
||||
0x00FFFC04, 0x0FFFFC04, 0x0FF77C04, 0x1FFFFC05, 0xFFFFFFFF,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
|
||||
|
||||
/* Refresh (offset 30 in UPMA RAM) */
|
||||
0x0FF77C04, 0x0FFFFC04, 0x0FF5FC84, 0x0FFFFC04, 0x0FFFFC04,
|
||||
0x0FFFFC84, 0x1FFFFC05, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
|
||||
0xFFFFFFFF, 0xFFFFFFFF,
|
||||
|
||||
/* Exception. (offset 3c in UPMA RAM) */
|
||||
0x7FFFFC05, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, /* 0x3C new WV */
|
||||
};
|
||||
|
||||
/*********************************************************************/
|
||||
/* UPMB initilization table. */
|
||||
/*********************************************************************/
|
||||
const uint mpm_upm_table[] = {
|
||||
/* single read. (offset 0 in upm RAM) */
|
||||
0x8FF00004, 0x0FF00004, 0x0FF81004, 0x1FF00001,
|
||||
0x1FF00001, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
|
||||
|
||||
/* burst read. (Offset 8 in upm RAM) */
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
|
||||
|
||||
/* single write. (Offset 0x18 in upm RAM) */
|
||||
0x8FF00004, 0x0FF00004, 0x0FF81004, 0x0FF00004,
|
||||
0x0FF00004, 0x1FF00001, 0xFFFFFFFF, 0xFFFFFFFF,
|
||||
|
||||
/* burst write. (Offset 0x20 in upm RAM) */
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
|
||||
|
||||
/* Refresh cycle, offset 0x30 */
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
|
||||
|
||||
/* Exception, 0ffset 0x3C */
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
|
||||
};
|
||||
|
||||
|
||||
int board_switch(void)
|
||||
{
|
||||
volatile pcmconf8xx_t *pcmp;
|
||||
|
||||
pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia));
|
||||
|
||||
return ((pcmp->pcmc_pipr >> 24) & 0xf);
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* Check Board Identity:
|
||||
*/
|
||||
int checkboard (void)
|
||||
{
|
||||
unsigned char str[64];
|
||||
int i = getenv_r ("serial#", str, sizeof(str));
|
||||
|
||||
puts ("Board: ");
|
||||
|
||||
if (i == -1) {
|
||||
puts ("### No HW ID - assuming UC100");
|
||||
} else {
|
||||
puts(str);
|
||||
}
|
||||
|
||||
printf (" (SWITCH=%1X)\n", board_switch());
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* Initialize SDRAM
|
||||
*/
|
||||
long int initdram (int board_type)
|
||||
{
|
||||
volatile immap_t *immap = (immap_t *) CFG_IMMR;
|
||||
volatile memctl8xx_t *memctl = &immap->im_memctl;
|
||||
|
||||
/*---------------------------------------------------------------------*/
|
||||
/* Initialize the UPMA/UPMB registers with the appropriate table. */
|
||||
/*---------------------------------------------------------------------*/
|
||||
upmconfig (UPMA, (uint *) sdram_init_upm_table,
|
||||
sizeof (sdram_init_upm_table) / sizeof (uint));
|
||||
upmconfig (UPMB, (uint *) mpm_upm_table,
|
||||
sizeof (mpm_upm_table) / sizeof (uint));
|
||||
|
||||
/*---------------------------------------------------------------------*/
|
||||
/* Memory Periodic Timer Prescaler: divide by 16 */
|
||||
/*---------------------------------------------------------------------*/
|
||||
memctl->memc_mptpr = 0x0200; /* Divide by 32 WV */
|
||||
|
||||
memctl->memc_mamr = CFG_MAMR_VAL & 0xFF7FFFFF; /* Bit 8 := "0" Kein Refresh WV */
|
||||
memctl->memc_mbmr = CFG_MBMR_VAL;
|
||||
|
||||
/*---------------------------------------------------------------------*/
|
||||
/* Initialize the Memory Controller registers, MPTPR, Chip Select 1 */
|
||||
/* for SDRAM */
|
||||
/* */
|
||||
/* NOTE: The refresh rate in MAMR reg is set according to the lowest */
|
||||
/* clock rate (16.67MHz) to allow proper operation for all ADS */
|
||||
/* clock frequencies. */
|
||||
/*---------------------------------------------------------------------*/
|
||||
memctl->memc_or1 = CFG_OR1_PRELIM;
|
||||
memctl->memc_br1 = CFG_BR1_PRELIM;
|
||||
|
||||
/*-------------------------------------------------------------------*/
|
||||
/* Wait at least 200 usec for DRAM to stabilize, this magic number */
|
||||
/* obtained from the init code. */
|
||||
/*-------------------------------------------------------------------*/
|
||||
udelay(200);
|
||||
|
||||
memctl->memc_mamr = (memctl->memc_mamr | 0x04) & ~0x08;
|
||||
|
||||
memctl->memc_br1 = CFG_BR1_PRELIM;
|
||||
memctl->memc_or1 = CFG_OR1_PRELIM;
|
||||
|
||||
/*---------------------------------------------------------------------*/
|
||||
/* run MRS command in location 5-8 of UPMB. */
|
||||
/*---------------------------------------------------------------------*/
|
||||
memctl->memc_mar = 0x88;
|
||||
/* RUN UPMA on CS1 1-time from UPMA addr 0x05 */
|
||||
|
||||
memctl->memc_mcr = 0x80002100;
|
||||
/* RUN UPMA on CS1 1-time from UPMA addr 0x00 WV */
|
||||
|
||||
udelay(200);
|
||||
|
||||
/*---------------------------------------------------------------------*/
|
||||
/* Initialisation for normal access WV */
|
||||
/*---------------------------------------------------------------------*/
|
||||
|
||||
/*---------------------------------------------------------------------*/
|
||||
/* Initialize the UPMA register with the appropriate table. */
|
||||
/*---------------------------------------------------------------------*/
|
||||
upmconfig (UPMA, (uint *) sdram_upm_table,
|
||||
sizeof (sdram_upm_table) / sizeof (uint));
|
||||
|
||||
/*---------------------------------------------------------------------*/
|
||||
/* rerstore MBMR value (4-beat refresh burst.) */
|
||||
/*---------------------------------------------------------------------*/
|
||||
memctl->memc_mamr = CFG_MAMR_VAL | 0x00800000; /* Bit 8 := "1" Refresh Enable WV */
|
||||
|
||||
udelay(200);
|
||||
|
||||
return (64 * 1024 * 1024); /* fixed setup for 64MBytes! */
|
||||
}
|
||||
|
||||
|
||||
int misc_init_r (void)
|
||||
{
|
||||
uchar val;
|
||||
|
||||
/*
|
||||
* Make sure that RTC has clock output enabled (triggers watchdog!)
|
||||
*/
|
||||
val = i2c_reg_read (CFG_I2C_RTC_ADDR, 0x0D);
|
||||
val |= 0x80;
|
||||
i2c_reg_write (CFG_I2C_RTC_ADDR, 0x0D, val);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
#ifdef CONFIG_POST
|
||||
/*
|
||||
* Returns 1 if keys pressed to start the power-on long-running tests
|
||||
* Called from board_init_f().
|
||||
*/
|
||||
int post_hotkeys_pressed (void)
|
||||
{
|
||||
return 0; /* No hotkeys supported */
|
||||
}
|
||||
#endif
|
||||
@ -3090,6 +3090,199 @@ static void cfg_ports (void)
|
||||
#endif /* NETTA */
|
||||
|
||||
|
||||
/* -------------------------------------------------------------------- */
|
||||
/* UC100 Boards */
|
||||
/* -------------------------------------------------------------------- */
|
||||
|
||||
#if defined(CONFIG_UC100)
|
||||
|
||||
#define PCMCIA_BOARD_MSG "UC100"
|
||||
|
||||
/*
|
||||
* Remark: don't turn off OE "__MY_PCMCIA_GCRX_CXOE" on UC100 board.
|
||||
* This leads to board-hangup! (sr, 8 Dez. 2004)
|
||||
*/
|
||||
|
||||
static void cfg_ports (void);
|
||||
|
||||
static int hardware_enable(int slot)
|
||||
{
|
||||
volatile immap_t *immap;
|
||||
volatile cpm8xx_t *cp;
|
||||
volatile pcmconf8xx_t *pcmp;
|
||||
volatile sysconf8xx_t *sysp;
|
||||
uint reg, mask;
|
||||
|
||||
debug ("hardware_enable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot);
|
||||
|
||||
udelay(10000);
|
||||
|
||||
immap = (immap_t *)CFG_IMMR;
|
||||
sysp = (sysconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_siu_conf));
|
||||
pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia));
|
||||
cp = (cpm8xx_t *)(&(((immap_t *)CFG_IMMR)->im_cpm));
|
||||
|
||||
/* Configure Ports for TPS2211A PC-Card Power-Interface Switch */
|
||||
cfg_ports ();
|
||||
|
||||
/*
|
||||
* Configure SIUMCR to enable PCMCIA port B
|
||||
* (VFLS[0:1] are not used for debugging, we connect FRZ# instead)
|
||||
*/
|
||||
sysp->sc_siumcr &= ~SIUMCR_DBGC11; /* set DBGC to 00 */
|
||||
|
||||
/* clear interrupt state, and disable interrupts */
|
||||
pcmp->pcmc_pscr = PCMCIA_MASK(_slot_);
|
||||
pcmp->pcmc_per &= ~PCMCIA_MASK(_slot_);
|
||||
|
||||
/*
|
||||
* Disable interrupts, DMA, and PCMCIA buffers
|
||||
* (isolate the interface) and assert RESET signal
|
||||
*/
|
||||
debug ("Disable PCMCIA buffers and assert RESET\n");
|
||||
reg = 0;
|
||||
reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */
|
||||
PCMCIA_PGCRX(_slot_) = reg;
|
||||
udelay(500);
|
||||
|
||||
/*
|
||||
* Make sure there is a card in the slot, then configure the interface.
|
||||
*/
|
||||
udelay(10000);
|
||||
debug ("[%d] %s: PIPR(%p)=0x%x\n",
|
||||
__LINE__,__FUNCTION__,
|
||||
&(pcmp->pcmc_pipr),pcmp->pcmc_pipr);
|
||||
if (pcmp->pcmc_pipr & (0x18000000 >> (slot << 4))) {
|
||||
printf (" No Card found\n");
|
||||
return (1);
|
||||
}
|
||||
|
||||
/*
|
||||
* Power On.
|
||||
*/
|
||||
mask = PCMCIA_VS1(slot) | PCMCIA_VS2(slot);
|
||||
reg = pcmp->pcmc_pipr;
|
||||
debug ("PIPR: 0x%x ==> VS1=o%s, VS2=o%s\n",
|
||||
reg,
|
||||
(reg&PCMCIA_VS1(slot))?"n":"ff",
|
||||
(reg&PCMCIA_VS2(slot))?"n":"ff");
|
||||
if ((reg & mask) == mask) {
|
||||
puts (" 5.0V card found: ");
|
||||
} else {
|
||||
puts (" 3.3V card found: ");
|
||||
}
|
||||
|
||||
/* switch VCC on */
|
||||
immap->im_ioport.iop_padat |= 0x8000; /* power enable 3.3V */
|
||||
|
||||
udelay(10000);
|
||||
|
||||
debug ("Enable PCMCIA buffers and stop RESET\n");
|
||||
reg = PCMCIA_PGCRX(_slot_);
|
||||
reg &= ~__MY_PCMCIA_GCRX_CXRESET; /* active high */
|
||||
reg &= ~__MY_PCMCIA_GCRX_CXOE; /* active low */
|
||||
PCMCIA_PGCRX(_slot_) = reg;
|
||||
|
||||
udelay(250000); /* some cards need >150 ms to come up :-( */
|
||||
|
||||
debug ("# hardware_enable done\n");
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA)
|
||||
static int hardware_disable(int slot)
|
||||
{
|
||||
volatile immap_t *immap;
|
||||
volatile cpm8xx_t *cp;
|
||||
volatile pcmconf8xx_t *pcmp;
|
||||
u_long reg;
|
||||
|
||||
debug ("hardware_disable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot);
|
||||
|
||||
immap = (immap_t *)CFG_IMMR;
|
||||
pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia));
|
||||
|
||||
/* switch VCC off */
|
||||
immap->im_ioport.iop_padat &= ~0x8000; /* power disable 3.3V */
|
||||
|
||||
/* Configure PCMCIA General Control Register */
|
||||
debug ("Disable PCMCIA buffers and assert RESET\n");
|
||||
reg = 0;
|
||||
reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */
|
||||
PCMCIA_PGCRX(_slot_) = reg;
|
||||
|
||||
udelay(10000);
|
||||
|
||||
return (0);
|
||||
}
|
||||
#endif /* CFG_CMD_PCMCIA */
|
||||
|
||||
|
||||
static int voltage_set(int slot, int vcc, int vpp)
|
||||
{
|
||||
volatile immap_t *immap;
|
||||
volatile pcmconf8xx_t *pcmp;
|
||||
u_long reg;
|
||||
|
||||
debug ("voltage_set: "
|
||||
PCMCIA_BOARD_MSG
|
||||
" Slot %c, Vcc=%d.%d, Vpp=%d.%d\n",
|
||||
'A'+slot, vcc/10, vcc%10, vpp/10, vcc%10);
|
||||
|
||||
immap = (immap_t *)CFG_IMMR;
|
||||
pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia));
|
||||
/*
|
||||
* Disable PCMCIA buffers (isolate the interface)
|
||||
* and assert RESET signal
|
||||
*/
|
||||
debug ("Disable PCMCIA buffers and assert RESET\n");
|
||||
reg = PCMCIA_PGCRX(_slot_);
|
||||
reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */
|
||||
PCMCIA_PGCRX(_slot_) = reg;
|
||||
udelay(500);
|
||||
|
||||
/*
|
||||
* Configure Port C pins for
|
||||
* 5 Volts Enable and 3 Volts enable,
|
||||
* Turn all power pins to Hi-Z
|
||||
*/
|
||||
debug ("PCMCIA power OFF\n");
|
||||
cfg_ports (); /* Enables switch, but all in Hi-Z */
|
||||
|
||||
debug ("Enable PCMCIA buffers and stop RESET\n");
|
||||
reg = PCMCIA_PGCRX(_slot_);
|
||||
reg &= ~__MY_PCMCIA_GCRX_CXRESET; /* active high */
|
||||
reg &= ~__MY_PCMCIA_GCRX_CXOE; /* active low */
|
||||
PCMCIA_PGCRX(_slot_) = reg;
|
||||
udelay(500);
|
||||
|
||||
debug ("voltage_set: " PCMCIA_BOARD_MSG " Slot %c, DONE\n",
|
||||
slot+'A');
|
||||
return (0);
|
||||
}
|
||||
|
||||
static void cfg_ports (void)
|
||||
{
|
||||
volatile immap_t *immap;
|
||||
|
||||
immap = (immap_t *)CFG_IMMR;
|
||||
|
||||
/*
|
||||
* Configure Port A for MAX1602 PC-Card Power-Interface Switch
|
||||
*/
|
||||
immap->im_ioport.iop_padat &= ~0x8000; /* set port x output to low */
|
||||
immap->im_ioport.iop_padir |= 0x8000; /* enable port x as output */
|
||||
|
||||
debug ("Set Port A: PAR: %08x DIR: %08x DAT: %08x\n",
|
||||
immap->im_ioport.iop_papar, immap->im_ioport.iop_padir,
|
||||
immap->im_ioport.iop_padat);
|
||||
}
|
||||
|
||||
#endif /* UC100 */
|
||||
|
||||
|
||||
/* -------------------------------------------------------------------- */
|
||||
|
||||
#endif /* CFG_CMD_PCMCIA || (CFG_CMD_IDE && CONFIG_IDE_8xx_PCCARD) */
|
||||
|
||||
@ -190,10 +190,17 @@ static int check_CPU (long clock, uint pvr, uint immr)
|
||||
default: suf = NULL; break;
|
||||
}
|
||||
|
||||
#ifndef CONFIG_MPC857
|
||||
if (suf)
|
||||
printf ("%cPC862%sZPnn%s", pre, mid, suf);
|
||||
else
|
||||
printf ("unknown MPC862 (0x%08x)", k);
|
||||
#else
|
||||
if (suf)
|
||||
printf ("%cPC857TZPnn%s", pre, suf); /* only 857T tested right now! */
|
||||
else
|
||||
printf ("unknown MPC857 (0x%08x)", k);
|
||||
#endif
|
||||
|
||||
printf (" at %s MHz:", strmhz (buf, clock));
|
||||
|
||||
|
||||
@ -144,6 +144,12 @@
|
||||
#define CFI_CMDSET_SST 258
|
||||
|
||||
|
||||
#ifdef CFG_FLASH_CFI_AMD_RESET /* needed for STM_ID_29W320DB on UC100 */
|
||||
# undef FLASH_CMD_RESET
|
||||
# define FLASH_CMD_RESET AMD_CMD_RESET /* use AMD-Reset instead */
|
||||
#endif
|
||||
|
||||
|
||||
typedef union {
|
||||
unsigned char c;
|
||||
unsigned short w;
|
||||
|
||||
505
include/configs/UC100.h
Normal file
505
include/configs/UC100.h
Normal file
@ -0,0 +1,505 @@
|
||||
/*
|
||||
* (C) Copyright 2000-2004
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
/*
|
||||
* board/config.h - configuration options, board specific
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
/*
|
||||
* High Level Configuration Options
|
||||
* (easy to change)
|
||||
*/
|
||||
|
||||
#define CONFIG_MPC860 1
|
||||
#define CONFIG_MPC860T 1
|
||||
#define CONFIG_MPC862 1 /* enable 862 since the */
|
||||
#define CONFIG_MPC857 1 /* 857 is a variant of the 862 */
|
||||
|
||||
#define CONFIG_UC100 1 /* ...on a UC100 module */
|
||||
|
||||
#define MPC8XX_FACT 4 /* Multiply by 4 */
|
||||
#define MPC8XX_XIN 25000000 /* 25.0 MHz in */
|
||||
#define CONFIG_8xx_GCLK_FREQ (MPC8XX_FACT * MPC8XX_XIN)
|
||||
/* define if cant' use get_gclk_freq */
|
||||
|
||||
#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
|
||||
#undef CONFIG_8xx_CONS_SMC2
|
||||
#undef CONFIG_8xx_CONS_NONE
|
||||
|
||||
#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
|
||||
|
||||
#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
|
||||
|
||||
#define CONFIG_BOOTCOUNT_LIMIT
|
||||
|
||||
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
|
||||
|
||||
#define CONFIG_BOARD_TYPES 1 /* support board types */
|
||||
|
||||
#define CONFIG_PREBOOT "echo;" \
|
||||
"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
|
||||
"echo"
|
||||
|
||||
#undef CONFIG_BOOTARGS
|
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
"netdev=eth0\0" \
|
||||
"nfsargs=setenv bootargs root=/dev/nfs rw " \
|
||||
"nfsroot=$(serverip):$(rootpath)\0" \
|
||||
"ramargs=setenv bootargs root=/dev/ram rw\0" \
|
||||
"addip=setenv bootargs $(bootargs) " \
|
||||
"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
|
||||
":$(hostname):$(netdev):off panic=1\0" \
|
||||
"addtty=setenv bootargs $(bootargs) console=ttyS0,$(baudrate)\0"\
|
||||
"flash_nfs=run nfsargs addip addtty;" \
|
||||
"bootm $(kernel_addr)\0" \
|
||||
"flash_self=run ramargs addip addtty;" \
|
||||
"bootm $(kernel_addr) $(ramdisk_addr)\0" \
|
||||
"net_nfs=tftp 200000 $(bootfile);run nfsargs addip addtty;" \
|
||||
"bootm\0" \
|
||||
"rootpath=/opt/eldk/ppc_8xx\0" \
|
||||
"bootfile=/tftpboot/uc100/uImage\0" \
|
||||
"kernel_addr=40000000\0" \
|
||||
"ramdisk_addr=40100000\0" \
|
||||
"load=tftp 100000 /tftpboot/uc100/u-boot.bin\0" \
|
||||
"update=protect off 40700000 4073ffff;era 40700000 4073ffff;" \
|
||||
"cp.b 100000 40700000 $(filesize);" \
|
||||
"setenv filesize;saveenv\0" \
|
||||
""
|
||||
#define CONFIG_BOOTCOMMAND "run flash_self"
|
||||
|
||||
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
|
||||
#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
|
||||
|
||||
#undef CONFIG_WATCHDOG /* watchdog disabled */
|
||||
|
||||
#undef CONFIG_STATUS_LED /* no status-led */
|
||||
|
||||
#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
|
||||
|
||||
#define CONFIG_MAC_PARTITION
|
||||
#define CONFIG_DOS_PARTITION
|
||||
|
||||
#undef CONFIG_RTC_MPC8xx
|
||||
#define CFG_I2C_RTC_ADDR 0x51 /* PCF8563 RTC */
|
||||
#define CONFIG_RTC_PCF8563 /* use Philips PCF8563 RTC */
|
||||
|
||||
/*
|
||||
* Power On Self Test support
|
||||
*/
|
||||
#define CONFIG_POST ( CFG_POST_CACHE | \
|
||||
CFG_POST_MEMORY | \
|
||||
CFG_POST_CPU | \
|
||||
CFG_POST_UART | \
|
||||
CFG_POST_SPR )
|
||||
#undef CONFIG_POST
|
||||
|
||||
#ifdef CONFIG_POST
|
||||
#define CFG_CMD_POST_DIAG CFG_CMD_DIAG
|
||||
#else
|
||||
#define CFG_CMD_POST_DIAG 0
|
||||
#endif
|
||||
|
||||
#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
|
||||
CFG_CMD_ASKENV | \
|
||||
CFG_CMD_DHCP | \
|
||||
CFG_CMD_ELF | \
|
||||
CFG_CMD_IDE | \
|
||||
CFG_CMD_FAT | \
|
||||
CFG_CMD_MII | \
|
||||
CFG_CMD_PING | \
|
||||
CFG_CMD_I2C | \
|
||||
CFG_CMD_EEPROM | \
|
||||
CFG_CMD_DATE | \
|
||||
CFG_CMD_POST_DIAG )
|
||||
|
||||
#define CONFIG_NETCONSOLE
|
||||
|
||||
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
|
||||
#include <cmd_confdefs.h>
|
||||
|
||||
/*
|
||||
* Miscellaneous configurable options
|
||||
*/
|
||||
#define CFG_LONGHELP /* undef to save memory */
|
||||
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
|
||||
|
||||
#if 0
|
||||
#define CFG_HUSH_PARSER 1 /* use "hush" command parser */
|
||||
#endif
|
||||
#ifdef CFG_HUSH_PARSER
|
||||
#define CFG_PROMPT_HUSH_PS2 "> "
|
||||
#endif
|
||||
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
|
||||
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
|
||||
#else
|
||||
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
|
||||
#endif
|
||||
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
|
||||
#define CFG_MAXARGS 16 /* max number of command args */
|
||||
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
|
||||
|
||||
#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
|
||||
#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
|
||||
|
||||
#define CFG_LOAD_ADDR 0x100000 /* default load address */
|
||||
|
||||
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
|
||||
|
||||
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
|
||||
|
||||
#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */
|
||||
|
||||
/*
|
||||
* Low Level Configuration Settings
|
||||
* (address mappings, register initial values, etc.)
|
||||
* You should know what you are doing if you make changes here.
|
||||
*/
|
||||
/*-----------------------------------------------------------------------
|
||||
* Internal Memory Mapped Register
|
||||
*/
|
||||
#define CFG_IMMR 0xF0000000
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Definitions for initial stack pointer and data area (in DPRAM)
|
||||
*/
|
||||
#define CFG_INIT_RAM_ADDR CFG_IMMR
|
||||
#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
|
||||
#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
|
||||
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
|
||||
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Start addresses for the final memory configuration
|
||||
* (Set up by the startup code)
|
||||
* Please note that CFG_SDRAM_BASE _must_ start at 0
|
||||
*/
|
||||
#define CFG_SDRAM_BASE 0x00000000
|
||||
#define CFG_FLASH_BASE 0x40000000
|
||||
#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
|
||||
#define CFG_MONITOR_BASE (CFG_FLASH_BASE+0x00700000) /* resetvec fff00100*/
|
||||
#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Address accessed to reset the board - must not be mapped/assigned
|
||||
*/
|
||||
#define CFG_RESET_ADDRESS 0x90000000
|
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data
|
||||
* have to be in the first 8 MB of memory, since this is
|
||||
* the maximum mapped by the Linux kernel during initialization.
|
||||
*/
|
||||
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* FLASH organization
|
||||
*/
|
||||
#define CFG_FLASH_CFI /* The flash is CFI compatible */
|
||||
#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */
|
||||
#define CFG_FLASH_CFI_AMD_RESET 1 /* AMD RESET for STM 29W320DB! */
|
||||
|
||||
#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
|
||||
#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
|
||||
|
||||
#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
|
||||
#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
|
||||
|
||||
#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
|
||||
|
||||
#define CFG_ENV_IS_IN_FLASH 1
|
||||
#define CFG_ENV_ADDR (CFG_MONITOR_BASE+CFG_MONITOR_LEN)
|
||||
#define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
|
||||
#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
|
||||
|
||||
/* Address and size of Redundant Environment Sector */
|
||||
#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR+CFG_ENV_SECT_SIZE)
|
||||
#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Cache Configuration
|
||||
*/
|
||||
#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
|
||||
#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
|
||||
#endif
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SYPCR - System Protection Control 11-9
|
||||
* SYPCR can only be written once after reset!
|
||||
*-----------------------------------------------------------------------
|
||||
* Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
|
||||
*/
|
||||
#if defined(CONFIG_WATCHDOG)
|
||||
#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
|
||||
SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
|
||||
#else
|
||||
#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
|
||||
#endif
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SIUMCR - SIU Module Configuration 11-6
|
||||
*-----------------------------------------------------------------------
|
||||
* PCMCIA config., multi-function pin tri-state
|
||||
*/
|
||||
#define CFG_SIUMCR (SIUMCR_FRC | SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* TBSCR - Time Base Status and Control 11-26
|
||||
*-----------------------------------------------------------------------
|
||||
* Clear Reference Interrupt Status, Timebase freezing enabled
|
||||
*/
|
||||
#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* RTCSC - Real-Time Clock Status and Control Register 11-27
|
||||
*-----------------------------------------------------------------------
|
||||
*/
|
||||
#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PISCR - Periodic Interrupt Status and Control 11-31
|
||||
*-----------------------------------------------------------------------
|
||||
* Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
|
||||
*/
|
||||
#define CFG_PISCR (PISCR_PS | PISCR_PITF)
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
|
||||
*-----------------------------------------------------------------------
|
||||
* Reset PLL lock status sticky bit, timer expired status bit and timer
|
||||
* interrupt status bit
|
||||
*/
|
||||
#define CFG_PLPRCR (((MPC8XX_FACT-1) << PLPRCR_MF_SHIFT) | \
|
||||
PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SCCR - System Clock and reset Control Register 15-27
|
||||
*-----------------------------------------------------------------------
|
||||
* Set clock output, timebase and RTC source and divider,
|
||||
* power management and some other internal clocks
|
||||
*/
|
||||
#define SCCR_MASK 0x00000000
|
||||
#define CFG_SCCR (SCCR_EBDF11)
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PCMCIA stuff
|
||||
*-----------------------------------------------------------------------
|
||||
*
|
||||
*/
|
||||
#define CFG_PCMCIA_MEM_ADDR (0xE0000000)
|
||||
#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 )
|
||||
#define CFG_PCMCIA_DMA_ADDR (0xE4000000)
|
||||
#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 )
|
||||
#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000)
|
||||
#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 )
|
||||
#define CFG_PCMCIA_IO_ADDR (0xEC000000)
|
||||
#define CFG_PCMCIA_IO_SIZE ( 64 << 20 )
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
|
||||
*-----------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
|
||||
|
||||
#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
|
||||
#undef CONFIG_IDE_LED /* LED for ide not supported */
|
||||
#undef CONFIG_IDE_RESET /* reset for ide not supported */
|
||||
|
||||
#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
|
||||
#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
|
||||
|
||||
#define CFG_ATA_IDE0_OFFSET 0x0000
|
||||
|
||||
#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR
|
||||
|
||||
/* Offset for data I/O */
|
||||
#define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320)
|
||||
|
||||
/* Offset for normal register accesses */
|
||||
#define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320)
|
||||
|
||||
/* Offset for alternate registers */
|
||||
#define CFG_ATA_ALT_OFFSET 0x0100
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*
|
||||
*-----------------------------------------------------------------------
|
||||
*
|
||||
*/
|
||||
#define CFG_DER 0
|
||||
|
||||
/*
|
||||
* Init Memory Controller:
|
||||
*
|
||||
* BR0/1 and OR0/1 (FLASH)
|
||||
*/
|
||||
|
||||
#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
|
||||
#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */
|
||||
|
||||
/* used to re-map FLASH both when starting from SRAM or FLASH:
|
||||
* restrict access enough to keep SRAM working (if any)
|
||||
* but not too much to meddle with FLASH accesses
|
||||
*/
|
||||
#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */
|
||||
#define CFG_PRELIM_OR_AM 0xFF800000 /* OR addr mask */
|
||||
|
||||
/*
|
||||
* FLASH timing:
|
||||
*/
|
||||
#define CFG_OR_TIMING_FLASH (0x00000d24)
|
||||
|
||||
#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH)
|
||||
#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
|
||||
#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
|
||||
|
||||
#define CFG_BR1_PRELIM 0x00000081 /* Chip select for SDRAM (32 Bit, UPMA) */
|
||||
#define CFG_OR1_PRELIM 0xfc000a00
|
||||
#define CFG_BR2_PRELIM 0x80000001 /* Chip select for SRAM (32 Bit, GPCM) */
|
||||
#define CFG_OR2_PRELIM 0xfff00d24
|
||||
#define CFG_BR3_PRELIM 0x80600401 /* Chip select for Display (8 Bit, GPCM) */
|
||||
#define CFG_OR3_PRELIM 0xffff8f44
|
||||
#define CFG_BR4_PRELIM 0xc05108c1 /* Chip select for Interbus MPM (16 Bit, UPMB) */
|
||||
#define CFG_OR4_PRELIM 0xffff0300
|
||||
#define CFG_BR5_PRELIM 0xc0500401 /* Chip select for Interbus Status (8 Bit, GPCM) */
|
||||
#define CFG_OR5_PRELIM 0xffff8db0
|
||||
|
||||
/*
|
||||
* Memory Periodic Timer Prescaler
|
||||
*
|
||||
* The Divider for PTA (refresh timer) configuration is based on an
|
||||
* example SDRAM configuration (64 MBit, one bank). The adjustment to
|
||||
* the number of chip selects (NCS) and the actually needed refresh
|
||||
* rate is done by setting MPTPR.
|
||||
*
|
||||
* PTA is calculated from
|
||||
* PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
|
||||
*
|
||||
* gclk CPU clock (not bus clock!)
|
||||
* Trefresh Refresh cycle * 4 (four word bursts used)
|
||||
*
|
||||
* 4096 Rows from SDRAM example configuration
|
||||
* 1000 factor s -> ms
|
||||
* 32 PTP (pre-divider from MPTPR) from SDRAM example configuration
|
||||
* 4 Number of refresh cycles per period
|
||||
* 64 Refresh cycle in ms per number of rows
|
||||
* --------------------------------------------
|
||||
* Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
|
||||
*
|
||||
* 50 MHz => 50.000.000 / Divider = 98
|
||||
* 66 Mhz => 66.000.000 / Divider = 129
|
||||
* 80 Mhz => 80.000.000 / Divider = 156
|
||||
* 100 Mhz => 100.000.000 / Divider = 195
|
||||
*/
|
||||
|
||||
#define CFG_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64))
|
||||
#define CFG_MAMR_PTA 98
|
||||
|
||||
/*
|
||||
* For 16 MBit, refresh rates could be 31.3 us
|
||||
* (= 64 ms / 2K = 125 / quad bursts).
|
||||
* For a simpler initialization, 15.6 us is used instead.
|
||||
*
|
||||
* #define CFG_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks
|
||||
* #define CFG_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank
|
||||
*/
|
||||
#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
|
||||
#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
|
||||
|
||||
/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
|
||||
#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
|
||||
#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
|
||||
|
||||
/*
|
||||
* MAMR settings for SDRAM
|
||||
*/
|
||||
|
||||
/* 8 column SDRAM */
|
||||
#define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
|
||||
MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
|
||||
MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
|
||||
/* 9 column SDRAM */
|
||||
#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
|
||||
MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
|
||||
MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
|
||||
|
||||
#define CFG_MAMR_VAL 0x30904114 /* for SDRAM */
|
||||
#define CFG_MBMR_VAL 0xff001111 /* for Interbus-MPM */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* I2C stuff
|
||||
*/
|
||||
|
||||
/* enable I2C and select the hardware/software driver */
|
||||
#undef CONFIG_HARD_I2C /* I2C with hardware support */
|
||||
#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
|
||||
|
||||
#define CFG_I2C_SPEED 93000 /* 93 kHz is supposed to work */
|
||||
#define CFG_I2C_SLAVE 0xFE
|
||||
|
||||
#ifdef CONFIG_SOFT_I2C
|
||||
/*
|
||||
* Software (bit-bang) I2C driver configuration
|
||||
*/
|
||||
#define PB_SCL 0x00000020 /* PB 26 */
|
||||
#define PB_SDA 0x00000010 /* PB 27 */
|
||||
|
||||
#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL)
|
||||
#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA)
|
||||
#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA)
|
||||
#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
|
||||
#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \
|
||||
else immr->im_cpm.cp_pbdat &= ~PB_SDA
|
||||
#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \
|
||||
else immr->im_cpm.cp_pbdat &= ~PB_SCL
|
||||
#define I2C_DELAY udelay(2) /* 1/4 I2C clock duration */
|
||||
#endif /* CONFIG_SOFT_I2C */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* I2C EEPROM (24C164)
|
||||
*/
|
||||
#define CFG_I2C_EEPROM_ADDR 0x58 /* EEPROM AT24C164 */
|
||||
#define CFG_I2C_EEPROM_ADDR_LEN 1
|
||||
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* takes up to 10 msec */
|
||||
#define CFG_EEPROM_PAGE_WRITE_BITS 4
|
||||
|
||||
/*
|
||||
* Internal Definitions
|
||||
*
|
||||
* Boot Flags
|
||||
*/
|
||||
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
|
||||
#define BOOTFLAG_WARM 0x02 /* Software reboot */
|
||||
|
||||
#define CONFIG_FEC_ENET 1 /* use FEC ethernet */
|
||||
#define FEC_ENET
|
||||
#define CONFIG_MII
|
||||
#define CFG_DISCOVER_PHY 1
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
@ -66,6 +66,8 @@
|
||||
# define CONFIG_PCMCIA_SLOT_A
|
||||
#elif defined(CONFIG_NETTA)
|
||||
# define CONFIG_PCMCIA_SLOT_A
|
||||
#elif defined(CONFIG_UC100) /* The UC100 use SLOT_B */
|
||||
# define CONFIG_PCMCIA_SLOT_B
|
||||
#else
|
||||
# error "PCMCIA Slot not configured"
|
||||
#endif
|
||||
|
||||
Loading…
Reference in New Issue
Block a user