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powerpc/mpc85xx: change RCW MEM_PLL_PLAT for Chassis generation 2

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Chassis generation 2 has different mask and shift. Use macro instead of
magic numbers.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
This commit is contained in:
York Sun 2012-10-08 07:44:09 +00:00 committed by Andy Fleming
parent 6d2b9da19c
commit f77329cfcf
2 changed files with 10 additions and 1 deletions
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4
arch/powerpc/cpu/mpc85xx/speed.c
View File

@ -85,7 +85,9 @@ void get_sys_info (sys_info_t * sysInfo)
sysInfo->freqDDRBus = sysclk;
sysInfo->freqSystemBus *= (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
mem_pll_rat = (in_be32(&gur->rcwsr[0]) >> 17) & 0x1f;
mem_pll_rat = (in_be32(&gur->rcwsr[0]) >>
FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT)
& FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK;
if (mem_pll_rat > 2)
sysInfo->freqDDRBus *= mem_pll_rat;
else

7
arch/powerpc/include/asm/immap_85xx.h
View File

@ -1757,6 +1757,13 @@ typedef struct ccsr_gur {
u32 brrl; /* Boot release */
u8 res17[24];
u32 rcwsr[16]; /* Reset control word status */
#ifndef CONFIG_SYS_FSL_QORIQ_CHASSIS2
#define FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT 17
#define FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK 0x1f
#else
#define FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT 16
#define FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK 0x3f
#endif
#define FSL_CORENET_RCWSR4_SRDS_PRTCL 0xfc000000
#define FSL_CORENET_RCWSR5_DDR_SYNC 0x00000080
#define FSL_CORENET_RCWSR5_DDR_SYNC_SHIFT 7