MX31: add support for setting pin pads
The patch adds a utility function and defines to set the pad as it is done in linux. Signed-off-by: Stefano Babic <sbabic@denx.de>
This commit is contained in:
Stefano Babic
parent
b9eb3fdf2f
commit
f76888c294
@ -23,6 +23,7 @@
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#include <common.h>
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#include <asm/arch/mx31-regs.h>
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#include <asm/io.h>
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static u32 mx31_decode_pll(u32 reg, u32 infreq)
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{
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@ -90,6 +91,22 @@ void mx31_gpio_mux(unsigned long mode)
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__REG(reg) = tmp;
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}
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void mx31_set_pad(enum iomux_pins pin, u32 config)
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{
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u32 field, l;
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void *reg;
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pin &= IOMUX_PADNUM_MASK;
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reg = (IOMUXC_BASE + 0x154) + (pin + 2) / 3 * 4;
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field = (pin + 2) % 3;
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l = __raw_readl(reg);
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l &= ~(0x1ff << (field * 10));
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l |= config << (field * 10);
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__raw_writel(l, reg);
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}
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#if defined(CONFIG_DISPLAY_CPUINFO)
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int print_cpuinfo (void)
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{
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@ -64,6 +64,370 @@ struct gpio_regs {
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u32 gpio_psr;
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};
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#define IOMUX_PADNUM_MASK 0x1ff
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#define IOMUX_PIN(gpionum, padnum) ((padnum) & IOMUX_PADNUM_MASK)
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/*
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* various IOMUX pad functions
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*/
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enum iomux_pad_config {
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PAD_CTL_NOLOOPBACK = 0x0 << 9,
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PAD_CTL_LOOPBACK = 0x1 << 9,
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PAD_CTL_PKE_NONE = 0x0 << 8,
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PAD_CTL_PKE_ENABLE = 0x1 << 8,
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PAD_CTL_PUE_KEEPER = 0x0 << 7,
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PAD_CTL_PUE_PUD = 0x1 << 7,
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PAD_CTL_100K_PD = 0x0 << 5,
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PAD_CTL_100K_PU = 0x1 << 5,
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PAD_CTL_47K_PU = 0x2 << 5,
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PAD_CTL_22K_PU = 0x3 << 5,
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PAD_CTL_HYS_CMOS = 0x0 << 4,
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PAD_CTL_HYS_SCHMITZ = 0x1 << 4,
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PAD_CTL_ODE_CMOS = 0x0 << 3,
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PAD_CTL_ODE_OpenDrain = 0x1 << 3,
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PAD_CTL_DRV_NORMAL = 0x0 << 1,
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PAD_CTL_DRV_HIGH = 0x1 << 1,
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PAD_CTL_DRV_MAX = 0x2 << 1,
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PAD_CTL_SRE_SLOW = 0x0 << 0,
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PAD_CTL_SRE_FAST = 0x1 << 0
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};
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/*
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* This enumeration is constructed based on the Section
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* "sw_pad_ctl & sw_mux_ctl details" of the MX31 IC Spec. Each enumerated
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* value is constructed based on the rules described above.
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*/
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enum iomux_pins {
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MX31_PIN_TTM_PAD = IOMUX_PIN(0xff, 0),
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MX31_PIN_CSPI3_SPI_RDY = IOMUX_PIN(0xff, 1),
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MX31_PIN_CSPI3_SCLK = IOMUX_PIN(0xff, 2),
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MX31_PIN_CSPI3_MISO = IOMUX_PIN(0xff, 3),
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MX31_PIN_CSPI3_MOSI = IOMUX_PIN(0xff, 4),
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MX31_PIN_CLKSS = IOMUX_PIN(0xff, 5),
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MX31_PIN_CE_CONTROL = IOMUX_PIN(0xff, 6),
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MX31_PIN_ATA_RESET_B = IOMUX_PIN(95, 7),
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MX31_PIN_ATA_DMACK = IOMUX_PIN(94, 8),
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MX31_PIN_ATA_DIOW = IOMUX_PIN(93, 9),
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MX31_PIN_ATA_DIOR = IOMUX_PIN(92, 10),
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MX31_PIN_ATA_CS1 = IOMUX_PIN(91, 11),
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MX31_PIN_ATA_CS0 = IOMUX_PIN(90, 12),
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MX31_PIN_SD1_DATA3 = IOMUX_PIN(63, 13),
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MX31_PIN_SD1_DATA2 = IOMUX_PIN(62, 14),
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MX31_PIN_SD1_DATA1 = IOMUX_PIN(61, 15),
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MX31_PIN_SD1_DATA0 = IOMUX_PIN(60, 16),
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MX31_PIN_SD1_CLK = IOMUX_PIN(59, 17),
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MX31_PIN_SD1_CMD = IOMUX_PIN(58, 18),
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MX31_PIN_D3_SPL = IOMUX_PIN(0xff, 19),
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MX31_PIN_D3_CLS = IOMUX_PIN(0xff, 20),
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MX31_PIN_D3_REV = IOMUX_PIN(0xff, 21),
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MX31_PIN_CONTRAST = IOMUX_PIN(0xff, 22),
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MX31_PIN_VSYNC3 = IOMUX_PIN(0xff, 23),
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MX31_PIN_READ = IOMUX_PIN(0xff, 24),
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MX31_PIN_WRITE = IOMUX_PIN(0xff, 25),
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MX31_PIN_PAR_RS = IOMUX_PIN(0xff, 26),
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MX31_PIN_SER_RS = IOMUX_PIN(89, 27),
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MX31_PIN_LCS1 = IOMUX_PIN(88, 28),
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MX31_PIN_LCS0 = IOMUX_PIN(87, 29),
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MX31_PIN_SD_D_CLK = IOMUX_PIN(86, 30),
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MX31_PIN_SD_D_IO = IOMUX_PIN(85, 31),
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MX31_PIN_SD_D_I = IOMUX_PIN(84, 32),
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MX31_PIN_DRDY0 = IOMUX_PIN(0xff, 33),
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MX31_PIN_FPSHIFT = IOMUX_PIN(0xff, 34),
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MX31_PIN_HSYNC = IOMUX_PIN(0xff, 35),
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MX31_PIN_VSYNC0 = IOMUX_PIN(0xff, 36),
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MX31_PIN_LD17 = IOMUX_PIN(0xff, 37),
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MX31_PIN_LD16 = IOMUX_PIN(0xff, 38),
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MX31_PIN_LD15 = IOMUX_PIN(0xff, 39),
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MX31_PIN_LD14 = IOMUX_PIN(0xff, 40),
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MX31_PIN_LD13 = IOMUX_PIN(0xff, 41),
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MX31_PIN_LD12 = IOMUX_PIN(0xff, 42),
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MX31_PIN_LD11 = IOMUX_PIN(0xff, 43),
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MX31_PIN_LD10 = IOMUX_PIN(0xff, 44),
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MX31_PIN_LD9 = IOMUX_PIN(0xff, 45),
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MX31_PIN_LD8 = IOMUX_PIN(0xff, 46),
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MX31_PIN_LD7 = IOMUX_PIN(0xff, 47),
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MX31_PIN_LD6 = IOMUX_PIN(0xff, 48),
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MX31_PIN_LD5 = IOMUX_PIN(0xff, 49),
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MX31_PIN_LD4 = IOMUX_PIN(0xff, 50),
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MX31_PIN_LD3 = IOMUX_PIN(0xff, 51),
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MX31_PIN_LD2 = IOMUX_PIN(0xff, 52),
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MX31_PIN_LD1 = IOMUX_PIN(0xff, 53),
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MX31_PIN_LD0 = IOMUX_PIN(0xff, 54),
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MX31_PIN_USBH2_DATA1 = IOMUX_PIN(0xff, 55),
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MX31_PIN_USBH2_DATA0 = IOMUX_PIN(0xff, 56),
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MX31_PIN_USBH2_NXT = IOMUX_PIN(0xff, 57),
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MX31_PIN_USBH2_STP = IOMUX_PIN(0xff, 58),
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MX31_PIN_USBH2_DIR = IOMUX_PIN(0xff, 59),
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MX31_PIN_USBH2_CLK = IOMUX_PIN(0xff, 60),
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MX31_PIN_USBOTG_DATA7 = IOMUX_PIN(0xff, 61),
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MX31_PIN_USBOTG_DATA6 = IOMUX_PIN(0xff, 62),
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MX31_PIN_USBOTG_DATA5 = IOMUX_PIN(0xff, 63),
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MX31_PIN_USBOTG_DATA4 = IOMUX_PIN(0xff, 64),
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MX31_PIN_USBOTG_DATA3 = IOMUX_PIN(0xff, 65),
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MX31_PIN_USBOTG_DATA2 = IOMUX_PIN(0xff, 66),
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MX31_PIN_USBOTG_DATA1 = IOMUX_PIN(0xff, 67),
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MX31_PIN_USBOTG_DATA0 = IOMUX_PIN(0xff, 68),
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MX31_PIN_USBOTG_NXT = IOMUX_PIN(0xff, 69),
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MX31_PIN_USBOTG_STP = IOMUX_PIN(0xff, 70),
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MX31_PIN_USBOTG_DIR = IOMUX_PIN(0xff, 71),
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MX31_PIN_USBOTG_CLK = IOMUX_PIN(0xff, 72),
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MX31_PIN_USB_BYP = IOMUX_PIN(31, 73),
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MX31_PIN_USB_OC = IOMUX_PIN(30, 74),
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MX31_PIN_USB_PWR = IOMUX_PIN(29, 75),
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MX31_PIN_SJC_MOD = IOMUX_PIN(0xff, 76),
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MX31_PIN_DE_B = IOMUX_PIN(0xff, 77),
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MX31_PIN_TRSTB = IOMUX_PIN(0xff, 78),
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MX31_PIN_TDO = IOMUX_PIN(0xff, 79),
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MX31_PIN_TDI = IOMUX_PIN(0xff, 80),
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MX31_PIN_TMS = IOMUX_PIN(0xff, 81),
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MX31_PIN_TCK = IOMUX_PIN(0xff, 82),
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MX31_PIN_RTCK = IOMUX_PIN(0xff, 83),
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MX31_PIN_KEY_COL7 = IOMUX_PIN(57, 84),
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MX31_PIN_KEY_COL6 = IOMUX_PIN(56, 85),
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MX31_PIN_KEY_COL5 = IOMUX_PIN(55, 86),
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MX31_PIN_KEY_COL4 = IOMUX_PIN(54, 87),
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MX31_PIN_KEY_COL3 = IOMUX_PIN(0xff, 88),
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MX31_PIN_KEY_COL2 = IOMUX_PIN(0xff, 89),
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MX31_PIN_KEY_COL1 = IOMUX_PIN(0xff, 90),
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MX31_PIN_KEY_COL0 = IOMUX_PIN(0xff, 91),
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MX31_PIN_KEY_ROW7 = IOMUX_PIN(53, 92),
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MX31_PIN_KEY_ROW6 = IOMUX_PIN(52, 93),
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MX31_PIN_KEY_ROW5 = IOMUX_PIN(51, 94),
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MX31_PIN_KEY_ROW4 = IOMUX_PIN(50, 95),
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MX31_PIN_KEY_ROW3 = IOMUX_PIN(0xff, 96),
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MX31_PIN_KEY_ROW2 = IOMUX_PIN(0xff, 97),
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MX31_PIN_KEY_ROW1 = IOMUX_PIN(0xff, 98),
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MX31_PIN_KEY_ROW0 = IOMUX_PIN(0xff, 99),
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MX31_PIN_BATT_LINE = IOMUX_PIN(49, 100),
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MX31_PIN_CTS2 = IOMUX_PIN(0xff, 101),
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MX31_PIN_RTS2 = IOMUX_PIN(0xff, 102),
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MX31_PIN_TXD2 = IOMUX_PIN(28, 103),
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MX31_PIN_RXD2 = IOMUX_PIN(27, 104),
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MX31_PIN_DTR_DCE2 = IOMUX_PIN(48, 105),
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MX31_PIN_DCD_DTE1 = IOMUX_PIN(47, 106),
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MX31_PIN_RI_DTE1 = IOMUX_PIN(46, 107),
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MX31_PIN_DSR_DTE1 = IOMUX_PIN(45, 108),
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MX31_PIN_DTR_DTE1 = IOMUX_PIN(44, 109),
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MX31_PIN_DCD_DCE1 = IOMUX_PIN(43, 110),
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MX31_PIN_RI_DCE1 = IOMUX_PIN(42, 111),
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MX31_PIN_DSR_DCE1 = IOMUX_PIN(41, 112),
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MX31_PIN_DTR_DCE1 = IOMUX_PIN(40, 113),
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MX31_PIN_CTS1 = IOMUX_PIN(39, 114),
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MX31_PIN_RTS1 = IOMUX_PIN(38, 115),
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MX31_PIN_TXD1 = IOMUX_PIN(37, 116),
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MX31_PIN_RXD1 = IOMUX_PIN(36, 117),
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MX31_PIN_CSPI2_SPI_RDY = IOMUX_PIN(0xff, 118),
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MX31_PIN_CSPI2_SCLK = IOMUX_PIN(0xff, 119),
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MX31_PIN_CSPI2_SS2 = IOMUX_PIN(0xff, 120),
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MX31_PIN_CSPI2_SS1 = IOMUX_PIN(0xff, 121),
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MX31_PIN_CSPI2_SS0 = IOMUX_PIN(0xff, 122),
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MX31_PIN_CSPI2_MISO = IOMUX_PIN(0xff, 123),
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MX31_PIN_CSPI2_MOSI = IOMUX_PIN(0xff, 124),
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MX31_PIN_CSPI1_SPI_RDY = IOMUX_PIN(0xff, 125),
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MX31_PIN_CSPI1_SCLK = IOMUX_PIN(0xff, 126),
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MX31_PIN_CSPI1_SS2 = IOMUX_PIN(0xff, 127),
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MX31_PIN_CSPI1_SS1 = IOMUX_PIN(0xff, 128),
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MX31_PIN_CSPI1_SS0 = IOMUX_PIN(0xff, 129),
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MX31_PIN_CSPI1_MISO = IOMUX_PIN(0xff, 130),
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MX31_PIN_CSPI1_MOSI = IOMUX_PIN(0xff, 131),
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MX31_PIN_SFS6 = IOMUX_PIN(26, 132),
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MX31_PIN_SCK6 = IOMUX_PIN(25, 133),
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MX31_PIN_SRXD6 = IOMUX_PIN(24, 134),
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MX31_PIN_STXD6 = IOMUX_PIN(23, 135),
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MX31_PIN_SFS5 = IOMUX_PIN(0xff, 136),
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MX31_PIN_SCK5 = IOMUX_PIN(0xff, 137),
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MX31_PIN_SRXD5 = IOMUX_PIN(22, 138),
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MX31_PIN_STXD5 = IOMUX_PIN(21, 139),
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MX31_PIN_SFS4 = IOMUX_PIN(0xff, 140),
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MX31_PIN_SCK4 = IOMUX_PIN(0xff, 141),
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MX31_PIN_SRXD4 = IOMUX_PIN(20, 142),
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MX31_PIN_STXD4 = IOMUX_PIN(19, 143),
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MX31_PIN_SFS3 = IOMUX_PIN(0xff, 144),
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MX31_PIN_SCK3 = IOMUX_PIN(0xff, 145),
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MX31_PIN_SRXD3 = IOMUX_PIN(18, 146),
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MX31_PIN_STXD3 = IOMUX_PIN(17, 147),
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MX31_PIN_I2C_DAT = IOMUX_PIN(0xff, 148),
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MX31_PIN_I2C_CLK = IOMUX_PIN(0xff, 149),
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MX31_PIN_CSI_PIXCLK = IOMUX_PIN(83, 150),
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MX31_PIN_CSI_HSYNC = IOMUX_PIN(82, 151),
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MX31_PIN_CSI_VSYNC = IOMUX_PIN(81, 152),
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MX31_PIN_CSI_MCLK = IOMUX_PIN(80, 153),
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MX31_PIN_CSI_D15 = IOMUX_PIN(79, 154),
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MX31_PIN_CSI_D14 = IOMUX_PIN(78, 155),
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MX31_PIN_CSI_D13 = IOMUX_PIN(77, 156),
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MX31_PIN_CSI_D12 = IOMUX_PIN(76, 157),
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MX31_PIN_CSI_D11 = IOMUX_PIN(75, 158),
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MX31_PIN_CSI_D10 = IOMUX_PIN(74, 159),
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MX31_PIN_CSI_D9 = IOMUX_PIN(73, 160),
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MX31_PIN_CSI_D8 = IOMUX_PIN(72, 161),
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MX31_PIN_CSI_D7 = IOMUX_PIN(71, 162),
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MX31_PIN_CSI_D6 = IOMUX_PIN(70, 163),
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MX31_PIN_CSI_D5 = IOMUX_PIN(69, 164),
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MX31_PIN_CSI_D4 = IOMUX_PIN(68, 165),
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MX31_PIN_M_GRANT = IOMUX_PIN(0xff, 166),
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MX31_PIN_M_REQUEST = IOMUX_PIN(0xff, 167),
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MX31_PIN_PC_POE = IOMUX_PIN(0xff, 168),
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MX31_PIN_PC_RW_B = IOMUX_PIN(0xff, 169),
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MX31_PIN_IOIS16 = IOMUX_PIN(0xff, 170),
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MX31_PIN_PC_RST = IOMUX_PIN(0xff, 171),
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MX31_PIN_PC_BVD2 = IOMUX_PIN(0xff, 172),
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MX31_PIN_PC_BVD1 = IOMUX_PIN(0xff, 173),
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MX31_PIN_PC_VS2 = IOMUX_PIN(0xff, 174),
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MX31_PIN_PC_VS1 = IOMUX_PIN(0xff, 175),
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MX31_PIN_PC_PWRON = IOMUX_PIN(0xff, 176),
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MX31_PIN_PC_READY = IOMUX_PIN(0xff, 177),
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MX31_PIN_PC_WAIT_B = IOMUX_PIN(0xff, 178),
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MX31_PIN_PC_CD2_B = IOMUX_PIN(0xff, 179),
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MX31_PIN_PC_CD1_B = IOMUX_PIN(0xff, 180),
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MX31_PIN_D0 = IOMUX_PIN(0xff, 181),
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MX31_PIN_D1 = IOMUX_PIN(0xff, 182),
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MX31_PIN_D2 = IOMUX_PIN(0xff, 183),
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MX31_PIN_D3 = IOMUX_PIN(0xff, 184),
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MX31_PIN_D4 = IOMUX_PIN(0xff, 185),
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MX31_PIN_D5 = IOMUX_PIN(0xff, 186),
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MX31_PIN_D6 = IOMUX_PIN(0xff, 187),
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MX31_PIN_D7 = IOMUX_PIN(0xff, 188),
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MX31_PIN_D8 = IOMUX_PIN(0xff, 189),
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MX31_PIN_D9 = IOMUX_PIN(0xff, 190),
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MX31_PIN_D10 = IOMUX_PIN(0xff, 191),
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MX31_PIN_D11 = IOMUX_PIN(0xff, 192),
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MX31_PIN_D12 = IOMUX_PIN(0xff, 193),
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MX31_PIN_D13 = IOMUX_PIN(0xff, 194),
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MX31_PIN_D14 = IOMUX_PIN(0xff, 195),
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MX31_PIN_D15 = IOMUX_PIN(0xff, 196),
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MX31_PIN_NFRB = IOMUX_PIN(16, 197),
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MX31_PIN_NFCE_B = IOMUX_PIN(15, 198),
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MX31_PIN_NFWP_B = IOMUX_PIN(14, 199),
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MX31_PIN_NFCLE = IOMUX_PIN(13, 200),
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MX31_PIN_NFALE = IOMUX_PIN(12, 201),
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MX31_PIN_NFRE_B = IOMUX_PIN(11, 202),
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MX31_PIN_NFWE_B = IOMUX_PIN(10, 203),
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MX31_PIN_SDQS3 = IOMUX_PIN(0xff, 204),
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MX31_PIN_SDQS2 = IOMUX_PIN(0xff, 205),
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MX31_PIN_SDQS1 = IOMUX_PIN(0xff, 206),
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MX31_PIN_SDQS0 = IOMUX_PIN(0xff, 207),
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MX31_PIN_SDCLK_B = IOMUX_PIN(0xff, 208),
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MX31_PIN_SDCLK = IOMUX_PIN(0xff, 209),
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MX31_PIN_SDCKE1 = IOMUX_PIN(0xff, 210),
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MX31_PIN_SDCKE0 = IOMUX_PIN(0xff, 211),
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MX31_PIN_SDWE = IOMUX_PIN(0xff, 212),
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MX31_PIN_CAS = IOMUX_PIN(0xff, 213),
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MX31_PIN_RAS = IOMUX_PIN(0xff, 214),
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MX31_PIN_RW = IOMUX_PIN(0xff, 215),
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MX31_PIN_BCLK = IOMUX_PIN(0xff, 216),
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MX31_PIN_LBA = IOMUX_PIN(0xff, 217),
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MX31_PIN_ECB = IOMUX_PIN(0xff, 218),
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MX31_PIN_CS5 = IOMUX_PIN(0xff, 219),
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MX31_PIN_CS4 = IOMUX_PIN(0xff, 220),
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MX31_PIN_CS3 = IOMUX_PIN(0xff, 221),
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MX31_PIN_CS2 = IOMUX_PIN(0xff, 222),
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MX31_PIN_CS1 = IOMUX_PIN(0xff, 223),
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MX31_PIN_CS0 = IOMUX_PIN(0xff, 224),
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MX31_PIN_OE = IOMUX_PIN(0xff, 225),
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MX31_PIN_EB1 = IOMUX_PIN(0xff, 226),
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MX31_PIN_EB0 = IOMUX_PIN(0xff, 227),
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MX31_PIN_DQM3 = IOMUX_PIN(0xff, 228),
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MX31_PIN_DQM2 = IOMUX_PIN(0xff, 229),
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MX31_PIN_DQM1 = IOMUX_PIN(0xff, 230),
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MX31_PIN_DQM0 = IOMUX_PIN(0xff, 231),
|
||||
MX31_PIN_SD31 = IOMUX_PIN(0xff, 232),
|
||||
MX31_PIN_SD30 = IOMUX_PIN(0xff, 233),
|
||||
MX31_PIN_SD29 = IOMUX_PIN(0xff, 234),
|
||||
MX31_PIN_SD28 = IOMUX_PIN(0xff, 235),
|
||||
MX31_PIN_SD27 = IOMUX_PIN(0xff, 236),
|
||||
MX31_PIN_SD26 = IOMUX_PIN(0xff, 237),
|
||||
MX31_PIN_SD25 = IOMUX_PIN(0xff, 238),
|
||||
MX31_PIN_SD24 = IOMUX_PIN(0xff, 239),
|
||||
MX31_PIN_SD23 = IOMUX_PIN(0xff, 240),
|
||||
MX31_PIN_SD22 = IOMUX_PIN(0xff, 241),
|
||||
MX31_PIN_SD21 = IOMUX_PIN(0xff, 242),
|
||||
MX31_PIN_SD20 = IOMUX_PIN(0xff, 243),
|
||||
MX31_PIN_SD19 = IOMUX_PIN(0xff, 244),
|
||||
MX31_PIN_SD18 = IOMUX_PIN(0xff, 245),
|
||||
MX31_PIN_SD17 = IOMUX_PIN(0xff, 246),
|
||||
MX31_PIN_SD16 = IOMUX_PIN(0xff, 247),
|
||||
MX31_PIN_SD15 = IOMUX_PIN(0xff, 248),
|
||||
MX31_PIN_SD14 = IOMUX_PIN(0xff, 249),
|
||||
MX31_PIN_SD13 = IOMUX_PIN(0xff, 250),
|
||||
MX31_PIN_SD12 = IOMUX_PIN(0xff, 251),
|
||||
MX31_PIN_SD11 = IOMUX_PIN(0xff, 252),
|
||||
MX31_PIN_SD10 = IOMUX_PIN(0xff, 253),
|
||||
MX31_PIN_SD9 = IOMUX_PIN(0xff, 254),
|
||||
MX31_PIN_SD8 = IOMUX_PIN(0xff, 255),
|
||||
MX31_PIN_SD7 = IOMUX_PIN(0xff, 256),
|
||||
MX31_PIN_SD6 = IOMUX_PIN(0xff, 257),
|
||||
MX31_PIN_SD5 = IOMUX_PIN(0xff, 258),
|
||||
MX31_PIN_SD4 = IOMUX_PIN(0xff, 259),
|
||||
MX31_PIN_SD3 = IOMUX_PIN(0xff, 260),
|
||||
MX31_PIN_SD2 = IOMUX_PIN(0xff, 261),
|
||||
MX31_PIN_SD1 = IOMUX_PIN(0xff, 262),
|
||||
MX31_PIN_SD0 = IOMUX_PIN(0xff, 263),
|
||||
MX31_PIN_SDBA0 = IOMUX_PIN(0xff, 264),
|
||||
MX31_PIN_SDBA1 = IOMUX_PIN(0xff, 265),
|
||||
MX31_PIN_A25 = IOMUX_PIN(0xff, 266),
|
||||
MX31_PIN_A24 = IOMUX_PIN(0xff, 267),
|
||||
MX31_PIN_A23 = IOMUX_PIN(0xff, 268),
|
||||
MX31_PIN_A22 = IOMUX_PIN(0xff, 269),
|
||||
MX31_PIN_A21 = IOMUX_PIN(0xff, 270),
|
||||
MX31_PIN_A20 = IOMUX_PIN(0xff, 271),
|
||||
MX31_PIN_A19 = IOMUX_PIN(0xff, 272),
|
||||
MX31_PIN_A18 = IOMUX_PIN(0xff, 273),
|
||||
MX31_PIN_A17 = IOMUX_PIN(0xff, 274),
|
||||
MX31_PIN_A16 = IOMUX_PIN(0xff, 275),
|
||||
MX31_PIN_A14 = IOMUX_PIN(0xff, 276),
|
||||
MX31_PIN_A15 = IOMUX_PIN(0xff, 277),
|
||||
MX31_PIN_A13 = IOMUX_PIN(0xff, 278),
|
||||
MX31_PIN_A12 = IOMUX_PIN(0xff, 279),
|
||||
MX31_PIN_A11 = IOMUX_PIN(0xff, 280),
|
||||
MX31_PIN_MA10 = IOMUX_PIN(0xff, 281),
|
||||
MX31_PIN_A10 = IOMUX_PIN(0xff, 282),
|
||||
MX31_PIN_A9 = IOMUX_PIN(0xff, 283),
|
||||
MX31_PIN_A8 = IOMUX_PIN(0xff, 284),
|
||||
MX31_PIN_A7 = IOMUX_PIN(0xff, 285),
|
||||
MX31_PIN_A6 = IOMUX_PIN(0xff, 286),
|
||||
MX31_PIN_A5 = IOMUX_PIN(0xff, 287),
|
||||
MX31_PIN_A4 = IOMUX_PIN(0xff, 288),
|
||||
MX31_PIN_A3 = IOMUX_PIN(0xff, 289),
|
||||
MX31_PIN_A2 = IOMUX_PIN(0xff, 290),
|
||||
MX31_PIN_A1 = IOMUX_PIN(0xff, 291),
|
||||
MX31_PIN_A0 = IOMUX_PIN(0xff, 292),
|
||||
MX31_PIN_VPG1 = IOMUX_PIN(0xff, 293),
|
||||
MX31_PIN_VPG0 = IOMUX_PIN(0xff, 294),
|
||||
MX31_PIN_DVFS1 = IOMUX_PIN(0xff, 295),
|
||||
MX31_PIN_DVFS0 = IOMUX_PIN(0xff, 296),
|
||||
MX31_PIN_VSTBY = IOMUX_PIN(0xff, 297),
|
||||
MX31_PIN_POWER_FAIL = IOMUX_PIN(0xff, 298),
|
||||
MX31_PIN_CKIL = IOMUX_PIN(0xff, 299),
|
||||
MX31_PIN_BOOT_MODE4 = IOMUX_PIN(0xff, 300),
|
||||
MX31_PIN_BOOT_MODE3 = IOMUX_PIN(0xff, 301),
|
||||
MX31_PIN_BOOT_MODE2 = IOMUX_PIN(0xff, 302),
|
||||
MX31_PIN_BOOT_MODE1 = IOMUX_PIN(0xff, 303),
|
||||
MX31_PIN_BOOT_MODE0 = IOMUX_PIN(0xff, 304),
|
||||
MX31_PIN_CLKO = IOMUX_PIN(0xff, 305),
|
||||
MX31_PIN_POR_B = IOMUX_PIN(0xff, 306),
|
||||
MX31_PIN_RESET_IN_B = IOMUX_PIN(0xff, 307),
|
||||
MX31_PIN_CKIH = IOMUX_PIN(0xff, 308),
|
||||
MX31_PIN_SIMPD0 = IOMUX_PIN(35, 309),
|
||||
MX31_PIN_SRX0 = IOMUX_PIN(34, 310),
|
||||
MX31_PIN_STX0 = IOMUX_PIN(33, 311),
|
||||
MX31_PIN_SVEN0 = IOMUX_PIN(32, 312),
|
||||
MX31_PIN_SRST0 = IOMUX_PIN(67, 313),
|
||||
MX31_PIN_SCLK0 = IOMUX_PIN(66, 314),
|
||||
MX31_PIN_GPIO3_1 = IOMUX_PIN(65, 315),
|
||||
MX31_PIN_GPIO3_0 = IOMUX_PIN(64, 316),
|
||||
MX31_PIN_GPIO1_6 = IOMUX_PIN(6, 317),
|
||||
MX31_PIN_GPIO1_5 = IOMUX_PIN(5, 318),
|
||||
MX31_PIN_GPIO1_4 = IOMUX_PIN(4, 319),
|
||||
MX31_PIN_GPIO1_3 = IOMUX_PIN(3, 320),
|
||||
MX31_PIN_GPIO1_2 = IOMUX_PIN(2, 321),
|
||||
MX31_PIN_GPIO1_1 = IOMUX_PIN(1, 322),
|
||||
MX31_PIN_GPIO1_0 = IOMUX_PIN(0, 323),
|
||||
MX31_PIN_PWMO = IOMUX_PIN(9, 324),
|
||||
MX31_PIN_WATCHDOG_RST = IOMUX_PIN(0xff, 325),
|
||||
MX31_PIN_COMPARE = IOMUX_PIN(8, 326),
|
||||
MX31_PIN_CAPTURE = IOMUX_PIN(7, 327),
|
||||
};
|
||||
|
||||
/* Bit definitions for RCSR register in CCM */
|
||||
#define CCM_RCSR_NF16B (1 << 31)
|
||||
@ -194,6 +558,12 @@ struct gpio_regs {
|
||||
|
||||
/* Register offsets based on IOMUXC_BASE */
|
||||
/* 0x00 .. 0x7b */
|
||||
#define MUX_CTL_USBH2_DATA1 0x40
|
||||
#define MUX_CTL_USBH2_DIR 0x44
|
||||
#define MUX_CTL_USBH2_STP 0x45
|
||||
#define MUX_CTL_USBH2_NXT 0x46
|
||||
#define MUX_CTL_USBH2_DATA0 0x47
|
||||
#define MUX_CTL_USBH2_CLK 0x4B
|
||||
#define MUX_CTL_RTS1 0x7c
|
||||
#define MUX_CTL_CTS1 0x7d
|
||||
#define MUX_CTL_DTR_DCE1 0x7e
|
||||
@ -219,6 +589,11 @@ struct gpio_regs {
|
||||
#define MUX_CTL_SCK6 0x92
|
||||
#define MUX_CTL_SFS6 0x93
|
||||
|
||||
#define MUX_CTL_STXD3 0x9C
|
||||
#define MUX_CTL_SRXD3 0x9D
|
||||
#define MUX_CTL_SCK3 0x9E
|
||||
#define MUX_CTL_SFS3 0x9F
|
||||
|
||||
#define MUX_CTL_NFC_WP 0xD0
|
||||
#define MUX_CTL_NFC_CE 0xD1
|
||||
#define MUX_CTL_NFC_RB 0xD2
|
||||
@ -324,4 +699,33 @@ struct gpio_regs {
|
||||
#define IRAM_BASE_ADDR 0x1FFFC000
|
||||
#define IRAM_SIZE (16 * 1024)
|
||||
|
||||
#define MX31_AIPS1_BASE_ADDR 0x43f00000
|
||||
#define MX31_OTG_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x88000)
|
||||
|
||||
/* USB portsc */
|
||||
/* values for portsc field */
|
||||
#define MXC_EHCI_PHY_LOW_POWER_SUSPEND (1 << 23)
|
||||
#define MXC_EHCI_FORCE_FS (1 << 24)
|
||||
#define MXC_EHCI_UTMI_8BIT (0 << 28)
|
||||
#define MXC_EHCI_UTMI_16BIT (1 << 28)
|
||||
#define MXC_EHCI_SERIAL (1 << 29)
|
||||
#define MXC_EHCI_MODE_UTMI (0 << 30)
|
||||
#define MXC_EHCI_MODE_PHILIPS (1 << 30)
|
||||
#define MXC_EHCI_MODE_ULPI (2 << 30)
|
||||
#define MXC_EHCI_MODE_SERIAL (3 << 30)
|
||||
|
||||
/* values for flags field */
|
||||
#define MXC_EHCI_INTERFACE_DIFF_UNI (0 << 0)
|
||||
#define MXC_EHCI_INTERFACE_DIFF_BI (1 << 0)
|
||||
#define MXC_EHCI_INTERFACE_SINGLE_UNI (2 << 0)
|
||||
#define MXC_EHCI_INTERFACE_SINGLE_BI (3 << 0)
|
||||
#define MXC_EHCI_INTERFACE_MASK (0xf)
|
||||
|
||||
#define MXC_EHCI_POWER_PINS_ENABLED (1 << 5)
|
||||
#define MXC_EHCI_TTL_ENABLED (1 << 6)
|
||||
|
||||
#define MXC_EHCI_INTERNAL_PHY (1 << 7)
|
||||
#define MXC_EHCI_IPPUE_DOWN (1 << 8)
|
||||
#define MXC_EHCI_IPPUE_UP (1 << 9)
|
||||
|
||||
#endif /* __ASM_ARCH_MX31_REGS_H */
|
||||
|
||||
@ -334,37 +334,6 @@ enum ipu_panel {
|
||||
|
||||
#define IOMUX_MODE_L(pin, mode) IOMUX_MODE(((pin) + 0xc) ^ 3, mode)
|
||||
|
||||
enum lcd_pin {
|
||||
MX31_PIN_D3_SPL = IOMUX_PIN(0xff, 19),
|
||||
MX31_PIN_D3_CLS = IOMUX_PIN(0xff, 20),
|
||||
MX31_PIN_D3_REV = IOMUX_PIN(0xff, 21),
|
||||
MX31_PIN_CONTRAST = IOMUX_PIN(0xff, 22),
|
||||
MX31_PIN_VSYNC3 = IOMUX_PIN(0xff, 23),
|
||||
|
||||
MX31_PIN_DRDY0 = IOMUX_PIN(0xff, 33),
|
||||
MX31_PIN_FPSHIFT = IOMUX_PIN(0xff, 34),
|
||||
MX31_PIN_HSYNC = IOMUX_PIN(0xff, 35),
|
||||
|
||||
MX31_PIN_LD17 = IOMUX_PIN(0xff, 37),
|
||||
MX31_PIN_LD16 = IOMUX_PIN(0xff, 38),
|
||||
MX31_PIN_LD15 = IOMUX_PIN(0xff, 39),
|
||||
MX31_PIN_LD14 = IOMUX_PIN(0xff, 40),
|
||||
MX31_PIN_LD13 = IOMUX_PIN(0xff, 41),
|
||||
MX31_PIN_LD12 = IOMUX_PIN(0xff, 42),
|
||||
MX31_PIN_LD11 = IOMUX_PIN(0xff, 43),
|
||||
MX31_PIN_LD10 = IOMUX_PIN(0xff, 44),
|
||||
MX31_PIN_LD9 = IOMUX_PIN(0xff, 45),
|
||||
MX31_PIN_LD8 = IOMUX_PIN(0xff, 46),
|
||||
MX31_PIN_LD7 = IOMUX_PIN(0xff, 47),
|
||||
MX31_PIN_LD6 = IOMUX_PIN(0xff, 48),
|
||||
MX31_PIN_LD5 = IOMUX_PIN(0xff, 49),
|
||||
MX31_PIN_LD4 = IOMUX_PIN(0xff, 50),
|
||||
MX31_PIN_LD3 = IOMUX_PIN(0xff, 51),
|
||||
MX31_PIN_LD2 = IOMUX_PIN(0xff, 52),
|
||||
MX31_PIN_LD1 = IOMUX_PIN(0xff, 53),
|
||||
MX31_PIN_LD0 = IOMUX_PIN(0xff, 54),
|
||||
};
|
||||
|
||||
struct chan_param_mem_planar {
|
||||
/* Word 0 */
|
||||
u32 xv:10;
|
||||
|
||||
Loading…
Reference in New Issue
Block a user