From fb265a74cfed2c655e02390d4fb13ffcfece2101 Mon Sep 17 00:00:00 2001 From: Hector Palacios Date: Fri, 17 Aug 2018 13:06:40 +0200 Subject: [PATCH 01/13] cmd: mii: don't check address for 'device' subcommand All mii operations require a valid PHY address except the 'device' command, which expects the PHY name rather than the address. Signed-off-by: Hector Palacios Acked-by: Joe Hershberger --- cmd/mii.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/cmd/mii.c b/cmd/mii.c index ce7b393eea..c0c42a851f 100644 --- a/cmd/mii.c +++ b/cmd/mii.c @@ -313,7 +313,7 @@ static int do_mii(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) mask = simple_strtoul(argv[5], NULL, 16); } - if (addrhi > 31) { + if (addrhi > 31 && strncmp(op, "de", 2)) { printf("Incorrect PHY address. Range should be 0-31\n"); return CMD_RET_USAGE; } From 9215bb1f37fbeb9dc9c18953040a5170214e9039 Mon Sep 17 00:00:00 2001 From: Pankaj Bansal Date: Tue, 18 Sep 2018 15:46:48 +0530 Subject: [PATCH 02/13] miiphy: Add function to retrieve MDIO bus list head In upcoming freescale board LX2160AQDS, the MDIO bus is muxed. i.e. same MDIO bus can be routed to eight different slots depending on mux register settings. To support this mdio mux behavior, we add each MDIO bus mux as a separate MDIO bus. Now, various phy devices can be attached to each of these slots(mux). The information about these devices is passed to OS via device tree. To do the fdt fixups related to MDIO bus, its necessary that MDIO bus list is accessed.Therefore, add a function to retrieve the list head. Signed-off-by: Pankaj Bansal Acked-by: Joe Hershberger --- common/miiphyutil.c | 5 +++++ include/miiphy.h | 1 + 2 files changed, 6 insertions(+) diff --git a/common/miiphyutil.c b/common/miiphyutil.c index 8d89751122..2db067876e 100644 --- a/common/miiphyutil.c +++ b/common/miiphyutil.c @@ -177,6 +177,11 @@ struct mii_dev *mdio_get_current_dev(void) return current_mii; } +struct list_head *mdio_get_list_head(void) +{ + return &mii_devs; +} + struct phy_device *mdio_phydev_for_ethname(const char *ethname) { struct list_head *entry; diff --git a/include/miiphy.h b/include/miiphy.h index 2da28e311a..f11763affd 100644 --- a/include/miiphy.h +++ b/include/miiphy.h @@ -39,6 +39,7 @@ void miiphy_init(void); int miiphy_set_current_dev(const char *devname); const char *miiphy_get_current_dev(void); struct mii_dev *mdio_get_current_dev(void); +struct list_head *mdio_get_list_head(void); struct mii_dev *miiphy_get_dev_by_name(const char *devname); struct phy_device *mdio_phydev_for_ethname(const char *devname); From 1c6501088ecab1eaa959aae54a560c3e1970ba4c Mon Sep 17 00:00:00 2001 From: Jeremy Gebben Date: Tue, 18 Sep 2018 15:49:35 -0600 Subject: [PATCH 03/13] configs: migrate CONFIG_PHY_AQUANTIA to Kconfig The aquantia driver requires both CONFIG_PHY_GIGE and CONFIG_PHYLIB_10G. Signed-off-by: Jeremy Gebben Acked-by: Joe Hershberger --- configs/T1023RDB_NAND_defconfig | 2 +- configs/T1023RDB_SDCARD_defconfig | 2 +- configs/T1023RDB_SECURE_BOOT_defconfig | 2 +- configs/T1023RDB_SPIFLASH_defconfig | 2 +- configs/T1023RDB_defconfig | 2 +- configs/T1024RDB_NAND_defconfig | 2 +- configs/T1024RDB_SDCARD_defconfig | 2 +- configs/T1024RDB_SECURE_BOOT_defconfig | 2 +- configs/T1024RDB_SPIFLASH_defconfig | 2 +- configs/T1024RDB_defconfig | 2 +- configs/T2080QDS_NAND_defconfig | 2 +- configs/T2080QDS_SDCARD_defconfig | 2 +- configs/T2080QDS_SECURE_BOOT_defconfig | 2 +- configs/T2080QDS_SPIFLASH_defconfig | 2 +- configs/T2080QDS_SRIO_PCIE_BOOT_defconfig | 2 +- configs/T2080QDS_defconfig | 2 +- configs/T2080RDB_NAND_defconfig | 2 +- configs/T2080RDB_SDCARD_defconfig | 2 +- configs/T2080RDB_SECURE_BOOT_defconfig | 2 +- configs/T2080RDB_SPIFLASH_defconfig | 2 +- configs/T2080RDB_SRIO_PCIE_BOOT_defconfig | 2 +- configs/T2080RDB_defconfig | 2 +- configs/T2081QDS_NAND_defconfig | 2 +- configs/T2081QDS_SDCARD_defconfig | 2 +- configs/T2081QDS_SPIFLASH_defconfig | 2 +- configs/T2081QDS_SRIO_PCIE_BOOT_defconfig | 2 +- configs/T2081QDS_defconfig | 2 +- configs/ls1043ardb_defconfig | 2 +- configs/ls1043ardb_nand_SECURE_BOOT_defconfig | 2 +- configs/ls1043ardb_nand_defconfig | 2 +- configs/ls1043ardb_sdcard_defconfig | 2 +- configs/ls1046ardb_emmc_defconfig | 2 +- configs/ls1046ardb_qspi_SECURE_BOOT_defconfig | 2 +- configs/ls1046ardb_qspi_defconfig | 2 +- configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig | 2 +- configs/ls1046ardb_sdcard_defconfig | 2 +- configs/ls1088ardb_qspi_SECURE_BOOT_defconfig | 1 + configs/ls1088ardb_qspi_defconfig | 1 + configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig | 1 + configs/ls1088ardb_sdcard_qspi_defconfig | 1 + configs/ls2080ardb_SECURE_BOOT_defconfig | 2 +- configs/ls2080ardb_defconfig | 2 +- configs/ls2080ardb_nand_defconfig | 2 +- configs/ls2081ardb_defconfig | 2 +- configs/ls2088ardb_qspi_SECURE_BOOT_defconfig | 2 +- configs/ls2088ardb_qspi_defconfig | 2 +- drivers/net/phy/Kconfig | 2 ++ drivers/net/phy/aquantia.c | 4 ---- include/configs/T102xRDB.h | 2 -- include/configs/T208xQDS.h | 1 - include/configs/T208xRDB.h | 2 -- include/configs/ls1043ardb.h | 2 -- include/configs/ls1046ardb.h | 2 -- include/configs/ls1088ardb.h | 3 --- include/configs/ls2080ardb.h | 3 --- 55 files changed, 48 insertions(+), 61 deletions(-) diff --git a/configs/T1023RDB_NAND_defconfig b/configs/T1023RDB_NAND_defconfig index 3cab0707bb..be034abdcd 100644 --- a/configs/T1023RDB_NAND_defconfig +++ b/configs/T1023RDB_NAND_defconfig @@ -52,7 +52,7 @@ CONFIG_NAND=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHYLIB=y -CONFIG_PHY_GIGE=y +CONFIG_PHY_AQUANTIA=y CONFIG_E1000=y CONFIG_MII=y CONFIG_SYS_NS16550=y diff --git a/configs/T1023RDB_SDCARD_defconfig b/configs/T1023RDB_SDCARD_defconfig index 4b2f59b561..f1df742497 100644 --- a/configs/T1023RDB_SDCARD_defconfig +++ b/configs/T1023RDB_SDCARD_defconfig @@ -51,7 +51,7 @@ CONFIG_SYS_FLASH_CFI=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHYLIB=y -CONFIG_PHY_GIGE=y +CONFIG_PHY_AQUANTIA=y CONFIG_E1000=y CONFIG_MII=y CONFIG_SYS_NS16550=y diff --git a/configs/T1023RDB_SECURE_BOOT_defconfig b/configs/T1023RDB_SECURE_BOOT_defconfig index f75ee2e35c..473bb1548a 100644 --- a/configs/T1023RDB_SECURE_BOOT_defconfig +++ b/configs/T1023RDB_SECURE_BOOT_defconfig @@ -41,7 +41,7 @@ CONFIG_SYS_FLASH_CFI=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHYLIB=y -CONFIG_PHY_GIGE=y +CONFIG_PHY_AQUANTIA=y CONFIG_E1000=y CONFIG_MII=y CONFIG_SYS_NS16550=y diff --git a/configs/T1023RDB_SPIFLASH_defconfig b/configs/T1023RDB_SPIFLASH_defconfig index 0ad7c28641..18866d0336 100644 --- a/configs/T1023RDB_SPIFLASH_defconfig +++ b/configs/T1023RDB_SPIFLASH_defconfig @@ -52,7 +52,7 @@ CONFIG_SYS_FLASH_CFI=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHYLIB=y -CONFIG_PHY_GIGE=y +CONFIG_PHY_AQUANTIA=y CONFIG_E1000=y CONFIG_MII=y CONFIG_SYS_NS16550=y diff --git a/configs/T1023RDB_defconfig b/configs/T1023RDB_defconfig index d3c3740a75..f4434ab782 100644 --- a/configs/T1023RDB_defconfig +++ b/configs/T1023RDB_defconfig @@ -40,7 +40,7 @@ CONFIG_SYS_FLASH_CFI=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHYLIB=y -CONFIG_PHY_GIGE=y +CONFIG_PHY_AQUANTIA=y CONFIG_E1000=y CONFIG_MII=y CONFIG_SYS_NS16550=y diff --git a/configs/T1024RDB_NAND_defconfig b/configs/T1024RDB_NAND_defconfig index fc35fb3366..6a37a7ff83 100644 --- a/configs/T1024RDB_NAND_defconfig +++ b/configs/T1024RDB_NAND_defconfig @@ -54,7 +54,7 @@ CONFIG_NAND=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_PHYLIB=y -CONFIG_PHY_GIGE=y +CONFIG_PHY_AQUANTIA=y CONFIG_E1000=y CONFIG_MII=y CONFIG_SYS_NS16550=y diff --git a/configs/T1024RDB_SDCARD_defconfig b/configs/T1024RDB_SDCARD_defconfig index 079d7721fc..dce5bdc21e 100644 --- a/configs/T1024RDB_SDCARD_defconfig +++ b/configs/T1024RDB_SDCARD_defconfig @@ -53,7 +53,7 @@ CONFIG_SYS_FLASH_CFI=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_PHYLIB=y -CONFIG_PHY_GIGE=y +CONFIG_PHY_AQUANTIA=y CONFIG_E1000=y CONFIG_MII=y CONFIG_SYS_NS16550=y diff --git a/configs/T1024RDB_SECURE_BOOT_defconfig b/configs/T1024RDB_SECURE_BOOT_defconfig index 376010fd2a..84bdffa6fc 100644 --- a/configs/T1024RDB_SECURE_BOOT_defconfig +++ b/configs/T1024RDB_SECURE_BOOT_defconfig @@ -43,7 +43,7 @@ CONFIG_SYS_FLASH_CFI=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_PHYLIB=y -CONFIG_PHY_GIGE=y +CONFIG_PHY_AQUANTIA=y CONFIG_E1000=y CONFIG_MII=y CONFIG_SYS_NS16550=y diff --git a/configs/T1024RDB_SPIFLASH_defconfig b/configs/T1024RDB_SPIFLASH_defconfig index 006d25c066..bf28b13561 100644 --- a/configs/T1024RDB_SPIFLASH_defconfig +++ b/configs/T1024RDB_SPIFLASH_defconfig @@ -54,7 +54,7 @@ CONFIG_SYS_FLASH_CFI=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_PHYLIB=y -CONFIG_PHY_GIGE=y +CONFIG_PHY_AQUANTIA=y CONFIG_E1000=y CONFIG_MII=y CONFIG_SYS_NS16550=y diff --git a/configs/T1024RDB_defconfig b/configs/T1024RDB_defconfig index 86411a57be..a666e7e779 100644 --- a/configs/T1024RDB_defconfig +++ b/configs/T1024RDB_defconfig @@ -42,7 +42,7 @@ CONFIG_SYS_FLASH_CFI=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_PHYLIB=y -CONFIG_PHY_GIGE=y +CONFIG_PHY_AQUANTIA=y CONFIG_E1000=y CONFIG_MII=y CONFIG_SYS_NS16550=y diff --git a/configs/T2080QDS_NAND_defconfig b/configs/T2080QDS_NAND_defconfig index 84a70c9207..4dcd9e26a6 100644 --- a/configs/T2080QDS_NAND_defconfig +++ b/configs/T2080QDS_NAND_defconfig @@ -52,7 +52,7 @@ CONFIG_SPI_FLASH_EON=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_SPI_FLASH_SST=y CONFIG_PHYLIB=y -CONFIG_PHY_GIGE=y +CONFIG_PHY_AQUANTIA=y CONFIG_E1000=y CONFIG_MII=y CONFIG_SYS_NS16550=y diff --git a/configs/T2080QDS_SDCARD_defconfig b/configs/T2080QDS_SDCARD_defconfig index 02a5655582..9b523870b5 100644 --- a/configs/T2080QDS_SDCARD_defconfig +++ b/configs/T2080QDS_SDCARD_defconfig @@ -51,7 +51,7 @@ CONFIG_SPI_FLASH_EON=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_SPI_FLASH_SST=y CONFIG_PHYLIB=y -CONFIG_PHY_GIGE=y +CONFIG_PHY_AQUANTIA=y CONFIG_E1000=y CONFIG_MII=y CONFIG_SYS_NS16550=y diff --git a/configs/T2080QDS_SECURE_BOOT_defconfig b/configs/T2080QDS_SECURE_BOOT_defconfig index d742b1514a..6e5e477269 100644 --- a/configs/T2080QDS_SECURE_BOOT_defconfig +++ b/configs/T2080QDS_SECURE_BOOT_defconfig @@ -39,7 +39,7 @@ CONFIG_SPI_FLASH_EON=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_SPI_FLASH_SST=y CONFIG_PHYLIB=y -CONFIG_PHY_GIGE=y +CONFIG_PHY_AQUANTIA=y CONFIG_E1000=y CONFIG_MII=y CONFIG_SYS_NS16550=y diff --git a/configs/T2080QDS_SPIFLASH_defconfig b/configs/T2080QDS_SPIFLASH_defconfig index 221e045158..602f6724ba 100644 --- a/configs/T2080QDS_SPIFLASH_defconfig +++ b/configs/T2080QDS_SPIFLASH_defconfig @@ -52,7 +52,7 @@ CONFIG_SPI_FLASH_EON=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_SPI_FLASH_SST=y CONFIG_PHYLIB=y -CONFIG_PHY_GIGE=y +CONFIG_PHY_AQUANTIA=y CONFIG_E1000=y CONFIG_MII=y CONFIG_SYS_NS16550=y diff --git a/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig b/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig index 38216b84f9..9c9a436d81 100644 --- a/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig +++ b/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig @@ -30,7 +30,7 @@ CONFIG_SPI_FLASH_EON=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_SPI_FLASH_SST=y CONFIG_PHYLIB=y -CONFIG_PHY_GIGE=y +CONFIG_PHY_AQUANTIA=y CONFIG_E1000=y CONFIG_MII=y CONFIG_SYS_NS16550=y diff --git a/configs/T2080QDS_defconfig b/configs/T2080QDS_defconfig index 27e06b6c44..676c9f7488 100644 --- a/configs/T2080QDS_defconfig +++ b/configs/T2080QDS_defconfig @@ -41,7 +41,7 @@ CONFIG_SPI_FLASH_EON=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_SPI_FLASH_SST=y CONFIG_PHYLIB=y -CONFIG_PHY_GIGE=y +CONFIG_PHY_AQUANTIA=y CONFIG_E1000=y CONFIG_MII=y CONFIG_SYS_NS16550=y diff --git a/configs/T2080RDB_NAND_defconfig b/configs/T2080RDB_NAND_defconfig index 505dd14aae..38b7bf7069 100644 --- a/configs/T2080RDB_NAND_defconfig +++ b/configs/T2080RDB_NAND_defconfig @@ -50,7 +50,7 @@ CONFIG_NAND=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_PHYLIB=y -CONFIG_PHY_GIGE=y +CONFIG_PHY_AQUANTIA=y CONFIG_E1000=y CONFIG_MII=y CONFIG_SYS_NS16550=y diff --git a/configs/T2080RDB_SDCARD_defconfig b/configs/T2080RDB_SDCARD_defconfig index 71c641605b..c5621d485e 100644 --- a/configs/T2080RDB_SDCARD_defconfig +++ b/configs/T2080RDB_SDCARD_defconfig @@ -49,7 +49,7 @@ CONFIG_SYS_FLASH_CFI=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_PHYLIB=y -CONFIG_PHY_GIGE=y +CONFIG_PHY_AQUANTIA=y CONFIG_E1000=y CONFIG_MII=y CONFIG_SYS_NS16550=y diff --git a/configs/T2080RDB_SECURE_BOOT_defconfig b/configs/T2080RDB_SECURE_BOOT_defconfig index 28e671201a..4887433cb1 100644 --- a/configs/T2080RDB_SECURE_BOOT_defconfig +++ b/configs/T2080RDB_SECURE_BOOT_defconfig @@ -39,7 +39,7 @@ CONFIG_SYS_FLASH_CFI=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_PHYLIB=y -CONFIG_PHY_GIGE=y +CONFIG_PHY_AQUANTIA=y CONFIG_E1000=y CONFIG_MII=y CONFIG_SYS_NS16550=y diff --git a/configs/T2080RDB_SPIFLASH_defconfig b/configs/T2080RDB_SPIFLASH_defconfig index b6960df27f..3169d018c7 100644 --- a/configs/T2080RDB_SPIFLASH_defconfig +++ b/configs/T2080RDB_SPIFLASH_defconfig @@ -50,7 +50,7 @@ CONFIG_SYS_FLASH_CFI=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_PHYLIB=y -CONFIG_PHY_GIGE=y +CONFIG_PHY_AQUANTIA=y CONFIG_E1000=y CONFIG_MII=y CONFIG_SYS_NS16550=y diff --git a/configs/T2080RDB_SRIO_PCIE_BOOT_defconfig b/configs/T2080RDB_SRIO_PCIE_BOOT_defconfig index 947f8eceda..297c31f3c5 100644 --- a/configs/T2080RDB_SRIO_PCIE_BOOT_defconfig +++ b/configs/T2080RDB_SRIO_PCIE_BOOT_defconfig @@ -30,7 +30,7 @@ CONFIG_FSL_ESDHC=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_PHYLIB=y -CONFIG_PHY_GIGE=y +CONFIG_PHY_AQUANTIA=y CONFIG_E1000=y CONFIG_MII=y CONFIG_SYS_NS16550=y diff --git a/configs/T2080RDB_defconfig b/configs/T2080RDB_defconfig index 89bd8dad72..e991734729 100644 --- a/configs/T2080RDB_defconfig +++ b/configs/T2080RDB_defconfig @@ -38,7 +38,7 @@ CONFIG_SYS_FLASH_CFI=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_PHYLIB=y -CONFIG_PHY_GIGE=y +CONFIG_PHY_AQUANTIA=y CONFIG_E1000=y CONFIG_MII=y CONFIG_SYS_NS16550=y diff --git a/configs/T2081QDS_NAND_defconfig b/configs/T2081QDS_NAND_defconfig index d0147d8377..56792e1792 100644 --- a/configs/T2081QDS_NAND_defconfig +++ b/configs/T2081QDS_NAND_defconfig @@ -50,7 +50,7 @@ CONFIG_SPI_FLASH_EON=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_SPI_FLASH_SST=y CONFIG_PHYLIB=y -CONFIG_PHY_GIGE=y +CONFIG_PHY_AQUANTIA=y CONFIG_E1000=y CONFIG_MII=y CONFIG_SYS_NS16550=y diff --git a/configs/T2081QDS_SDCARD_defconfig b/configs/T2081QDS_SDCARD_defconfig index 39d8f1dfef..2492f3da84 100644 --- a/configs/T2081QDS_SDCARD_defconfig +++ b/configs/T2081QDS_SDCARD_defconfig @@ -49,7 +49,7 @@ CONFIG_SPI_FLASH_EON=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_SPI_FLASH_SST=y CONFIG_PHYLIB=y -CONFIG_PHY_GIGE=y +CONFIG_PHY_AQUANTIA=y CONFIG_E1000=y CONFIG_MII=y CONFIG_SYS_NS16550=y diff --git a/configs/T2081QDS_SPIFLASH_defconfig b/configs/T2081QDS_SPIFLASH_defconfig index db2409f985..e7e90107ce 100644 --- a/configs/T2081QDS_SPIFLASH_defconfig +++ b/configs/T2081QDS_SPIFLASH_defconfig @@ -50,7 +50,7 @@ CONFIG_SPI_FLASH_EON=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_SPI_FLASH_SST=y CONFIG_PHYLIB=y -CONFIG_PHY_GIGE=y +CONFIG_PHY_AQUANTIA=y CONFIG_E1000=y CONFIG_MII=y CONFIG_SYS_NS16550=y diff --git a/configs/T2081QDS_SRIO_PCIE_BOOT_defconfig b/configs/T2081QDS_SRIO_PCIE_BOOT_defconfig index 88102aecff..43fe470320 100644 --- a/configs/T2081QDS_SRIO_PCIE_BOOT_defconfig +++ b/configs/T2081QDS_SRIO_PCIE_BOOT_defconfig @@ -30,7 +30,7 @@ CONFIG_SPI_FLASH_EON=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_SPI_FLASH_SST=y CONFIG_PHYLIB=y -CONFIG_PHY_GIGE=y +CONFIG_PHY_AQUANTIA=y CONFIG_E1000=y CONFIG_MII=y CONFIG_SYS_NS16550=y diff --git a/configs/T2081QDS_defconfig b/configs/T2081QDS_defconfig index 7846a42c60..15f7bc1600 100644 --- a/configs/T2081QDS_defconfig +++ b/configs/T2081QDS_defconfig @@ -38,7 +38,7 @@ CONFIG_SPI_FLASH_EON=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_SPI_FLASH_SST=y CONFIG_PHYLIB=y -CONFIG_PHY_GIGE=y +CONFIG_PHY_AQUANTIA=y CONFIG_E1000=y CONFIG_MII=y CONFIG_SYS_NS16550=y diff --git a/configs/ls1043ardb_defconfig b/configs/ls1043ardb_defconfig index e67273a199..7541fad3db 100644 --- a/configs/ls1043ardb_defconfig +++ b/configs/ls1043ardb_defconfig @@ -33,7 +33,7 @@ CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_CFI=y CONFIG_SPI_FLASH=y CONFIG_PHYLIB=y -CONFIG_PHY_GIGE=y +CONFIG_PHY_AQUANTIA=y CONFIG_E1000=y CONFIG_PCI=y CONFIG_DM_PCI=y diff --git a/configs/ls1043ardb_nand_SECURE_BOOT_defconfig b/configs/ls1043ardb_nand_SECURE_BOOT_defconfig index 356569c907..2879f45d56 100644 --- a/configs/ls1043ardb_nand_SECURE_BOOT_defconfig +++ b/configs/ls1043ardb_nand_SECURE_BOOT_defconfig @@ -50,7 +50,7 @@ CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_CFI=y CONFIG_SPI_FLASH=y CONFIG_PHYLIB=y -CONFIG_PHY_GIGE=y +CONFIG_PHY_AQUANTIA=y CONFIG_E1000=y CONFIG_PCI=y CONFIG_DM_PCI=y diff --git a/configs/ls1043ardb_nand_defconfig b/configs/ls1043ardb_nand_defconfig index 154df22d8c..5a23e3cfff 100644 --- a/configs/ls1043ardb_nand_defconfig +++ b/configs/ls1043ardb_nand_defconfig @@ -50,7 +50,7 @@ CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_CFI=y CONFIG_SPI_FLASH=y CONFIG_PHYLIB=y -CONFIG_PHY_GIGE=y +CONFIG_PHY_AQUANTIA=y CONFIG_E1000=y CONFIG_PCI=y CONFIG_DM_PCI=y diff --git a/configs/ls1043ardb_sdcard_defconfig b/configs/ls1043ardb_sdcard_defconfig index 6424f85eaa..144e48b885 100644 --- a/configs/ls1043ardb_sdcard_defconfig +++ b/configs/ls1043ardb_sdcard_defconfig @@ -48,7 +48,7 @@ CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_CFI=y CONFIG_SPI_FLASH=y CONFIG_PHYLIB=y -CONFIG_PHY_GIGE=y +CONFIG_PHY_AQUANTIA=y CONFIG_E1000=y CONFIG_PCI=y CONFIG_DM_PCI=y diff --git a/configs/ls1046ardb_emmc_defconfig b/configs/ls1046ardb_emmc_defconfig index 3968136ec0..16aa1c91db 100644 --- a/configs/ls1046ardb_emmc_defconfig +++ b/configs/ls1046ardb_emmc_defconfig @@ -45,7 +45,7 @@ CONFIG_FSL_CAAM=y CONFIG_FSL_ESDHC=y CONFIG_SPI_FLASH=y CONFIG_PHYLIB=y -CONFIG_PHY_GIGE=y +CONFIG_PHY_AQUANTIA=y CONFIG_E1000=y CONFIG_PCI=y CONFIG_DM_PCI=y diff --git a/configs/ls1046ardb_qspi_SECURE_BOOT_defconfig b/configs/ls1046ardb_qspi_SECURE_BOOT_defconfig index c142df3832..a6159ca406 100644 --- a/configs/ls1046ardb_qspi_SECURE_BOOT_defconfig +++ b/configs/ls1046ardb_qspi_SECURE_BOOT_defconfig @@ -30,7 +30,7 @@ CONFIG_FSL_ESDHC=y CONFIG_SPI_FLASH=y # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set CONFIG_PHYLIB=y -CONFIG_PHY_GIGE=y +CONFIG_PHY_AQUANTIA=y CONFIG_E1000=y CONFIG_PCI=y CONFIG_DM_PCI=y diff --git a/configs/ls1046ardb_qspi_defconfig b/configs/ls1046ardb_qspi_defconfig index f9660c03cf..e9d03d3813 100644 --- a/configs/ls1046ardb_qspi_defconfig +++ b/configs/ls1046ardb_qspi_defconfig @@ -31,7 +31,7 @@ CONFIG_FSL_ESDHC=y CONFIG_SPI_FLASH=y # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set CONFIG_PHYLIB=y -CONFIG_PHY_GIGE=y +CONFIG_PHY_AQUANTIA=y CONFIG_E1000=y CONFIG_PCI=y CONFIG_DM_PCI=y diff --git a/configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig b/configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig index 9f04424c7a..24a08b6e01 100644 --- a/configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig +++ b/configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig @@ -45,7 +45,7 @@ CONFIG_SPL_DM=y CONFIG_FSL_ESDHC=y CONFIG_SPI_FLASH=y CONFIG_PHYLIB=y -CONFIG_PHY_GIGE=y +CONFIG_PHY_AQUANTIA=y CONFIG_E1000=y CONFIG_PCI=y CONFIG_DM_PCI=y diff --git a/configs/ls1046ardb_sdcard_defconfig b/configs/ls1046ardb_sdcard_defconfig index 9486e90edb..c14884caf1 100644 --- a/configs/ls1046ardb_sdcard_defconfig +++ b/configs/ls1046ardb_sdcard_defconfig @@ -44,7 +44,7 @@ CONFIG_FSL_CAAM=y CONFIG_FSL_ESDHC=y CONFIG_SPI_FLASH=y CONFIG_PHYLIB=y -CONFIG_PHY_GIGE=y +CONFIG_PHY_AQUANTIA=y CONFIG_E1000=y CONFIG_PCI=y CONFIG_DM_PCI=y diff --git a/configs/ls1088ardb_qspi_SECURE_BOOT_defconfig b/configs/ls1088ardb_qspi_SECURE_BOOT_defconfig index f54b4a9f5a..f8f1f4de47 100644 --- a/configs/ls1088ardb_qspi_SECURE_BOOT_defconfig +++ b/configs/ls1088ardb_qspi_SECURE_BOOT_defconfig @@ -35,6 +35,7 @@ CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_SPANSION=y # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +CONFIG_PHY_AQUANTIA=y CONFIG_E1000=y CONFIG_MII=y CONFIG_PCI=y diff --git a/configs/ls1088ardb_qspi_defconfig b/configs/ls1088ardb_qspi_defconfig index 1feadedf70..7e9cb99188 100644 --- a/configs/ls1088ardb_qspi_defconfig +++ b/configs/ls1088ardb_qspi_defconfig @@ -35,6 +35,7 @@ CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_SPANSION=y # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +CONFIG_PHY_AQUANTIA=y CONFIG_E1000=y CONFIG_MII=y CONFIG_PCI=y diff --git a/configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig b/configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig index f7ec11fe05..f584dd3c59 100644 --- a/configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig +++ b/configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig @@ -48,6 +48,7 @@ CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_SPANSION=y # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +CONFIG_PHY_AQUANTIA=y CONFIG_E1000=y CONFIG_MII=y CONFIG_PCI=y diff --git a/configs/ls1088ardb_sdcard_qspi_defconfig b/configs/ls1088ardb_sdcard_qspi_defconfig index 4b6695d1b3..886255e3da 100644 --- a/configs/ls1088ardb_sdcard_qspi_defconfig +++ b/configs/ls1088ardb_sdcard_qspi_defconfig @@ -45,6 +45,7 @@ CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_SPANSION=y # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +CONFIG_PHY_AQUANTIA=y CONFIG_E1000=y CONFIG_MII=y CONFIG_PCI=y diff --git a/configs/ls2080ardb_SECURE_BOOT_defconfig b/configs/ls2080ardb_SECURE_BOOT_defconfig index bf4ab46063..8f18d93667 100644 --- a/configs/ls2080ardb_SECURE_BOOT_defconfig +++ b/configs/ls2080ardb_SECURE_BOOT_defconfig @@ -39,7 +39,7 @@ CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_CFI=y CONFIG_DM_SPI_FLASH=y CONFIG_PHYLIB=y -CONFIG_PHY_GIGE=y +CONFIG_PHY_AQUANTIA=y CONFIG_E1000=y CONFIG_MII=y CONFIG_PCI=y diff --git a/configs/ls2080ardb_defconfig b/configs/ls2080ardb_defconfig index a604bc1cb9..1c13bbabbc 100644 --- a/configs/ls2080ardb_defconfig +++ b/configs/ls2080ardb_defconfig @@ -40,7 +40,7 @@ CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_CFI=y CONFIG_DM_SPI_FLASH=y CONFIG_PHYLIB=y -CONFIG_PHY_GIGE=y +CONFIG_PHY_AQUANTIA=y CONFIG_E1000=y CONFIG_MII=y CONFIG_PCI=y diff --git a/configs/ls2080ardb_nand_defconfig b/configs/ls2080ardb_nand_defconfig index 135cd80253..061d5cdc2b 100644 --- a/configs/ls2080ardb_nand_defconfig +++ b/configs/ls2080ardb_nand_defconfig @@ -47,7 +47,7 @@ CONFIG_FLASH_CFI_DRIVER=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_CFI=y CONFIG_PHYLIB=y -CONFIG_PHY_GIGE=y +CONFIG_PHY_AQUANTIA=y CONFIG_E1000=y CONFIG_MII=y CONFIG_PCI=y diff --git a/configs/ls2081ardb_defconfig b/configs/ls2081ardb_defconfig index a2f657b55b..323f63b907 100644 --- a/configs/ls2081ardb_defconfig +++ b/configs/ls2081ardb_defconfig @@ -34,7 +34,7 @@ CONFIG_FSL_CAAM=y CONFIG_FSL_ESDHC=y CONFIG_DM_SPI_FLASH=y CONFIG_PHYLIB=y -CONFIG_PHY_GIGE=y +CONFIG_PHY_AQUANTIA=y CONFIG_E1000=y CONFIG_MII=y CONFIG_PCI=y diff --git a/configs/ls2088ardb_qspi_SECURE_BOOT_defconfig b/configs/ls2088ardb_qspi_SECURE_BOOT_defconfig index 6ae87248f5..6d3708fec9 100644 --- a/configs/ls2088ardb_qspi_SECURE_BOOT_defconfig +++ b/configs/ls2088ardb_qspi_SECURE_BOOT_defconfig @@ -32,7 +32,7 @@ CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_SPANSION=y # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set CONFIG_PHYLIB=y -CONFIG_PHY_GIGE=y +CONFIG_PHY_AQUANTIA=y CONFIG_E1000=y CONFIG_MII=y CONFIG_PCI=y diff --git a/configs/ls2088ardb_qspi_defconfig b/configs/ls2088ardb_qspi_defconfig index ba1f1687b0..44b7d2a40e 100644 --- a/configs/ls2088ardb_qspi_defconfig +++ b/configs/ls2088ardb_qspi_defconfig @@ -36,7 +36,7 @@ CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_SPANSION=y # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set CONFIG_PHYLIB=y -CONFIG_PHY_GIGE=y +CONFIG_PHY_AQUANTIA=y CONFIG_E1000=y CONFIG_MII=y CONFIG_PCI=y diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig index f5821dfed9..28f3ee35f1 100644 --- a/drivers/net/phy/Kconfig +++ b/drivers/net/phy/Kconfig @@ -66,6 +66,8 @@ config PHYLIB_10G config PHY_AQUANTIA bool "Aquantia Ethernet PHYs support" + select PHY_GIGE + select PHYLIB_10G config PHY_ATHEROS bool "Atheros Ethernet PHYs support" diff --git a/drivers/net/phy/aquantia.c b/drivers/net/phy/aquantia.c index fe81217432..a44fba0f1a 100644 --- a/drivers/net/phy/aquantia.c +++ b/drivers/net/phy/aquantia.c @@ -9,10 +9,6 @@ #include #include -#ifndef CONFIG_PHYLIB_10G -#error The Aquantia PHY needs 10G support -#endif - #define AQUNTIA_10G_CTL 0x20 #define AQUNTIA_VENDOR_P1 0xc400 diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h index e30779f9a9..673d1112e2 100644 --- a/include/configs/T102xRDB.h +++ b/include/configs/T102xRDB.h @@ -709,9 +709,7 @@ unsigned long get_board_ddr_clk(void); #ifdef CONFIG_SYS_DPAA_FMAN #define CONFIG_FMAN_ENET -#define CONFIG_PHYLIB_10G #define CONFIG_PHY_REALTEK -#define CONFIG_PHY_AQUANTIA #if defined(CONFIG_TARGET_T1024RDB) #define RGMII_PHY1_ADDR 0x2 #define RGMII_PHY2_ADDR 0x6 diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h index 286db0204d..833a0608bf 100644 --- a/include/configs/T208xQDS.h +++ b/include/configs/T208xQDS.h @@ -630,7 +630,6 @@ unsigned long get_board_ddr_clk(void); #ifdef CONFIG_SYS_DPAA_FMAN #define CONFIG_FMAN_ENET -#define CONFIG_PHYLIB_10G #define CONFIG_PHY_VITESSE #define CONFIG_PHY_REALTEK #define CONFIG_PHY_TERANETICS diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h index d076d6ebe4..ddb60b3d6d 100644 --- a/include/configs/T208xRDB.h +++ b/include/configs/T208xRDB.h @@ -582,8 +582,6 @@ unsigned long get_board_ddr_clk(void); #ifdef CONFIG_SYS_DPAA_FMAN #define CONFIG_FMAN_ENET -#define CONFIG_PHYLIB_10G -#define CONFIG_PHY_AQUANTIA #define CONFIG_PHY_CORTINA #define CONFIG_PHY_REALTEK #define CONFIG_CORTINA_FW_LENGTH 0x40000 diff --git a/include/configs/ls1043ardb.h b/include/configs/ls1043ardb.h index ffd92dbb43..54e6eef417 100644 --- a/include/configs/ls1043ardb.h +++ b/include/configs/ls1043ardb.h @@ -251,8 +251,6 @@ #ifdef CONFIG_SYS_DPAA_FMAN #define CONFIG_FMAN_ENET -#define CONFIG_PHYLIB_10G -#define CONFIG_PHY_AQUANTIA #define RGMII_PHY1_ADDR 0x1 #define RGMII_PHY2_ADDR 0x2 diff --git a/include/configs/ls1046ardb.h b/include/configs/ls1046ardb.h index ffca410b1a..dcb5854046 100644 --- a/include/configs/ls1046ardb.h +++ b/include/configs/ls1046ardb.h @@ -180,8 +180,6 @@ #ifdef CONFIG_SYS_DPAA_FMAN #define CONFIG_FMAN_ENET -#define CONFIG_PHY_AQUANTIA -#define CONFIG_PHYLIB_10G #define RGMII_PHY1_ADDR 0x1 #define RGMII_PHY2_ADDR 0x2 diff --git a/include/configs/ls1088ardb.h b/include/configs/ls1088ardb.h index 421d44716e..14731c5337 100644 --- a/include/configs/ls1088ardb.h +++ b/include/configs/ls1088ardb.h @@ -420,12 +420,9 @@ /* MAC/PHY configuration */ #ifdef CONFIG_FSL_MC_ENET -#define CONFIG_PHYLIB_10G -#define CONFIG_PHY_GIGE #define CONFIG_PHYLIB #define CONFIG_PHY_VITESSE -#define CONFIG_PHY_AQUANTIA #define AQ_PHY_ADDR1 0x00 #define AQR105_IRQ_MASK 0x00000004 diff --git a/include/configs/ls2080ardb.h b/include/configs/ls2080ardb.h index 6641a1bed9..295b824aa0 100644 --- a/include/configs/ls2080ardb.h +++ b/include/configs/ls2080ardb.h @@ -452,8 +452,6 @@ unsigned long get_board_sys_clk(void); /* MAC/PHY configuration */ #ifdef CONFIG_FSL_MC_ENET -#define CONFIG_PHYLIB_10G -#define CONFIG_PHY_AQUANTIA #define CONFIG_PHY_CORTINA #define CONFIG_SYS_CORTINA_FW_IN_NOR #ifdef CONFIG_QSPI_BOOT @@ -474,7 +472,6 @@ unsigned long get_board_sys_clk(void); #define AQR405_IRQ_MASK 0x36 #define CONFIG_ETHPRIME "DPMAC1@xgmii" -#define CONFIG_PHY_AQUANTIA #endif #include From 4506423ad23749a28ae48720bc64ad40caf089b2 Mon Sep 17 00:00:00 2001 From: Jeremy Gebben Date: Tue, 18 Sep 2018 15:49:36 -0600 Subject: [PATCH 04/13] net: phy: aquantia: add firmware loading support Aquantia phys have firmware that can be loaded automatically from storage directly attached to the phy or via MDIO commands. Add support for loading firmware from either a file or a raw location on an MMC device. Signed-off-by: Jeremy Gebben Acked-by: Joe Hershberger --- drivers/net/phy/Kconfig | 24 +++- drivers/net/phy/aquantia.c | 234 ++++++++++++++++++++++++++++++++++++- 2 files changed, 256 insertions(+), 2 deletions(-) diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig index 28f3ee35f1..3dc0822d9c 100644 --- a/drivers/net/phy/Kconfig +++ b/drivers/net/phy/Kconfig @@ -64,11 +64,33 @@ endif # MV88E61XX_SWITCH config PHYLIB_10G bool "Generic 10G PHY support" -config PHY_AQUANTIA +menuconfig PHY_AQUANTIA bool "Aquantia Ethernet PHYs support" select PHY_GIGE select PHYLIB_10G +config PHY_AQUANTIA_UPLOAD_FW + bool "Aquantia firmware loading support" + default n + depends on PHY_AQUANTIA + help + Aquantia PHYs use firmware which can be either loaded automatically + from storage directly attached to the phy or loaded by the boot loader + via MDIO commands. The firmware is loaded from a file, specified by + the PHY_AQUANTIA_FW_PART and PHY_AQUANTIA_FW_NAME options. + +config PHY_AQUANTIA_FW_PART + string "Aquantia firmware partition" + depends on PHY_AQUANTIA_UPLOAD_FW + help + Partition containing the firmware file. + +config PHY_AQUANTIA_FW_NAME + string "Aquantia firmware filename" + depends on PHY_AQUANTIA_UPLOAD_FW + help + Firmware filename. + config PHY_ATHEROS bool "Atheros Ethernet PHYs support" diff --git a/drivers/net/phy/aquantia.c b/drivers/net/phy/aquantia.c index a44fba0f1a..cbd70120d1 100644 --- a/drivers/net/phy/aquantia.c +++ b/drivers/net/phy/aquantia.c @@ -8,6 +8,10 @@ #include #include #include +#include +#include +#include +#include #define AQUNTIA_10G_CTL 0x20 #define AQUNTIA_VENDOR_P1 0xc400 @@ -15,9 +19,237 @@ #define AQUNTIA_SPEED_LSB_MASK 0x2000 #define AQUNTIA_SPEED_MSB_MASK 0x40 +/* registers in MDIO_MMD_VEND1 region */ +#define GLOBAL_FIRMWARE_ID 0x20 +#define GLOBAL_FAULT 0xc850 +#define GLOBAL_RSTATUS_1 0xc885 + +#define GLOBAL_STANDARD_CONTROL 0x0 +#define SOFT_RESET BIT(15) +#define LOW_POWER BIT(11) + +#define MAILBOX_CONTROL 0x0200 +#define MAILBOX_EXECUTE BIT(15) +#define MAILBOX_WRITE BIT(14) +#define MAILBOX_RESET_CRC BIT(12) +#define MAILBOX_BUSY BIT(8) + +#define MAILBOX_CRC 0x0201 + +#define MAILBOX_ADDR_MSW 0x0202 +#define MAILBOX_ADDR_LSW 0x0203 + +#define MAILBOX_DATA_MSW 0x0204 +#define MAILBOX_DATA_LSW 0x0205 + +#define UP_CONTROL 0xc001 +#define UP_RESET BIT(15) +#define UP_RUN_STALL_OVERRIDE BIT(6) +#define UP_RUN_STALL BIT(0) + +/* addresses of memory segments in the phy */ +#define DRAM_BASE_ADDR 0x3FFE0000 +#define IRAM_BASE_ADDR 0x40000000 + +/* firmware image format constants */ +#define VERSION_STRING_SIZE 0x40 +#define VERSION_STRING_OFFSET 0x0200 +#define HEADER_OFFSET 0x300 + +#pragma pack(1) +struct fw_header { + u8 padding[4]; + u8 iram_offset[3]; + u8 iram_size[3]; + u8 dram_offset[3]; + u8 dram_size[3]; +}; + +#pragma pack() + +#if defined(CONFIG_PHY_AQUANTIA_UPLOAD_FW) +static int aquantia_read_fw(u8 **fw_addr, size_t *fw_length) +{ + loff_t length, read; + int ret; + void *addr = NULL; + + *fw_addr = NULL; + *fw_length = 0; + debug("Loading Acquantia microcode from %s %s\n", + CONFIG_PHY_AQUANTIA_FW_PART, CONFIG_PHY_AQUANTIA_FW_NAME); + ret = fs_set_blk_dev("mmc", CONFIG_PHY_AQUANTIA_FW_PART, FS_TYPE_ANY); + if (ret < 0) + goto cleanup; + + ret = fs_size(CONFIG_PHY_AQUANTIA_FW_NAME, &length); + if (ret < 0) + goto cleanup; + + addr = malloc(length); + if (!addr) { + ret = -ENOMEM; + goto cleanup; + } + + ret = fs_set_blk_dev("mmc", CONFIG_PHY_AQUANTIA_FW_PART, FS_TYPE_ANY); + if (ret < 0) + goto cleanup; + + ret = fs_read(CONFIG_PHY_AQUANTIA_FW_NAME, (ulong)addr, 0, length, + &read); + if (ret < 0) + goto cleanup; + + *fw_addr = addr; + *fw_length = length; + debug("Found Acquantia microcode.\n"); + +cleanup: + if (ret < 0) { + printf("loading firmware file %s %s failed with error %d\n", + CONFIG_PHY_AQUANTIA_FW_PART, + CONFIG_PHY_AQUANTIA_FW_NAME, ret); + free(addr); + } + return ret; +} + +/* load data into the phy's memory */ +static int aquantia_load_memory(struct phy_device *phydev, u32 addr, + const u8 *data, size_t len) +{ + size_t pos; + u16 crc = 0, up_crc; + + phy_write(phydev, MDIO_MMD_VEND1, MAILBOX_CONTROL, MAILBOX_RESET_CRC); + phy_write(phydev, MDIO_MMD_VEND1, MAILBOX_ADDR_MSW, addr >> 16); + phy_write(phydev, MDIO_MMD_VEND1, MAILBOX_ADDR_LSW, addr & 0xfffc); + + for (pos = 0; pos < len; pos += min(sizeof(u32), len - pos)) { + u32 word = 0; + + memcpy(&word, &data[pos], min(sizeof(u32), len - pos)); + + phy_write(phydev, MDIO_MMD_VEND1, MAILBOX_DATA_MSW, + (word >> 16)); + phy_write(phydev, MDIO_MMD_VEND1, MAILBOX_DATA_LSW, + word & 0xffff); + + phy_write(phydev, MDIO_MMD_VEND1, MAILBOX_CONTROL, + MAILBOX_EXECUTE | MAILBOX_WRITE); + + /* keep a big endian CRC to match the phy processor */ + word = cpu_to_be32(word); + crc = crc16_ccitt(crc, (u8 *)&word, sizeof(word)); + } + + up_crc = phy_read(phydev, MDIO_MMD_VEND1, MAILBOX_CRC); + if (crc != up_crc) { + printf("%s crc mismatch: calculated 0x%04hx phy 0x%04hx\n", + phydev->dev->name, crc, up_crc); + return -EINVAL; + } + return 0; +} + +static u32 unpack_u24(const u8 *data) +{ + return (data[2] << 16) + (data[1] << 8) + data[0]; +} + +static int aquantia_upload_firmware(struct phy_device *phydev) +{ + int ret; + u8 *addr = NULL; + size_t fw_length = 0; + u16 calculated_crc, read_crc; + char version[VERSION_STRING_SIZE]; + u32 primary_offset, iram_offset, iram_size, dram_offset, dram_size; + const struct fw_header *header; + + ret = aquantia_read_fw(&addr, &fw_length); + if (ret != 0) + return ret; + + read_crc = (addr[fw_length - 2] << 8) | addr[fw_length - 1]; + calculated_crc = crc16_ccitt(0, addr, fw_length - 2); + if (read_crc != calculated_crc) { + printf("%s bad firmware crc: file 0x%04x calculated 0x%04x\n", + phydev->dev->name, read_crc, calculated_crc); + ret = -EINVAL; + goto done; + } + + /* Find the DRAM and IRAM sections within the firmware file. */ + primary_offset = ((addr[9] & 0xf) << 8 | addr[8]) << 12; + + header = (struct fw_header *)&addr[primary_offset + HEADER_OFFSET]; + + iram_offset = primary_offset + unpack_u24(header->iram_offset); + iram_size = unpack_u24(header->iram_size); + + dram_offset = primary_offset + unpack_u24(header->dram_offset); + dram_size = unpack_u24(header->dram_size); + + debug("primary %d iram offset=%d size=%d dram offset=%d size=%d\n", + primary_offset, iram_offset, iram_size, dram_offset, dram_size); + + strlcpy(version, (char *)&addr[dram_offset + VERSION_STRING_OFFSET], + VERSION_STRING_SIZE); + printf("%s loading firmare version '%s'\n", phydev->dev->name, version); + + /* stall the microcprocessor */ + phy_write(phydev, MDIO_MMD_VEND1, UP_CONTROL, + UP_RUN_STALL | UP_RUN_STALL_OVERRIDE); + + debug("loading dram 0x%08x from offset=%d size=%d\n", + DRAM_BASE_ADDR, dram_offset, dram_size); + ret = aquantia_load_memory(phydev, DRAM_BASE_ADDR, &addr[dram_offset], + dram_size); + if (ret != 0) + goto done; + + debug("loading iram 0x%08x from offset=%d size=%d\n", + IRAM_BASE_ADDR, iram_offset, iram_size); + ret = aquantia_load_memory(phydev, IRAM_BASE_ADDR, &addr[iram_offset], + iram_size); + if (ret != 0) + goto done; + + /* make sure soft reset and low power mode are clear */ + phy_write(phydev, MDIO_MMD_VEND1, GLOBAL_STANDARD_CONTROL, 0); + + /* Release the microprocessor. UP_RESET must be held for 100 usec. */ + phy_write(phydev, MDIO_MMD_VEND1, UP_CONTROL, + UP_RUN_STALL | UP_RUN_STALL_OVERRIDE | UP_RESET); + + udelay(100); + + phy_write(phydev, MDIO_MMD_VEND1, UP_CONTROL, UP_RUN_STALL_OVERRIDE); + + printf("%s firmare loading done.\n", phydev->dev->name); +done: + free(addr); + return ret; +} +#else +static int aquantia_upload_firmware(struct phy_device *phydev) +{ + return 0; +} +#endif + int aquantia_config(struct phy_device *phydev) { - u32 val = phy_read(phydev, MDIO_MMD_PMAPMD, MII_BMCR); + u32 val; + int ret; + + ret = aquantia_upload_firmware(phydev); + if (ret != 0) + return ret; + + val = phy_read(phydev, MDIO_MMD_PMAPMD, MII_BMCR); if (phydev->interface == PHY_INTERFACE_MODE_SGMII) { /* 1000BASE-T mode */ From 30a2c8cca80ed71384e5c1ebc4e52695c3db8fff Mon Sep 17 00:00:00 2001 From: Jeremy Gebben Date: Tue, 18 Sep 2018 15:49:37 -0600 Subject: [PATCH 05/13] net: phy: aquantia: autodetect if firmware needs to be loaded If the phy reports a valid firmware version and doesn't indicate a fault, skip loading the firmware. This allows the same image to be used on boards that have firmware storage and those that do not. Signed-off-by: Jeremy Gebben Acked-by: Joe Hershberger --- drivers/net/phy/aquantia.c | 28 ++++++++++++++++++++++------ 1 file changed, 22 insertions(+), 6 deletions(-) diff --git a/drivers/net/phy/aquantia.c b/drivers/net/phy/aquantia.c index cbd70120d1..37749e0185 100644 --- a/drivers/net/phy/aquantia.c +++ b/drivers/net/phy/aquantia.c @@ -236,18 +236,34 @@ done: #else static int aquantia_upload_firmware(struct phy_device *phydev) { - return 0; + printf("ERROR %s firmware loading disabled.\n", phydev->dev->name); + return -1; } #endif int aquantia_config(struct phy_device *phydev) { - u32 val; - int ret; + u32 val, id, rstatus, fault; - ret = aquantia_upload_firmware(phydev); - if (ret != 0) - return ret; + id = phy_read(phydev, MDIO_MMD_VEND1, GLOBAL_FIRMWARE_ID); + rstatus = phy_read(phydev, MDIO_MMD_VEND1, GLOBAL_RSTATUS_1); + fault = phy_read(phydev, MDIO_MMD_VEND1, GLOBAL_FAULT); + + if (id != 0) + printf("%s running firmware version %X.%X.%X\n", + phydev->dev->name, (id >> 8), id & 0xff, + (rstatus >> 4) & 0xf); + + if (fault != 0) + printf("%s fault 0x%04x detected\n", phydev->dev->name, fault); + + if (id == 0 || fault != 0) { + int ret; + + ret = aquantia_upload_firmware(phydev); + if (ret != 0) + return ret; + } val = phy_read(phydev, MDIO_MMD_PMAPMD, MII_BMCR); From 9b8b91888493d25873b835d262b89f1c4efa0df7 Mon Sep 17 00:00:00 2001 From: Martin Fuzzey Date: Thu, 4 Oct 2018 19:59:18 +0200 Subject: [PATCH 06/13] net: dm: fec: Fix time unit error in phy-reset-duration The DT binding says that phy-reset-duration is in ms, but the driver currently uses udelay(). Switch to mdelay() to fix this. Signed-off-by: Martin Fuzzey Reviewed-by: Michael Trimarchi Acked-by: Joe Hershberger --- drivers/net/fec_mxc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c index dac07b6e34..a1295fcdf6 100644 --- a/drivers/net/fec_mxc.c +++ b/drivers/net/fec_mxc.c @@ -1254,7 +1254,7 @@ static void fec_gpio_reset(struct fec_priv *priv) debug("fec_gpio_reset: fec_gpio_reset(dev)\n"); if (dm_gpio_is_valid(&priv->phy_reset_gpio)) { dm_gpio_set_value(&priv->phy_reset_gpio, 1); - udelay(priv->reset_delay); + mdelay(priv->reset_delay); dm_gpio_set_value(&priv->phy_reset_gpio, 0); } } From 331fcabe4f9b4c7ec58d070da039f875673c9c9d Mon Sep 17 00:00:00 2001 From: Martin Fuzzey Date: Thu, 4 Oct 2018 19:59:19 +0200 Subject: [PATCH 07/13] net: dm: fec: Fix phy-reset-duration clamping and defaults The DT binding says: - phy-reset-duration : Reset duration in milliseconds. Should present only if property "phy-reset-gpios" is available. Missing the property will have the duration be 1 millisecond. Numbers greater than 1000 are invalid and 1 millisecond will be used instead. However the current code: - clamps values greater than 1000ms to 1000ms rather than 1. - does not initialize the delay if the property does not exist (else clause mismatch) - returns an error if phy-reset-gpios is not defined Fix all this and simplify by using dev_read_u32_default() Signed-off-by: Martin Fuzzey Acked-by: Joe Hershberger --- drivers/net/fec_mxc.c | 19 ++++++++----------- 1 file changed, 8 insertions(+), 11 deletions(-) diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c index a1295fcdf6..da970ef864 100644 --- a/drivers/net/fec_mxc.c +++ b/drivers/net/fec_mxc.c @@ -1352,22 +1352,19 @@ static int fecmxc_ofdata_to_platdata(struct udevice *dev) #ifdef CONFIG_DM_GPIO ret = gpio_request_by_name(dev, "phy-reset-gpios", 0, - &priv->phy_reset_gpio, GPIOD_IS_OUT); - if (ret == 0) { - ret = dev_read_u32_array(dev, "phy-reset-duration", - &priv->reset_delay, 1); - } else if (ret == -ENOENT) { - priv->reset_delay = 1000; - ret = 0; - } + &priv->phy_reset_gpio, GPIOD_IS_OUT); + if (ret < 0) + return 0; /* property is optional, don't return error! */ + priv->reset_delay = dev_read_u32_default(dev, "phy-reset-duration", 1); if (priv->reset_delay > 1000) { - printf("FEX MXC: gpio reset timeout should be less the 1000\n"); - priv->reset_delay = 1000; + printf("FEC MXC: phy reset duration should be <= 1000ms\n"); + /* property value wrong, use default value */ + priv->reset_delay = 1; } #endif - return ret; + return 0; } static const struct udevice_id fecmxc_ids[] = { From ad8c43cbcafbbb21efc9e26bda7a6b1e37428adc Mon Sep 17 00:00:00 2001 From: Martin Fuzzey Date: Thu, 4 Oct 2018 19:59:20 +0200 Subject: [PATCH 08/13] net: dm: fec: Support the phy-supply binding Configure the phy regulator if defined by the "phy-supply" DT phandle. Signed-off-by: Martin Fuzzey Acked-by: Joe Hershberger --- drivers/net/fec_mxc.c | 20 ++++++++++++++++++++ drivers/net/fec_mxc.h | 3 +++ 2 files changed, 23 insertions(+) diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c index da970ef864..d3a926dc73 100644 --- a/drivers/net/fec_mxc.c +++ b/drivers/net/fec_mxc.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include @@ -1272,6 +1273,16 @@ static int fecmxc_probe(struct udevice *dev) if (ret) return ret; +#ifdef CONFIG_DM_REGULATOR + if (priv->phy_supply) { + ret = regulator_autoset(priv->phy_supply); + if (ret) { + printf("%s: Error enabling phy supply\n", dev->name); + return ret; + } + } +#endif + #ifdef CONFIG_DM_GPIO fec_gpio_reset(priv); #endif @@ -1327,6 +1338,11 @@ static int fecmxc_remove(struct udevice *dev) mdio_unregister(priv->bus); mdio_free(priv->bus); +#ifdef CONFIG_DM_REGULATOR + if (priv->phy_supply) + regulator_set_enable(priv->phy_supply, false); +#endif + return 0; } @@ -1350,6 +1366,10 @@ static int fecmxc_ofdata_to_platdata(struct udevice *dev) return -EINVAL; } +#ifdef CONFIG_DM_REGULATOR + device_get_supply_regulator(dev, "phy-supply", &priv->phy_supply); +#endif + #ifdef CONFIG_DM_GPIO ret = gpio_request_by_name(dev, "phy-reset-gpios", 0, &priv->phy_reset_gpio, GPIOD_IS_OUT); diff --git a/drivers/net/fec_mxc.h b/drivers/net/fec_mxc.h index fd89443205..848cd7c227 100644 --- a/drivers/net/fec_mxc.h +++ b/drivers/net/fec_mxc.h @@ -250,6 +250,9 @@ struct fec_priv { int phy_id; int (*mii_postcall)(int); #endif +#ifdef CONFIG_DM_REGULATOR + struct udevice *phy_supply; +#endif #ifdef CONFIG_DM_GPIO struct gpio_desc phy_reset_gpio; uint32_t reset_delay; From 0126c641e80f7285c891fb98b832d8258d1862ca Mon Sep 17 00:00:00 2001 From: Martin Fuzzey Date: Thu, 4 Oct 2018 19:59:21 +0200 Subject: [PATCH 09/13] net: dm: fec: Obtain the transceiver type from the DT The DT property "phy-mode" already provides the transceiver type. Use it so that we do not have to also set CONFIG_FEC_XCV_TYPE Signed-off-by: Martin Fuzzey Acked-by: Joe Hershberger --- drivers/net/fec_mxc.c | 21 ++++++++++++++++++++- 1 file changed, 20 insertions(+), 1 deletion(-) diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c index d3a926dc73..03df92c6c1 100644 --- a/drivers/net/fec_mxc.c +++ b/drivers/net/fec_mxc.c @@ -1312,8 +1312,27 @@ static int fecmxc_probe(struct udevice *dev) } priv->bus = bus; - priv->xcv_type = CONFIG_FEC_XCV_TYPE; priv->interface = pdata->phy_interface; + switch (priv->interface) { + case PHY_INTERFACE_MODE_MII: + priv->xcv_type = MII100; + break; + case PHY_INTERFACE_MODE_RMII: + priv->xcv_type = RMII; + break; + case PHY_INTERFACE_MODE_RGMII: + case PHY_INTERFACE_MODE_RGMII_ID: + case PHY_INTERFACE_MODE_RGMII_RXID: + case PHY_INTERFACE_MODE_RGMII_TXID: + priv->xcv_type = RGMII; + break; + default: + priv->xcv_type = CONFIG_FEC_XCV_TYPE; + printf("Unsupported interface type %d defaulting to %d\n", + priv->interface, priv->xcv_type); + break; + } + ret = fec_phy_init(priv, dev); if (ret) goto err_phy; From 1ddcf5edbbe48347ecdfdeb904b62ba5f8345757 Mon Sep 17 00:00:00 2001 From: Priyanka Jain Date: Thu, 11 Oct 2018 04:47:05 +0000 Subject: [PATCH 10/13] net/phy: Add phy-id for IN112525_S03 Signed-off-by: Priyanka Jain Acked-by: Joe Hershberger --- include/phy.h | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/include/phy.h b/include/phy.h index d6a83150cf..b86fdfb2ce 100644 --- a/include/phy.h +++ b/include/phy.h @@ -275,8 +275,9 @@ static inline bool phy_interface_is_sgmii(struct phy_device *phydev) } /* PHY UIDs for various PHYs that are referenced in external code */ -#define PHY_UID_CS4340 0x13e51002 -#define PHY_UID_CS4223 0x03e57003 -#define PHY_UID_TN2020 0x00a19410 +#define PHY_UID_CS4340 0x13e51002 +#define PHY_UID_CS4223 0x03e57003 +#define PHY_UID_TN2020 0x00a19410 +#define PHY_UID_IN112525_S03 0x02107440 #endif From fa14027d5c54e6715d2df9526bc951df7ffc78e7 Mon Sep 17 00:00:00 2001 From: Baruch Siach Date: Mon, 15 Oct 2018 13:16:47 +0300 Subject: [PATCH 11/13] net: mvpp2: fix polarity of PHY reset signal The dm_gpio_set_value() call sets the logical level of the GPIO signal. That is, it takes the GPIO_ACTIVE_{LOW,HIGH} property into account. The driver needs to assert the reset, and then deassert it. Not the other way around. Cc: Stefan Chulski Signed-off-by: Baruch Siach Acked-by: Joe Hershberger Reviewed-by: Stefan Roese --- drivers/net/mvpp2.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/net/mvpp2.c b/drivers/net/mvpp2.c index f34245ba77..48728d168a 100644 --- a/drivers/net/mvpp2.c +++ b/drivers/net/mvpp2.c @@ -4792,9 +4792,9 @@ static int phy_info_parse(struct udevice *dev, struct mvpp2_port *port) static void mvpp2_gpio_init(struct mvpp2_port *port) { if (dm_gpio_is_valid(&port->phy_reset_gpio)) { - dm_gpio_set_value(&port->phy_reset_gpio, 0); - udelay(1000); dm_gpio_set_value(&port->phy_reset_gpio, 1); + udelay(1000); + dm_gpio_set_value(&port->phy_reset_gpio, 0); } if (dm_gpio_is_valid(&port->phy_tx_disable_gpio)) From 18593fa80b64801768be5657a3b41ef4533a9fc9 Mon Sep 17 00:00:00 2001 From: Baruch Siach Date: Mon, 15 Oct 2018 13:16:48 +0300 Subject: [PATCH 12/13] net: mvpp2: increase PHY reset pulse The default Linux PHY reset delay is 10ms. This is also the requirement for Marvell 88E151x PHYs, which are likely to be used with this Ethernet MAC. Cc: Stefan Chulski Signed-off-by: Baruch Siach Acked-by: Joe Hershberger Reviewed-by: Stefan Roese --- drivers/net/mvpp2.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/mvpp2.c b/drivers/net/mvpp2.c index 48728d168a..9b3ab25c19 100644 --- a/drivers/net/mvpp2.c +++ b/drivers/net/mvpp2.c @@ -4793,7 +4793,7 @@ static void mvpp2_gpio_init(struct mvpp2_port *port) { if (dm_gpio_is_valid(&port->phy_reset_gpio)) { dm_gpio_set_value(&port->phy_reset_gpio, 1); - udelay(1000); + mdelay(10); dm_gpio_set_value(&port->phy_reset_gpio, 0); } From 58ec4d3342f4ffd195f3f3f2e570f772500c6ecb Mon Sep 17 00:00:00 2001 From: Anatolij Gustschin Date: Thu, 18 Oct 2018 16:15:11 +0200 Subject: [PATCH 13/13] net: fec_mxc: add support for i.MX8X Add compatible property and enable the FEC ipg clock when probing on i.MX8X. Add specific function for reading FEC clock rate via clock driver when configuring MII speed register. Allow FEC_MXC selection for i.MX8. Signed-off-by: Anatolij Gustschin Cc: Joe Hershberger Acked-by: Joe Hershberger --- drivers/net/Kconfig | 2 +- drivers/net/fec_mxc.c | 59 ++++++++++++++++++++++++++++++++++++++++--- drivers/net/fec_mxc.h | 4 +++ 3 files changed, 61 insertions(+), 4 deletions(-) diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index f1f0e2d94e..39687431fb 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -176,7 +176,7 @@ config FEC_MXC_MDIO_BASE config FEC_MXC bool "FEC Ethernet controller" - depends on MX5 || MX6 || MX7 + depends on MX5 || MX6 || MX7 || IMX8 help This driver supports the 10/100 Fast Ethernet controller for NXP i.MX processors. diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c index 03df92c6c1..99c5c649a0 100644 --- a/drivers/net/fec_mxc.c +++ b/drivers/net/fec_mxc.c @@ -123,6 +123,32 @@ static int fec_mdio_read(struct ethernet_regs *eth, uint8_t phyaddr, return val; } +static int fec_get_clk_rate(void *udev, int idx) +{ +#if IS_ENABLED(CONFIG_IMX8) + struct fec_priv *fec; + struct udevice *dev; + int ret; + + dev = udev; + if (!dev) { + ret = uclass_get_device(UCLASS_ETH, idx, &dev); + if (ret < 0) { + debug("Can't get FEC udev: %d\n", ret); + return ret; + } + } + + fec = dev_get_priv(dev); + if (fec) + return fec->clk_rate; + + return -EINVAL; +#else + return imx_get_fecclk(); +#endif +} + static void fec_mii_setspeed(struct ethernet_regs *eth) { /* @@ -140,9 +166,20 @@ static void fec_mii_setspeed(struct ethernet_regs *eth) * Given that ceil(clkrate / 5000000) <= 64, the calculation for * holdtime cannot result in a value greater than 3. */ - u32 pclk = imx_get_fecclk(); - u32 speed = DIV_ROUND_UP(pclk, 5000000); - u32 hold = DIV_ROUND_UP(pclk, 100000000) - 1; + u32 pclk; + u32 speed; + u32 hold; + int ret; + + ret = fec_get_clk_rate(NULL, 0); + if (ret < 0) { + printf("Can't find FEC0 clk rate: %d\n", ret); + return; + } + pclk = ret; + speed = DIV_ROUND_UP(pclk, 5000000); + hold = DIV_ROUND_UP(pclk, 100000000) - 1; + #ifdef FEC_QUIRK_ENET_MAC speed--; #endif @@ -1269,6 +1306,21 @@ static int fecmxc_probe(struct udevice *dev) uint32_t start; int ret; + if (IS_ENABLED(CONFIG_IMX8)) { + ret = clk_get_by_name(dev, "ipg", &priv->ipg_clk); + if (ret < 0) { + debug("Can't get FEC ipg clk: %d\n", ret); + return ret; + } + ret = clk_enable(&priv->ipg_clk); + if (ret < 0) { + debug("Can't enable FEC ipg clk: %d\n", ret); + return ret; + } + + priv->clk_rate = clk_get_rate(&priv->ipg_clk); + } + ret = fec_alloc_descs(priv); if (ret) return ret; @@ -1412,6 +1464,7 @@ static const struct udevice_id fecmxc_ids[] = { { .compatible = "fsl,imx6sx-fec" }, { .compatible = "fsl,imx6ul-fec" }, { .compatible = "fsl,imx53-fec" }, + { .compatible = "fsl,imx7d-fec" }, { } }; diff --git a/drivers/net/fec_mxc.h b/drivers/net/fec_mxc.h index 848cd7c227..e9a661f0a1 100644 --- a/drivers/net/fec_mxc.h +++ b/drivers/net/fec_mxc.h @@ -16,6 +16,8 @@ #ifndef __FEC_MXC_H #define __FEC_MXC_H +#include + /* Layout description of the FEC */ struct ethernet_regs { /* [10:2]addr = 00 */ @@ -260,6 +262,8 @@ struct fec_priv { #ifdef CONFIG_DM_ETH u32 interface; #endif + struct clk ipg_clk; + u32 clk_rate; }; void imx_get_mac_from_fuse(int dev_id, unsigned char *mac);