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board: apalis_imx6: Add KSZ9131 phy skew settings

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This patch adds skew register settings for KSZ9131. It checks first
which phy is on the board and then applies the correct skew settings.

Skew settings calculation for the KSZ9131:
The i.MX6 SoC has an output skew tolerance of -100ps to 900ps. All
PCB traces where routed exactly the same length so we can calculate
the skew settings without taking the length into consideration. The
traces are all length matched.

RXC skew (PHY to MAC):
- We use the 2ns DLL controlled delay on the PHY
- We do not use the skew registers

This results in the following values:

		RXC
PHY fixed Delay	2000ps
PHY Added Delay	0ps
T_setup_R min	2.00ns
T_setup_R typ	2.00ns
T_setup_R max	2.00ns
T_hold_R min	1.60ns
T_hold_R typ	2.00ns
T_hold_R max	2.40ns

That means we are well within RGMII specs.

TXC skew (MAC to PHY):
- We use the 2ns DLL controlled delay on the PHY
- We then subtract ~0.6ns with TXD[0:3] and TXC clock pad skew
  register in a resulting ~1.4ns delay.

This results in the following values under consideration of the
tolerances:

		TXC min	TXC typ	TXC max
MAC min		-100ps	-100ps	-100ps
MAC max		900ps	900ps	900ps
PHY fixed Delay	2000ps	2000ps	2000ps
PHY added Delay	-340ps	-600ps	-859ps
T_setup_T min	1.56ns	1.30ns	1.04ns
T_setup_T typ	2.06ns	1.80ns	1.54ns
T_setup_T max	2.56ns	2.30ns	2.04ns
T_hold_T min	1.04ns	1.30ns	1.56ns
T_hold_T typ	1.94ns	2.20ns	2.46ns
T_hold_T max	2.84ns	3.10ns	3.36ns

This shows that T_hold_T min and T_setup_T min times are out of spec
for RGMII timing. However the KSZ9131 has a minimal value for this time
of 0.8ns which is met under all circumstances.

Signed-off-by: Philippe Schenker <philippe.schenker@toradex.com>
This commit is contained in:
Philippe Schenker 2020-03-11 11:59:26 +01:00 committed by Stefano Babic
parent c4b650befc
commit f72e48ba4d
2 changed files with 77 additions and 16 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

89
board/toradex/apalis_imx6/apalis_imx6.c
View File

@ -137,22 +137,79 @@ iomux_v3_cfg_t const usdhc3_pads[] = {
int mx6_rgmii_rework(struct phy_device *phydev) int mx6_rgmii_rework(struct phy_device *phydev)
{ {
/* control data pad skew - devaddr = 0x02, register = 0x04 */ int tmp;
ksz9031_phy_extended_write(phydev, 0x02,
MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW, switch (ksz9xx1_phy_get_id(phydev) & MII_KSZ9x31_SILICON_REV_MASK) {
MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000); case PHY_ID_KSZ9131:
/* rx data pad skew - devaddr = 0x02, register = 0x05 */ /* read rxc dll control - devaddr = 0x02, register = 0x4c */
ksz9031_phy_extended_write(phydev, 0x02, tmp = ksz9031_phy_extended_read(phydev, 0x02,
MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW, MII_KSZ9131_EXT_RGMII_2NS_SKEW_RXDLL,
MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000); MII_KSZ9031_MOD_DATA_NO_POST_INC);
/* tx data pad skew - devaddr = 0x02, register = 0x05 */ /* disable rxdll bypass (enable 2ns skew delay on RXC) */
ksz9031_phy_extended_write(phydev, 0x02, tmp &= ~MII_KSZ9131_RXTXDLL_BYPASS;
MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW, /* rxc data pad skew 2ns - devaddr = 0x02, register = 0x4c */
MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000); ksz9031_phy_extended_write(phydev, 0x02,
/* gtx and rx clock pad skew - devaddr = 0x02, register = 0x08 */ MII_KSZ9131_EXT_RGMII_2NS_SKEW_RXDLL,
ksz9031_phy_extended_write(phydev, 0x02, MII_KSZ9031_MOD_DATA_NO_POST_INC,
MII_KSZ9031_EXT_RGMII_CLOCK_SKEW, tmp);
MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x03FF); /* read txc dll control - devaddr = 0x02, register = 0x4d */
tmp = ksz9031_phy_extended_read(phydev, 0x02,
MII_KSZ9131_EXT_RGMII_2NS_SKEW_TXDLL,
MII_KSZ9031_MOD_DATA_NO_POST_INC);
/* disable rxdll bypass (enable 2ns skew delay on TXC) */
tmp &= ~MII_KSZ9131_RXTXDLL_BYPASS;
/* txc data pad skew 2ns - devaddr = 0x02, register = 0x4d */
ksz9031_phy_extended_write(phydev, 0x02,
MII_KSZ9131_EXT_RGMII_2NS_SKEW_TXDLL,
MII_KSZ9031_MOD_DATA_NO_POST_INC,
tmp);
/* control data pad skew - devaddr = 0x02, register = 0x04 */
ksz9031_phy_extended_write(phydev, 0x02,
MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW,
MII_KSZ9031_MOD_DATA_NO_POST_INC,
0x007d);
/* rx data pad skew - devaddr = 0x02, register = 0x05 */
ksz9031_phy_extended_write(phydev, 0x02,
MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW,
MII_KSZ9031_MOD_DATA_NO_POST_INC,
0x7777);
/* tx data pad skew - devaddr = 0x02, register = 0x05 */
ksz9031_phy_extended_write(phydev, 0x02,
MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW,
MII_KSZ9031_MOD_DATA_NO_POST_INC,
0xdddd);
/* gtx and rx clock pad skew - devaddr = 0x02,register = 0x08 */
ksz9031_phy_extended_write(phydev, 0x02,
MII_KSZ9031_EXT_RGMII_CLOCK_SKEW,
MII_KSZ9031_MOD_DATA_NO_POST_INC,
0x0007);
break;
case PHY_ID_KSZ9031:
default:
/* control data pad skew - devaddr = 0x02, register = 0x04 */
ksz9031_phy_extended_write(phydev, 0x02,
MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW,
MII_KSZ9031_MOD_DATA_NO_POST_INC,
0x0000);
/* rx data pad skew - devaddr = 0x02, register = 0x05 */
ksz9031_phy_extended_write(phydev, 0x02,
MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW,
MII_KSZ9031_MOD_DATA_NO_POST_INC,
0x0000);
/* tx data pad skew - devaddr = 0x02, register = 0x05 */
ksz9031_phy_extended_write(phydev, 0x02,
MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW,
MII_KSZ9031_MOD_DATA_NO_POST_INC,
0x0000);
/* gtx and rx clock pad skew - devaddr = 0x02,register = 0x08 */
ksz9031_phy_extended_write(phydev, 0x02,
MII_KSZ9031_EXT_RGMII_CLOCK_SKEW,
MII_KSZ9031_MOD_DATA_NO_POST_INC,
0x03FF);
break;
}
return 0; return 0;
} }

4
include/micrel.h
View File

@ -25,6 +25,10 @@
#define MII_KSZ9x31_SILICON_REV_MASK 0xfffff0 #define MII_KSZ9x31_SILICON_REV_MASK 0xfffff0
#define MII_KSZ9131_RXTXDLL_BYPASS BIT(12)
#define MII_KSZ9131_EXT_RGMII_2NS_SKEW_RXDLL 0x4c
#define MII_KSZ9131_EXT_RGMII_2NS_SKEW_TXDLL 0x4d
#define PHY_ID_KSZ9031 0x00221620 #define PHY_ID_KSZ9031 0x00221620
#define PHY_ID_KSZ9131 0x00221640 #define PHY_ID_KSZ9131 0x00221640