tegra: Add flow, gp_padctl, fuse, sdram headers
These headers provide access to additional Tegra features. flow - start/stop CPUs sdram - parameters for SDRAM fuse - access to on-chip fuses / security settings gp_padctl - pad control and general purpose registers Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Yen Lin <yelin@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
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36
arch/arm/include/asm/arch-tegra2/flow.h
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36
arch/arm/include/asm/arch-tegra2/flow.h
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/*
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* (C) Copyright 2010, 2011
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* NVIDIA Corporation <www.nvidia.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef _FLOW_H_
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#define _FLOW_H_
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struct flow_ctlr {
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u32 halt_cpu_events;
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u32 halt_cop_events;
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u32 cpu_csr;
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u32 cop_csr;
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u32 halt_cpu1_events;
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u32 cpu1_csr;
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};
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#endif
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39
arch/arm/include/asm/arch-tegra2/fuse.h
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arch/arm/include/asm/arch-tegra2/fuse.h
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/*
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* (C) Copyright 2010,2011
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* NVIDIA Corporation <www.nvidia.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef _FUSE_H_
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#define _FUSE_H_
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/* FUSE registers */
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struct fuse_regs {
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u32 reserved0[64]; /* 0x00 - 0xFC: */
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u32 production_mode; /* 0x100: FUSE_PRODUCTION_MODE */
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u32 reserved1[3]; /* 0x104 - 0x10c: */
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u32 sku_info; /* 0x110 */
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u32 reserved2[13]; /* 0x114 - 0x144: */
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u32 fa; /* 0x148: FUSE_FA */
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u32 reserved3[21]; /* 0x14C - 0x19C: */
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u32 security_mode; /* 0x1A0: FUSE_SECURITY_MODE */
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};
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#endif /* ifndef _FUSE_H_ */
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64
arch/arm/include/asm/arch-tegra2/gp_padctrl.h
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arch/arm/include/asm/arch-tegra2/gp_padctrl.h
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/*
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* (C) Copyright 2010,2011
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* NVIDIA Corporation <www.nvidia.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef _GP_PADCTRL_H_
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#define _GP_PADCTRL_H_
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/* APB_MISC_GP and padctrl registers */
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struct apb_misc_gp_ctlr {
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u32 modereg; /* 0x00: APB_MISC_GP_MODEREG */
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u32 hidrev; /* 0x04: APB_MISC_GP_HIDREV */
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u32 reserved0[22]; /* 0x08 - 0x5C: */
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u32 emu_revid; /* 0x60: APB_MISC_GP_EMU_REVID */
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u32 xactor_scratch; /* 0x64: APB_MISC_GP_XACTOR_SCRATCH */
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u32 aocfg1; /* 0x68: APB_MISC_GP_AOCFG1PADCTRL */
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u32 aocfg2; /* 0x6c: APB_MISC_GP_AOCFG2PADCTRL */
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u32 atcfg1; /* 0x70: APB_MISC_GP_ATCFG1PADCTRL */
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u32 atcfg2; /* 0x74: APB_MISC_GP_ATCFG2PADCTRL */
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u32 cdevcfg1; /* 0x78: APB_MISC_GP_CDEV1CFGPADCTRL */
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u32 cdevcfg2; /* 0x7C: APB_MISC_GP_CDEV2CFGPADCTRL */
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u32 csuscfg; /* 0x80: APB_MISC_GP_CSUSCFGPADCTRL */
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u32 dap1cfg; /* 0x84: APB_MISC_GP_DAP1CFGPADCTRL */
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u32 dap2cfg; /* 0x88: APB_MISC_GP_DAP2CFGPADCTRL */
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u32 dap3cfg; /* 0x8C: APB_MISC_GP_DAP3CFGPADCTRL */
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u32 dap4cfg; /* 0x90: APB_MISC_GP_DAP4CFGPADCTRL */
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u32 dbgcfg; /* 0x94: APB_MISC_GP_DBGCFGPADCTRL */
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u32 lcdcfg1; /* 0x98: APB_MISC_GP_LCDCFG1PADCTRL */
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u32 lcdcfg2; /* 0x9C: APB_MISC_GP_LCDCFG2PADCTRL */
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u32 sdmmc2_cfg; /* 0xA0: APB_MISC_GP_SDMMC2CFGPADCTRL */
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u32 sdmmc3_cfg; /* 0xA4: APB_MISC_GP_SDMMC3CFGPADCTRL */
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u32 spicfg; /* 0xA8: APB_MISC_GP_SPICFGPADCTRL */
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u32 uaacfg; /* 0xAC: APB_MISC_GP_UAACFGPADCTRL */
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u32 uabcfg; /* 0xB0: APB_MISC_GP_UABCFGPADCTRL */
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u32 uart2cfg; /* 0xB4: APB_MISC_GP_UART2CFGPADCTRL */
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u32 uart3cfg; /* 0xB8: APB_MISC_GP_UART3CFGPADCTRL */
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u32 vicfg1; /* 0xBC: APB_MISC_GP_VICFG1PADCTRL */
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u32 vicfg2; /* 0xC0: APB_MISC_GP_VICFG2PADCTRL */
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u32 xm2cfga; /* 0xC4: APB_MISC_GP_XM2CFGAPADCTRL */
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u32 xm2cfgc; /* 0xC8: APB_MISC_GP_XM2CFGCPADCTRL */
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u32 xm2cfgd; /* 0xCC: APB_MISC_GP_XM2CFGDPADCTRL */
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u32 xm2clkcfg; /* 0xD0: APB_MISC_GP_XM2CLKCFGPADCTRL */
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u32 memcomp; /* 0xD4: APB_MISC_GP_MEMCOMPPADCTRL */
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};
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#endif
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148
arch/arm/include/asm/arch-tegra2/sdram_param.h
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arch/arm/include/asm/arch-tegra2/sdram_param.h
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/*
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* (C) Copyright 2010, 2011
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* NVIDIA Corporation <www.nvidia.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef _SDRAM_PARAM_H_
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#define _SDRAM_PARAM_H_
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/*
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* Defines the number of 32-bit words provided in each set of SDRAM parameters
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* for arbitration configuration data.
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*/
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#define BCT_SDRAM_ARB_CONFIG_WORDS 27
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enum memory_type {
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MEMORY_TYPE_NONE = 0,
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MEMORY_TYPE_DDR,
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MEMORY_TYPE_LPDDR,
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MEMORY_TYPE_DDR2,
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MEMORY_TYPE_LPDDR2,
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MEMORY_TYPE_NUM,
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MEMORY_TYPE_FORCE32 = 0x7FFFFFFF
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};
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/* Defines the SDRAM parameter structure */
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struct sdram_params {
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enum memory_type memory_type;
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u32 pllm_charge_pump_setup_control;
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u32 pllm_loop_filter_setup_control;
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u32 pllm_input_divider;
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u32 pllm_feedback_divider;
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u32 pllm_post_divider;
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u32 pllm_stable_time;
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u32 emc_clock_divider;
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u32 emc_auto_cal_interval;
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u32 emc_auto_cal_config;
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u32 emc_auto_cal_wait;
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u32 emc_pin_program_wait;
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u32 emc_rc;
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u32 emc_rfc;
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u32 emc_ras;
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u32 emc_rp;
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u32 emc_r2w;
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u32 emc_w2r;
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u32 emc_r2p;
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u32 emc_w2p;
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u32 emc_rd_rcd;
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u32 emc_wr_rcd;
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u32 emc_rrd;
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u32 emc_rext;
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u32 emc_wdv;
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u32 emc_quse;
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u32 emc_qrst;
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u32 emc_qsafe;
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u32 emc_rdv;
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u32 emc_refresh;
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u32 emc_burst_refresh_num;
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u32 emc_pdex2wr;
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u32 emc_pdex2rd;
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u32 emc_pchg2pden;
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u32 emc_act2pden;
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u32 emc_ar2pden;
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u32 emc_rw2pden;
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u32 emc_txsr;
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u32 emc_tcke;
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u32 emc_tfaw;
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u32 emc_trpab;
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u32 emc_tclkstable;
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u32 emc_tclkstop;
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u32 emc_trefbw;
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u32 emc_quseextra;
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u32 emc_fbioc_fg1;
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u32 emc_fbio_dqsib_dly;
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u32 emc_fbio_dqsib_dly_msb;
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u32 emc_fbio_quse_dly;
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u32 emc_fbio_quse_dly_msb;
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u32 emc_fbio_cfg5;
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u32 emc_fbio_cfg6;
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u32 emc_fbio_spare;
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u32 emc_mrs;
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u32 emc_emrs;
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u32 emc_mrw1;
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u32 emc_mrw2;
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u32 emc_mrw3;
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u32 emc_mrw_reset_command;
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u32 emc_mrw_reset_init_wait;
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u32 emc_adr_cfg;
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u32 emc_adr_cfg1;
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u32 emc_emem_cfg;
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u32 emc_low_latency_config;
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u32 emc_cfg;
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u32 emc_cfg2;
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u32 emc_dbg;
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u32 ahb_arbitration_xbar_ctrl;
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u32 emc_cfg_dig_dll;
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u32 emc_dll_xform_dqs;
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u32 emc_dll_xform_quse;
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u32 warm_boot_wait;
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u32 emc_ctt_term_ctrl;
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u32 emc_odt_write;
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u32 emc_odt_read;
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u32 emc_zcal_ref_cnt;
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u32 emc_zcal_wait_cnt;
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u32 emc_zcal_mrw_cmd;
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u32 emc_mrs_reset_dll;
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u32 emc_mrw_zq_init_dev0;
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u32 emc_mrw_zq_init_dev1;
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u32 emc_mrw_zq_init_wait;
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u32 emc_mrs_reset_dll_wait;
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u32 emc_emrs_emr2;
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u32 emc_emrs_emr3;
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u32 emc_emrs_ddr2_dll_enable;
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u32 emc_mrs_ddr2_dll_reset;
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u32 emc_emrs_ddr2_ocd_calib;
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u32 emc_edr2_wait;
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u32 emc_cfg_clktrim0;
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u32 emc_cfg_clktrim1;
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u32 emc_cfg_clktrim2;
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u32 pmc_ddr_pwr;
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u32 apb_misc_gp_xm2cfga_padctrl;
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u32 apb_misc_gp_xm2cfgc_padctrl;
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u32 apb_misc_gp_xm2cfgc_padctrl2;
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u32 apb_misc_gp_xm2cfgd_padctrl;
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u32 apb_misc_gp_xm2cfgd_padctrl2;
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u32 apb_misc_gp_xm2clkcfg_padctrl;
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u32 apb_misc_gp_xm2comp_padctrl;
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u32 apb_misc_gp_xm2vttgen_padctrl;
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u32 arbitration_config[BCT_SDRAM_ARB_CONFIG_WORDS];
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};
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#endif
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@ -40,6 +40,7 @@
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#define NV_PA_APB_UARTE_BASE (NV_PA_APB_MISC_BASE + 0x6400)
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#define TEGRA2_SPI_BASE (NV_PA_APB_MISC_BASE + 0xC380)
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#define TEGRA2_PMC_BASE (NV_PA_APB_MISC_BASE + 0xE400)
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#define TEGRA2_FUSE_BASE (NV_PA_APB_MISC_BASE + 0xF800)
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#define NV_PA_CSITE_BASE 0x70040000
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#define TEGRA_USB1_BASE 0xC5000000
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#define TEGRA_USB3_BASE 0xC5008000
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