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Convert CONFIG_SYS_FSL_CPC et al to Kconfig

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This converts the following to Kconfig:
   CONFIG_SYS_FSL_CPC
   CONFIG_SYS_CPC_REINIT_F

Signed-off-by: Tom Rini <trini@konsulko.com>
This commit is contained in:
Tom Rini 2022-06-25 11:02:45 -04:00
parent 5a4461867c
commit f6c1f91761
52 changed files with 50 additions and 15 deletions
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4
README
View File

@ -371,10 +371,6 @@ The following options need to be configured:
In this mode, a single differential clock is used to supply
clocks to the sysclock, ddrclock and usbclock.
CONFIG_SYS_CPC_REINIT_F
This CONFIG is defined when the CPC is configured as SRAM at the
time of U-Boot entry and is required to be re-initialized.
- Generic CPU options:
CONFIG_SYS_BIG_ENDIAN, CONFIG_SYS_LITTLE_ENDIAN

1
arch/Kconfig.nxp
View File

@ -16,6 +16,7 @@ config CHAIN_OF_TRUST
select SHA_HW_ACCEL
select SHA_PROG_HW_ACCEL
select ENV_IS_NOWHERE
select SYS_CPC_REINIT_F if MPC85xx && !SYS_RAMBOOT
select CMD_EXT4 if ARM
select CMD_EXT4_WRITE if ARM
imply CMD_BLOB

9
arch/powerpc/cpu/mpc85xx/Kconfig
View File

@ -1221,6 +1221,15 @@ config SYS_BOOK3E_HV
bool "Category E.HV is supported"
depends on BOOKE
config SYS_CPC_REINIT_F
bool
help
The CPC is configured as SRAM at the time of U-Boot entry and is
required to be re-initialized.
config SYS_FSL_CPC
bool "Corenet Platform Cache support"
config SYS_MPC85XX_NO_RESETVEC
bool "Discard resetvec section and move bootpg section up"
depends on MPC85xx

3
arch/powerpc/include/asm/fsl_secure_boot.h
View File

@ -21,9 +21,6 @@
defined(CONFIG_TARGET_T1042D4RDB) || \
defined(CONFIG_TARGET_T1042RDB_PI) || \
defined(CONFIG_ARCH_T1024)
#ifndef CONFIG_SYS_RAMBOOT
#define CONFIG_SYS_CPC_REINIT_F
#endif
#undef CONFIG_SYS_INIT_L3_ADDR
#define CONFIG_SYS_INIT_L3_ADDR 0xbff00000
#endif

1
configs/P2041RDB_NAND_defconfig
View File

@ -9,6 +9,7 @@ CONFIG_TARGET_P2041RDB=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
CONFIG_SYS_FSL_CPC=y
CONFIG_PCIE1=y
CONFIG_PCIE2=y
CONFIG_PCIE3=y

1
configs/P2041RDB_SDCARD_defconfig
View File

@ -9,6 +9,7 @@ CONFIG_TARGET_P2041RDB=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
CONFIG_SYS_FSL_CPC=y
CONFIG_PCIE1=y
CONFIG_PCIE2=y
CONFIG_PCIE3=y

1
configs/P2041RDB_SPIFLASH_defconfig
View File

@ -10,6 +10,7 @@ CONFIG_TARGET_P2041RDB=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
CONFIG_SYS_FSL_CPC=y
CONFIG_PCIE1=y
CONFIG_PCIE2=y
CONFIG_PCIE3=y

1
configs/P2041RDB_defconfig
View File

@ -10,6 +10,7 @@ CONFIG_TARGET_P2041RDB=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
CONFIG_SYS_FSL_CPC=y
CONFIG_PCIE1=y
CONFIG_PCIE2=y
CONFIG_PCIE3=y

1
configs/P3041DS_NAND_defconfig
View File

@ -9,6 +9,7 @@ CONFIG_TARGET_P3041DS=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
CONFIG_SYS_FSL_CPC=y
CONFIG_PCIE1=y
CONFIG_PCIE2=y
CONFIG_PCIE3=y

1
configs/P3041DS_SDCARD_defconfig
View File

@ -9,6 +9,7 @@ CONFIG_TARGET_P3041DS=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
CONFIG_SYS_FSL_CPC=y
CONFIG_PCIE1=y
CONFIG_PCIE2=y
CONFIG_PCIE3=y

1
configs/P3041DS_SPIFLASH_defconfig
View File

@ -10,6 +10,7 @@ CONFIG_TARGET_P3041DS=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
CONFIG_SYS_FSL_CPC=y
CONFIG_PCIE1=y
CONFIG_PCIE2=y
CONFIG_PCIE3=y

1
configs/P3041DS_defconfig
View File

@ -10,6 +10,7 @@ CONFIG_TARGET_P3041DS=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
CONFIG_SYS_FSL_CPC=y
CONFIG_PCIE1=y
CONFIG_PCIE2=y
CONFIG_PCIE3=y

1
configs/P4080DS_SDCARD_defconfig
View File

@ -9,6 +9,7 @@ CONFIG_TARGET_P4080DS=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
CONFIG_SYS_FSL_CPC=y
CONFIG_PCIE1=y
CONFIG_PCIE2=y
CONFIG_PCIE3=y

1
configs/P4080DS_SPIFLASH_defconfig
View File

@ -10,6 +10,7 @@ CONFIG_TARGET_P4080DS=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
CONFIG_SYS_FSL_CPC=y
CONFIG_PCIE1=y
CONFIG_PCIE2=y
CONFIG_PCIE3=y

1
configs/P4080DS_defconfig
View File

@ -10,6 +10,7 @@ CONFIG_TARGET_P4080DS=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
CONFIG_SYS_FSL_CPC=y
CONFIG_PCIE1=y
CONFIG_PCIE2=y
CONFIG_PCIE3=y

1
configs/P5040DS_NAND_defconfig
View File

@ -9,6 +9,7 @@ CONFIG_TARGET_P5040DS=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
CONFIG_SYS_FSL_CPC=y
CONFIG_PCIE1=y
CONFIG_PCIE2=y
CONFIG_PCIE3=y

1
configs/P5040DS_SDCARD_defconfig
View File

@ -9,6 +9,7 @@ CONFIG_TARGET_P5040DS=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
CONFIG_SYS_FSL_CPC=y
CONFIG_PCIE1=y
CONFIG_PCIE2=y
CONFIG_PCIE3=y

1
configs/P5040DS_SPIFLASH_defconfig
View File

@ -10,6 +10,7 @@ CONFIG_TARGET_P5040DS=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
CONFIG_SYS_FSL_CPC=y
CONFIG_PCIE1=y
CONFIG_PCIE2=y
CONFIG_PCIE3=y

1
configs/P5040DS_defconfig
View File

@ -10,6 +10,7 @@ CONFIG_TARGET_P5040DS=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
CONFIG_SYS_FSL_CPC=y
CONFIG_PCIE1=y
CONFIG_PCIE2=y
CONFIG_PCIE3=y

1
configs/T1024RDB_NAND_defconfig
View File

@ -14,6 +14,7 @@ CONFIG_MPC85xx=y
CONFIG_TARGET_T1024RDB=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
CONFIG_SYS_FSL_CPC=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_PCIE1=y

1
configs/T1024RDB_SDCARD_defconfig
View File

@ -15,6 +15,7 @@ CONFIG_MPC85xx=y
CONFIG_TARGET_T1024RDB=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
CONFIG_SYS_FSL_CPC=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_PCIE1=y
CONFIG_PCIE2=y

1
configs/T1024RDB_SPIFLASH_defconfig
View File

@ -17,6 +17,7 @@ CONFIG_MPC85xx=y
CONFIG_TARGET_T1024RDB=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
CONFIG_SYS_FSL_CPC=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_PCIE1=y
CONFIG_PCIE2=y

1
configs/T1024RDB_defconfig
View File

@ -10,6 +10,7 @@ CONFIG_TARGET_T1024RDB=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
CONFIG_SYS_FSL_CPC=y
CONFIG_PCIE1=y
CONFIG_PCIE2=y
CONFIG_PCIE3=y

1
configs/T1042D4RDB_NAND_defconfig
View File

@ -13,6 +13,7 @@ CONFIG_MPC85xx=y
CONFIG_TARGET_T1042D4RDB=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
CONFIG_SYS_FSL_CPC=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_PCIE1=y

1
configs/T1042D4RDB_SDCARD_defconfig
View File

@ -14,6 +14,7 @@ CONFIG_MPC85xx=y
CONFIG_TARGET_T1042D4RDB=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
CONFIG_SYS_FSL_CPC=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_PCIE1=y
CONFIG_PCIE2=y

1
configs/T1042D4RDB_SPIFLASH_defconfig
View File

@ -16,6 +16,7 @@ CONFIG_MPC85xx=y
CONFIG_TARGET_T1042D4RDB=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
CONFIG_SYS_FSL_CPC=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_PCIE1=y
CONFIG_PCIE2=y

1
configs/T1042D4RDB_defconfig
View File

@ -9,6 +9,7 @@ CONFIG_TARGET_T1042D4RDB=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
CONFIG_SYS_FSL_CPC=y
CONFIG_PCIE1=y
CONFIG_PCIE2=y
CONFIG_PCIE3=y

1
configs/T2080QDS_NAND_defconfig
View File

@ -20,6 +20,7 @@ CONFIG_MPC85xx=y
CONFIG_TARGET_T2080QDS=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
CONFIG_SYS_FSL_CPC=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y
<<<<<<< HEAD

1
configs/T2080QDS_SDCARD_defconfig
View File

@ -21,6 +21,7 @@ CONFIG_MPC85xx=y
CONFIG_TARGET_T2080QDS=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
CONFIG_SYS_FSL_CPC=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
<<<<<<< HEAD
=======

1
configs/T2080QDS_SECURE_BOOT_defconfig
View File

@ -7,6 +7,7 @@ CONFIG_TARGET_T2080QDS=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
CONFIG_SYS_FSL_CPC=y
CONFIG_NXP_ESBC=y
CONFIG_BOOTSCRIPT_HDR_ADDR=0xee020000
CONFIG_PCIE1=y

1
configs/T2080QDS_SPIFLASH_defconfig
View File

@ -23,6 +23,7 @@ CONFIG_MPC85xx=y
CONFIG_TARGET_T2080QDS=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
CONFIG_SYS_FSL_CPC=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
<<<<<<< HEAD
=======

1
configs/T2080QDS_SRIO_PCIE_BOOT_defconfig
View File

@ -10,6 +10,7 @@ CONFIG_TARGET_T2080QDS=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
CONFIG_SYS_FSL_CPC=y
CONFIG_SRIO_PCIE_BOOT_SLAVE=y
CONFIG_PCIE1=y
CONFIG_PCIE2=y

1
configs/T2080QDS_defconfig
View File

@ -11,6 +11,7 @@ CONFIG_TARGET_T2080QDS=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
CONFIG_SYS_FSL_CPC=y
CONFIG_PCIE1=y
CONFIG_PCIE2=y
CONFIG_PCIE3=y

1
configs/T2080RDB_NAND_defconfig
View File

@ -17,6 +17,7 @@ CONFIG_MPC85xx=y
CONFIG_TARGET_T2080RDB=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
CONFIG_SYS_FSL_CPC=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y
<<<<<<< HEAD

1
configs/T2080RDB_SDCARD_defconfig
View File

@ -18,6 +18,7 @@ CONFIG_MPC85xx=y
CONFIG_TARGET_T2080RDB=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
CONFIG_SYS_FSL_CPC=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
<<<<<<< HEAD
=======

1
configs/T2080RDB_SPIFLASH_defconfig
View File

@ -20,6 +20,7 @@ CONFIG_MPC85xx=y
CONFIG_TARGET_T2080RDB=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
CONFIG_SYS_FSL_CPC=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
<<<<<<< HEAD
=======

1
configs/T2080RDB_defconfig
View File

@ -13,6 +13,7 @@ CONFIG_TARGET_T2080RDB=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
CONFIG_SYS_FSL_CPC=y
CONFIG_PCIE1=y
CONFIG_PCIE2=y
CONFIG_PCIE3=y

1
configs/T2080RDB_revD_NAND_defconfig
View File

@ -17,6 +17,7 @@ CONFIG_MPC85xx=y
CONFIG_TARGET_T2080RDB=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
CONFIG_SYS_FSL_CPC=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_T2080RDB_REV_D=y

1
configs/T2080RDB_revD_SDCARD_defconfig
View File

@ -18,6 +18,7 @@ CONFIG_MPC85xx=y
CONFIG_TARGET_T2080RDB=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
CONFIG_SYS_FSL_CPC=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_T2080RDB_REV_D=y
<<<<<<< HEAD

1
configs/T2080RDB_revD_SPIFLASH_defconfig
View File

@ -20,6 +20,7 @@ CONFIG_MPC85xx=y
CONFIG_TARGET_T2080RDB=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
CONFIG_SYS_FSL_CPC=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_T2080RDB_REV_D=y
<<<<<<< HEAD

1
configs/T2080RDB_revD_defconfig
View File

@ -13,6 +13,7 @@ CONFIG_TARGET_T2080RDB=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
CONFIG_SYS_FSL_CPC=y
CONFIG_T2080RDB_REV_D=y
<<<<<<< HEAD
=======

1
configs/T4240RDB_SDCARD_defconfig
View File

@ -18,6 +18,7 @@ CONFIG_MPC85xx=y
CONFIG_TARGET_T4240RDB=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
CONFIG_SYS_FSL_CPC=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
<<<<<<< HEAD
=======

1
configs/T4240RDB_defconfig
View File

@ -13,6 +13,7 @@ CONFIG_TARGET_T4240RDB=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
CONFIG_SYS_FSL_CPC=y
CONFIG_PCIE1=y
CONFIG_PCIE2=y
CONFIG_PCIE3=y

1
configs/kmcent2_defconfig
View File

@ -12,6 +12,7 @@ CONFIG_TARGET_KMCENT2=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
CONFIG_SYS_FSL_CPC=y
# CONFIG_DEEP_SLEEP is not set
CONFIG_PCIE1=y
CONFIG_KM_DEF_NETDEV="eth2"

1
include/configs/P2041RDB.h
View File

@ -30,7 +30,6 @@
#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
#endif
#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
#define CONFIG_SYS_SRIO

1
include/configs/T102xRDB.h
View File

@ -15,7 +15,6 @@
/* High Level Configuration Options */
#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
#ifdef CONFIG_RAMBOOT_PBL

1
include/configs/T104xRDB.h
View File

@ -58,7 +58,6 @@
#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
#endif
#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
/*

1
include/configs/T208xQDS.h
View File

@ -22,7 +22,6 @@
/* High Level Configuration Options */
#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
#ifdef CONFIG_RAMBOOT_PBL

1
include/configs/T208xRDB.h
View File

@ -17,7 +17,6 @@
/* High Level Configuration Options */
#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
#ifdef CONFIG_RAMBOOT_PBL

1
include/configs/T4240RDB.h
View File

@ -39,7 +39,6 @@
#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
#endif
#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
/*

1
include/configs/corenet_ds.h
View File

@ -33,7 +33,6 @@
#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
#endif
#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
/*

1
include/configs/kmcent2.h
View File

@ -137,7 +137,6 @@
#define CONFIG_RESET_VECTOR_ADDRESS 0xebfffffc
#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
/* Environment in parallel NOR-Flash */