net: Remove cs8900 driver
This driver is not enabled by any board and not converted to DM_ETH. Remove. Signed-off-by: Tom Rini <trini@konsulko.com>
This commit is contained in:
Tom Rini
parent
122126adbd
commit
f693a921a3
@ -15,7 +15,6 @@ obj-$(CONFIG_BCM_SF2_ETH_GMAC) += bcm-sf2-eth-gmac.o
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obj-$(CONFIG_BNXT_ETH) += bnxt/
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obj-$(CONFIG_CALXEDA_XGMAC) += calxedaxgmac.o
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obj-$(CONFIG_CORTINA_NI_ENET) += cortina_ni.o
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obj-$(CONFIG_CS8900) += cs8900.o
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obj-$(CONFIG_DM_ETH_PHY) += eth-phy-uclass.o
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obj-$(CONFIG_DNET) += dnet.o
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obj-$(CONFIG_DRIVER_DM9000) += dm9000x.o
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@ -1,320 +0,0 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Cirrus Logic CS8900A Ethernet
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*
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* (C) 2009 Ben Warren , biggerbadderben@gmail.com
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* Converted to use CONFIG_NET_MULTI API
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*
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* (C) 2003 Wolfgang Denk, wd@denx.de
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* Extension to synchronize ethaddr environment variable
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* against value in EEPROM
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*
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* (C) Copyright 2002
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* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
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* Marius Groeger <mgroeger@sysgo.de>
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*
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* Copyright (C) 1999 Ben Williamson <benw@pobox.com>
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*
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* This program is loaded into SRAM in bootstrap mode, where it waits
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* for commands on UART1 to read and write memory, jump to code etc.
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* A design goal for this program is to be entirely independent of the
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* target board. Anything with a CL-PS7111 or EP7211 should be able to run
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* this code in bootstrap mode. All the board specifics can be handled on
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* the host.
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*/
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#include <common.h>
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#include <command.h>
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#include <log.h>
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#include <asm/io.h>
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#include <net.h>
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#include <malloc.h>
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#include <linux/delay.h>
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#include "cs8900.h"
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#undef DEBUG
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/* packet page register access functions */
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#ifdef CONFIG_CS8900_BUS32
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#define REG_WRITE(v, a) writel((v),(a))
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#define REG_READ(a) readl((a))
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/* we don't need 16 bit initialisation on 32 bit bus */
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#define get_reg_init_bus(r,d) get_reg((r),(d))
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#else
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#define REG_WRITE(v, a) writew((v),(a))
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#define REG_READ(a) readw((a))
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static u16 get_reg_init_bus(struct eth_device *dev, int regno)
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{
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/* force 16 bit busmode */
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struct cs8900_priv *priv = (struct cs8900_priv *)(dev->priv);
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uint8_t volatile * const iob = (uint8_t volatile * const)dev->iobase;
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readb(iob);
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readb(iob + 1);
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readb(iob);
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readb(iob + 1);
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readb(iob);
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REG_WRITE(regno, &priv->regs->pptr);
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return REG_READ(&priv->regs->pdata);
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}
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#endif
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static u16 get_reg(struct eth_device *dev, int regno)
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{
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struct cs8900_priv *priv = (struct cs8900_priv *)(dev->priv);
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REG_WRITE(regno, &priv->regs->pptr);
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return REG_READ(&priv->regs->pdata);
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}
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static void put_reg(struct eth_device *dev, int regno, u16 val)
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{
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struct cs8900_priv *priv = (struct cs8900_priv *)(dev->priv);
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REG_WRITE(regno, &priv->regs->pptr);
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REG_WRITE(val, &priv->regs->pdata);
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}
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static void cs8900_reset(struct eth_device *dev)
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{
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int tmo;
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u16 us;
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/* reset NIC */
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put_reg(dev, PP_SelfCTL, get_reg(dev, PP_SelfCTL) | PP_SelfCTL_Reset);
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/* wait for 200ms */
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udelay(200000);
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/* Wait until the chip is reset */
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tmo = get_timer(0) + 1 * CONFIG_SYS_HZ;
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while ((((us = get_reg_init_bus(dev, PP_SelfSTAT)) &
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PP_SelfSTAT_InitD) == 0) && tmo < get_timer(0))
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/*NOP*/;
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}
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static void cs8900_reginit(struct eth_device *dev)
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{
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/* receive only error free packets addressed to this card */
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put_reg(dev, PP_RxCTL,
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PP_RxCTL_IA | PP_RxCTL_Broadcast | PP_RxCTL_RxOK);
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/* do not generate any interrupts on receive operations */
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put_reg(dev, PP_RxCFG, 0);
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/* do not generate any interrupts on transmit operations */
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put_reg(dev, PP_TxCFG, 0);
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/* do not generate any interrupts on buffer operations */
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put_reg(dev, PP_BufCFG, 0);
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/* enable transmitter/receiver mode */
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put_reg(dev, PP_LineCTL, PP_LineCTL_Rx | PP_LineCTL_Tx);
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}
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void cs8900_get_enetaddr(struct eth_device *dev)
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{
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int i;
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/* verify chip id */
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if (get_reg_init_bus(dev, PP_ChipID) != 0x630e)
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return;
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cs8900_reset(dev);
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if ((get_reg(dev, PP_SelfSTAT) &
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(PP_SelfSTAT_EEPROM | PP_SelfSTAT_EEPROM_OK)) ==
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(PP_SelfSTAT_EEPROM | PP_SelfSTAT_EEPROM_OK)) {
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/* Load the MAC from EEPROM */
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for (i = 0; i < 3; i++) {
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u32 Addr;
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Addr = get_reg(dev, PP_IA + i * 2);
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dev->enetaddr[i * 2] = Addr & 0xFF;
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dev->enetaddr[i * 2 + 1] = Addr >> 8;
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}
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}
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}
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void cs8900_halt(struct eth_device *dev)
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{
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/* disable transmitter/receiver mode */
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put_reg(dev, PP_LineCTL, 0);
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/* "shutdown" to show ChipID or kernel wouldn't find he cs8900 ... */
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get_reg_init_bus(dev, PP_ChipID);
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}
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static int cs8900_init(struct eth_device *dev, struct bd_info * bd)
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{
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uchar *enetaddr = dev->enetaddr;
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u16 id;
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/* verify chip id */
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id = get_reg_init_bus(dev, PP_ChipID);
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if (id != 0x630e) {
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printf ("CS8900 Ethernet chip not found: "
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"ID=0x%04x instead 0x%04x\n", id, 0x630e);
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return 1;
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}
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cs8900_reset (dev);
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/* set the ethernet address */
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put_reg(dev, PP_IA + 0, enetaddr[0] | (enetaddr[1] << 8));
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put_reg(dev, PP_IA + 2, enetaddr[2] | (enetaddr[3] << 8));
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put_reg(dev, PP_IA + 4, enetaddr[4] | (enetaddr[5] << 8));
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cs8900_reginit(dev);
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return 0;
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}
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/* Get a data block via Ethernet */
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static int cs8900_recv(struct eth_device *dev)
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{
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int i;
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u16 rxlen;
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u16 *addr;
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u16 status;
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struct cs8900_priv *priv = (struct cs8900_priv *)(dev->priv);
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status = get_reg(dev, PP_RER);
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if ((status & PP_RER_RxOK) == 0)
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return 0;
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status = REG_READ(&priv->regs->rtdata);
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rxlen = REG_READ(&priv->regs->rtdata);
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if (rxlen > PKTSIZE_ALIGN + PKTALIGN)
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debug("packet too big!\n");
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for (addr = (u16 *)net_rx_packets[0], i = rxlen >> 1; i > 0; i--)
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*addr++ = REG_READ(&priv->regs->rtdata);
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if (rxlen & 1)
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*addr++ = REG_READ(&priv->regs->rtdata);
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/* Pass the packet up to the protocol layers. */
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net_process_received_packet(net_rx_packets[0], rxlen);
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return rxlen;
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}
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/* Send a data block via Ethernet. */
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static int cs8900_send(struct eth_device *dev, void *packet, int length)
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{
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volatile u16 *addr;
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int tmo;
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u16 s;
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struct cs8900_priv *priv = (struct cs8900_priv *)(dev->priv);
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retry:
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/* initiate a transmit sequence */
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REG_WRITE(PP_TxCmd_TxStart_Full, &priv->regs->txcmd);
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REG_WRITE(length, &priv->regs->txlen);
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/* Test to see if the chip has allocated memory for the packet */
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if ((get_reg(dev, PP_BusSTAT) & PP_BusSTAT_TxRDY) == 0) {
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/* Oops... this should not happen! */
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debug("cs: unable to send packet; retrying...\n");
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for (tmo = get_timer(0) + 5 * CONFIG_SYS_HZ;
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get_timer(0) < tmo;)
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/*NOP*/;
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cs8900_reset(dev);
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cs8900_reginit(dev);
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goto retry;
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}
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/* Write the contents of the packet */
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/* assume even number of bytes */
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for (addr = packet; length > 0; length -= 2)
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REG_WRITE(*addr++, &priv->regs->rtdata);
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/* wait for transfer to succeed */
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tmo = get_timer(0) + 5 * CONFIG_SYS_HZ;
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while ((s = get_reg(dev, PP_TER) & ~0x1F) == 0) {
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if (get_timer(0) >= tmo)
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break;
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}
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/* nothing */ ;
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if((s & (PP_TER_CRS | PP_TER_TxOK)) != PP_TER_TxOK) {
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debug("\ntransmission error %#x\n", s);
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}
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return 0;
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}
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static void cs8900_e2prom_ready(struct eth_device *dev)
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{
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while (get_reg(dev, PP_SelfSTAT) & SI_BUSY)
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;
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}
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/***********************************************************/
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/* read a 16-bit word out of the EEPROM */
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/***********************************************************/
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int cs8900_e2prom_read(struct eth_device *dev,
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u8 addr, u16 *value)
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{
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cs8900_e2prom_ready(dev);
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put_reg(dev, PP_EECMD, EEPROM_READ_CMD | addr);
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cs8900_e2prom_ready(dev);
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*value = get_reg(dev, PP_EEData);
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return 0;
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}
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/***********************************************************/
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/* write a 16-bit word into the EEPROM */
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/***********************************************************/
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int cs8900_e2prom_write(struct eth_device *dev, u8 addr, u16 value)
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{
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cs8900_e2prom_ready(dev);
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put_reg(dev, PP_EECMD, EEPROM_WRITE_EN);
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cs8900_e2prom_ready(dev);
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put_reg(dev, PP_EEData, value);
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put_reg(dev, PP_EECMD, EEPROM_WRITE_CMD | addr);
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cs8900_e2prom_ready(dev);
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put_reg(dev, PP_EECMD, EEPROM_WRITE_DIS);
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cs8900_e2prom_ready(dev);
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return 0;
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}
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int cs8900_initialize(u8 dev_num, int base_addr)
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{
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struct eth_device *dev;
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struct cs8900_priv *priv;
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dev = malloc(sizeof(*dev));
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if (!dev) {
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return 0;
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}
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memset(dev, 0, sizeof(*dev));
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priv = malloc(sizeof(*priv));
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if (!priv) {
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free(dev);
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return 0;
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}
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memset(priv, 0, sizeof(*priv));
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priv->regs = (struct cs8900_regs *)base_addr;
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dev->iobase = base_addr;
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dev->priv = priv;
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dev->init = cs8900_init;
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dev->halt = cs8900_halt;
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dev->send = cs8900_send;
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dev->recv = cs8900_recv;
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/* Load MAC address from EEPROM */
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cs8900_get_enetaddr(dev);
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sprintf(dev->name, "%s-%hu", CS8900_DRIVERNAME, dev_num);
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eth_register(dev);
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return 0;
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}
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@ -1,248 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0+ */
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#ifndef CS8900_H
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#define CS8900_H
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/*
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* Cirrus Logic CS8900A Ethernet
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*
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* (C) 2009 Ben Warren , biggerbadderben@gmail.com
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* Converted to use CONFIG_NET_MULTI API
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*
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* (C) Copyright 2002
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* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
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* Marius Groeger <mgroeger@sysgo.de>
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*
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* Copyright (C) 1999 Ben Williamson <benw@pobox.com>
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*
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* This program is loaded into SRAM in bootstrap mode, where it waits
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* for commands on UART1 to read and write memory, jump to code etc.
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* A design goal for this program is to be entirely independent of the
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* target board. Anything with a CL-PS7111 or EP7211 should be able to run
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* this code in bootstrap mode. All the board specifics can be handled on
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* the host.
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*/
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#include <asm/types.h>
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#include <config.h>
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#define CS8900_DRIVERNAME "CS8900"
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/* although the registers are 16 bit, they are 32-bit aligned on the
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EDB7111. so we have to read them as 32-bit registers and ignore the
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upper 16-bits. i'm not sure if this holds for the EDB7211. */
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#ifdef CONFIG_CS8900_BUS16
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/* 16 bit aligned registers, 16 bit wide */
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#define CS8900_REG u16
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#elif defined(CONFIG_CS8900_BUS32)
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/* 32 bit aligned registers, 16 bit wide (we ignore upper 16 bits) */
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#define CS8900_REG u32
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#else
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#error unknown bussize ...
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#endif
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struct cs8900_regs {
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CS8900_REG rtdata;
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CS8900_REG pad0;
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CS8900_REG txcmd;
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CS8900_REG txlen;
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CS8900_REG isq;
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CS8900_REG pptr;
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CS8900_REG pdata;
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};
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struct cs8900_priv {
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struct cs8900_regs *regs;
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};
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#define ISQ_RxEvent 0x04
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#define ISQ_TxEvent 0x08
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#define ISQ_BufEvent 0x0C
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#define ISQ_RxMissEvent 0x10
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#define ISQ_TxColEvent 0x12
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#define ISQ_EventMask 0x3F
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/* packet page register offsets */
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/* bus interface registers */
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#define PP_ChipID 0x0000 /* Chip identifier - must be 0x630E */
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#define PP_ChipRev 0x0002 /* Chip revision, model codes */
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#define PP_IntReg 0x0022 /* Interrupt configuration */
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#define PP_IntReg_IRQ0 0x0000 /* Use INTR0 pin */
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#define PP_IntReg_IRQ1 0x0001 /* Use INTR1 pin */
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#define PP_IntReg_IRQ2 0x0002 /* Use INTR2 pin */
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#define PP_IntReg_IRQ3 0x0003 /* Use INTR3 pin */
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/* status and control registers */
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#define PP_RxCFG 0x0102 /* Receiver configuration */
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#define PP_RxCFG_Skip1 0x0040 /* Skip (i.e. discard) current frame */
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#define PP_RxCFG_Stream 0x0080 /* Enable streaming mode */
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#define PP_RxCFG_RxOK 0x0100 /* RxOK interrupt enable */
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#define PP_RxCFG_RxDMAonly 0x0200 /* Use RxDMA for all frames */
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#define PP_RxCFG_AutoRxDMA 0x0400 /* Select RxDMA automatically */
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#define PP_RxCFG_BufferCRC 0x0800 /* Include CRC characters in frame */
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#define PP_RxCFG_CRC 0x1000 /* Enable interrupt on CRC error */
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#define PP_RxCFG_RUNT 0x2000 /* Enable interrupt on RUNT frames */
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#define PP_RxCFG_EXTRA 0x4000 /* Enable interrupt on frames with extra data */
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#define PP_RxCTL 0x0104 /* Receiver control */
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#define PP_RxCTL_IAHash 0x0040 /* Accept frames that match hash */
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#define PP_RxCTL_Promiscuous 0x0080 /* Accept any frame */
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#define PP_RxCTL_RxOK 0x0100 /* Accept well formed frames */
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#define PP_RxCTL_Multicast 0x0200 /* Accept multicast frames */
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#define PP_RxCTL_IA 0x0400 /* Accept frame that matches IA */
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#define PP_RxCTL_Broadcast 0x0800 /* Accept broadcast frames */
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#define PP_RxCTL_CRC 0x1000 /* Accept frames with bad CRC */
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#define PP_RxCTL_RUNT 0x2000 /* Accept runt frames */
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#define PP_RxCTL_EXTRA 0x4000 /* Accept frames that are too long */
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#define PP_TxCFG 0x0106 /* Transmit configuration */
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#define PP_TxCFG_CRS 0x0040 /* Enable interrupt on loss of carrier */
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#define PP_TxCFG_SQE 0x0080 /* Enable interrupt on Signal Quality Error */
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#define PP_TxCFG_TxOK 0x0100 /* Enable interrupt on successful xmits */
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#define PP_TxCFG_Late 0x0200 /* Enable interrupt on "out of window" */
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#define PP_TxCFG_Jabber 0x0400 /* Enable interrupt on jabber detect */
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#define PP_TxCFG_Collision 0x0800 /* Enable interrupt if collision */
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#define PP_TxCFG_16Collisions 0x8000 /* Enable interrupt if > 16 collisions */
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#define PP_TxCmd 0x0108 /* Transmit command status */
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#define PP_TxCmd_TxStart_5 0x0000 /* Start after 5 bytes in buffer */
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#define PP_TxCmd_TxStart_381 0x0040 /* Start after 381 bytes in buffer */
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#define PP_TxCmd_TxStart_1021 0x0080 /* Start after 1021 bytes in buffer */
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#define PP_TxCmd_TxStart_Full 0x00C0 /* Start after all bytes loaded */
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#define PP_TxCmd_Force 0x0100 /* Discard any pending packets */
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#define PP_TxCmd_OneCollision 0x0200 /* Abort after a single collision */
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#define PP_TxCmd_NoCRC 0x1000 /* Do not add CRC */
|
||||
#define PP_TxCmd_NoPad 0x2000 /* Do not pad short packets */
|
||||
|
||||
#define PP_BufCFG 0x010A /* Buffer configuration */
|
||||
#define PP_BufCFG_SWI 0x0040 /* Force interrupt via software */
|
||||
#define PP_BufCFG_RxDMA 0x0080 /* Enable interrupt on Rx DMA */
|
||||
#define PP_BufCFG_TxRDY 0x0100 /* Enable interrupt when ready for Tx */
|
||||
#define PP_BufCFG_TxUE 0x0200 /* Enable interrupt in Tx underrun */
|
||||
#define PP_BufCFG_RxMiss 0x0400 /* Enable interrupt on missed Rx packets */
|
||||
#define PP_BufCFG_Rx128 0x0800 /* Enable Rx interrupt after 128 bytes */
|
||||
#define PP_BufCFG_TxCol 0x1000 /* Enable int on Tx collision ctr overflow */
|
||||
#define PP_BufCFG_Miss 0x2000 /* Enable int on Rx miss ctr overflow */
|
||||
#define PP_BufCFG_RxDest 0x8000 /* Enable int on Rx dest addr match */
|
||||
|
||||
#define PP_LineCTL 0x0112 /* Line control */
|
||||
#define PP_LineCTL_Rx 0x0040 /* Enable receiver */
|
||||
#define PP_LineCTL_Tx 0x0080 /* Enable transmitter */
|
||||
#define PP_LineCTL_AUIonly 0x0100 /* AUI interface only */
|
||||
#define PP_LineCTL_AutoAUI10BT 0x0200 /* Autodetect AUI or 10BaseT interface */
|
||||
#define PP_LineCTL_ModBackoffE 0x0800 /* Enable modified backoff algorithm */
|
||||
#define PP_LineCTL_PolarityDis 0x1000 /* Disable Rx polarity autodetect */
|
||||
#define PP_LineCTL_2partDefDis 0x2000 /* Disable two-part defferal */
|
||||
#define PP_LineCTL_LoRxSquelch 0x4000 /* Reduce receiver squelch threshold */
|
||||
|
||||
#define PP_SelfCTL 0x0114 /* Chip self control */
|
||||
#define PP_SelfCTL_Reset 0x0040 /* Self-clearing reset */
|
||||
#define PP_SelfCTL_SWSuspend 0x0100 /* Initiate suspend mode */
|
||||
#define PP_SelfCTL_HWSleepE 0x0200 /* Enable SLEEP input */
|
||||
#define PP_SelfCTL_HWStandbyE 0x0400 /* Enable standby mode */
|
||||
#define PP_SelfCTL_HC0E 0x1000 /* use HCB0 for LINK LED */
|
||||
#define PP_SelfCTL_HC1E 0x2000 /* use HCB1 for BSTATUS LED */
|
||||
#define PP_SelfCTL_HCB0 0x4000 /* control LINK LED if HC0E set */
|
||||
#define PP_SelfCTL_HCB1 0x8000 /* control BSTATUS LED if HC1E set */
|
||||
|
||||
#define PP_BusCTL 0x0116 /* Bus control */
|
||||
#define PP_BusCTL_ResetRxDMA 0x0040 /* Reset RxDMA pointer */
|
||||
#define PP_BusCTL_DMAextend 0x0100 /* Extend DMA cycle */
|
||||
#define PP_BusCTL_UseSA 0x0200 /* Assert MEMCS16 on address decode */
|
||||
#define PP_BusCTL_MemoryE 0x0400 /* Enable memory mode */
|
||||
#define PP_BusCTL_DMAburst 0x0800 /* Limit DMA access burst */
|
||||
#define PP_BusCTL_IOCHRDYE 0x1000 /* Set IOCHRDY high impedence */
|
||||
#define PP_BusCTL_RxDMAsize 0x2000 /* Set DMA buffer size 64KB */
|
||||
#define PP_BusCTL_EnableIRQ 0x8000 /* Generate interrupt on interrupt event */
|
||||
|
||||
#define PP_TestCTL 0x0118 /* Test control */
|
||||
#define PP_TestCTL_DisableLT 0x0080 /* Disable link status */
|
||||
#define PP_TestCTL_ENDECloop 0x0200 /* Internal loopback */
|
||||
#define PP_TestCTL_AUIloop 0x0400 /* AUI loopback */
|
||||
#define PP_TestCTL_DisBackoff 0x0800 /* Disable backoff algorithm */
|
||||
#define PP_TestCTL_FDX 0x4000 /* Enable full duplex mode */
|
||||
|
||||
#define PP_ISQ 0x0120 /* Interrupt Status Queue */
|
||||
|
||||
#define PP_RER 0x0124 /* Receive event */
|
||||
#define PP_RER_IAHash 0x0040 /* Frame hash match */
|
||||
#define PP_RER_Dribble 0x0080 /* Frame had 1-7 extra bits after last byte */
|
||||
#define PP_RER_RxOK 0x0100 /* Frame received with no errors */
|
||||
#define PP_RER_Hashed 0x0200 /* Frame address hashed OK */
|
||||
#define PP_RER_IA 0x0400 /* Frame address matched IA */
|
||||
#define PP_RER_Broadcast 0x0800 /* Broadcast frame */
|
||||
#define PP_RER_CRC 0x1000 /* Frame had CRC error */
|
||||
#define PP_RER_RUNT 0x2000 /* Runt frame */
|
||||
#define PP_RER_EXTRA 0x4000 /* Frame was too long */
|
||||
|
||||
#define PP_TER 0x0128 /* Transmit event */
|
||||
#define PP_TER_CRS 0x0040 /* Carrier lost */
|
||||
#define PP_TER_SQE 0x0080 /* Signal Quality Error */
|
||||
#define PP_TER_TxOK 0x0100 /* Packet sent without error */
|
||||
#define PP_TER_Late 0x0200 /* Out of window */
|
||||
#define PP_TER_Jabber 0x0400 /* Stuck transmit? */
|
||||
#define PP_TER_NumCollisions 0x7800 /* Number of collisions */
|
||||
#define PP_TER_16Collisions 0x8000 /* > 16 collisions */
|
||||
|
||||
#define PP_BER 0x012C /* Buffer event */
|
||||
#define PP_BER_SWint 0x0040 /* Software interrupt */
|
||||
#define PP_BER_RxDMAFrame 0x0080 /* Received framed DMAed */
|
||||
#define PP_BER_Rdy4Tx 0x0100 /* Ready for transmission */
|
||||
#define PP_BER_TxUnderrun 0x0200 /* Transmit underrun */
|
||||
#define PP_BER_RxMiss 0x0400 /* Received frame missed */
|
||||
#define PP_BER_Rx128 0x0800 /* 128 bytes received */
|
||||
#define PP_BER_RxDest 0x8000 /* Received framed passed address filter */
|
||||
|
||||
#define PP_RxMiss 0x0130 /* Receiver miss counter */
|
||||
|
||||
#define PP_TxCol 0x0132 /* Transmit collision counter */
|
||||
|
||||
#define PP_LineSTAT 0x0134 /* Line status */
|
||||
#define PP_LineSTAT_LinkOK 0x0080 /* Line is connected and working */
|
||||
#define PP_LineSTAT_AUI 0x0100 /* Connected via AUI */
|
||||
#define PP_LineSTAT_10BT 0x0200 /* Connected via twisted pair */
|
||||
#define PP_LineSTAT_Polarity 0x1000 /* Line polarity OK (10BT only) */
|
||||
#define PP_LineSTAT_CRS 0x4000 /* Frame being received */
|
||||
|
||||
#define PP_SelfSTAT 0x0136 /* Chip self status */
|
||||
#define PP_SelfSTAT_33VActive 0x0040 /* supply voltage is 3.3V */
|
||||
#define PP_SelfSTAT_InitD 0x0080 /* Chip initialization complete */
|
||||
#define PP_SelfSTAT_SIBSY 0x0100 /* EEPROM is busy */
|
||||
#define PP_SelfSTAT_EEPROM 0x0200 /* EEPROM present */
|
||||
#define PP_SelfSTAT_EEPROM_OK 0x0400 /* EEPROM checks out */
|
||||
#define PP_SelfSTAT_ELPresent 0x0800 /* External address latch logic available */
|
||||
#define PP_SelfSTAT_EEsize 0x1000 /* Size of EEPROM */
|
||||
|
||||
#define PP_BusSTAT 0x0138 /* Bus status */
|
||||
#define PP_BusSTAT_TxBid 0x0080 /* Tx error */
|
||||
#define PP_BusSTAT_TxRDY 0x0100 /* Ready for Tx data */
|
||||
|
||||
#define PP_TDR 0x013C /* AUI Time Domain Reflectometer */
|
||||
|
||||
/* initiate transmit registers */
|
||||
|
||||
#define PP_TxCommand 0x0144 /* Tx Command */
|
||||
#define PP_TxLength 0x0146 /* Tx Length */
|
||||
|
||||
|
||||
/* address filter registers */
|
||||
|
||||
#define PP_LAF 0x0150 /* Logical address filter (6 bytes) */
|
||||
#define PP_IA 0x0158 /* Individual address (MAC) */
|
||||
|
||||
/* EEPROM Kram */
|
||||
#define SI_BUSY 0x0100
|
||||
#define PP_EECMD 0x0040 /* NVR Interface Command register */
|
||||
#define PP_EEData 0x0042 /* NVR Interface Data Register */
|
||||
#define EEPROM_WRITE_EN 0x00F0
|
||||
#define EEPROM_WRITE_DIS 0x0000
|
||||
#define EEPROM_WRITE_CMD 0x0100
|
||||
#define EEPROM_READ_CMD 0x0200
|
||||
#define EEPROM_ERASE_CMD 0x0300
|
||||
|
||||
/* Exported functions */
|
||||
int cs8900_e2prom_read(struct eth_device *dev, uchar, ushort *);
|
||||
int cs8900_e2prom_write(struct eth_device *dev, uchar, ushort);
|
||||
|
||||
#endif /* CS8900_H */
|
||||
Loading…
Reference in New Issue
Block a user