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arm: ls1021a: Add timer_init() in board_init_f for SPL

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I2C is used to access DDR SPD in the DDR initialization for SPL. In
i2c_write process, get_timer() will be called. In board_init_f for SPL,
timer_init() is not called before. The system counter is not enabled and
the counter frequency is not set to 12.5MHz in SPL. The parameters for
do_div() are zero too.

It could not be found until CONFIG_USE_PRIVATE_LIBGCC is enabled in
default. When CONFIG_USE_PRIVATE_LIBGCC is enabled, U-Boot will use its
own set of libgcc functions. As the parameters for do_div() are zero,
__div0 will be called. Then the processor will stay in an endless loop
after calling hang().

This patch will add timer_init() in board_init_f for SPL and fix a
series of issues it caused.

Signed-off-by: Alison Wang <alison.wang@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
This commit is contained in:
Alison Wang 2018-10-16 16:19:22 +08:00 committed by York Sun
parent 71037f62ff
commit f668c52033
2 changed files with 2 additions and 0 deletions
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1
board/freescale/ls1021aqds/ls1021aqds.c
View File

@ -244,6 +244,7 @@ void board_init_f(ulong dummy)
if (major == SOC_MAJOR_VER_1_0)
out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER);
timer_init();
dram_init();
/* Allow OCRAM access permission as R/W */

1
board/freescale/ls1021atwr/ls1021atwr.c
View File

@ -467,6 +467,7 @@ void board_init_f(ulong dummy)
preloader_console_init();
timer_init();
dram_init();
/* Allow OCRAM access permission as R/W */