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Merge branch 'master' of git://www.denx.de/git/u-boot-imx

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This commit is contained in:
Tom Rini
2016-10-07 22:02:10 -04:00
parent 1f95770807 3dddc793e0
commit f5fd45ff64
70 changed files with 7233 additions and 389 deletions
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11
arch/arm/cpu/armv7/mx6/Kconfig
View File

@@ -31,6 +31,10 @@ config MX6UL
select ROM_UNIFIED_SECTIONS
bool
config MX6ULL
bool
select MX6UL
choice
prompt "MX6 board select"
optional
@@ -133,6 +137,12 @@ config TARGET_MX6UL_14X14_EVK
select DM_THERMAL
select SUPPORT_SPL
config TARGET_MX6ULL_14X14_EVK
bool "Support mx6ull_14x14_evk"
select MX6ULL
select DM
select DM_THERMAL
config TARGET_NITROGEN6X
bool "nitrogen6x"
@@ -222,6 +232,7 @@ source "board/freescale/mx6slevk/Kconfig"
source "board/freescale/mx6sxsabresd/Kconfig"
source "board/freescale/mx6sxsabreauto/Kconfig"
source "board/freescale/mx6ul_14x14_evk/Kconfig"
source "board/freescale/mx6ullevk/Kconfig"
source "board/phytec/pcm058/Kconfig"
source "board/gateworks/gw_ventana/Kconfig"
source "board/kosagi/novena/Kconfig"

59
arch/arm/cpu/armv7/mx6/clock.c
View File

@@ -97,7 +97,10 @@ void enable_enet_clk(unsigned char enable)
{
u32 mask, *addr;
if (is_mx6ul()) {
if (is_mx6ull()) {
mask = MXC_CCM_CCGR0_ENET_CLK_ENABLE_MASK;
addr = &imx_ccm->CCGR0;
} else if (is_mx6ul()) {
mask = MXC_CCM_CCGR3_ENET_MASK;
addr = &imx_ccm->CCGR3;
} else {
@@ -117,7 +120,7 @@ void enable_uart_clk(unsigned char enable)
{
u32 mask;
if (is_mx6ul())
if (is_mx6ul() || is_mx6ull())
mask = MXC_CCM_CCGR5_UART_MASK;
else
mask = MXC_CCM_CCGR5_UART_MASK | MXC_CCM_CCGR5_UART_SERIAL_MASK;
@@ -168,7 +171,7 @@ int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
reg &= ~mask;
__raw_writel(reg, &imx_ccm->CCGR2);
} else {
if (is_mx6sx() || is_mx6ul()) {
if (is_mx6sx() || is_mx6ul() || is_mx6ull()) {
mask = MXC_CCM_CCGR6_I2C4_MASK;
addr = &imx_ccm->CCGR6;
} else {
@@ -279,7 +282,7 @@ static u32 mxc_get_pll_pfd(enum pll_clocks pll, int pfd_num)
switch (pll) {
case PLL_BUS:
if (!is_mx6ul()) {
if (!is_mx6ul() && !is_mx6ull()) {
if (pfd_num == 3) {
/* No PFD3 on PLL2 */
return 0;
@@ -380,7 +383,7 @@ static u32 get_ipg_per_clk(void)
reg = __raw_readl(&imx_ccm->cscmr1);
if (is_mx6sl() || is_mx6sx() ||
is_mx6dqp() || is_mx6ul()) {
is_mx6dqp() || is_mx6ul() || is_mx6ull()) {
if (reg & MXC_CCM_CSCMR1_PER_CLK_SEL_MASK)
return MXC_HCLK; /* OSC 24Mhz */
}
@@ -396,7 +399,8 @@ static u32 get_uart_clk(void)
u32 freq = decode_pll(PLL_USBOTG, MXC_HCLK) / 6; /* static divider */
reg = __raw_readl(&imx_ccm->cscdr1);
if (is_mx6sl() || is_mx6sx() || is_mx6dqp() || is_mx6ul()) {
if (is_mx6sl() || is_mx6sx() || is_mx6dqp() || is_mx6ul() ||
is_mx6ull()) {
if (reg & MXC_CCM_CSCDR1_UART_CLK_SEL)
freq = MXC_HCLK;
}
@@ -415,7 +419,8 @@ static u32 get_cspi_clk(void)
cspi_podf = (reg & MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK) >>
MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET;
if (is_mx6dqp() || is_mx6sl() || is_mx6sx() || is_mx6ul()) {
if (is_mx6dqp() || is_mx6sl() || is_mx6sx() || is_mx6ul() ||
is_mx6ull()) {
if (reg & MXC_CCM_CSCDR2_ECSPI_CLK_SEL_MASK)
return MXC_HCLK / (cspi_podf + 1);
}
@@ -477,7 +482,7 @@ static u32 get_mmdc_ch0_clk(void)
u32 freq, podf, per2_clk2_podf, pmu_misc2_audio_div;
if (is_mx6sx() || is_mx6ul() || is_mx6sl()) {
if (is_mx6sx() || is_mx6ul() || is_mx6ull() || is_mx6sl()) {
podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH1_PODF_MASK) >>
MXC_CCM_CBCDR_MMDC_CH1_PODF_OFFSET;
if (cbcdr & MXC_CCM_CBCDR_PERIPH2_CLK_SEL) {
@@ -615,7 +620,7 @@ void mxs_set_lcdclk(u32 base_addr, u32 freq)
debug("mxs_set_lcdclk, freq = %dKHz\n", freq);
if (!is_mx6sx() && !is_mx6ul()) {
if (!is_mx6sx() && !is_mx6ul() && !is_mx6ull()) {
debug("This chip not support lcd!\n");
return;
}
@@ -749,7 +754,7 @@ int enable_lcdif_clock(u32 base_addr)
MXC_CCM_CCGR3_DISP_AXI_MASK) :
(MXC_CCM_CCGR3_LCDIF1_PIX_MASK |
MXC_CCM_CCGR3_DISP_AXI_MASK);
} else if (is_mx6ul()) {
} else if (is_mx6ul() || is_mx6ull()) {
if (base_addr != LCDIF1_BASE_ADDR) {
puts("Wrong LCD interface!\n");
return -EINVAL;
@@ -847,7 +852,7 @@ int enable_fec_anatop_clock(int fec_id, enum enet_freq freq)
reg |= BF_ANADIG_PLL_ENET_DIV_SELECT(freq);
} else if (fec_id == 1) {
/* Only i.MX6SX/UL support ENET2 */
if (!(is_mx6sx() || is_mx6ul()))
if (!(is_mx6sx() || is_mx6ul() || is_mx6ull()))
return -EINVAL;
reg &= ~BM_ANADIG_PLL_ENET2_DIV_SELECT;
reg |= BF_ANADIG_PLL_ENET2_DIV_SELECT(freq);
@@ -1069,17 +1074,27 @@ void hab_caam_clock_enable(unsigned char enable)
{
u32 reg;
/* CG4 ~ CG6, CAAM clocks */
reg = __raw_readl(&imx_ccm->CCGR0);
if (enable)
reg |= (MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK |
MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK |
MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK);
else
reg &= ~(MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK |
MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK |
MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK);
__raw_writel(reg, &imx_ccm->CCGR0);
if (is_mx6ull()) {
/* CG5, DCP clock */
reg = __raw_readl(&imx_ccm->CCGR0);
if (enable)
reg |= MXC_CCM_CCGR0_DCP_CLK_MASK;
else
reg &= ~MXC_CCM_CCGR0_DCP_CLK_MASK;
__raw_writel(reg, &imx_ccm->CCGR0);
} else {
/* CG4 ~ CG6, CAAM clocks */
reg = __raw_readl(&imx_ccm->CCGR0);
if (enable)
reg |= (MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK |
MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK |
MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK);
else
reg &= ~(MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK |
MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK |
MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK);
__raw_writel(reg, &imx_ccm->CCGR0);
}
/* EMI slow clk */
reg = __raw_readl(&imx_ccm->CCGR6);

57
arch/arm/cpu/armv7/mx6/soc.c
View File

@@ -126,7 +126,7 @@ u32 get_cpu_speed_grade_hz(void)
val >>= OCOTP_CFG3_SPEED_SHIFT;
val &= 0x3;
if (is_mx6ul()) {
if (is_mx6ul() || is_mx6ull()) {
if (val == OCOTP_CFG3_SPEED_528MHZ)
return 528000000;
else if (val == OCOTP_CFG3_SPEED_696MHZ)
@@ -293,7 +293,7 @@ static void clear_mmdc_ch_mask(void)
reg = readl(&mxc_ccm->ccdr);
/* Clear MMDC channel mask */
if (is_mx6sx() || is_mx6ul() || is_mx6sl())
if (is_mx6sx() || is_mx6ul() || is_mx6ull() || is_mx6sl())
reg &= ~(MXC_CCM_CCDR_MMDC_CH1_HS_MASK);
else
reg &= ~(MXC_CCM_CCDR_MMDC_CH1_HS_MASK | MXC_CCM_CCDR_MMDC_CH0_HS_MASK);
@@ -314,6 +314,12 @@ static void init_bandgap(void)
* be set.
*/
writel(BM_ANADIG_ANA_MISC0_REFTOP_SELBIASOFF, &anatop->ana_misc0_set);
/*
* On i.MX6ULL, the LDO 1.2V bandgap voltage is 30mV higher. so set
* VBGADJ bits to 2b'110 to adjust it.
*/
if (is_mx6ull())
writel(BM_ANADIG_ANA_MISC0_REFTOP_VBGADJ, &anatop->ana_misc0_set);
}
@@ -343,7 +349,7 @@ int arch_cpu_init(void)
*/
init_bandgap();
if (!IS_ENABLED(CONFIG_MX6UL)) {
if (!is_mx6ul() && !is_mx6ull()) {
/*
* When low freq boot is enabled, ROM will not set AHB
* freq, so we need to ensure AHB freq is 132MHz in such
@@ -356,14 +362,41 @@ int arch_cpu_init(void)
set_ahb_rate(132000000);
}
if (IS_ENABLED(CONFIG_MX6UL) && is_soc_rev(CHIP_REV_1_0) == 0) {
if (is_mx6ul()) {
if (is_soc_rev(CHIP_REV_1_0) == 0) {
/*
* According to the design team's requirement on
* i.MX6UL,the PMIC_STBY_REQ PAD should be configured
* as open drain 100K (0x0000b8a0).
* Only exists on TO1.0
*/
writel(0x0000b8a0, IOMUXC_BASE_ADDR + 0x29c);
} else {
/*
* From TO1.1, SNVS adds internal pull up control
* for POR_B, the register filed is GPBIT[1:0],
* after system boot up, it can be set to 2b'01
* to disable internal pull up.It can save about
* 30uA power in SNVS mode.
*/
writel((readl(MX6UL_SNVS_LP_BASE_ADDR + 0x10) &
(~0x1400)) | 0x400,
MX6UL_SNVS_LP_BASE_ADDR + 0x10);
}
}
if (is_mx6ull()) {
/*
* According to the design team's requirement on i.MX6UL,
* the PMIC_STBY_REQ PAD should be configured as open
* drain 100K (0x0000b8a0).
* Only exists on TO1.0
* GPBIT[1:0] is suggested to set to 2'b11:
* 2'b00 : always PUP100K
* 2'b01 : PUP100K when PMIC_ON_REQ or SOC_NOT_FAIL
* 2'b10 : always disable PUP100K
* 2'b11 : PDN100K when SOC_FAIL, PUP100K when SOC_NOT_FAIL
* register offset is different from i.MX6UL, since
* i.MX6UL is fixed by ECO.
*/
writel(0x0000b8a0, IOMUXC_BASE_ADDR + 0x29c);
writel(readl(MX6UL_SNVS_LP_BASE_ADDR) |
0x3, MX6UL_SNVS_LP_BASE_ADDR);
}
/* Set perclk to source from OSC 24MHz */
@@ -459,7 +492,7 @@ void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
struct fuse_bank4_regs *fuse =
(struct fuse_bank4_regs *)bank->fuse_regs;
if ((is_mx6sx() || is_mx6ul()) && dev_id == 1) {
if ((is_mx6sx() || is_mx6ul() || is_mx6ull()) && dev_id == 1) {
u32 value = readl(&fuse->mac_addr2);
mac[0] = value >> 24 ;
mac[1] = value >> 16 ;
@@ -494,7 +527,7 @@ void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
const struct boot_mode soc_boot_modes[] = {
{"normal", MAKE_CFGVAL(0x00, 0x00, 0x00, 0x00)},
/* reserved value should start rom usb */
{"usb", MAKE_CFGVAL(0x01, 0x00, 0x00, 0x00)},
{"usb", MAKE_CFGVAL(0x10, 0x00, 0x00, 0x00)},
{"sata", MAKE_CFGVAL(0x20, 0x00, 0x00, 0x00)},
{"ecspi1:0", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x08)},
{"ecspi1:1", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x18)},
@@ -523,7 +556,7 @@ void s_init(void)
u32 mask528;
u32 reg, periph1, periph2;
if (is_mx6sx() || is_mx6ul())
if (is_mx6sx() || is_mx6ul() || is_mx6ull())
return;
/* Due to hardware limitation, on MX6Q we need to gate/ungate all PFDs

5
arch/arm/cpu/armv7/vf610/Makefile
View File

@@ -6,3 +6,8 @@
obj-y += generic.o
obj-y += timer.o
MKIMAGEFLAGS_u-boot.vyb = -T vybridimage
u-boot.vyb: u-boot.imx
$(call if_changed,mkimage)

2
arch/arm/cpu/armv7/vf610/generic.c
View File

@@ -322,7 +322,7 @@ int arch_misc_init(void)
{
char soc[6];
strcat(soc, "vf");
strcpy(soc, "vf");
strcat(soc, soc_type);
setenv("soc", soc);