arm: ls1021atwr: Convert to use driver model TSEC driver
Now that we have added driver model support to the TSEC driver, convert ls1021atwr board to use it. This depends on previous DM series for ls1021atwr: http://patchwork.ozlabs.org/patch/561855/ Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Vladimir Oltean <olteanv@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> [Vladimir] Made the following changes: - Added 'status = "disabled";' for all Ethernet ports in ls1021a.dtsi - Fixed the confusion between the SGMII/TBI PCS for enet0 and enet1 - a mistake ported over from Linux. Each SGMII PCS lies on the private MDIO bus of the interface (and the RGMII enet2 has no SGMII PCS). - Added CONFIG_DM_ETH to all ls1021atwr_* defconfigs - Completely removed non-DM_ETH support from ls1021atwr - Changed "compatible" string from "fsl,tsec-mdio" to "fsl,etsec2-mdio" and from "fsl,tsec" to "fsl,etsec2" to match Linux
This commit is contained in:
Bin Meng
Joe Hershberger
parent
1c8ad08674
commit
f588b4d205
@ -296,7 +296,7 @@ int cpu_mmc_init(bd_t *bis)
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int cpu_eth_init(bd_t *bis)
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{
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#ifdef CONFIG_TSEC_ENET
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#if defined(CONFIG_TSEC_ENET) && !defined(CONFIG_DM_ETH)
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tsec_standard_init(bis);
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#endif
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@ -16,12 +16,17 @@
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#include <tsec.h>
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#include <asm/arch/immap_ls102xa.h>
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#include <fsl_sec.h>
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#include <dm.h>
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DECLARE_GLOBAL_DATA_PTR;
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void ft_fixup_enet_phy_connect_type(void *fdt)
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{
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#ifdef CONFIG_DM_ETH
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struct udevice *dev;
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#else
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struct eth_device *dev;
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#endif
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struct tsec_private *priv;
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const char *enet_path, *phy_path;
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char enet[16];
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@ -29,7 +34,12 @@ void ft_fixup_enet_phy_connect_type(void *fdt)
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int phy_node;
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int i = 0;
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uint32_t ph;
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#ifdef CONFIG_DM_ETH
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char *name[3] = { "ethernet@2d10000", "ethernet@2d50000",
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"ethernet@2d90000" };
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#else
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char *name[3] = { "eTSEC1", "eTSEC2", "eTSEC3" };
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#endif
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for (; i < ARRAY_SIZE(name); i++) {
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dev = eth_get_dev_by_name(name[i]);
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@ -51,6 +51,26 @@
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};
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};
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&enet0 {
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tbi-handle = <&tbi0>;
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phy-handle = <&sgmii_phy2>;
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phy-connection-type = "sgmii";
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status = "okay";
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};
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&enet1 {
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tbi-handle = <&tbi1>;
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phy-handle = <&sgmii_phy0>;
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phy-connection-type = "sgmii";
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status = "okay";
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};
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&enet2 {
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phy-handle = <&rgmii_phy1>;
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phy-connection-type = "rgmii-id";
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status = "okay";
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};
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&i2c0 {
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status = "okay";
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};
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@ -84,12 +104,24 @@
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sgmii_phy0: ethernet-phy@0 {
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reg = <0x0>;
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};
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rgmii_phy1: ethernet-phy@1 {
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reg = <0x1>;
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};
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sgmii_phy2: ethernet-phy@2 {
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reg = <0x2>;
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};
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/* SGMII PCS for enet0 */
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tbi0: tbi-phy@1f {
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reg = <0x1f>;
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device_type = "tbi-phy";
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};
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};
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&mdio1 {
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/* SGMII PCS for enet1 */
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tbi1: tbi-phy@1f {
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reg = <0x1f>;
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device_type = "tbi-phy";
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@ -350,12 +350,36 @@
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<&platform_clk 1>;
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};
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enet0: ethernet@2d10000 {
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compatible = "fsl,etsec2";
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reg = <0x2d10000 0x1000>;
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status = "disabled";
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};
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enet1: ethernet@2d50000 {
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compatible = "fsl,etsec2";
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reg = <0x2d50000 0x1000>;
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status = "disabled";
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};
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enet2: ethernet@2d90000 {
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compatible = "fsl,etsec2";
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reg = <0x2d90000 0x1000>;
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status = "disabled";
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};
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mdio0: mdio@2d24000 {
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compatible = "gianfar";
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device_type = "mdio";
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compatible = "fsl,etsec2-mdio";
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reg = <0x2d24000 0x4000>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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mdio1: mdio@2d64000 {
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compatible = "fsl,etsec2-mdio";
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reg = <0x2d64000 0x4000>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x2d24000 0x4000>;
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};
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usb@8600000 {
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@ -248,44 +248,6 @@ int board_mmc_init(bd_t *bis)
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int board_eth_init(bd_t *bis)
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{
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#ifdef CONFIG_TSEC_ENET
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struct fsl_pq_mdio_info mdio_info;
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struct tsec_info_struct tsec_info[4];
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int num = 0;
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#ifdef CONFIG_TSEC1
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SET_STD_TSEC_INFO(tsec_info[num], 1);
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if (is_serdes_configured(SGMII_TSEC1)) {
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puts("eTSEC1 is in sgmii mode.\n");
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tsec_info[num].flags |= TSEC_SGMII;
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}
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num++;
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#endif
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#ifdef CONFIG_TSEC2
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SET_STD_TSEC_INFO(tsec_info[num], 2);
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if (is_serdes_configured(SGMII_TSEC2)) {
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puts("eTSEC2 is in sgmii mode.\n");
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tsec_info[num].flags |= TSEC_SGMII;
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}
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num++;
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#endif
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#ifdef CONFIG_TSEC3
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SET_STD_TSEC_INFO(tsec_info[num], 3);
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tsec_info[num].interface = PHY_INTERFACE_MODE_RGMII_ID;
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num++;
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#endif
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if (!num) {
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printf("No TSECs initialized\n");
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return 0;
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}
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mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
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mdio_info.name = DEFAULT_MII_NAME;
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fsl_pq_mdio_init(bis, &mdio_info);
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tsec_eth_init(bis, tsec_info, num);
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#endif
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return pci_eth_init(bis);
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}
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@ -40,7 +40,9 @@ CONFIG_SYS_FLASH_CFI=y
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CONFIG_PHY_GIGE=y
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CONFIG_E1000=y
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CONFIG_MII=y
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CONFIG_DM_ETH=y
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CONFIG_TSEC_ENET=y
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CONFIG_PHY_ATHEROS=y
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CONFIG_PCI=y
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CONFIG_DM_PCI=y
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CONFIG_DM_PCI_COMPAT=y
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@ -40,7 +40,9 @@ CONFIG_SYS_FLASH_CFI=y
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CONFIG_PHY_GIGE=y
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CONFIG_E1000=y
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CONFIG_MII=y
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CONFIG_DM_ETH=y
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CONFIG_TSEC_ENET=y
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CONFIG_PHY_ATHEROS=y
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CONFIG_PCI=y
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CONFIG_DM_PCI=y
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CONFIG_DM_PCI_COMPAT=y
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@ -42,7 +42,9 @@ CONFIG_SYS_FLASH_CFI=y
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CONFIG_PHY_GIGE=y
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CONFIG_E1000=y
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CONFIG_MII=y
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CONFIG_DM_ETH=y
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CONFIG_TSEC_ENET=y
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CONFIG_PHY_ATHEROS=y
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CONFIG_PCI=y
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CONFIG_DM_PCI=y
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CONFIG_DM_PCI_COMPAT=y
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@ -42,7 +42,9 @@ CONFIG_SPI_FLASH_STMICRO=y
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CONFIG_PHY_GIGE=y
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CONFIG_E1000=y
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CONFIG_MII=y
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CONFIG_DM_ETH=y
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CONFIG_TSEC_ENET=y
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CONFIG_PHY_ATHEROS=y
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CONFIG_PCI=y
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CONFIG_DM_PCI=y
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CONFIG_DM_PCI_COMPAT=y
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@ -53,7 +53,9 @@ CONFIG_SYS_FLASH_CFI=y
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CONFIG_PHY_GIGE=y
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CONFIG_E1000=y
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CONFIG_MII=y
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CONFIG_DM_ETH=y
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CONFIG_TSEC_ENET=y
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CONFIG_PHY_ATHEROS=y
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CONFIG_PCI=y
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CONFIG_DM_PCI=y
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CONFIG_DM_PCI_COMPAT=y
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@ -54,7 +54,9 @@ CONFIG_SYS_FLASH_CFI=y
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CONFIG_PHY_GIGE=y
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CONFIG_E1000=y
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CONFIG_MII=y
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CONFIG_DM_ETH=y
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CONFIG_TSEC_ENET=y
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CONFIG_PHY_ATHEROS=y
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CONFIG_PCI=y
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CONFIG_DM_PCI=y
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CONFIG_DM_PCI_COMPAT=y
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@ -53,7 +53,9 @@ CONFIG_SPI_FLASH_STMICRO=y
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CONFIG_PHY_GIGE=y
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CONFIG_E1000=y
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CONFIG_MII=y
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CONFIG_DM_ETH=y
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CONFIG_TSEC_ENET=y
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CONFIG_PHY_ATHEROS=y
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CONFIG_PCI=y
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CONFIG_DM_PCI=y
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CONFIG_DM_PCI_COMPAT=y
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@ -260,33 +260,7 @@
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*/
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#ifdef CONFIG_TSEC_ENET
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#define CONFIG_MII_DEFAULT_TSEC 1
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#define CONFIG_TSEC1 1
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#define CONFIG_TSEC1_NAME "eTSEC1"
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#define CONFIG_TSEC2 1
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#define CONFIG_TSEC2_NAME "eTSEC2"
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#define CONFIG_TSEC3 1
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#define CONFIG_TSEC3_NAME "eTSEC3"
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#define TSEC1_PHY_ADDR 2
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#define TSEC2_PHY_ADDR 0
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#define TSEC3_PHY_ADDR 1
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#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
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#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
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#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
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#define TSEC1_PHYIDX 0
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#define TSEC2_PHYIDX 0
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#define TSEC3_PHYIDX 0
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#define CONFIG_ETHPRIME "eTSEC1"
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#define CONFIG_PHY_ATHEROS
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#define CONFIG_HAS_ETH0
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#define CONFIG_HAS_ETH1
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#define CONFIG_HAS_ETH2
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#define CONFIG_ETHPRIME "ethernet@2d10000"
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#endif
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/* PCIe */
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