leandrof/u-boot
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

ppc4xx: Sequoia: Remove cpu/ppc4xx/speed.c from NAND booting

Browse Source 
Using cpu/ppc4xx/speed.c to calculate the bus frequency is too big
for the 4k NAND boot image so define bus_frequency to 133MHz here
which is save for the refresh counter setup.

Signed-off-by: Stefan Roese <sr@denx.de>
This commit is contained in:
Stefan Roese 2007-05-05 08:29:01 +02:00
parent bd38b7ecfd
commit f544ff6656
2 changed files with 10 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
board/amcc/sequoia/sdram.c
View File

@ -371,6 +371,14 @@ void denali_core_search_data_eye(unsigned long memory_size)
}
#endif /* CONFIG_DDR_DATA_EYE */
#if defined(CONFIG_NAND_SPL)
/* Using cpu/ppc4xx/speed.c to calculate the bus frequency is too big
* for the 4k NAND boot image so define bus_frequency to 133MHz here
* which is save for the refresh counter setup.
*/
#define get_bus_freq(val) 133000000
#endif
/*************************************************************************
*
* initdram -- 440EPx's DDR controller is a DENALI Core
@ -404,7 +412,7 @@ long int initdram (int board_type)
mtsdram(DDR0_22, 0x00267F0B);
mtsdram(DDR0_23, 0x00000000);
mtsdram(DDR0_24, 0x01010002);
if (speed > 133333333)
if (speed > 133333334)
mtsdram(DDR0_26, 0x5B26050C);
else
mtsdram(DDR0_26, 0x5B260408);

6
nand_spl/board/amcc/sequoia/Makefile
View File

@ -30,7 +30,7 @@ AFLAGS += -DCONFIG_NAND_SPL
CFLAGS += -DCONFIG_NAND_SPL
SOBJS = start.o init.o resetvec.o
COBJS = nand_boot.o ndfc.o sdram.o speed.o
COBJS = nand_boot.o ndfc.o sdram.o
SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c))
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
@ -69,10 +69,6 @@ $(obj)start.S:
@rm -f $(obj)start.S
ln -s $(SRCTREE)/cpu/ppc4xx/start.S $(obj)start.S
$(obj)speed.c:
@rm -f $(obj)speed.c
ln -s $(SRCTREE)/cpu/ppc4xx/speed.c $(obj)speed.c
# from board directory
$(obj)init.S:
@rm -f $(obj)init.S