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83xx/85xx/86xx: LBC register cleanup

Browse Source 
Currently, 83xx, 86xx, and 85xx have a lot of duplicated code
dedicated to defining and manipulating the LBC registers.  Merge
this into a single spot.

To do this, we have to decide on a common name for the data structure
that holds the lbc registers - it will now be known as fsl_lbc_t, and we
adopt a common name for the immap layouts that include the lbc - this was
previously known as either im_lbc or lbus; use the former.

In addition, create accessors for the BR/OR regs that use in/out_be32
and use those instead of the mismash of access methods currently in play.

I have done a successful ppc build all and tested a board or two from
each processor family.

Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
Acked-by: Kim Phillips <kim.phillips@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This commit is contained in:
Becky Bruce 2010-06-17 11:37:20 -05:00 committed by Kumar Gala
parent 0914f48328
commit f51cdaf191
52 changed files with 317 additions and 499 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

12
arch/powerpc/cpu/mpc83xx/cpu.c
View File

@ -157,16 +157,16 @@ int checkcpu(void)
void upmconfig (uint upm, uint *table, uint size)
{
volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
volatile fsl_lbus_t *lbus = &immap->lbus;
volatile fsl_lbc_t *lbc = &immap->im_lbc;
volatile uchar *dummy = NULL;
const u32 msel = (upm + 4) << BR_MSEL_SHIFT; /* What the MSEL field in BRn should be */
volatile u32 *mxmr = &lbus->mamr + upm; /* Pointer to mamr, mbmr, or mcmr */
volatile u32 *mxmr = &lbc->mamr + upm; /* ptr to mamr, mbmr, or mcmr */
uint i;
/* Scan all the banks to determine the base address of the device */
/* Find the address for the dummy write transaction */
for (i = 0; i < 8; i++) {
if ((lbus->bank[i].br & BR_MSEL) == msel) {
dummy = (uchar *) (lbus->bank[i].br & BR_BA);
if ((get_lbc_br(i) & BR_MSEL) == msel) {
dummy = (uchar *) (get_lbc_br(i) & BR_BA);
break;
}
}
@ -180,7 +180,7 @@ void upmconfig (uint upm, uint *table, uint size)
*mxmr = (*mxmr & 0xCFFFFFC0) | 0x10000000;
for (i = 0; i < size; i++) {
lbus->mdr = table[i];
lbc->mdr = table[i];
__asm__ __volatile__ ("sync");
*dummy = 0; /* Write the value to memory and increment MAD */
__asm__ __volatile__ ("sync");

53
arch/powerpc/cpu/mpc83xx/cpu_init.c
View File

@ -236,8 +236,8 @@ void cpu_init_f (volatile immap_t * im)
/* LCRR - Clock Ratio Register (10.3.1.16)
* write, read, and isync per MPC8379ERM rev.1 CLKDEV field description
*/
clrsetbits_be32(&im->lbus.lcrr, lcrr_mask, lcrr_val);
__raw_readl(&im->lbus.lcrr);
clrsetbits_be32(&im->im_lbc.lcrr, lcrr_mask, lcrr_val);
__raw_readl(&im->im_lbc.lcrr);
isync();
/* Enable Time Base & Decrementer ( so we will have udelay() )*/
@ -267,80 +267,41 @@ void cpu_init_f (volatile immap_t * im)
/* Config QE ioports */
config_qe_ioports();
#endif
/* Set up preliminary BR/OR regs */
init_early_memctl_regs();
/*
* Memory Controller:
*/
/* Map banks 0 and 1 to the FLASH banks 0 and 1 at preliminary
* addresses - these have to be modified later when FLASH size
* has been determined
*/
#if defined(CONFIG_SYS_BR0_PRELIM) \
&& defined(CONFIG_SYS_OR0_PRELIM) \
&& defined(CONFIG_SYS_LBLAWBAR0_PRELIM) \
&& defined(CONFIG_SYS_LBLAWAR0_PRELIM)
im->lbus.bank[0].br = CONFIG_SYS_BR0_PRELIM;
im->lbus.bank[0].or = CONFIG_SYS_OR0_PRELIM;
/* Local Access window setup */
#if defined(CONFIG_SYS_LBLAWBAR0_PRELIM) && defined(CONFIG_SYS_LBLAWAR0_PRELIM)
im->sysconf.lblaw[0].bar = CONFIG_SYS_LBLAWBAR0_PRELIM;
im->sysconf.lblaw[0].ar = CONFIG_SYS_LBLAWAR0_PRELIM;
#else
#error CONFIG_SYS_BR0_PRELIM, CONFIG_SYS_OR0_PRELIM, CONFIG_SYS_LBLAWBAR0_PRELIM & CONFIG_SYS_LBLAWAR0_PRELIM must be defined
#error CONFIG_SYS_LBLAWBAR0_PRELIM & CONFIG_SYS_LBLAWAR0_PRELIM must be defined
#endif
#if defined(CONFIG_SYS_BR1_PRELIM) && defined(CONFIG_SYS_OR1_PRELIM)
im->lbus.bank[1].br = CONFIG_SYS_BR1_PRELIM;
im->lbus.bank[1].or = CONFIG_SYS_OR1_PRELIM;
#endif
#if defined(CONFIG_SYS_LBLAWBAR1_PRELIM) && defined(CONFIG_SYS_LBLAWAR1_PRELIM)
im->sysconf.lblaw[1].bar = CONFIG_SYS_LBLAWBAR1_PRELIM;
im->sysconf.lblaw[1].ar = CONFIG_SYS_LBLAWAR1_PRELIM;
#endif
#if defined(CONFIG_SYS_BR2_PRELIM) && defined(CONFIG_SYS_OR2_PRELIM)
im->lbus.bank[2].br = CONFIG_SYS_BR2_PRELIM;
im->lbus.bank[2].or = CONFIG_SYS_OR2_PRELIM;
#endif
#if defined(CONFIG_SYS_LBLAWBAR2_PRELIM) && defined(CONFIG_SYS_LBLAWAR2_PRELIM)
im->sysconf.lblaw[2].bar = CONFIG_SYS_LBLAWBAR2_PRELIM;
im->sysconf.lblaw[2].ar = CONFIG_SYS_LBLAWAR2_PRELIM;
#endif
#if defined(CONFIG_SYS_BR3_PRELIM) && defined(CONFIG_SYS_OR3_PRELIM)
im->lbus.bank[3].br = CONFIG_SYS_BR3_PRELIM;
im->lbus.bank[3].or = CONFIG_SYS_OR3_PRELIM;
#endif
#if defined(CONFIG_SYS_LBLAWBAR3_PRELIM) && defined(CONFIG_SYS_LBLAWAR3_PRELIM)
im->sysconf.lblaw[3].bar = CONFIG_SYS_LBLAWBAR3_PRELIM;
im->sysconf.lblaw[3].ar = CONFIG_SYS_LBLAWAR3_PRELIM;
#endif
#if defined(CONFIG_SYS_BR4_PRELIM) && defined(CONFIG_SYS_OR4_PRELIM)
im->lbus.bank[4].br = CONFIG_SYS_BR4_PRELIM;
im->lbus.bank[4].or = CONFIG_SYS_OR4_PRELIM;
#endif
#if defined(CONFIG_SYS_LBLAWBAR4_PRELIM) && defined(CONFIG_SYS_LBLAWAR4_PRELIM)
im->sysconf.lblaw[4].bar = CONFIG_SYS_LBLAWBAR4_PRELIM;
im->sysconf.lblaw[4].ar = CONFIG_SYS_LBLAWAR4_PRELIM;
#endif
#if defined(CONFIG_SYS_BR5_PRELIM) && defined(CONFIG_SYS_OR5_PRELIM)
im->lbus.bank[5].br = CONFIG_SYS_BR5_PRELIM;
im->lbus.bank[5].or = CONFIG_SYS_OR5_PRELIM;
#endif
#if defined(CONFIG_SYS_LBLAWBAR5_PRELIM) && defined(CONFIG_SYS_LBLAWAR5_PRELIM)
im->sysconf.lblaw[5].bar = CONFIG_SYS_LBLAWBAR5_PRELIM;
im->sysconf.lblaw[5].ar = CONFIG_SYS_LBLAWAR5_PRELIM;
#endif
#if defined(CONFIG_SYS_BR6_PRELIM) && defined(CONFIG_SYS_OR6_PRELIM)
im->lbus.bank[6].br = CONFIG_SYS_BR6_PRELIM;
im->lbus.bank[6].or = CONFIG_SYS_OR6_PRELIM;
#endif
#if defined(CONFIG_SYS_LBLAWBAR6_PRELIM) && defined(CONFIG_SYS_LBLAWAR6_PRELIM)
im->sysconf.lblaw[6].bar = CONFIG_SYS_LBLAWBAR6_PRELIM;
im->sysconf.lblaw[6].ar = CONFIG_SYS_LBLAWAR6_PRELIM;
#endif
#if defined(CONFIG_SYS_BR7_PRELIM) && defined(CONFIG_SYS_OR7_PRELIM)
im->lbus.bank[7].br = CONFIG_SYS_BR7_PRELIM;
im->lbus.bank[7].or = CONFIG_SYS_OR7_PRELIM;
#endif
#if defined(CONFIG_SYS_LBLAWBAR7_PRELIM) && defined(CONFIG_SYS_LBLAWAR7_PRELIM)
im->sysconf.lblaw[7].bar = CONFIG_SYS_LBLAWBAR7_PRELIM;
im->sysconf.lblaw[7].ar = CONFIG_SYS_LBLAWAR7_PRELIM;

4
arch/powerpc/cpu/mpc83xx/nand_init.c
View File

@ -88,8 +88,8 @@ void cpu_init_f (volatile immap_t * im)
&& defined(CONFIG_SYS_NAND_OR_PRELIM) \
&& defined(CONFIG_SYS_NAND_LBLAWBAR_PRELIM) \
&& defined(CONFIG_SYS_NAND_LBLAWAR_PRELIM)
im->lbus.bank[0].br = CONFIG_SYS_NAND_BR_PRELIM;
im->lbus.bank[0].or = CONFIG_SYS_NAND_OR_PRELIM;
set_lbc_br(0, CONFIG_SYS_NAND_BR_PRELIM);
set_lbc_or(0, CONFIG_SYS_NAND_OR_PRELIM);
im->sysconf.lblaw[0].bar = CONFIG_SYS_NAND_LBLAWBAR_PRELIM;
im->sysconf.lblaw[0].ar = CONFIG_SYS_NAND_LBLAWAR_PRELIM;
#else

2
arch/powerpc/cpu/mpc83xx/speed.c
View File

@ -393,7 +393,7 @@ int get_clocks(void)
lbiu_clk = csb_clk *
(1 + ((im->reset.rcwl & HRCWL_LBIUCM) >> HRCWL_LBIUCM_SHIFT));
lcrr = (im->lbus.lcrr & LCRR_CLKDIV) >> LCRR_CLKDIV_SHIFT;
lcrr = (im->im_lbc.lcrr & LCRR_CLKDIV) >> LCRR_CLKDIV_SHIFT;
switch (lcrr) {
case 2:
case 4:

12
arch/powerpc/cpu/mpc85xx/cpu.c
View File

@ -257,8 +257,7 @@ void upmconfig (uint upm, uint * table, uint size)
{
int i, mdr, mad, old_mad = 0;
volatile u32 *mxmr;
volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
volatile u32 *brp,*orp;
volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
volatile u8* dummy = NULL;
int upmmask;
@ -281,12 +280,9 @@ void upmconfig (uint upm, uint * table, uint size)
}
/* Find the address for the dummy write transaction */
for (brp = &lbc->br0, orp = &lbc->or0, i = 0; i < 8;
i++, brp += 2, orp += 2) {
/* Look for a valid BR with selected UPM */
if ((in_be32(brp) & (BR_V | BR_MSEL)) == (BR_V | upmmask)) {
dummy = (volatile u8*)(in_be32(brp) & BR_BA);
for (i = 0; i < 8; i++) {
if ((get_lbc_br(i) & (BR_V | BR_MSEL)) == (BR_V | upmmask)) {
dummy = (volatile u8 *)(get_lbc_br(i) & BR_BA);
break;
}
}

58
arch/powerpc/cpu/mpc85xx/cpu_init.c
View File

@ -154,7 +154,6 @@ static void corenet_tb_init(void)
void cpu_init_f (void)
{
volatile ccsr_lbc_t *memctl = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
extern void m8560_cpm_reset (void);
#ifdef CONFIG_MPC8548
ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
@ -177,60 +176,7 @@ void cpu_init_f (void)
config_8560_ioports((ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR);
#endif
/* Map banks 0 and 1 to the FLASH banks 0 and 1 at preliminary
* addresses - these have to be modified later when FLASH size
* has been determined
*/
#if defined(CONFIG_SYS_OR0_REMAP)
out_be32(&memctl->or0, CONFIG_SYS_OR0_REMAP);
#endif
#if defined(CONFIG_SYS_OR1_REMAP)
out_be32(&memctl->or1, CONFIG_SYS_OR1_REMAP);
#endif
/* now restrict to preliminary range */
/* if cs1 is already set via debugger, leave cs0/cs1 alone */
if (! memctl->br1 & 1) {
#if defined(CONFIG_SYS_BR0_PRELIM) && defined(CONFIG_SYS_OR0_PRELIM)
out_be32(&memctl->br0, CONFIG_SYS_BR0_PRELIM);
out_be32(&memctl->or0, CONFIG_SYS_OR0_PRELIM);
#endif
#if defined(CONFIG_SYS_BR1_PRELIM) && defined(CONFIG_SYS_OR1_PRELIM)
out_be32(&memctl->or1, CONFIG_SYS_OR1_PRELIM);
out_be32(&memctl->br1, CONFIG_SYS_BR1_PRELIM);
#endif
}
#if defined(CONFIG_SYS_BR2_PRELIM) && defined(CONFIG_SYS_OR2_PRELIM)
out_be32(&memctl->or2, CONFIG_SYS_OR2_PRELIM);
out_be32(&memctl->br2, CONFIG_SYS_BR2_PRELIM);
#endif
#if defined(CONFIG_SYS_BR3_PRELIM) && defined(CONFIG_SYS_OR3_PRELIM)
out_be32(&memctl->or3, CONFIG_SYS_OR3_PRELIM);
out_be32(&memctl->br3, CONFIG_SYS_BR3_PRELIM);
#endif
#if defined(CONFIG_SYS_BR4_PRELIM) && defined(CONFIG_SYS_OR4_PRELIM)
out_be32(&memctl->or4, CONFIG_SYS_OR4_PRELIM);
out_be32(&memctl->br4, CONFIG_SYS_BR4_PRELIM);
#endif
#if defined(CONFIG_SYS_BR5_PRELIM) && defined(CONFIG_SYS_OR5_PRELIM)
out_be32(&memctl->or5, CONFIG_SYS_OR5_PRELIM);
out_be32(&memctl->br5, CONFIG_SYS_BR5_PRELIM);
#endif
#if defined(CONFIG_SYS_BR6_PRELIM) && defined(CONFIG_SYS_OR6_PRELIM)
out_be32(&memctl->or6, CONFIG_SYS_OR6_PRELIM);
out_be32(&memctl->br6, CONFIG_SYS_BR6_PRELIM);
#endif
#if defined(CONFIG_SYS_BR7_PRELIM) && defined(CONFIG_SYS_OR7_PRELIM)
out_be32(&memctl->or7, CONFIG_SYS_OR7_PRELIM);
out_be32(&memctl->br7, CONFIG_SYS_BR7_PRELIM);
#endif
init_early_memctl_regs();
#if defined(CONFIG_CPM2)
m8560_cpm_reset();
@ -263,7 +209,7 @@ void cpu_init_f (void)
int cpu_init_r(void)
{
#ifdef CONFIG_SYS_LBC_LCRR
volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
#endif
puts ("L2: ");

6
arch/powerpc/cpu/mpc85xx/cpu_init_nand.c
View File

@ -25,7 +25,7 @@
void cpu_init_f(void)
{
ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
fsl_lbc_t *lbc = LBC_BASE_ADDR;
/*
* LCRR - Clock Ratio Register - set up local bus timing
@ -34,8 +34,8 @@ void cpu_init_f(void)
out_be32(&lbc->lcrr, LCRR_DBYP | LCRR_CLKDIV_8);
#if defined(CONFIG_NAND_BR_PRELIM) && defined(CONFIG_NAND_OR_PRELIM)
out_be32(&lbc->br0, CONFIG_NAND_BR_PRELIM);
out_be32(&lbc->or0, CONFIG_NAND_OR_PRELIM);
set_lbc_br(0, CONFIG_NAND_BR_PRELIM);
set_lbc_or(0, CONFIG_NAND_OR_PRELIM);
#else
#error CONFIG_NAND_BR_PRELIM, CONFIG_NAND_OR_PRELIM must be defined
#endif

5
arch/powerpc/cpu/mpc85xx/speed.c
View File

@ -172,10 +172,7 @@ void get_sys_info (sys_info_t * sysInfo)
/* We will program LCRR to this value later */
lcrr_div = CONFIG_SYS_LBC_LCRR & LCRR_CLKDIV;
#else
{
volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
lcrr_div = in_be32(&lbc->lcrr) & LCRR_CLKDIV;
}
lcrr_div = in_be32(&(LBC_BASE_ADDR)->lcrr) & LCRR_CLKDIV;
#endif
if (lcrr_div == 2 || lcrr_div == 4 || lcrr_div == 8) {
#if defined(CONFIG_FSL_CORENET)

15
arch/powerpc/cpu/mpc86xx/cpu.c
View File

@ -180,22 +180,9 @@ watchdog_reset(void)
*/
void mpc86xx_reginfo(void)
{
immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
ccsr_lbc_t *lbc = &immap->im_lbc;
print_bats();
print_laws();
printf ("Local Bus Controller Registers\n"
"\tBR0\t0x%08X\tOR0\t0x%08X \n", in_be32(&lbc->br0), in_be32(&lbc->or0));
printf("\tBR1\t0x%08X\tOR1\t0x%08X \n", in_be32(&lbc->br1), in_be32(&lbc->or1));
printf("\tBR2\t0x%08X\tOR2\t0x%08X \n", in_be32(&lbc->br2), in_be32(&lbc->or2));
printf("\tBR3\t0x%08X\tOR3\t0x%08X \n", in_be32(&lbc->br3), in_be32(&lbc->or3));
printf("\tBR4\t0x%08X\tOR4\t0x%08X \n", in_be32(&lbc->br4), in_be32(&lbc->or4));
printf("\tBR5\t0x%08X\tOR5\t0x%08X \n", in_be32(&lbc->br5), in_be32(&lbc->or5));
printf("\tBR6\t0x%08X\tOR6\t0x%08X \n", in_be32(&lbc->br6), in_be32(&lbc->or6));
printf("\tBR7\t0x%08X\tOR7\t0x%08X \n", in_be32(&lbc->br7), in_be32(&lbc->or7));
print_lbc_regs();
}
/*

55
arch/powerpc/cpu/mpc86xx/cpu_init.c
View File

@ -46,9 +46,6 @@ DECLARE_GLOBAL_DATA_PTR;
void cpu_init_f(void)
{
volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
volatile ccsr_lbc_t *memctl = &immap->im_lbc;
/* Pointer is writable since we allocated a register for it */
gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
@ -61,58 +58,8 @@ void cpu_init_f(void)
setup_bats();
/* Map banks 0 and 1 to the FLASH banks 0 and 1 at preliminary
* addresses - these have to be modified later when FLASH size
* has been determined
*/
init_early_memctl_regs();
#if defined(CONFIG_SYS_OR0_REMAP)
memctl->or0 = CONFIG_SYS_OR0_REMAP;
#endif
#if defined(CONFIG_SYS_OR1_REMAP)
memctl->or1 = CONFIG_SYS_OR1_REMAP;
#endif
/* now restrict to preliminary range */
#if defined(CONFIG_SYS_BR0_PRELIM) && defined(CONFIG_SYS_OR0_PRELIM)
memctl->br0 = CONFIG_SYS_BR0_PRELIM;
memctl->or0 = CONFIG_SYS_OR0_PRELIM;
#endif
#if defined(CONFIG_SYS_BR1_PRELIM) && defined(CONFIG_SYS_OR1_PRELIM)
memctl->or1 = CONFIG_SYS_OR1_PRELIM;
memctl->br1 = CONFIG_SYS_BR1_PRELIM;
#endif
#if defined(CONFIG_SYS_BR2_PRELIM) && defined(CONFIG_SYS_OR2_PRELIM)
memctl->or2 = CONFIG_SYS_OR2_PRELIM;
memctl->br2 = CONFIG_SYS_BR2_PRELIM;
#endif
#if defined(CONFIG_SYS_BR3_PRELIM) && defined(CONFIG_SYS_OR3_PRELIM)
memctl->or3 = CONFIG_SYS_OR3_PRELIM;
memctl->br3 = CONFIG_SYS_BR3_PRELIM;
#endif
#if defined(CONFIG_SYS_BR4_PRELIM) && defined(CONFIG_SYS_OR4_PRELIM)
memctl->or4 = CONFIG_SYS_OR4_PRELIM;
memctl->br4 = CONFIG_SYS_BR4_PRELIM;
#endif
#if defined(CONFIG_SYS_BR5_PRELIM) && defined(CONFIG_SYS_OR5_PRELIM)
memctl->or5 = CONFIG_SYS_OR5_PRELIM;
memctl->br5 = CONFIG_SYS_BR5_PRELIM;
#endif
#if defined(CONFIG_SYS_BR6_PRELIM) && defined(CONFIG_SYS_OR6_PRELIM)
memctl->or6 = CONFIG_SYS_OR6_PRELIM;
memctl->br6 = CONFIG_SYS_BR6_PRELIM;
#endif
#if defined(CONFIG_SYS_BR7_PRELIM) && defined(CONFIG_SYS_OR7_PRELIM)
memctl->or7 = CONFIG_SYS_OR7_PRELIM;
memctl->br7 = CONFIG_SYS_BR7_PRELIM;
#endif
#if defined(CONFIG_FSL_DMA)
dma_init();
#endif

5
arch/powerpc/cpu/mpc86xx/speed.c
View File

@ -97,10 +97,7 @@ void get_sys_info(sys_info_t *sysInfo)
/* We will program LCRR to this value later */
lcrr_div = CONFIG_SYS_LBC_LCRR & LCRR_CLKDIV;
#else
{
volatile ccsr_lbc_t *lbc = &immap->im_lbc;
lcrr_div = in_be32(&lbc->lcrr) & LCRR_CLKDIV;
}
lcrr_div = in_be32(&immap->im_lbc.lcrr) & LCRR_CLKDIV;
#endif
if (lcrr_div == 2 || lcrr_div == 4 || lcrr_div == 8) {
sysInfo->freqLocalBus = sysInfo->freqSystemBus / (lcrr_div * 2);

1
arch/powerpc/cpu/mpc8xxx/Makefile
View File

@ -16,6 +16,7 @@ COBJS-$(CONFIG_PCI) += pci_cfg.o
endif
COBJS-$(CONFIG_OF_LIBFDT) += fdt.o
COBJS-$(CONFIG_FSL_LBC) += fsl_lbc.o
SRCS := $(START:.o=.S) $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))

84
arch/powerpc/cpu/mpc8xxx/fsl_lbc.c Normal file
View File

@ -0,0 +1,84 @@
/*
* Copyright 2010 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* Version 2 as published by the Free Software Foundation.
*/
#include <common.h>
#include <asm/fsl_lbc.h>
void print_lbc_regs(void)
{
int i;
printf("\nLocal Bus Controller Registers\n");
for (i = 0; i < 8; i++) {
printf("BR%d\t0x%08X\tOR%d\t0x%08X\n",
i, get_lbc_br(i), i, get_lbc_or(i));
}
}
void init_early_memctl_regs(void)
{
uint init_br1 = 1;
#ifdef CONFIG_MPC85xx
/* if cs1 is already set via debugger, leave cs0/cs1 alone */
if (get_lbc_br(1) & BR_V)
init_br1 = 0;
#endif
/*
* Map banks 0 (and maybe 1) to the FLASH banks 0 (and 1) at
* preliminary addresses - these have to be modified later
* when FLASH size has been determined
*/
#if defined(CONFIG_SYS_OR0_REMAP)
set_lbc_or(0, CONFIG_SYS_OR0_REMAP);
#endif
#if defined(CONFIG_SYS_OR1_REMAP)
set_lbc_or(1, CONFIG_SYS_OR1_REMAP);
#endif
/* now restrict to preliminary range */
if (init_br1) {
set_lbc_br(0, CONFIG_SYS_BR0_PRELIM);
set_lbc_or(0, CONFIG_SYS_OR0_PRELIM);
#if defined(CONFIG_SYS_BR1_PRELIM) && defined(CONFIG_SYS_OR1_PRELIM)
set_lbc_or(1, CONFIG_SYS_OR1_PRELIM);
set_lbc_br(1, CONFIG_SYS_BR1_PRELIM);
#endif
}
#if defined(CONFIG_SYS_BR2_PRELIM) && defined(CONFIG_SYS_OR2_PRELIM)
set_lbc_or(2, CONFIG_SYS_OR2_PRELIM);
set_lbc_br(2, CONFIG_SYS_BR2_PRELIM);
#endif
#if defined(CONFIG_SYS_BR3_PRELIM) && defined(CONFIG_SYS_OR3_PRELIM)
set_lbc_or(3, CONFIG_SYS_OR3_PRELIM);
set_lbc_br(3, CONFIG_SYS_BR3_PRELIM);
#endif
#if defined(CONFIG_SYS_BR4_PRELIM) && defined(CONFIG_SYS_OR4_PRELIM)
set_lbc_or(4, CONFIG_SYS_OR4_PRELIM);
set_lbc_br(4, CONFIG_SYS_BR4_PRELIM);
#endif
#if defined(CONFIG_SYS_BR5_PRELIM) && defined(CONFIG_SYS_OR5_PRELIM)
set_lbc_or(5, CONFIG_SYS_OR5_PRELIM);
set_lbc_br(5, CONFIG_SYS_BR5_PRELIM);
#endif
#if defined(CONFIG_SYS_BR6_PRELIM) && defined(CONFIG_SYS_OR6_PRELIM)
set_lbc_or(6, CONFIG_SYS_OR6_PRELIM);
set_lbc_br(6, CONFIG_SYS_BR6_PRELIM);
#endif
#if defined(CONFIG_SYS_BR7_PRELIM) && defined(CONFIG_SYS_OR7_PRELIM)
set_lbc_or(7, CONFIG_SYS_OR7_PRELIM);
set_lbc_br(7, CONFIG_SYS_BR7_PRELIM);
#endif
}

6
arch/powerpc/include/asm/config.h
View File

@ -85,4 +85,10 @@
/* Relocation to SDRAM works on all PPC boards */
#define CONFIG_RELOC_FIXUP_WORKS
/* Since so many PPC SOCs have a semi-common LBC, define this here */
#if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) || \
defined(CONFIG_MPC83xx)
#define CONFIG_FSL_LBC
#endif
#endif /* _ASM_CONFIG_H_ */

107
arch/powerpc/include/asm/fsl_lbc.h
View File

@ -14,6 +14,7 @@
#define __ASM_PPC_FSL_LBC_H
#include <config.h>
#include <common.h>
/* BR - Base Registers
*/
@ -453,49 +454,69 @@
#define LTESR_CC 0x00000001
#ifndef __ASSEMBLY__
/*
* Local Bus Controller Registers.
*/
typedef struct lbus_bank {
u32 br; /* Base Register */
u32 or; /* Option Register */
} lbus_bank_t;
#include <asm/io.h>
extern void print_lbc_regs(void);
extern void init_early_memctl_regs(void);
#define LBC_BASE_ADDR ((fsl_lbc_t *)CONFIG_SYS_LBC_ADDR)
#define get_lbc_br(i) (in_be32(&(LBC_BASE_ADDR)->bank[i].br))
#define get_lbc_or(i) (in_be32(&(LBC_BASE_ADDR)->bank[i].or))
#define set_lbc_br(i, v) (out_be32(&(LBC_BASE_ADDR)->bank[i].br, v))
#define set_lbc_or(i, v) (out_be32(&(LBC_BASE_ADDR)->bank[i].or, v))
typedef struct lbc_bank {
u32 br;
u32 or;
} lbc_bank_t;
/* Local Bus Controller Registers */
typedef struct fsl_lbc {
lbc_bank_t bank[8];
u8 res1[40];
u32 mar; /* LBC UPM Addr */
u8 res2[4];
u32 mamr; /* LBC UPMA Mode */
u32 mbmr; /* LBC UPMB Mode */
u32 mcmr; /* LBC UPMC Mode */
u8 res3[8];
u32 mrtpr; /* LBC Memory Refresh Timer Prescaler */
u32 mdr; /* LBC UPM Data */
#ifdef CONFIG_FSL_ELBC
u8 res4[4];
u32 lsor;
u8 res5[12];
u32 lurt; /* LBC UPM Refresh Timer */
u8 res6[4];
#else
u8 res4[8];
u32 lsdmr; /* LBC SDRAM Mode */
u8 res5[8];
u32 lurt; /* LBC UPM Refresh Timer */
u32 lsrt; /* LBC SDRAM Refresh Timer */
#endif
u8 res7[8];
u32 ltesr; /* LBC Transfer Error Status */
u32 ltedr; /* LBC Transfer Error Disable */
u32 lteir; /* LBC Transfer Error IRQ */
u32 lteatr; /* LBC Transfer Error Attrs */
u32 ltear; /* LBC Transfer Error Addr */
u8 res8[12];
u32 lbcr; /* LBC Configuration */
u32 lcrr; /* LBC Clock Ratio */
#ifdef CONFIG_NAND_FSL_ELBC
u8 res9[0x8];
u32 fmr; /* Flash Mode Register */
u32 fir; /* Flash Instruction Register */
u32 fcr; /* Flash Command Register */
u32 fbar; /* Flash Block Addr Register */
u32 fpar; /* Flash Page Addr Register */
u32 fbcr; /* Flash Byte Count Register */
u8 res10[0xF08];
#else
u8 res9[0xF28];
#endif
} fsl_lbc_t;
typedef struct fsl_lbus {
lbus_bank_t bank[8];
u8 res0[0x28];
u32 mar; /* UPM Address Register */
u8 res1[0x4];
u32 mamr; /* UPMA Mode Register */
u32 mbmr; /* UPMB Mode Register */
u32 mcmr; /* UPMC Mode Register */
u8 res2[0x8];
u32 mrtpr; /* Memory Refresh Timer Prescaler Register */
u32 mdr; /* UPM Data Register */
u8 res3[0x4];
u32 lsor; /* Special Operation Initiation Register */
u32 lsdmr; /* SDRAM Mode Register */
u8 res4[0x8];
u32 lurt; /* UPM Refresh Timer */
u32 lsrt; /* SDRAM Refresh Timer */
u8 res5[0x8];
u32 ltesr; /* Transfer Error Status Register */
u32 ltedr; /* Transfer Error Disable Register */
u32 lteir; /* Transfer Error Interrupt Register */
u32 lteatr; /* Transfer Error Attributes Register */
u32 ltear; /* Transfer Error Address Register */
u8 res6[0xC];
u32 lbcr; /* Configuration Register */
u32 lcrr; /* Clock Ratio Register */
u8 res7[0x8];
u32 fmr; /* Flash Mode Register */
u32 fir; /* Flash Instruction Register */
u32 fcr; /* Flash Command Register */
u32 fbar; /* Flash Block Addr Register */
u32 fpar; /* Flash Page Addr Register */
u32 fbcr; /* Flash Byte Count Register */
u8 res8[0xF08];
} fsl_lbus_t;
#endif /* __ASSEMBLY__ */
#endif /* __ASM_PPC_FSL_LBC_H */

13
arch/powerpc/include/asm/immap_83xx.h
View File

@ -646,7 +646,7 @@ typedef struct immap {
u8 res2[0x1300];
duart83xx_t duart[2]; /* DUART */
u8 res3[0x900];
fsl_lbus_t lbus; /* Local Bus Controller Registers */
fsl_lbc_t im_lbc; /* Local Bus Controller Regs */
u8 res4[0x1000];
spi8xxx_t spi; /* Serial Peripheral Interface */
dma83xx_t dma; /* DMA */
@ -686,7 +686,7 @@ typedef struct immap {
u8 res1[0x1300];
duart83xx_t duart[2]; /* DUART */
u8 res2[0x900];
fsl_lbus_t lbus; /* Local Bus Controller Registers */
fsl_lbc_t im_lbc; /* Local Bus Controller Regs */
u8 res3[0x1000];
spi8xxx_t spi; /* Serial Peripheral Interface */
dma83xx_t dma; /* DMA */
@ -721,7 +721,7 @@ typedef struct immap {
u8 res1[0x1300];
duart83xx_t duart[2]; /* DUART */
u8 res2[0x900];
fsl_lbus_t lbus; /* Local Bus Controller Registers */
fsl_lbc_t im_lbc; /* Local Bus Controller Regs */
u8 res3[0x1000];
spi8xxx_t spi; /* Serial Peripheral Interface */
dma83xx_t dma; /* DMA */
@ -766,7 +766,7 @@ typedef struct immap {
u8 res1[0x1300];
duart83xx_t duart[2]; /* DUART */
u8 res2[0x900];
fsl_lbus_t lbus; /* Local Bus Controller Registers */
fsl_lbc_t im_lbc; /* Local Bus Controller Regs */
u8 res3[0x1000];
spi8xxx_t spi; /* Serial Peripheral Interface */
dma83xx_t dma; /* DMA */
@ -816,7 +816,7 @@ typedef struct immap {
u8 res4[0x1300];
duart83xx_t duart[2]; /* DUART */
u8 res5[0x900];
fsl_lbus_t lbus; /* Local Bus Controller Registers */
fsl_lbc_t im_lbc; /* Local Bus Controller Regs */
u8 res6[0x2000];
dma83xx_t dma; /* DMA */
pciconf83xx_t pci_conf[1]; /* PCI Software Configuration Registers */
@ -855,7 +855,7 @@ typedef struct immap {
u8 res3[0x1300];
duart83xx_t duart[2]; /* DUART */
u8 res4[0x900];
fsl_lbus_t lbus; /* Local Bus Controller Registers */
fsl_lbc_t im_lbc; /* Local Bus Controller Regs */
u8 res5[0x2000];
dma83xx_t dma; /* DMA */
pciconf83xx_t pci_conf[1]; /* PCI Software Configuration Registers */
@ -879,6 +879,7 @@ typedef struct immap {
#endif
#define CONFIG_SYS_MPC83xx_USB_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_MPC83xx_USB_OFFSET)
#define CONFIG_SYS_LBC_ADDR (&((immap_t *)CONFIG_SYS_IMMR)->im_lbc)
#define CONFIG_SYS_TSEC1_OFFSET 0x24000
#define CONFIG_SYS_MDIO1_OFFSET 0x24000

46
arch/powerpc/include/asm/immap_85xx.h
View File

@ -266,50 +266,6 @@ typedef struct ccsr_duart {
} ccsr_duart_t;
#endif
/* Local Bus Controller Registers */
typedef struct ccsr_lbc {
u32 br0; /* LBC Base 0 */
u32 or0; /* LBC Options 0 */
u32 br1; /* LBC Base 1 */
u32 or1; /* LBC Options 1 */
u32 br2; /* LBC Base 2 */
u32 or2; /* LBC Options 2 */
u32 br3; /* LBC Base 3 */
u32 or3; /* LBC Options 3 */
u32 br4; /* LBC Base 4 */
u32 or4; /* LBC Options 4 */
u32 br5; /* LBC Base 5 */
u32 or5; /* LBC Options 5 */
u32 br6; /* LBC Base 6 */
u32 or6; /* LBC Options 6 */
u32 br7; /* LBC Base 7 */
u32 or7; /* LBC Options 7 */
u8 res1[40];
u32 mar; /* LBC UPM Addr */
u8 res2[4];
u32 mamr; /* LBC UPMA Mode */
u32 mbmr; /* LBC UPMB Mode */
u32 mcmr; /* LBC UPMC Mode */
u8 res3[8];
u32 mrtpr; /* LBC Memory Refresh Timer Prescaler */
u32 mdr; /* LBC UPM Data */
u8 res4[8];
u32 lsdmr; /* LBC SDRAM Mode */
u8 res5[8];
u32 lurt; /* LBC UPM Refresh Timer */
u32 lsrt; /* LBC SDRAM Refresh Timer */
u8 res6[8];
u32 ltesr; /* LBC Transfer Error Status */
u32 ltedr; /* LBC Transfer Error Disable */
u32 lteir; /* LBC Transfer Error IRQ */
u32 lteatr; /* LBC Transfer Error Attrs */
u32 ltear; /* LBC Transfer Error Addr */
u8 res7[12];
u32 lbcr; /* LBC Configuration */
u32 lcrr; /* LBC Clock Ratio */
u8 res8[3880];
} ccsr_lbc_t;
/* eSPI Registers */
typedef struct ccsr_espi {
u32 mode; /* eSPI mode */
@ -2147,7 +2103,7 @@ typedef struct ccsr_sec {
(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_DDR_OFFSET)
#define CONFIG_SYS_MPC85xx_DDR2_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_DDR2_OFFSET)
#define CONFIG_SYS_MPC85xx_LBC_ADDR \
#define CONFIG_SYS_LBC_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_LBC_OFFSET)
#define CONFIG_SYS_MPC85xx_ESPI_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_ESPI_OFFSET)

49
arch/powerpc/include/asm/immap_86xx.h
View File

@ -12,6 +12,7 @@
#include <asm/types.h>
#include <asm/fsl_dma.h>
#include <asm/fsl_lbc.h>
#include <asm/fsl_i2c.h>
/* Local-Access Registers and MCM Registers(0x0000-0x2000) */
@ -190,51 +191,6 @@ typedef struct ccsr_duart {
char res5[2543];
} ccsr_duart_t;
/* Local Bus Controller Registers(0x5000-0x6000) */
typedef struct ccsr_lbc {
uint br0; /* 0x5000 - LBC Base Register 0 */
uint or0; /* 0x5004 - LBC Options Register 0 */
uint br1; /* 0x5008 - LBC Base Register 1 */
uint or1; /* 0x500c - LBC Options Register 1 */
uint br2; /* 0x5010 - LBC Base Register 2 */
uint or2; /* 0x5014 - LBC Options Register 2 */
uint br3; /* 0x5018 - LBC Base Register 3 */
uint or3; /* 0x501c - LBC Options Register 3 */
uint br4; /* 0x5020 - LBC Base Register 4 */
uint or4; /* 0x5024 - LBC Options Register 4 */
uint br5; /* 0x5028 - LBC Base Register 5 */
uint or5; /* 0x502c - LBC Options Register 5 */
uint br6; /* 0x5030 - LBC Base Register 6 */
uint or6; /* 0x5034 - LBC Options Register 6 */
uint br7; /* 0x5038 - LBC Base Register 7 */
uint or7; /* 0x503c - LBC Options Register 7 */
char res1[40];
uint mar; /* 0x5068 - LBC UPM Address Register */
char res2[4];
uint mamr; /* 0x5070 - LBC UPMA Mode Register */
uint mbmr; /* 0x5074 - LBC UPMB Mode Register */
uint mcmr; /* 0x5078 - LBC UPMC Mode Register */
char res3[8];
uint mrtpr; /* 0x5084 - LBC Memory Refresh Timer Prescaler Register */
uint mdr; /* 0x5088 - LBC UPM Data Register */
char res4[8];
uint lsdmr; /* 0x5094 - LBC SDRAM Mode Register */
char res5[8];
uint lurt; /* 0x50a0 - LBC UPM Refresh Timer */
uint lsrt; /* 0x50a4 - LBC SDRAM Refresh Timer */
char res6[8];
uint ltesr; /* 0x50b0 - LBC Transfer Error Status Register */
uint ltedr; /* 0x50b4 - LBC Transfer Error Disable Register */
uint lteir; /* 0x50b8 - LBC Transfer Error Interrupt Register */
uint lteatr; /* 0x50bc - LBC Transfer Error Attributes Register */
uint ltear; /* 0x50c0 - LBC Transfer Error Address Register */
char res7[12];
uint lbcr; /* 0x50d0 - LBC Configuration Register */
uint lcrr; /* 0x50d4 - LBC Clock Ratio Register */
char res8[3880];
} ccsr_lbc_t;
/* PCI Express Registers(0x8000-0x9000) and (0x9000-0xA000) */
typedef struct ccsr_pex {
uint cfg_addr; /* 0x8000 - PEX Configuration Address Register */
@ -1270,7 +1226,7 @@ typedef struct immap {
ccsr_ddr_t im_ddr1;
ccsr_i2c_t im_i2c;
ccsr_duart_t im_duart;
ccsr_lbc_t im_lbc;
fsl_lbc_t im_lbc;
ccsr_ddr_t im_ddr2;
char res1[4096];
ccsr_pex_t im_pex1;
@ -1303,6 +1259,7 @@ extern immap_t *immr;
#define CONFIG_SYS_TSEC1_OFFSET 0x24000
#define CONFIG_SYS_MDIO1_OFFSET 0x24000
#define CONFIG_SYS_LBC_ADDR (&((immap_t *)CONFIG_SYS_IMMR)->im_lbc)
#define TSEC_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
#define MDIO_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MDIO1_OFFSET)

2
board/atum8548/atum8548.c
View File

@ -47,7 +47,7 @@ int board_early_init_f (void)
int checkboard (void)
{
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
if ((uint)&gur->porpllsr != 0xe00e0000) {

2
board/esd/vme8349/vme8349.c
View File

@ -105,7 +105,7 @@ int misc_init_r()
{
immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
clrsetbits_be32(&im->lbus.lcrr, LBCR_LDIS, 0);
clrsetbits_be32(&im->im_lbc.lcrr, LBCR_LDIS, 0);
return 0;
}

2
board/freescale/mpc8313erdb/sdram.c
View File

@ -110,7 +110,7 @@ static long fixed_sdram(void)
phys_size_t initdram(int board_type)
{
volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
volatile fsl_lbus_t *lbc = &im->lbus;
volatile fsl_lbc_t *lbc = &im->im_lbc;
u32 msize;
if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)

2
board/freescale/mpc8349emds/mpc8349emds.c
View File

@ -192,7 +192,7 @@ int checkboard (void)
void sdram_init(void)
{
volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
volatile fsl_lbus_t *lbc = &immap->lbus;
volatile fsl_lbc_t *lbc = &immap->im_lbc;
uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
/*

7
board/freescale/mpc8349itx/mpc8349itx.c
View File

@ -221,15 +221,14 @@ int misc_init_f(void)
0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01
};
volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
volatile fsl_lbus_t *lbus = &immap->lbus;
lbus->bank[3].br = CONFIG_SYS_BR3_PRELIM;
lbus->bank[3].or = CONFIG_SYS_OR3_PRELIM;
set_lbc_br(3, CONFIG_SYS_BR3_PRELIM);
set_lbc_or(3, CONFIG_SYS_OR3_PRELIM);
/* Program the MAMR. RFEN=0, OP=00, UWPL=1, AM=000, DS=01, G0CL=000,
GPL4=0, RLF=0001, WLF=0001, TLF=0001, MAD=000000
*/
lbus->mamr = 0x08404440;
immap->im_lbc.mamr = 0x08404440;
upmconfig(0, UPMATable, sizeof(UPMATable) / sizeof(UPMATable[0]));

6
board/freescale/mpc8360emds/mpc8360emds.c
View File

@ -280,7 +280,7 @@ int checkboard(void)
static int sdram_init(unsigned int base)
{
volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
volatile fsl_lbus_t *lbc = &immap->lbus;
fsl_lbc_t *lbc = LBC_BASE_ADDR;
const int sdram_size = CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024;
int rem = base % sdram_size;
uint *sdram_addr;
@ -293,8 +293,8 @@ static int sdram_init(unsigned int base)
/*
* Setup SDRAM Base and Option Registers
*/
immap->lbus.bank[2].br = base | CONFIG_SYS_BR2;
immap->lbus.bank[2].or = CONFIG_SYS_OR2;
set_lbc_br(2, base | CONFIG_SYS_BR2);
set_lbc_or(2, CONFIG_SYS_OR2);
immap->sysconf.lblaw[2].bar = base;
immap->sysconf.lblaw[2].ar = CONFIG_SYS_LBLAWAR2;

6
board/freescale/mpc8360erdk/nand.c
View File

@ -82,9 +82,9 @@ static struct fsl_upm_nand fun = {
int board_nand_init(struct nand_chip *nand)
{
fun.upm.mxmr = &im->lbus.mamr;
fun.upm.mdr = &im->lbus.mdr;
fun.upm.mar = &im->lbus.mar;
fun.upm.mxmr = &im->im_lbc.mamr;
fun.upm.mdr = &im->im_lbc.mdr;
fun.upm.mar = &im->im_lbc.mar;
upm_setup(&fun.upm);

8
board/freescale/mpc8540ads/mpc8540ads.c
View File

@ -117,7 +117,7 @@ void
local_bus_init(void)
{
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
uint clkdiv;
uint lbc_hz;
@ -176,7 +176,7 @@ local_bus_init(void)
void
sdram_init(void)
{
volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
puts(" SDRAM: ");
@ -185,8 +185,8 @@ sdram_init(void)
/*
* Setup SDRAM Base and Option Registers
*/
lbc->or2 = CONFIG_SYS_OR2_PRELIM;
lbc->br2 = CONFIG_SYS_BR2_PRELIM;
set_lbc_or(2, CONFIG_SYS_OR2_PRELIM);
set_lbc_br(2, CONFIG_SYS_BR2_PRELIM);
lbc->lbcr = CONFIG_SYS_LBC_LBCR;
asm("msync");

13
board/freescale/mpc8541cds/mpc8541cds.c
View File

@ -291,7 +291,7 @@ void
local_bus_init(void)
{
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
uint clkdiv;
uint lbc_hz;
@ -340,7 +340,7 @@ sdram_init(void)
#if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM)
uint idx;
volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
uint cpu_board_rev;
uint lsdmr_common;
@ -352,16 +352,11 @@ sdram_init(void)
/*
* Setup SDRAM Base and Option Registers
*/
lbc->or2 = CONFIG_SYS_OR2_PRELIM;
asm("msync");
lbc->br2 = CONFIG_SYS_BR2_PRELIM;
asm("msync");
set_lbc_or(2, CONFIG_SYS_OR2_PRELIM);
set_lbc_br(2, CONFIG_SYS_BR2_PRELIM);
lbc->lbcr = CONFIG_SYS_LBC_LBCR;
asm("msync");
lbc->lsrt = CONFIG_SYS_LBC_LSRT;
lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
asm("msync");

2
board/freescale/mpc8544ds/mpc8544ds.c
View File

@ -40,7 +40,7 @@
int checkboard (void)
{
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
u8 vboot;
u8 *pixis_base = (u8 *)PIXIS_BASE;

13
board/freescale/mpc8548cds/mpc8548cds.c
View File

@ -118,7 +118,7 @@ void
local_bus_init(void)
{
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
uint clkdiv;
uint lbc_hz;
@ -154,7 +154,7 @@ sdram_init(void)
#if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM)
uint idx;
volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
uint cpu_board_rev;
uint lsdmr_common;
@ -166,16 +166,11 @@ sdram_init(void)
/*
* Setup SDRAM Base and Option Registers
*/
lbc->or2 = CONFIG_SYS_OR2_PRELIM;
asm("msync");
lbc->br2 = CONFIG_SYS_BR2_PRELIM;
asm("msync");
set_lbc_or(2, CONFIG_SYS_OR2_PRELIM);
set_lbc_br(2, CONFIG_SYS_BR2_PRELIM);
lbc->lbcr = CONFIG_SYS_LBC_LBCR;
asm("msync");
lbc->lsrt = CONFIG_SYS_LBC_LSRT;
lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
asm("msync");

12
board/freescale/mpc8555cds/mpc8555cds.c
View File

@ -291,7 +291,7 @@ void
local_bus_init(void)
{
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
uint clkdiv;
uint lbc_hz;
@ -340,7 +340,7 @@ sdram_init(void)
#if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM)
uint idx;
volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
uint cpu_board_rev;
uint lsdmr_common;
@ -352,12 +352,8 @@ sdram_init(void)
/*
* Setup SDRAM Base and Option Registers
*/
lbc->or2 = CONFIG_SYS_OR2_PRELIM;
asm("msync");
lbc->br2 = CONFIG_SYS_BR2_PRELIM;
asm("msync");
set_lbc_or(2, CONFIG_SYS_OR2_PRELIM);
set_lbc_br(2, CONFIG_SYS_BR2_PRELIM);
lbc->lbcr = CONFIG_SYS_LBC_LBCR;
asm("msync");

8
board/freescale/mpc8560ads/mpc8560ads.c
View File

@ -322,7 +322,7 @@ void
local_bus_init(void)
{
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
uint clkdiv;
uint lbc_hz;
@ -381,7 +381,7 @@ local_bus_init(void)
void
sdram_init(void)
{
volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
puts(" SDRAM: ");
@ -390,8 +390,8 @@ sdram_init(void)
/*
* Setup SDRAM Base and Option Registers
*/
lbc->or2 = CONFIG_SYS_OR2_PRELIM;
lbc->br2 = CONFIG_SYS_BR2_PRELIM;
set_lbc_or(2, CONFIG_SYS_OR2_PRELIM);
set_lbc_br(2, CONFIG_SYS_BR2_PRELIM);
lbc->lbcr = CONFIG_SYS_LBC_LBCR;
asm("msync");

11
board/freescale/mpc8568mds/mpc8568mds.c
View File

@ -181,7 +181,7 @@ void
local_bus_init(void)
{
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
uint clkdiv;
uint lbc_hz;
@ -214,7 +214,7 @@ sdram_init(void)
#if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM)
uint idx;
volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
uint lsdmr_common;
@ -225,16 +225,13 @@ sdram_init(void)
/*
* Setup SDRAM Base and Option Registers
*/
lbc->or2 = CONFIG_SYS_OR2_PRELIM;
asm("msync");
lbc->br2 = CONFIG_SYS_BR2_PRELIM;
set_lbc_or(2, CONFIG_SYS_OR2_PRELIM);
set_lbc_br(2, CONFIG_SYS_BR2_PRELIM);
asm("msync");
lbc->lbcr = CONFIG_SYS_LBC_LBCR;
asm("msync");
lbc->lsrt = CONFIG_SYS_LBC_LSRT;
lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
asm("msync");

2
board/freescale/mpc8569mds/mpc8569mds.c
View File

@ -308,7 +308,7 @@ void
local_bus_init(void)
{
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
uint clkdiv;
uint lbc_hz;

6
board/mpc8540eval/mpc8540eval.c
View File

@ -69,7 +69,7 @@ phys_size_t initdram (int board_type)
long dram_size = 0;
#if !defined(CONFIG_RAM_AS_FLASH)
volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
sys_info_t sysinfo;
uint temp_lbcdll = 0;
#endif
@ -110,8 +110,8 @@ phys_size_t initdram (int board_type)
gur->lbcdllcr = ((temp_lbcdll & 0xff) << 16 ) | 0x80000000;
asm("sync;isync;msync");
}
lbc->or2 = CONFIG_SYS_OR2_PRELIM; /* 64MB SDRAM */
lbc->br2 = CONFIG_SYS_BR2_PRELIM;
set_lbc_or(2, CONFIG_SYS_OR2_PRELIM); /* 64MB SDRAM */
set_lbc_br(2, CONFIG_SYS_BR2_PRELIM);
lbc->lbcr = CONFIG_SYS_LBC_LBCR;
lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_1;
asm("sync");

2
board/pm854/pm854.c
View File

@ -134,7 +134,7 @@ void
local_bus_init(void)
{
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
uint clkdiv;
uint lbc_hz;

2
board/pm856/pm856.c
View File

@ -290,7 +290,7 @@ void
local_bus_init(void)
{
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
uint clkdiv;
uint lbc_hz;

2
board/sbc8349/sbc8349.c
View File

@ -160,7 +160,7 @@ int checkboard (void)
void sdram_init(void)
{
volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
volatile fsl_lbus_t *lbc = &immap->lbus;
volatile fsl_lbc_t *lbc = &immap->im_lbc;
uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
puts("\n SDRAM on Local Bus: ");

20
board/sbc8548/sbc8548.c
View File

@ -116,7 +116,7 @@ void
local_bus_init(void)
{
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
uint clkdiv;
uint lbc_hz;
@ -152,7 +152,7 @@ sdram_init(void)
#if defined(CONFIG_SYS_LBC_SDRAM_SIZE)
uint idx;
volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
uint lsdmr_common;
@ -163,22 +163,14 @@ sdram_init(void)
/*
* Setup SDRAM Base and Option Registers
*/
out_be32(&lbc->or3, CONFIG_SYS_OR3_PRELIM);
asm("msync");
out_be32(&lbc->br3, CONFIG_SYS_BR3_PRELIM);
asm("msync");
out_be32(&lbc->or4, CONFIG_SYS_OR4_PRELIM);
asm("msync");
out_be32(&lbc->br4, CONFIG_SYS_BR4_PRELIM);
asm("msync");
set_lbc_or(3, CONFIG_SYS_OR3_PRELIM);
set_lbc_br(3, CONFIG_SYS_BR3_PRELIM);
set_lbc_or(4, CONFIG_SYS_OR4_PRELIM);
set_lbc_br(4, CONFIG_SYS_BR4_PRELIM);
out_be32(&lbc->lbcr, CONFIG_SYS_LBC_LBCR);
asm("msync");
out_be32(&lbc->lsrt, CONFIG_SYS_LBC_LSRT);
out_be32(&lbc->mrtpr, CONFIG_SYS_LBC_MRTPR);
asm("msync");

6
board/sbc8560/sbc8560.c
View File

@ -269,7 +269,7 @@ phys_size_t initdram (int board_type)
#if 0
#if !defined(CONFIG_RAM_AS_FLASH)
volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
sys_info_t sysinfo;
uint temp_lbcdll = 0;
#endif
@ -310,8 +310,8 @@ phys_size_t initdram (int board_type)
gur->lbcdllcr = ((temp_lbcdll & 0xff) << 16 ) | 0x80000000;
asm("sync;isync;msync");
}
lbc->or2 = CONFIG_SYS_OR2_PRELIM; /* 64MB SDRAM */
lbc->br2 = CONFIG_SYS_BR2_PRELIM;
set_lbc_or(2, CONFIG_SYS_OR2_PRELIM); /* 64MB SDRAM */
set_lbc_br(2, CONFIG_SYS_BR2_PRELIM);
lbc->lbcr = CONFIG_SYS_LBC_LBCR;
lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_1;
asm("sync");

2
board/sheldon/simpc8313/sdram.c
View File

@ -129,7 +129,7 @@ void si_read_i2c(u32 lbyte, int count, u8 *buffer)
phys_size_t initdram(int board_type)
{
volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
volatile fsl_lbus_t *lbc= &im->lbus;
volatile fsl_lbc_t *lbc = &im->im_lbc;
u32 msize;
if ((__raw_readl(&im->sysconf.immrbar) & IMMRBAR_BASE_ADDR) != (u32) im)

2
board/sheldon/simpc8313/simpc8313.c
View File

@ -93,7 +93,7 @@ int misc_init_r(void)
{
int rc = 0;
immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
fsl_lbus_t *lbus = &immap->lbus;
fsl_lbc_t *lbus = &immap->im_lbc;
u32 *mxmr = &lbus->mamr; /* Pointer to mamr */
/* UPM Table Configuration Code */

31
board/socrates/socrates.c
View File

@ -87,8 +87,6 @@ int checkboard (void)
int misc_init_r (void)
{
volatile ccsr_lbc_t *memctl = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
/*
* Adjust flash start and offset to detected values
*/
@ -99,8 +97,10 @@ int misc_init_r (void)
* Check if boot FLASH isn't max size
*/
if (gd->bd->bi_flashsize < (0 - CONFIG_SYS_FLASH0)) {
memctl->or0 = gd->bd->bi_flashstart | (CONFIG_SYS_OR0_PRELIM & 0x00007fff);
memctl->br0 = gd->bd->bi_flashstart | (CONFIG_SYS_BR0_PRELIM & 0x00007fff);
set_lbc_or(0, gd->bd->bi_flashstart |
(CONFIG_SYS_OR0_PRELIM & 0x00007fff));
set_lbc_br(0, gd->bd->bi_flashstart |
(CONFIG_SYS_BR0_PRELIM & 0x00007fff));
/*
* Re-check to get correct base address
@ -112,8 +112,8 @@ int misc_init_r (void)
* Check if only one FLASH bank is available
*/
if (gd->bd->bi_flashsize != CONFIG_SYS_MAX_FLASH_BANKS * (0 - CONFIG_SYS_FLASH0)) {
memctl->or1 = 0;
memctl->br1 = 0;
set_lbc_or(1, 0);
set_lbc_br(1, 0);
/*
* Re-do flash protection upon new addresses
@ -148,7 +148,7 @@ int misc_init_r (void)
*/
void local_bus_init (void)
{
volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
sys_info_t sysinfo;
uint clkdiv;
@ -299,26 +299,25 @@ const gdc_regs *board_get_regs (void)
int lime_probe(void)
{
volatile ccsr_lbc_t *memctl = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
uint cfg_br2;
uint cfg_or2;
int type;
cfg_br2 = memctl->br2;
cfg_or2 = memctl->or2;
cfg_br2 = get_lbc_br(2);
cfg_or2 = get_lbc_or(2);
/* Configure GPCM for CS2 */
memctl->br2 = 0;
memctl->or2 = 0xfc000410;
memctl->br2 = (CONFIG_SYS_LIME_BASE) | 0x00001901;
set_lbc_br(2, 0);
set_lbc_or(2, 0xfc000410);
set_lbc_br(2, (CONFIG_SYS_LIME_BASE) | 0x00001901);
/* Get controller type */
type = mb862xx_probe(CONFIG_SYS_LIME_BASE);
/* Restore previous CS2 configuration */
memctl->br2 = 0;
memctl->or2 = cfg_or2;
memctl->br2 = cfg_br2;
set_lbc_br(2, 0);
set_lbc_or(2, cfg_or2);
set_lbc_br(2, cfg_br2);
return (type == MB862XX_TYPE_LIME) ? 1 : 0;
}

8
board/tqc/tqm834x/tqm834x.c
View File

@ -253,10 +253,10 @@ static int detect_num_flash_banks(void)
debug("Number of flash banks detected: %d\n", tqm834x_num_flash_banks);
/* set OR0 and BR0 */
im->lbus.bank[0].or = CONFIG_SYS_OR_TIMING_FLASH |
(-(total_size) & OR_GPCM_AM);
im->lbus.bank[0].br = (CONFIG_SYS_FLASH_BASE & BR_BA) |
(BR_MS_GPCM | BR_PS_32 | BR_V);
set_lbc_or(0, CONFIG_SYS_OR_TIMING_FLASH |
(-(total_size) & OR_GPCM_AM));
set_lbc_br(0, (CONFIG_SYS_FLASH_BASE & BR_BA) |
(BR_MS_GPCM | BR_PS_32 | BR_V));
return (0);
}

12
board/tqc/tqm85xx/nand.c
View File

@ -377,7 +377,7 @@ volatile const u32 *nand_upm_patt;
*/
static void upmb_write (u_char addr, ulong val)
{
volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
out_be32 (&lbc->mdr, val);
@ -393,14 +393,14 @@ static void upmb_write (u_char addr, ulong val)
/*
* Initialize UPM for NAND flash access.
*/
static void nand_upm_setup (volatile ccsr_lbc_t *lbc)
static void nand_upm_setup (volatile fsl_lbc_t *lbc)
{
uint i, j;
uint or3 = CONFIG_SYS_OR3_PRELIM;
uint clock = get_lbc_clock ();
out_be32 (&lbc->br3, 0); /* disable bank and reset all bits */
out_be32 (&lbc->br3, CONFIG_SYS_BR3_PRELIM);
set_lbc_br(3, 0); /* disable bank and reset all bits */
set_lbc_br(3, CONFIG_SYS_BR3_PRELIM);
/*
* Search appropriate UPM table for bus clock.
@ -424,7 +424,7 @@ static void nand_upm_setup (volatile ccsr_lbc_t *lbc)
/* EAD must be set due to TQM8548 timing specification */
or3 |= OR_UPM_EAD;
out_be32 (&lbc->or3, or3);
set_lbc_or(3, or3);
/* Assign address of table */
nand_upm_patt = upm_freq_table[i].upm_patt;
@ -458,7 +458,7 @@ void board_nand_select_device (struct nand_chip *nand, int chip)
int board_nand_init (struct nand_chip *nand)
{
volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
if (!nand_upm_patt)
nand_upm_setup (lbc);

35
board/tqc/tqm85xx/tqm85xx.c
View File

@ -269,8 +269,6 @@ int checkboard (void)
int misc_init_r (void)
{
volatile ccsr_lbc_t *memctl = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
/*
* Adjust flash start and offset to detected values
*/
@ -281,26 +279,27 @@ int misc_init_r (void)
* Recalculate CS configuration if second FLASH bank is available
*/
if (flash_info[0].size > 0) {
memctl->or1 = ((-flash_info[0].size) & 0xffff8000) |
(CONFIG_SYS_OR1_PRELIM & 0x00007fff);
memctl->br1 = gd->bd->bi_flashstart |
(CONFIG_SYS_BR1_PRELIM & 0x00007fff);
set_lbc_or(1, ((-flash_info[0].size) & 0xffff8000) |
(CONFIG_SYS_OR1_PRELIM & 0x00007fff));
set_lbc_br(1, gd->bd->bi_flashstart |
(CONFIG_SYS_BR1_PRELIM & 0x00007fff));
/*
* Re-check to get correct base address for bank 1
*/
flash_get_size (gd->bd->bi_flashstart, 0);
} else {
memctl->or1 = 0;
memctl->br1 = 0;
set_lbc_or(1, 0);
set_lbc_br(1, 0);
}
/*
* If bank 1 is equipped, bank 0 is mapped after bank 1
*/
memctl->or0 = ((-flash_info[1].size) & 0xffff8000) |
(CONFIG_SYS_OR0_PRELIM & 0x00007fff);
memctl->br0 = (gd->bd->bi_flashstart + flash_info[0].size) |
(CONFIG_SYS_BR0_PRELIM & 0x00007fff);
set_lbc_or(0, ((-flash_info[1].size) & 0xffff8000) |
(CONFIG_SYS_OR0_PRELIM & 0x00007fff));
set_lbc_br(0, gd->bd->bi_flashstart |
(CONFIG_SYS_BR0_PRELIM & 0x00007fff));
/*
* Re-check to get correct base address for bank 0
*/
@ -341,7 +340,7 @@ int misc_init_r (void)
*/
static void upmc_write (u_char addr, uint val)
{
volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
out_be32 (&lbc->mdr, val);
@ -358,7 +357,7 @@ static void upmc_write (u_char addr, uint val)
uint get_lbc_clock (void)
{
volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
sys_info_t sys_info;
ulong clkdiv = lbc->lcrr & LCRR_CLKDIV;
@ -386,7 +385,7 @@ uint get_lbc_clock (void)
void local_bus_init (void)
{
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
uint lbc_mhz = get_lbc_clock () / 1000000;
#ifdef CONFIG_MPC8548
@ -502,10 +501,10 @@ void local_bus_init (void)
* set if Local Bus Clock is > 83 MHz.
*/
if (lbc_mhz > 83)
out_be32 (&lbc->or2, CONFIG_SYS_OR2_CAN | OR_UPM_EAD);
set_lbc_or(2, CONFIG_SYS_OR2_CAN | OR_UPM_EAD);
else
out_be32 (&lbc->or2, CONFIG_SYS_OR2_CAN);
out_be32 (&lbc->br2, CONFIG_SYS_BR2_CAN);
set_lbc_or(2, CONFIG_SYS_OR2_CAN);
set_lbc_br(2, CONFIG_SYS_BR2_CAN);
/* LGPL4 is UPWAIT */
out_be32(&lbc->mcmr, MxMR_DSx_3_CYCL | MxMR_GPL_x4DIS | MxMR_WLFx_3X);

10
board/xes/xpedite5170/xpedite5170.c
View File

@ -56,8 +56,6 @@ int checkboard(void)
*/
static void flash_cs_fixup(void)
{
immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
ccsr_lbc_t *lbc = &immap->im_lbc;
int flash_sel;
/*
@ -70,11 +68,11 @@ static void flash_cs_fixup(void)
printf("FLASH: Executed from FLASH%d\n", flash_sel ? 2 : 1);
if (flash_sel) {
out_be32(&lbc->br0, CONFIG_SYS_BR1_PRELIM);
out_be32(&lbc->or0, CONFIG_SYS_OR1_PRELIM);
set_lbc_br(0, CONFIG_SYS_BR1_PRELIM);
set_lbc_or(0, CONFIG_SYS_OR1_PRELIM);
out_be32(&lbc->br1, CONFIG_SYS_BR0_PRELIM);
out_be32(&lbc->or1, CONFIG_SYS_OR0_PRELIM);
set_lbc_br(1, CONFIG_SYS_BR0_PRELIM);
set_lbc_or(1, CONFIG_SYS_OR0_PRELIM);
}
}

11
board/xes/xpedite5200/xpedite5200.c
View File

@ -38,7 +38,7 @@ extern void ft_board_pci_setup(void *blob, bd_t *bd);
int checkboard(void)
{
volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
char *s;
@ -65,7 +65,6 @@ int checkboard(void)
static void flash_cs_fixup(void)
{
volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
int flash_sel;
/*
@ -78,11 +77,11 @@ static void flash_cs_fixup(void)
printf("FLASH: Executed from FLASH%d\n", flash_sel ? 2 : 1);
if (flash_sel) {
out_be32(&lbc->br0, CONFIG_SYS_BR1_PRELIM);
out_be32(&lbc->or0, CONFIG_SYS_OR1_PRELIM);
set_lbc_br(0, CONFIG_SYS_BR1_PRELIM);
set_lbc_or(0, CONFIG_SYS_OR1_PRELIM);
out_be32(&lbc->br1, CONFIG_SYS_BR0_PRELIM);
out_be32(&lbc->or1, CONFIG_SYS_OR0_PRELIM);
set_lbc_br(1, CONFIG_SYS_BR0_PRELIM);
set_lbc_or(1, CONFIG_SYS_OR0_PRELIM);
}
}

9
board/xes/xpedite5370/xpedite5370.c
View File

@ -58,7 +58,6 @@ int checkboard(void)
static void flash_cs_fixup(void)
{
volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
int flash_sel;
/*
@ -71,11 +70,11 @@ static void flash_cs_fixup(void)
printf("FLASH: Executed from FLASH%d\n", flash_sel ? 2 : 1);
if (flash_sel) {
out_be32(&lbc->br0, CONFIG_SYS_BR1_PRELIM);
out_be32(&lbc->or0, CONFIG_SYS_OR1_PRELIM);
set_lbc_br(0, CONFIG_SYS_BR1_PRELIM);
set_lbc_or(0, CONFIG_SYS_OR1_PRELIM);
out_be32(&lbc->br1, CONFIG_SYS_BR0_PRELIM);
out_be32(&lbc->or1, CONFIG_SYS_OR0_PRELIM);
set_lbc_br(1, CONFIG_SYS_BR0_PRELIM);
set_lbc_or(1, CONFIG_SYS_OR0_PRELIM);
}
}

18
drivers/mtd/nand/fsl_elbc_nand.c
View File

@ -75,7 +75,7 @@ struct fsl_elbc_ctrl {
struct fsl_elbc_mtd *chips[MAX_BANKS];
/* device info */
fsl_lbus_t *regs;
fsl_lbc_t *regs;
u8 __iomem *addr; /* Address of assigned FCM buffer */
unsigned int page; /* Last page written to / read from */
unsigned int read_bytes; /* Number of bytes read during command */
@ -171,7 +171,7 @@ static void set_addr(struct mtd_info *mtd, int column, int page_addr, int oob)
struct nand_chip *chip = mtd->priv;
struct fsl_elbc_mtd *priv = chip->priv;
struct fsl_elbc_ctrl *ctrl = priv->ctrl;
fsl_lbus_t *lbc = ctrl->regs;
fsl_lbc_t *lbc = ctrl->regs;
int buf_num;
ctrl->page = page_addr;
@ -211,7 +211,7 @@ static int fsl_elbc_run_command(struct mtd_info *mtd)
struct nand_chip *chip = mtd->priv;
struct fsl_elbc_mtd *priv = chip->priv;
struct fsl_elbc_ctrl *ctrl = priv->ctrl;
fsl_lbus_t *lbc = ctrl->regs;
fsl_lbc_t *lbc = ctrl->regs;
long long end_tick;
u32 ltesr;
@ -261,7 +261,7 @@ static void fsl_elbc_do_read(struct nand_chip *chip, int oob)
{
struct fsl_elbc_mtd *priv = chip->priv;
struct fsl_elbc_ctrl *ctrl = priv->ctrl;
fsl_lbus_t *lbc = ctrl->regs;
fsl_lbc_t *lbc = ctrl->regs;
if (priv->page_size) {
out_be32(&lbc->fir,
@ -295,7 +295,7 @@ static void fsl_elbc_cmdfunc(struct mtd_info *mtd, unsigned int command,
struct nand_chip *chip = mtd->priv;
struct fsl_elbc_mtd *priv = chip->priv;
struct fsl_elbc_ctrl *ctrl = priv->ctrl;
fsl_lbus_t *lbc = ctrl->regs;
fsl_lbc_t *lbc = ctrl->regs;
ctrl->use_mdr = 0;
@ -633,7 +633,7 @@ static int fsl_elbc_wait(struct mtd_info *mtd, struct nand_chip *chip)
{
struct fsl_elbc_mtd *priv = chip->priv;
struct fsl_elbc_ctrl *ctrl = priv->ctrl;
fsl_lbus_t *lbc = ctrl->regs;
fsl_lbc_t *lbc = ctrl->regs;
if (ctrl->status != LTESR_CC)
return NAND_STATUS_FAIL;
@ -697,11 +697,7 @@ static void fsl_elbc_ctrl_init(void)
if (!elbc_ctrl)
return;
#ifdef CONFIG_MPC85xx
elbc_ctrl->regs = (void *)CONFIG_SYS_MPC85xx_LBC_ADDR;
#else
elbc_ctrl->regs = &((immap_t *)CONFIG_SYS_IMMR)->lbus;
#endif
elbc_ctrl->regs = LBC_BASE_ADDR;
/* clear event registers */
out_be32(&elbc_ctrl->regs->ltesr, LTESR_NAND_MASK);

2
include/mpc85xx.h
View File

@ -6,8 +6,6 @@
#ifndef __MPC85xx_H__
#define __MPC85xx_H__
#include <asm/fsl_lbc.h>
/* define for common ppc_asm.tmpl */
#define EXC_OFF_SYS_RESET 0x100 /* System reset */
#define _START_OFFSET 0

5
nand_spl/board/freescale/mpc8536ds/nand_boot.c
View File

@ -34,12 +34,11 @@ void board_init_f(ulong bootflag)
int px_spd;
u32 plat_ratio, bus_clk, sys_clk;
ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
ccsr_lbc_t *lbc = (void *)CONFIG_SYS_MPC85xx_LBC_ADDR;
#if defined(CONFIG_SYS_BR3_PRELIM) && defined(CONFIG_SYS_OR3_PRELIM)
/* for FPGA */
out_be32(&lbc->br3, CONFIG_SYS_BR3_PRELIM);
out_be32(&lbc->or3, CONFIG_SYS_OR3_PRELIM);
set_lbc_br(3, CONFIG_SYS_BR3_PRELIM);
set_lbc_or(3, CONFIG_SYS_OR3_PRELIM);
#else
#error CONFIG_SYS_BR3_PRELIM, CONFIG_SYS_OR3_PRELIM must be defined
#endif

4
nand_spl/nand_boot_fsl_elbc.c
View File

@ -32,7 +32,7 @@
static void nand_wait(void)
{
fsl_lbus_t *regs = (fsl_lbus_t *)(CONFIG_SYS_IMMR + 0x5000);
fsl_lbc_t *regs = LBC_BASE_ADDR;
for (;;) {
uint32_t status = in_be32(&regs->ltesr);
@ -49,7 +49,7 @@ static void nand_wait(void)
static void nand_load(unsigned int offs, int uboot_size, uchar *dst)
{
fsl_lbus_t *regs = (fsl_lbus_t *)(CONFIG_SYS_IMMR + 0x5000);
fsl_lbc_t *regs = LBC_BASE_ADDR;
uchar *buf = (uchar *)CONFIG_SYS_NAND_BASE;
int large = in_be32(&regs->bank[0].or) & OR_FCM_PGS;
int block_shift = large ? 17 : 14;