arm: rmobile: Add support lager board
The lager board has R8A7790, 4GB DDR3-SDRAM, USB, Ethernet, and more. This patch supports the following functions: - DDR3-SDRAM - SCIF Signed-off-by: Kouei Abe <kouei.abe.cp@renesas.com> Signed-off-by: Hisashi Nakamura <hisashi.nakamura.ak@renesas.com> Signed-off-by: Ryo Kataoka <ryo.kataoka.wt@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> CC: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> CC: Albert Aribaud <albert.u.boot@aribaud.net>
This commit is contained in:
Nobuhiro Iwamatsu
Nobuhiro Iwamatsu
parent
1d0e92782f
commit
f4ec452297
9
board/renesas/lager/Makefile
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9
board/renesas/lager/Makefile
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@ -0,0 +1,9 @@
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#
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# board/renesas/lager/Makefile
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#
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# Copyright (C) 2013 Renesas Electronics Corporation
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#
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# SPDX-License-Identifier: GPL-2.0
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#
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obj-y := lager.o qos.o
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287
board/renesas/lager/lager.c
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287
board/renesas/lager/lager.c
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@ -0,0 +1,287 @@
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/*
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* board/renesas/lager/lager.c
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* This file is lager board support.
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*
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* Copyright (C) 2013 Renesas Electronics Corporation
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* Copyright (C) 2013 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
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*
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* SPDX-License-Identifier: GPL-2.0
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*/
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#include <common.h>
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#include <malloc.h>
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#include <netdev.h>
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#include <asm/processor.h>
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#include <asm/mach-types.h>
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#include <asm/io.h>
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#include <asm/errno.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/gpio.h>
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#include <asm/arch/rmobile.h>
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#include "qos.h"
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DECLARE_GLOBAL_DATA_PTR;
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#define s_init_wait(cnt) \
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({ \
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u32 i = 0x10000 * cnt; \
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while (i > 0) \
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i--; \
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})
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#define dbpdrgd_check(bsc) \
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({ \
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while ((readl(&bsc->dbpdrgd) & 0x1) != 0x1) \
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; \
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})
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#if defined(CONFIG_NORFLASH)
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static void bsc_init(void)
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{
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struct r8a7790_lbsc *lbsc = (struct r8a7790_lbsc *)LBSC_BASE;
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struct r8a7790_dbsc3 *dbsc3_0 = (struct r8a7790_dbsc3 *)DBSC3_0_BASE;
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/* LBSC */
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writel(0x00000020, &lbsc->cs0ctrl);
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writel(0x00000020, &lbsc->cs1ctrl);
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writel(0x00002020, &lbsc->ecs0ctrl);
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writel(0x00002020, &lbsc->ecs1ctrl);
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writel(0x077F077F, &lbsc->cswcr0);
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writel(0x077F077F, &lbsc->cswcr1);
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writel(0x077F077F, &lbsc->ecswcr0);
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writel(0x077F077F, &lbsc->ecswcr1);
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/* DBSC3 */
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s_init_wait(10);
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writel(0x0000A55A, &dbsc3_0->dbpdlck);
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writel(0x00000001, &dbsc3_0->dbpdrga);
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writel(0x80000000, &dbsc3_0->dbpdrgd);
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writel(0x00000004, &dbsc3_0->dbpdrga);
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dbpdrgd_check(dbsc3_0);
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writel(0x00000006, &dbsc3_0->dbpdrga);
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writel(0x0001C000, &dbsc3_0->dbpdrgd);
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writel(0x00000023, &dbsc3_0->dbpdrga);
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writel(0x00FD2480, &dbsc3_0->dbpdrgd);
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writel(0x00000010, &dbsc3_0->dbpdrga);
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writel(0xF004649B, &dbsc3_0->dbpdrgd);
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writel(0x0000000F, &dbsc3_0->dbpdrga);
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writel(0x00181EE4, &dbsc3_0->dbpdrgd);
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writel(0x0000000E, &dbsc3_0->dbpdrga);
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writel(0x33C03812, &dbsc3_0->dbpdrgd);
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writel(0x00000003, &dbsc3_0->dbpdrga);
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writel(0x0300C481, &dbsc3_0->dbpdrgd);
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writel(0x00000007, &dbsc3_0->dbkind);
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writel(0x10030A02, &dbsc3_0->dbconf0);
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writel(0x00000001, &dbsc3_0->dbphytype);
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writel(0x00000000, &dbsc3_0->dbbl);
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writel(0x0000000B, &dbsc3_0->dbtr0);
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writel(0x00000008, &dbsc3_0->dbtr1);
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writel(0x00000000, &dbsc3_0->dbtr2);
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writel(0x0000000B, &dbsc3_0->dbtr3);
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writel(0x000C000B, &dbsc3_0->dbtr4);
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writel(0x00000027, &dbsc3_0->dbtr5);
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writel(0x0000001C, &dbsc3_0->dbtr6);
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writel(0x00000005, &dbsc3_0->dbtr7);
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writel(0x00000018, &dbsc3_0->dbtr8);
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writel(0x00000008, &dbsc3_0->dbtr9);
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writel(0x0000000C, &dbsc3_0->dbtr10);
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writel(0x00000009, &dbsc3_0->dbtr11);
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writel(0x00000012, &dbsc3_0->dbtr12);
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writel(0x000000D0, &dbsc3_0->dbtr13);
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writel(0x00140005, &dbsc3_0->dbtr14);
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writel(0x00050004, &dbsc3_0->dbtr15);
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writel(0x70233005, &dbsc3_0->dbtr16);
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writel(0x000C0000, &dbsc3_0->dbtr17);
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writel(0x00000300, &dbsc3_0->dbtr18);
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writel(0x00000040, &dbsc3_0->dbtr19);
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writel(0x00000001, &dbsc3_0->dbrnk0);
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writel(0x00020001, &dbsc3_0->dbadj0);
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writel(0x20082008, &dbsc3_0->dbadj2);
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writel(0x00020002, &dbsc3_0->dbwt0cnf0);
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writel(0x0000000F, &dbsc3_0->dbwt0cnf4);
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writel(0x00000015, &dbsc3_0->dbpdrga);
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writel(0x00000D70, &dbsc3_0->dbpdrgd);
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writel(0x00000016, &dbsc3_0->dbpdrga);
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writel(0x00000006, &dbsc3_0->dbpdrgd);
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writel(0x00000017, &dbsc3_0->dbpdrga);
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writel(0x00000018, &dbsc3_0->dbpdrgd);
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writel(0x00000012, &dbsc3_0->dbpdrga);
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writel(0x9D5CBB66, &dbsc3_0->dbpdrgd);
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writel(0x00000013, &dbsc3_0->dbpdrga);
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writel(0x1A868300, &dbsc3_0->dbpdrgd);
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writel(0x00000023, &dbsc3_0->dbpdrga);
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writel(0x00FDB6C0, &dbsc3_0->dbpdrgd);
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writel(0x00000014, &dbsc3_0->dbpdrga);
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writel(0x300214D8, &dbsc3_0->dbpdrgd);
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writel(0x0000001A, &dbsc3_0->dbpdrga);
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writel(0x930035C7, &dbsc3_0->dbpdrgd);
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writel(0x00000060, &dbsc3_0->dbpdrga);
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writel(0x330657B2, &dbsc3_0->dbpdrgd);
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writel(0x00000011, &dbsc3_0->dbpdrga);
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writel(0x1000040B, &dbsc3_0->dbpdrgd);
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writel(0x0000FA00, &dbsc3_0->dbcmd);
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writel(0x00000001, &dbsc3_0->dbpdrga);
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writel(0x00000071, &dbsc3_0->dbpdrgd);
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writel(0x00000004, &dbsc3_0->dbpdrga);
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dbpdrgd_check(dbsc3_0);
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writel(0x0000FA00, &dbsc3_0->dbcmd);
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writel(0x2100FA00, &dbsc3_0->dbcmd);
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writel(0x0000FA00, &dbsc3_0->dbcmd);
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writel(0x0000FA00, &dbsc3_0->dbcmd);
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writel(0x0000FA00, &dbsc3_0->dbcmd);
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writel(0x0000FA00, &dbsc3_0->dbcmd);
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writel(0x0000FA00, &dbsc3_0->dbcmd);
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writel(0x0000FA00, &dbsc3_0->dbcmd);
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writel(0x0000FA00, &dbsc3_0->dbcmd);
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writel(0x110000DB, &dbsc3_0->dbcmd);
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writel(0x00000001, &dbsc3_0->dbpdrga);
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writel(0x00000181, &dbsc3_0->dbpdrgd);
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writel(0x00000004, &dbsc3_0->dbpdrga);
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dbpdrgd_check(dbsc3_0);
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writel(0x00000001, &dbsc3_0->dbpdrga);
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writel(0x0000FE01, &dbsc3_0->dbpdrgd);
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writel(0x00000004, &dbsc3_0->dbpdrga);
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dbpdrgd_check(dbsc3_0);
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writel(0x00000000, &dbsc3_0->dbbs0cnt1);
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writel(0x01004C20, &dbsc3_0->dbcalcnf);
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writel(0x014000AA, &dbsc3_0->dbcaltr);
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writel(0x00000140, &dbsc3_0->dbrfcnf0);
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writel(0x00081860, &dbsc3_0->dbrfcnf1);
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writel(0x00010000, &dbsc3_0->dbrfcnf2);
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writel(0x00000001, &dbsc3_0->dbrfen);
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writel(0x00000001, &dbsc3_0->dbacen);
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}
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#else
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#define bsc_init() do {} while (0)
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#endif /* CONFIG_NORFLASH */
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void s_init(void)
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{
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struct r8a7790_rwdt *rwdt = (struct r8a7790_rwdt *)RWDT_BASE;
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struct r8a7790_swdt *swdt = (struct r8a7790_swdt *)SWDT_BASE;
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/* Watchdog init */
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writel(0xA5A5A500, &rwdt->rwtcsra);
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writel(0xA5A5A500, &swdt->swtcsra);
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/* QoS(Quality-of-Service) Init */
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qos_init();
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/* BSC init */
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bsc_init();
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}
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#define MSTPSR1 0xE6150038
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#define SMSTPCR1 0xE6150134
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#define TMU0_MSTP125 (1 << 25)
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#define MSTPSR7 0xE61501C4
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#define SMSTPCR7 0xE615014C
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#define SCIF0_MSTP721 (1 << 21)
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#define PMMR 0xE6060000
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#define GPSR4 0xE6060014
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#define IPSR14 0xE6060058
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#define set_guard_reg(addr, mask, value) \
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{ \
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u32 val; \
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val = (readl(addr) & ~(mask)) | (value); \
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writel(~val, PMMR); \
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writel(val, addr); \
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}
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#define mstp_setbits(type, addr, saddr, set) \
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out_##type((saddr), in_##type(addr) | (set))
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#define mstp_clrbits(type, addr, saddr, clear) \
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out_##type((saddr), in_##type(addr) & ~(clear))
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#define mstp_setbits_le32(addr, saddr, set) \
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mstp_setbits(le32, addr, saddr, set)
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#define mstp_clrbits_le32(addr, saddr, clear) \
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mstp_clrbits(le32, addr, saddr, clear)
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int board_early_init_f(void)
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{
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/* TMU0 */
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mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
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#if defined(CONFIG_NORFLASH)
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/* SCIF0 */
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set_guard_reg(GPSR4, 0x34000000, 0x00000000);
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set_guard_reg(IPSR14, 0x00000FC7, 0x00000481);
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set_guard_reg(GPSR4, 0x00000000, 0x34000000);
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#endif
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mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF0_MSTP721);
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return 0;
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}
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DECLARE_GLOBAL_DATA_PTR;
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int board_init(void)
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{
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/* board id for linux */
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gd->bd->bi_arch_number = MACH_TYPE_LAGER;
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/* adress of boot parameters */
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gd->bd->bi_boot_params = LAGER_SDRAM_BASE + 0x100;
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/* Init PFC controller */
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r8a7790_pinmux_init();
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return 0;
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}
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int dram_init(void)
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{
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gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
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gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
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return 0;
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}
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const struct rmobile_sysinfo sysinfo = {
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CONFIG_RMOBILE_BOARD_STRING
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};
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void dram_init_banksize(void)
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{
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gd->bd->bi_dram[0].start = LAGER_SDRAM_BASE;
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gd->bd->bi_dram[0].size = LAGER_SDRAM_SIZE;
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}
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int board_late_init(void)
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{
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return 0;
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}
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void reset_cpu(ulong addr)
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{
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}
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1119
board/renesas/lager/qos.c
Normal file
1119
board/renesas/lager/qos.c
Normal file
File diff suppressed because it is too large
Load Diff
12
board/renesas/lager/qos.h
Normal file
12
board/renesas/lager/qos.h
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@ -0,0 +1,12 @@
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/*
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* Copyright (C) 2013 Renesas Electronics Corporation
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*
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* SPDX-License-Identifier: GPL-2.0
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*/
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#ifndef __QOS_H__
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#define __QOS_H__
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void qos_init(void);
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#endif
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@ -338,6 +338,8 @@ Active arm armv7 omap5 ti dra7xx
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Active arm armv7 omap5 ti omap5_uevm omap5_uevm - -
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Active arm armv7 rmobile atmark-techno armadillo-800eva armadillo-800eva - Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
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Active arm armv7 rmobile kmc kzm9g kzm9g - Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>:Tetsuyuki Kobayashi <koba@kmckk.co.jp>
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Active arm armv7 rmobile renesas lager lager - Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
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Active arm armv7 rmobile renesas lager lager_nor lager:NORFLASH Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
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Active arm armv7 s5pc1xx samsung goni s5p_goni - Minkyu Kang <mk7.kang@samsung.com>
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Active arm armv7 s5pc1xx samsung smdkc100 smdkc100 - Minkyu Kang <mk7.kang@samsung.com>
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Active arm armv7 socfpga altera socfpga socfpga_cyclone5 - -
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141
include/configs/lager.h
Normal file
141
include/configs/lager.h
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/*
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* include/configs/lager.h
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* This file is lager board configuration.
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*
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* Copyright (C) 2013 Renesas Electronics Corporation
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*
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* SPDX-License-Identifier: GPL-2.0
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*/
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#ifndef __LAGER_H
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#define __LAGER_H
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#undef DEBUG
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#define CONFIG_ARMV7
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#define CONFIG_R8A7790
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#define CONFIG_RMOBILE
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#define CONFIG_RMOBILE_BOARD_STRING "Lager"
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#define CONFIG_SH_GPIO_PFC
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#define MACH_TYPE_LAGER 4538
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#define CONFIG_MACH_TYPE MACH_TYPE_LAGER
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#include <asm/arch/rmobile.h>
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#define CONFIG_CMD_EDITENV
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#define CONFIG_CMD_SAVEENV
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#define CONFIG_CMD_MEMORY
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#define CONFIG_CMD_DFL
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#define CONFIG_CMD_SDRAM
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#define CONFIG_CMD_RUN
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#define CONFIG_CMD_LOADS
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#define CONFIG_CMD_BOOTZ
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#define CONFIG_CMD_FLASH
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#define CONFIG_CMDLINE_TAG
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#define CONFIG_SETUP_MEMORY_TAGS
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#define CONFIG_INITRD_TAG
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#define CONFIG_CMDLINE_EDITING
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#define CONFIG_OF_LIBFDT
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/* #define CONFIG_OF_LIBFDT */
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#define BOARD_LATE_INIT
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#define CONFIG_BAUDRATE 38400
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#define CONFIG_BOOTDELAY 3
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#define CONFIG_BOOTARGS ""
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#define CONFIG_VERSION_VARIABLE
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#undef CONFIG_SHOW_BOOT_PROGRESS
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#define CONFIG_ARCH_CPU_INIT
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#define CONFIG_DISPLAY_CPUINFO
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#define CONFIG_DISPLAY_BOARDINFO
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#define CONFIG_BOARD_EARLY_INIT_F
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#define CONFIG_USE_ARCH_MEMSET
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#define CONFIG_USE_ARCH_MEMCPY
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#define CONFIG_TMU_TIMER
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/* STACK */
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#define CONFIG_SYS_INIT_SP_ADDR 0xE827fffc
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#define STACK_AREA_SIZE 0xC000
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#define LOW_LEVEL_MERAM_STACK \
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(CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4)
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/* MEMORY */
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#define LAGER_SDRAM_BASE 0x40000000
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#define LAGER_SDRAM_SIZE (2048u * 1024 * 1024)
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||||
#define LAGER_UBOOT_SDRAM_SIZE (512 * 1024 * 1024)
|
||||
|
||||
#define CONFIG_SYS_LONGHELP
|
||||
#define CONFIG_SYS_CBSIZE 256
|
||||
#define CONFIG_SYS_PBSIZE 256
|
||||
#define CONFIG_SYS_MAXARGS 16
|
||||
#define CONFIG_SYS_BARGSIZE 512
|
||||
#define CONFIG_SYS_BAUDRATE_TABLE { 38400, 115200 }
|
||||
|
||||
/* SCIF */
|
||||
#define CONFIG_SCIF_CONSOLE
|
||||
#define CONFIG_CONS_SCIF0
|
||||
#define SCIF0_BASE 0xe6e60000
|
||||
#undef CONFIG_SYS_CONSOLE_INFO_QUIET
|
||||
#undef CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
|
||||
#undef CONFIG_SYS_CONSOLE_ENV_OVERWRITE
|
||||
|
||||
#define CONFIG_SYS_MEMTEST_START (LAGER_SDRAM_BASE)
|
||||
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \
|
||||
504 * 1024 * 1024)
|
||||
#undef CONFIG_SYS_ALT_MEMTEST
|
||||
#undef CONFIG_SYS_MEMTEST_SCRATCH
|
||||
#undef CONFIG_SYS_LOADS_BAUD_CHANGE
|
||||
|
||||
#define CONFIG_SYS_SDRAM_BASE (LAGER_SDRAM_BASE)
|
||||
#define CONFIG_SYS_SDRAM_SIZE (LAGER_UBOOT_SDRAM_SIZE)
|
||||
#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fc0)
|
||||
#define CONFIG_NR_DRAM_BANKS 1
|
||||
|
||||
#define CONFIG_SYS_MONITOR_BASE 0x00000000
|
||||
#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
|
||||
#define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024)
|
||||
#define CONFIG_SYS_GBL_DATA_SIZE (256)
|
||||
#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
|
||||
|
||||
/* USE NOR FLASH */
|
||||
#define CONFIG_SYS_TEXT_BASE 0x00000000
|
||||
#define CONFIG_SYS_FLASH_CFI
|
||||
#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
|
||||
#define CONFIG_FLASH_CFI_DRIVER
|
||||
#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
|
||||
#define CONFIG_FLASH_SHOW_PROGRESS 45
|
||||
#define CONFIG_SYS_FLASH_BASE 0x00000000
|
||||
#define CONFIG_SYS_FLASH_SIZE 0x04000000 /* 64 MB */
|
||||
#define CONFIG_SYS_MAX_FLASH_SECT 1024
|
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 1
|
||||
#define CONFIG_SYS_FLASH_BANKS_LIST { (CONFIG_SYS_FLASH_BASE) }
|
||||
#define CONFIG_SYS_FLASH_BANKS_SIZES { (CONFIG_SYS_FLASH_SIZE) }
|
||||
#define CONFIG_SYS_FLASH_ERASE_TOUT 3000
|
||||
#define CONFIG_SYS_FLASH_WRITE_TOUT 3000
|
||||
#define CONFIG_SYS_FLASH_LOCK_TOUT 3000
|
||||
#define CONFIG_SYS_FLASH_UNLOCK_TOUT 3000
|
||||
|
||||
/* ENV setting */
|
||||
#define CONFIG_ENV_IS_IN_FLASH
|
||||
#define CONFIG_ENV_OVERWRITE 1
|
||||
#define CONFIG_ENV_SECT_SIZE (256 * 1024)
|
||||
#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + \
|
||||
CONFIG_SYS_MONITOR_LEN)
|
||||
#define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR)
|
||||
#define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE)
|
||||
#define CONFIG_ENV_SIZE_REDUND (CONFIG_SYS_MONITOR_LEN)
|
||||
|
||||
/* Board Clock */
|
||||
#define CONFIG_BASE_CLK_FREQ 20000000u
|
||||
#define CONFIG_SH_TMU_CLK_FREQ (CONFIG_BASE_CLK_FREQ / 2) /* EXT / 2 */
|
||||
#define CONFIG_PLL1_CLK_FREQ (CONFIG_BASE_CLK_FREQ * 156 / 2)
|
||||
#define CONFIG_PLL1_DIV2_CLK_FREQ (CONFIG_PLL1_CLK_FREQ / 2)
|
||||
#define CONFIG_MP_CLK_FREQ (CONFIG_PLL1_DIV2_CLK_FREQ / 15)
|
||||
#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_MP_CLK_FREQ
|
||||
|
||||
#define CONFIG_SYS_TMU_CLK_DIV 4
|
||||
#define CONFIG_SYS_HZ 1000
|
||||
|
||||
#endif /* __LAGER_H */
|
||||
Loading…
Reference in New Issue
Block a user