Merge branch 'master' of git://git.denx.de/u-boot-i2c
This commit is contained in:
Tom Rini
commit
f4cfd73943
@ -450,9 +450,16 @@ config SYS_I2C_BUS_MAX
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help
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Define the maximum number of available I2C buses.
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config SYS_I2C_XILINX_XIIC
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bool "Xilinx AXI I2C driver"
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depends on DM_I2C
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help
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Support for Xilinx AXI I2C controller.
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config SYS_I2C_ZYNQ
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bool "Xilinx I2C driver"
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depends on ARCH_ZYNQMP || ARCH_ZYNQ
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depends on !DM_I2C
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help
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Support for Xilinx I2C controller.
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@ -37,6 +37,7 @@ obj-$(CONFIG_SYS_I2C_TEGRA) += tegra_i2c.o
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obj-$(CONFIG_SYS_I2C_UNIPHIER) += i2c-uniphier.o
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obj-$(CONFIG_SYS_I2C_UNIPHIER_F) += i2c-uniphier-f.o
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obj-$(CONFIG_SYS_I2C_VERSATILE) += i2c-versatile.o
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obj-$(CONFIG_SYS_I2C_XILINX_XIIC) += xilinx_xiic.o
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obj-$(CONFIG_SYS_I2C_ZYNQ) += zynq_i2c.o
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obj-$(CONFIG_TEGRA186_BPMP_I2C) += tegra186_bpmp_i2c.o
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@ -17,6 +17,7 @@
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#include <fdtdec.h>
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#include <mapmem.h>
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#include <wait_bit.h>
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#include <clk.h>
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/* i2c register set */
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struct cdns_i2c_regs {
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@ -415,6 +416,8 @@ static int cdns_i2c_ofdata_to_platdata(struct udevice *dev)
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struct i2c_cdns_bus *i2c_bus = dev_get_priv(dev);
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struct cdns_i2c_platform_data *pdata =
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(struct cdns_i2c_platform_data *)dev_get_driver_data(dev);
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struct clk clk;
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int ret;
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i2c_bus->regs = (struct cdns_i2c_regs *)devfdt_get_addr(dev);
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if (!i2c_bus->regs)
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@ -423,7 +426,11 @@ static int cdns_i2c_ofdata_to_platdata(struct udevice *dev)
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if (pdata)
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i2c_bus->quirks = pdata->quirks;
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i2c_bus->input_freq = 100000000; /* TODO hardcode input freq for now */
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ret = clk_get_by_index(dev, 0, &clk);
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if (ret)
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return ret;
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i2c_bus->input_freq = clk_get_rate(&clk);
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return 0;
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}
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@ -11,8 +11,6 @@
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#include <dm/lists.h>
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#include <dm/root.h>
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DECLARE_GLOBAL_DATA_PTR;
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/**
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* struct i2c_mux: Information the uclass stores about an I2C mux
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*
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@ -39,7 +37,7 @@ static int i2c_mux_child_post_bind(struct udevice *dev)
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struct i2c_mux_bus *plat = dev_get_parent_platdata(dev);
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int channel;
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channel = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), "reg", -1);
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channel = dev_read_u32_default(dev, "reg", -1);
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if (channel < 0)
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return -EINVAL;
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plat->channel = channel;
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@ -101,7 +101,7 @@ static int pca954x_ofdata_to_platdata(struct udevice *dev)
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struct pca954x_priv *priv = dev_get_priv(dev);
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const struct chip_desc *chip = &chips[dev_get_driver_data(dev)];
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priv->addr = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), "reg", 0);
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priv->addr = dev_read_u32_default(dev, "reg", 0);
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if (!priv->addr) {
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debug("MUX not found\n");
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return -ENODEV;
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340
drivers/i2c/xilinx_xiic.c
Normal file
340
drivers/i2c/xilinx_xiic.c
Normal file
@ -0,0 +1,340 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Xilinx AXI I2C driver
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*
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* Copyright (C) 2018 Marek Vasut <marex@denx.de>
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*
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* Based on Linux 4.14.y i2c-xiic.c
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* Copyright (c) 2002-2007 Xilinx Inc.
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* Copyright (c) 2009-2010 Intel Corporation
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*/
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#include <common.h>
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#include <clk.h>
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#include <dm.h>
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#include <i2c.h>
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#include <wait_bit.h>
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#include <asm/io.h>
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struct xilinx_xiic_priv {
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void __iomem *base;
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struct clk clk;
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};
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#define XIIC_MSB_OFFSET 0
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#define XIIC_REG_OFFSET (0x100+XIIC_MSB_OFFSET)
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/*
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* Register offsets in bytes from RegisterBase. Three is added to the
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* base offset to access LSB (IBM style) of the word
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*/
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#define XIIC_CR_REG_OFFSET (0x00+XIIC_REG_OFFSET) /* Control Register */
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#define XIIC_SR_REG_OFFSET (0x04+XIIC_REG_OFFSET) /* Status Register */
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#define XIIC_DTR_REG_OFFSET (0x08+XIIC_REG_OFFSET) /* Data Tx Register */
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#define XIIC_DRR_REG_OFFSET (0x0C+XIIC_REG_OFFSET) /* Data Rx Register */
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#define XIIC_ADR_REG_OFFSET (0x10+XIIC_REG_OFFSET) /* Address Register */
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#define XIIC_TFO_REG_OFFSET (0x14+XIIC_REG_OFFSET) /* Tx FIFO Occupancy */
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#define XIIC_RFO_REG_OFFSET (0x18+XIIC_REG_OFFSET) /* Rx FIFO Occupancy */
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#define XIIC_TBA_REG_OFFSET (0x1C+XIIC_REG_OFFSET) /* 10 Bit Address reg */
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#define XIIC_RFD_REG_OFFSET (0x20+XIIC_REG_OFFSET) /* Rx FIFO Depth reg */
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#define XIIC_GPO_REG_OFFSET (0x24+XIIC_REG_OFFSET) /* Output Register */
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/* Control Register masks */
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#define XIIC_CR_ENABLE_DEVICE_MASK 0x01 /* Device enable = 1 */
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#define XIIC_CR_TX_FIFO_RESET_MASK 0x02 /* Transmit FIFO reset=1 */
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#define XIIC_CR_MSMS_MASK 0x04 /* Master starts Txing=1 */
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#define XIIC_CR_DIR_IS_TX_MASK 0x08 /* Dir of tx. Txing=1 */
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#define XIIC_CR_NO_ACK_MASK 0x10 /* Tx Ack. NO ack = 1 */
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#define XIIC_CR_REPEATED_START_MASK 0x20 /* Repeated start = 1 */
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#define XIIC_CR_GENERAL_CALL_MASK 0x40 /* Gen Call enabled = 1 */
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/* Status Register masks */
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#define XIIC_SR_GEN_CALL_MASK 0x01 /* 1=a mstr issued a GC */
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#define XIIC_SR_ADDR_AS_SLAVE_MASK 0x02 /* 1=when addr as slave */
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#define XIIC_SR_BUS_BUSY_MASK 0x04 /* 1 = bus is busy */
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#define XIIC_SR_MSTR_RDING_SLAVE_MASK 0x08 /* 1=Dir: mstr <-- slave */
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#define XIIC_SR_TX_FIFO_FULL_MASK 0x10 /* 1 = Tx FIFO full */
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#define XIIC_SR_RX_FIFO_FULL_MASK 0x20 /* 1 = Rx FIFO full */
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#define XIIC_SR_RX_FIFO_EMPTY_MASK 0x40 /* 1 = Rx FIFO empty */
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#define XIIC_SR_TX_FIFO_EMPTY_MASK 0x80 /* 1 = Tx FIFO empty */
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/* Interrupt Status Register masks Interrupt occurs when... */
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#define XIIC_INTR_ARB_LOST_MASK 0x01 /* 1 = arbitration lost */
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#define XIIC_INTR_TX_ERROR_MASK 0x02 /* 1=Tx error/msg complete */
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#define XIIC_INTR_TX_EMPTY_MASK 0x04 /* 1 = Tx FIFO/reg empty */
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#define XIIC_INTR_RX_FULL_MASK 0x08 /* 1=Rx FIFO/reg=OCY level */
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#define XIIC_INTR_BNB_MASK 0x10 /* 1 = Bus not busy */
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#define XIIC_INTR_AAS_MASK 0x20 /* 1 = when addr as slave */
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#define XIIC_INTR_NAAS_MASK 0x40 /* 1 = not addr as slave */
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#define XIIC_INTR_TX_HALF_MASK 0x80 /* 1 = TX FIFO half empty */
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/* The following constants specify the depth of the FIFOs */
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#define IIC_RX_FIFO_DEPTH 16 /* Rx fifo capacity */
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#define IIC_TX_FIFO_DEPTH 16 /* Tx fifo capacity */
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/*
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* Tx Fifo upper bit masks.
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*/
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#define XIIC_TX_DYN_START_MASK 0x0100 /* 1 = Set dynamic start */
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#define XIIC_TX_DYN_STOP_MASK 0x0200 /* 1 = Set dynamic stop */
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/*
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* The following constants define the register offsets for the Interrupt
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* registers. There are some holes in the memory map for reserved addresses
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* to allow other registers to be added and still match the memory map of the
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* interrupt controller registers
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*/
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#define XIIC_DGIER_OFFSET 0x1C /* Device Global Interrupt Enable Register */
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#define XIIC_IISR_OFFSET 0x20 /* Interrupt Status Register */
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#define XIIC_IIER_OFFSET 0x28 /* Interrupt Enable Register */
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#define XIIC_RESETR_OFFSET 0x40 /* Reset Register */
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#define XIIC_RESET_MASK 0xAUL
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static u8 i2c_8bit_addr_from_flags(uint addr, u16 flags)
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{
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return (addr << 1) | (flags & I2C_M_RD ? 1 : 0);
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}
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static void xiic_irq_clr(struct xilinx_xiic_priv *priv, u32 mask)
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{
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u32 isr = readl(priv->base + XIIC_IISR_OFFSET);
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writel(isr & mask, priv->base + XIIC_IISR_OFFSET);
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}
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static int xiic_read_rx(struct xilinx_xiic_priv *priv,
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struct i2c_msg *msg, int nmsgs)
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{
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u8 bytes_in_fifo;
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u32 pos = 0;
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int i, ret;
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while (pos < msg->len) {
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ret = wait_for_bit_8(priv->base + XIIC_SR_REG_OFFSET,
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XIIC_SR_RX_FIFO_EMPTY_MASK, false,
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1000, true);
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if (ret)
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return ret;
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bytes_in_fifo = readb(priv->base + XIIC_RFO_REG_OFFSET) + 1;
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if (bytes_in_fifo > msg->len)
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bytes_in_fifo = msg->len;
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for (i = 0; i < bytes_in_fifo; i++) {
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msg->buf[pos++] = readb(priv->base +
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XIIC_DRR_REG_OFFSET);
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}
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}
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return 0;
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}
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static int xiic_tx_fifo_space(struct xilinx_xiic_priv *priv)
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{
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/* return the actual space left in the FIFO */
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return IIC_TX_FIFO_DEPTH - readb(priv->base + XIIC_TFO_REG_OFFSET) - 1;
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}
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static void xiic_fill_tx_fifo(struct xilinx_xiic_priv *priv,
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struct i2c_msg *msg, int nmsgs)
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{
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u8 fifo_space = xiic_tx_fifo_space(priv);
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int len = msg->len;
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u32 pos = 0;
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len = (len > fifo_space) ? fifo_space : len;
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while (len--) {
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u16 data = msg->buf[pos++];
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if (pos == len && nmsgs == 1) {
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/* last message in transfer -> STOP */
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data |= XIIC_TX_DYN_STOP_MASK;
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}
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writew(data, priv->base + XIIC_DTR_REG_OFFSET);
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}
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}
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static void xilinx_xiic_set_addr(struct udevice *dev, u8 addr,
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u16 flags, u32 len, u32 nmsgs)
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{
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struct xilinx_xiic_priv *priv = dev_get_priv(dev);
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xiic_irq_clr(priv, XIIC_INTR_TX_ERROR_MASK);
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if (!(flags & I2C_M_NOSTART)) {
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/* write the address */
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u16 data = i2c_8bit_addr_from_flags(addr, flags) |
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XIIC_TX_DYN_START_MASK;
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if (nmsgs == 1 && len == 0)
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/* no data and last message -> add STOP */
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data |= XIIC_TX_DYN_STOP_MASK;
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writew(data, priv->base + XIIC_DTR_REG_OFFSET);
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}
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}
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static int xilinx_xiic_read_common(struct udevice *dev, struct i2c_msg *msg,
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u32 nmsgs)
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{
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struct xilinx_xiic_priv *priv = dev_get_priv(dev);
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u8 rx_watermark;
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/* Clear and enable Rx full interrupt. */
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xiic_irq_clr(priv, XIIC_INTR_RX_FULL_MASK | XIIC_INTR_TX_ERROR_MASK);
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/* we want to get all but last byte, because the TX_ERROR IRQ is used
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* to inidicate error ACK on the address, and negative ack on the last
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* received byte, so to not mix them receive all but last.
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* In the case where there is only one byte to receive
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* we can check if ERROR and RX full is set at the same time
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*/
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rx_watermark = msg->len;
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if (rx_watermark > IIC_RX_FIFO_DEPTH)
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rx_watermark = IIC_RX_FIFO_DEPTH;
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writeb(rx_watermark - 1, priv->base + XIIC_RFD_REG_OFFSET);
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xilinx_xiic_set_addr(dev, msg->addr, msg->flags, msg->len, nmsgs);
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xiic_irq_clr(priv, XIIC_INTR_BNB_MASK);
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writew((msg->len & 0xff) | ((nmsgs == 1) ? XIIC_TX_DYN_STOP_MASK : 0),
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priv->base + XIIC_DTR_REG_OFFSET);
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if (nmsgs == 1)
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/* very last, enable bus not busy as well */
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xiic_irq_clr(priv, XIIC_INTR_BNB_MASK);
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return xiic_read_rx(priv, msg, nmsgs);
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}
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static int xilinx_xiic_write_common(struct udevice *dev, struct i2c_msg *msg,
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int nmsgs)
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{
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struct xilinx_xiic_priv *priv = dev_get_priv(dev);
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int ret;
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xilinx_xiic_set_addr(dev, msg->addr, msg->flags, msg->len, nmsgs);
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xiic_fill_tx_fifo(priv, msg, nmsgs);
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ret = wait_for_bit_8(priv->base + XIIC_SR_REG_OFFSET,
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XIIC_SR_TX_FIFO_EMPTY_MASK, false, 1000, true);
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if (ret)
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return ret;
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/* Clear any pending Tx empty, Tx Error and then enable them. */
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xiic_irq_clr(priv, XIIC_INTR_TX_EMPTY_MASK | XIIC_INTR_TX_ERROR_MASK |
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XIIC_INTR_BNB_MASK);
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return 0;
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}
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static void xiic_clear_rx_fifo(struct xilinx_xiic_priv *priv)
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{
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u8 sr;
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for (sr = readb(priv->base + XIIC_SR_REG_OFFSET);
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!(sr & XIIC_SR_RX_FIFO_EMPTY_MASK);
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sr = readb(priv->base + XIIC_SR_REG_OFFSET))
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readb(priv->base + XIIC_DRR_REG_OFFSET);
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}
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static void xiic_reinit(struct xilinx_xiic_priv *priv)
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{
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writel(XIIC_RESET_MASK, priv->base + XIIC_RESETR_OFFSET);
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/* Set receive Fifo depth to maximum (zero based). */
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writeb(IIC_RX_FIFO_DEPTH - 1, priv->base + XIIC_RFD_REG_OFFSET);
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/* Reset Tx Fifo. */
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writeb(XIIC_CR_TX_FIFO_RESET_MASK, priv->base + XIIC_CR_REG_OFFSET);
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/* Enable IIC Device, remove Tx Fifo reset & disable general call. */
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writeb(XIIC_CR_ENABLE_DEVICE_MASK, priv->base + XIIC_CR_REG_OFFSET);
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|
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/* make sure RX fifo is empty */
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xiic_clear_rx_fifo(priv);
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|
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/* Disable interrupts */
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writel(0, priv->base + XIIC_DGIER_OFFSET);
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|
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xiic_irq_clr(priv, XIIC_INTR_ARB_LOST_MASK);
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}
|
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|
||||
static int xilinx_xiic_xfer(struct udevice *dev, struct i2c_msg *msg, int nmsgs)
|
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{
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int ret = 0;
|
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|
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for (; nmsgs > 0; nmsgs--, msg++) {
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||||
if (msg->flags & I2C_M_RD)
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ret = xilinx_xiic_read_common(dev, msg, nmsgs);
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||||
else
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ret = xilinx_xiic_write_common(dev, msg, nmsgs);
|
||||
|
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if (ret)
|
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return -EREMOTEIO;
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||||
}
|
||||
|
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return ret;
|
||||
}
|
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|
||||
static int xilinx_xiic_probe_chip(struct udevice *dev, uint addr, uint flags)
|
||||
{
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struct xilinx_xiic_priv *priv = dev_get_priv(dev);
|
||||
u32 reg;
|
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int ret;
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|
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xiic_reinit(priv);
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xilinx_xiic_set_addr(dev, addr, 0, 0, 1);
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ret = wait_for_bit_8(priv->base + XIIC_SR_REG_OFFSET,
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XIIC_SR_BUS_BUSY_MASK, false, 1000, true);
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if (ret)
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return ret;
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reg = readl(priv->base + XIIC_IISR_OFFSET);
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if (reg & XIIC_INTR_TX_ERROR_MASK)
|
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return -ENODEV;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int xilinx_xiic_set_speed(struct udevice *dev, uint speed)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int xilinx_xiic_probe(struct udevice *dev)
|
||||
{
|
||||
struct xilinx_xiic_priv *priv = dev_get_priv(dev);
|
||||
|
||||
priv->base = dev_read_addr_ptr(dev);
|
||||
|
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writel(XIIC_CR_TX_FIFO_RESET_MASK, priv->base + XIIC_CR_REG_OFFSET);
|
||||
xiic_reinit(priv);
|
||||
|
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return 0;
|
||||
}
|
||||
|
||||
static const struct dm_i2c_ops xilinx_xiic_ops = {
|
||||
.xfer = xilinx_xiic_xfer,
|
||||
.probe_chip = xilinx_xiic_probe_chip,
|
||||
.set_bus_speed = xilinx_xiic_set_speed,
|
||||
};
|
||||
|
||||
static const struct udevice_id xilinx_xiic_ids[] = {
|
||||
{ .compatible = "xlnx,xps-iic-2.00.a" },
|
||||
{ }
|
||||
};
|
||||
|
||||
U_BOOT_DRIVER(xilinx_xiic) = {
|
||||
.name = "xilinx_axi_i2c",
|
||||
.id = UCLASS_I2C,
|
||||
.of_match = xilinx_xiic_ids,
|
||||
.probe = xilinx_xiic_probe,
|
||||
.priv_auto_alloc_size = sizeof(struct xilinx_xiic_priv),
|
||||
.ops = &xilinx_xiic_ops,
|
||||
};
|
||||
Loading…
Reference in New Issue
Block a user