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global: Migrate CONFIG_PL011_CLOCK to CFG

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Perform a simple rename of CONFIG_PL011_CLOCK to CFG_PL011_CLOCK

Signed-off-by: Tom Rini <trini@konsulko.com>
This commit is contained in:
Tom Rini 2022-12-04 10:13:30 -05:00
parent 830fd095a3
commit f410d0ac8a
15 changed files with 19 additions and 19 deletions
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2
README
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@ -413,7 +413,7 @@ The following options need to be configured:
controller register space controller register space
- Serial Ports: - Serial Ports:
CONFIG_PL011_CLOCK CFG_PL011_CLOCK
If you have Amba PrimeCell PL011 UARTs, set this variable to If you have Amba PrimeCell PL011 UARTs, set this variable to
the clock speed of the UARTs. the clock speed of the UARTs.

2
arch/arm/cpu/armv7/s5p4418/cpu.c
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@ -64,7 +64,7 @@ static void serial_device_init(void)
/* set clock */ /* set clock */
clk_disable(clk); clk_disable(clk);
clk_set_rate(clk, CONFIG_PL011_CLOCK); clk_set_rate(clk, CFG_PL011_CLOCK);
clk_enable(clk); clk_enable(clk);
} }
#endif #endif

2
board/armltd/total_compute/total_compute.c
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@ -13,7 +13,7 @@
static const struct pl01x_serial_plat serial_plat = { static const struct pl01x_serial_plat serial_plat = {
.base = UART0_BASE, .base = UART0_BASE,
.type = TYPE_PL011, .type = TYPE_PL011,
.clock = CONFIG_PL011_CLOCK, .clock = CFG_PL011_CLOCK,
}; };
U_BOOT_DRVINFO(total_compute_serials) = { U_BOOT_DRVINFO(total_compute_serials) = {

2
board/armltd/vexpress64/vexpress64.c
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@ -29,7 +29,7 @@ DECLARE_GLOBAL_DATA_PTR;
static const struct pl01x_serial_plat serial_plat = { static const struct pl01x_serial_plat serial_plat = {
.base = V2M_UART0, .base = V2M_UART0,
.type = TYPE_PL011, .type = TYPE_PL011,
.clock = CONFIG_PL011_CLOCK, .clock = CFG_PL011_CLOCK,
}; };
U_BOOT_DRVINFO(vexpress_serials) = { U_BOOT_DRVINFO(vexpress_serials) = {

8
drivers/serial/serial_pl01x.c
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@ -193,7 +193,7 @@ static void pl01x_serial_init_baud(int baudrate)
#if defined(CONFIG_PL011_SERIAL) #if defined(CONFIG_PL011_SERIAL)
pl01x_type = TYPE_PL011; pl01x_type = TYPE_PL011;
clock = CONFIG_PL011_CLOCK; clock = CFG_PL011_CLOCK;
#endif #endif
base_regs = (struct pl01x_regs *)port[CONFIG_CONS_INDEX]; base_regs = (struct pl01x_regs *)port[CONFIG_CONS_INDEX];
@ -343,8 +343,8 @@ static const struct udevice_id pl01x_serial_id[] ={
{} {}
}; };
#ifndef CONFIG_PL011_CLOCK #ifndef CFG_PL011_CLOCK
#define CONFIG_PL011_CLOCK 0 #define CFG_PL011_CLOCK 0
#endif #endif
int pl01x_serial_of_to_plat(struct udevice *dev) int pl01x_serial_of_to_plat(struct udevice *dev)
@ -359,7 +359,7 @@ int pl01x_serial_of_to_plat(struct udevice *dev)
return -EINVAL; return -EINVAL;
plat->base = addr; plat->base = addr;
plat->clock = dev_read_u32_default(dev, "clock", CONFIG_PL011_CLOCK); plat->clock = dev_read_u32_default(dev, "clock", CFG_PL011_CLOCK);
ret = clk_get_by_index(dev, 0, &clk); ret = clk_get_by_index(dev, 0, &clk);
if (!ret) { if (!ret) {
ret = clk_enable(&clk); ret = clk_enable(&clk);

2
include/configs/corstone1000.h
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@ -16,7 +16,7 @@
#define V2M_BASE 0x80000000 #define V2M_BASE 0x80000000
#define CONFIG_PL011_CLOCK 50000000 #define CFG_PL011_CLOCK 50000000
/* Physical Memory Map */ /* Physical Memory Map */
#define PHYS_SDRAM_1 (V2M_BASE) #define PHYS_SDRAM_1 (V2M_BASE)

2
include/configs/highbank.h
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@ -8,7 +8,7 @@
#define CFG_SYS_BOOTMAPSZ (16 << 20) #define CFG_SYS_BOOTMAPSZ (16 << 20)
#define CONFIG_PL011_CLOCK 150000000 #define CFG_PL011_CLOCK 150000000
/* /*
* Miscellaneous configurable options * Miscellaneous configurable options

2
include/configs/lx2160a_common.h
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@ -39,7 +39,7 @@
/* Serial Port */ /* Serial Port */
#define CONFIG_PL011_CLOCK (get_bus_freq(0) / 4) #define CFG_PL011_CLOCK (get_bus_freq(0) / 4)
#define CFG_SYS_SERIAL0 0x21c0000 #define CFG_SYS_SERIAL0 0x21c0000
#define CFG_SYS_SERIAL1 0x21d0000 #define CFG_SYS_SERIAL1 0x21d0000
#define CFG_SYS_SERIAL2 0x21e0000 #define CFG_SYS_SERIAL2 0x21e0000

2
include/configs/mxs.h
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@ -77,7 +77,7 @@
* DUART Serial Driver. * DUART Serial Driver.
* Conflicts with AUART driver which can be set by board. * Conflicts with AUART driver which can be set by board.
*/ */
#define CONFIG_PL011_CLOCK 24000000 #define CFG_PL011_CLOCK 24000000
#define CONFIG_PL01x_PORTS { (void *)MXS_UARTDBG_BASE } #define CONFIG_PL01x_PORTS { (void *)MXS_UARTDBG_BASE }
/* Default baudrate can be overridden by board! */ /* Default baudrate can be overridden by board! */

2
include/configs/s5p4418_nanopi2.h
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@ -76,7 +76,7 @@
/*----------------------------------------------------------------------- /*-----------------------------------------------------------------------
* serial console configuration * serial console configuration
*/ */
#define CONFIG_PL011_CLOCK 50000000 #define CFG_PL011_CLOCK 50000000
#define CONFIG_PL01x_PORTS {(void *)PHY_BASEADDR_UART0, \ #define CONFIG_PL01x_PORTS {(void *)PHY_BASEADDR_UART0, \
(void *)PHY_BASEADDR_UART1, \ (void *)PHY_BASEADDR_UART1, \
(void *)PHY_BASEADDR_UART2, \ (void *)PHY_BASEADDR_UART2, \

2
include/configs/synquacer.h
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@ -31,7 +31,7 @@
/* Serial (pl011) */ /* Serial (pl011) */
#define UART_CLK (62500000) #define UART_CLK (62500000)
#define CONFIG_PL011_CLOCK UART_CLK #define CFG_PL011_CLOCK UART_CLK
#define CONFIG_PL01x_PORTS {(void *)(0x2a400000)} #define CONFIG_PL01x_PORTS {(void *)(0x2a400000)}
/* Support MTD */ /* Support MTD */

2
include/configs/thunderx_88xx.h
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@ -17,7 +17,7 @@
/* PL011 Serial Configuration */ /* PL011 Serial Configuration */
#define CONFIG_PL011_CLOCK 24000000 #define CFG_PL011_CLOCK 24000000
/* Generic Interrupt Controller Definitions */ /* Generic Interrupt Controller Definitions */
#define GICD_BASE (0x801000000000) #define GICD_BASE (0x801000000000)

2
include/configs/total_compute.h
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@ -14,7 +14,7 @@
#define UART0_BASE 0x7ff80000 #define UART0_BASE 0x7ff80000
/* PL011 Serial Configuration */ /* PL011 Serial Configuration */
#define CONFIG_PL011_CLOCK 7372800 #define CFG_PL011_CLOCK 7372800
/* Miscellaneous configurable options */ /* Miscellaneous configurable options */

4
include/configs/vexpress_aemv8.h
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@ -86,9 +86,9 @@
/* PL011 Serial Configuration */ /* PL011 Serial Configuration */
#ifdef CONFIG_TARGET_VEXPRESS64_JUNO #ifdef CONFIG_TARGET_VEXPRESS64_JUNO
#define CONFIG_PL011_CLOCK 7372800 #define CFG_PL011_CLOCK 7372800
#else #else
#define CONFIG_PL011_CLOCK 24000000 #define CFG_PL011_CLOCK 24000000
#endif #endif
/* Physical Memory Map */ /* Physical Memory Map */

2
include/configs/vexpress_common.h
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@ -116,7 +116,7 @@
#define CFG_SYS_TIMER_COUNTER (V2M_TIMER01 + 0x4) #define CFG_SYS_TIMER_COUNTER (V2M_TIMER01 + 0x4)
/* PL011 Serial Configuration */ /* PL011 Serial Configuration */
#define CONFIG_PL011_CLOCK 24000000 #define CFG_PL011_CLOCK 24000000
#define CONFIG_PL01x_PORTS {(void *)CFG_SYS_SERIAL0, \ #define CONFIG_PL01x_PORTS {(void *)CFG_SYS_SERIAL0, \
(void *)CFG_SYS_SERIAL1} (void *)CFG_SYS_SERIAL1}