pci: tegra: actually program REFCLK_CFG* on recent SoCs
On recent SoCs, tegra_pcie_phy_enable() isn't called; but instead tegra_pcie_enable_controller() calls tegra_xusb_phy_enable(). However, part of tegra_pcie_phy_enable() needs to happen in all cases. Move that code to tegra_pcie_port_enable() instead. For reference, NVIDIA's downstream Linux kernel performs this operation in tegra_pcie_enable_rp_features(), which is called immediately after tegra_pcie_port_enable(). Since that function doesn't exist in the U-Boot driver, we'll just add it to the tail of tegra_pcie_port_enable() instead. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
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@ -620,11 +620,6 @@ static int tegra_pcie_phy_enable(struct tegra_pcie *pcie)
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value |= PADS_PLL_CTL_RST_B4SM;
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value |= PADS_PLL_CTL_RST_B4SM;
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pads_writel(pcie, value, soc->pads_pll_ctl);
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pads_writel(pcie, value, soc->pads_pll_ctl);
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/* configure the reference clock driver */
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pads_writel(pcie, soc->pads_refclk_cfg0, PADS_REFCLK_CFG0);
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if (soc->num_ports > 2)
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pads_writel(pcie, soc->pads_refclk_cfg1, PADS_REFCLK_CFG1);
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/* wait for the PLL to lock */
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/* wait for the PLL to lock */
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err = tegra_pcie_pll_wait(pcie, 500);
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err = tegra_pcie_pll_wait(pcie, 500);
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if (err < 0) {
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if (err < 0) {
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@ -818,20 +813,21 @@ static void tegra_pcie_port_reset(struct tegra_pcie_port *port)
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static void tegra_pcie_port_enable(struct tegra_pcie_port *port)
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static void tegra_pcie_port_enable(struct tegra_pcie_port *port)
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{
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{
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const struct tegra_pcie_soc *soc = port->pcie->soc;
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struct tegra_pcie *pcie = port->pcie;
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const struct tegra_pcie_soc *soc = pcie->soc;
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unsigned long ctrl = tegra_pcie_port_get_pex_ctrl(port);
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unsigned long ctrl = tegra_pcie_port_get_pex_ctrl(port);
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unsigned long value;
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unsigned long value;
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/* enable reference clock */
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/* enable reference clock */
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value = afi_readl(port->pcie, ctrl);
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value = afi_readl(pcie, ctrl);
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value |= AFI_PEX_CTRL_REFCLK_EN;
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value |= AFI_PEX_CTRL_REFCLK_EN;
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if (port->pcie->soc->has_pex_clkreq_en)
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if (pcie->soc->has_pex_clkreq_en)
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value |= AFI_PEX_CTRL_CLKREQ_EN;
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value |= AFI_PEX_CTRL_CLKREQ_EN;
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value |= AFI_PEX_CTRL_OVERRIDE_EN;
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value |= AFI_PEX_CTRL_OVERRIDE_EN;
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afi_writel(port->pcie, value, ctrl);
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afi_writel(pcie, value, ctrl);
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tegra_pcie_port_reset(port);
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tegra_pcie_port_reset(port);
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@ -840,6 +836,11 @@ static void tegra_pcie_port_enable(struct tegra_pcie_port *port)
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value |= RP_VEND_CTL2_PCA_ENABLE;
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value |= RP_VEND_CTL2_PCA_ENABLE;
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rp_writel(port, value, RP_VEND_CTL2);
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rp_writel(port, value, RP_VEND_CTL2);
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}
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}
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/* configure the reference clock driver */
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pads_writel(pcie, soc->pads_refclk_cfg0, PADS_REFCLK_CFG0);
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if (soc->num_ports > 2)
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pads_writel(pcie, soc->pads_refclk_cfg1, PADS_REFCLK_CFG1);
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}
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}
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static bool tegra_pcie_port_check_link(struct tegra_pcie_port *port)
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static bool tegra_pcie_port_check_link(struct tegra_pcie_port *port)
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