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Merge git://git.denx.de/u-boot-rockchip

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This commit is contained in:
Tom Rini
2018-01-28 13:56:19 -05:00
parent 4f6c7b12ed 0289e291a5
commit f2ee915018
32 changed files with 2554 additions and 1010 deletions
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8
arch/arm/dts/rk3128.dtsi
View File

@@ -315,7 +315,7 @@
pwm0: pwm0@20050000 {
compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm";
reg = <0x20050000 0x10>;
#pwm-cells = <2>;
#pwm-cells = <3>;
pinctrl-names = "default";
pinctrl-0 = <&pwm0_pin>;
clocks = <&cru PCLK_PWM>;
@@ -325,7 +325,7 @@
pwm1: pwm1@20050010 {
compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm";
reg = <0x20050010 0x10>;
#pwm-cells = <2>;
#pwm-cells = <3>;
pinctrl-names = "default";
pinctrl-0 = <&pwm1_pin>;
clocks = <&cru PCLK_PWM>;
@@ -335,7 +335,7 @@
pwm2: pwm2@20050020 {
compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm";
reg = <0x20050020 0x10>;
#pwm-cells = <2>;
#pwm-cells = <3>;
pinctrl-names = "default";
pinctrl-0 = <&pwm2_pin>;
clocks = <&cru PCLK_PWM>;
@@ -345,7 +345,7 @@
pwm3: pwm3@20050030 {
compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm";
reg = <0x20050030 0x10>;
#pwm-cells = <2>;
#pwm-cells = <3>;
pinctrl-names = "default";
pinctrl-0 = <&pwm3_pin>;
clocks = <&cru PCLK_PWM>;

7
arch/arm/dts/rk3288.dtsi
View File

@@ -604,19 +604,16 @@
u-boot,dm-pre-reloc;
#clock-cells = <1>;
#reset-cells = <1>;
assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>,
<&cru PLL_GPLL>, <&cru PLL_CPLL>,
assigned-clocks = <&cru PLL_GPLL>, <&cru PLL_CPLL>,
<&cru PLL_NPLL>, <&cru ACLK_CPU>,
<&cru HCLK_CPU>, <&cru PCLK_CPU>,
<&cru ACLK_PERI>, <&cru HCLK_PERI>,
<&cru PCLK_PERI>;
assigned-clock-rates = <0>, <0>,
<594000000>, <400000000>,
assigned-clock-rates = <594000000>, <400000000>,
<500000000>, <300000000>,
<150000000>, <75000000>,
<300000000>, <150000000>,
<75000000>;
assigned-clock-parents = <&cru PLL_NPLL>, <&cru PLL_GPLL>;
};
grf: syscon@ff770000 {

30
arch/arm/dts/rk3328-evb.dts
View File

@@ -15,6 +15,13 @@
stdout-path = &uart2;
};
gmac_clkin: external-gmac-clock {
compatible = "fixed-clock";
clock-frequency = <125000000>;
clock-output-names = "gmac_clkin";
#clock-cells = <0>;
};
vcc3v3_sdmmc: sdmmc-pwren {
compatible = "regulator-fixed";
regulator-name = "vcc3v3";
@@ -40,6 +47,13 @@
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
};
vcc_phy: vcc-phy-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc_phy";
regulator-always-on;
regulator-boot-on;
};
};
&saradc {
@@ -74,6 +88,22 @@
status = "okay";
};
&gmac2io {
phy-supply = <&vcc_phy>;
phy-mode = "rgmii";
clock_in_out = "input";
snps,reset-gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
snps,reset-active-low;
snps,reset-delays-us = <0 10000 50000>;
assigned-clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_EXT>;
assigned-clock-parents = <&gmac_clkin>, <&gmac_clkin>;
pinctrl-names = "default";
pinctrl-0 = <&rgmiim1_pins>;
tx_delay = <0x26>;
rx_delay = <0x11>;
status = "okay";
};
&usb_host0_ehci {
status = "okay";
};

19
arch/arm/dts/rk3328.dtsi
View File

@@ -456,6 +456,25 @@
status = "disabled";
};
gmac2io: ethernet@ff540000 {
compatible = "rockchip,rk3328-gmac";
reg = <0x0 0xff540000 0x0 0x10000>;
rockchip,grf = <&grf>;
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "macirq";
clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_RX>,
<&cru SCLK_MAC2IO_TX>, <&cru SCLK_MAC2IO_REF>,
<&cru SCLK_MAC2IO_REFOUT>, <&cru ACLK_MAC2IO>,
<&cru PCLK_MAC2IO>;
clock-names = "stmmaceth", "mac_clk_rx",
"mac_clk_tx", "clk_mac_ref",
"clk_mac_refout", "aclk_mac",
"pclk_mac";
resets = <&cru SRST_GMAC2IO_A>;
reset-names = "stmmaceth";
status = "disabled";
};
usb_host0_ehci: usb@ff5c0000 {
compatible = "generic-ehci";
reg = <0x0 0xff5c0000 0x0 0x10000>;

4
arch/arm/dts/rk3399-evb.dts
View File

@@ -279,7 +279,7 @@
assigned-clock-parents = <&clkin_gmac>;
pinctrl-names = "default";
pinctrl-0 = <&rgmii_pins>;
tx_delay = <0x10>;
rx_delay = <0x10>;
tx_delay = <0x28>;
rx_delay = <0x11>;
status = "okay";
};

7
arch/arm/include/asm/arch-rockchip/cru_rk3368.h
View File

@@ -95,6 +95,13 @@ enum {
CLK_SARADC_DIV_CON_WIDTH = 8,
/* CLKSEL43_CON */
GMAC_DIV_CON_SHIFT = 0x0,
GMAC_DIV_CON_MASK = GENMASK(4, 0),
GMAC_PLL_SHIFT = 6,
GMAC_PLL_MASK = GENMASK(7, 6),
GMAC_PLL_SELECT_NEW = (0x0 << GMAC_PLL_SHIFT),
GMAC_PLL_SELECT_CODEC = (0x1 << GMAC_PLL_SHIFT),
GMAC_PLL_SELECT_GENERAL = (0x2 << GMAC_PLL_SHIFT),
GMAC_MUX_SEL_EXTCLK = BIT(8),
/* CLKSEL51_CON */

455
arch/arm/include/asm/arch-rockchip/grf_rk322x.h
View File

@@ -88,461 +88,6 @@ struct rk322x_sgrf {
unsigned int busdmac_con[4];
};
/* GRF_GPIO0A_IOMUX */
enum {
GPIO0A7_SHIFT = 14,
GPIO0A7_MASK = 3 << GPIO0A7_SHIFT,
GPIO0A7_GPIO = 0,
GPIO0A7_I2C3_SDA,
GPIO0A7_HDMI_DDCSDA,
GPIO0A6_SHIFT = 12,
GPIO0A6_MASK = 3 << GPIO0A6_SHIFT,
GPIO0A6_GPIO = 0,
GPIO0A6_I2C3_SCL,
GPIO0A6_HDMI_DDCSCL,
GPIO0A3_SHIFT = 6,
GPIO0A3_MASK = 3 << GPIO0A3_SHIFT,
GPIO0A3_GPIO = 0,
GPIO0A3_I2C1_SDA,
GPIO0A3_SDIO_CMD,
GPIO0A2_SHIFT = 4,
GPIO0A2_MASK = 3 << GPIO0A2_SHIFT,
GPIO0A2_GPIO = 0,
GPIO0A2_I2C1_SCL,
GPIO0A1_SHIFT = 2,
GPIO0A1_MASK = 3 << GPIO0A1_SHIFT,
GPIO0A1_GPIO = 0,
GPIO0A1_I2C0_SDA,
GPIO0A0_SHIFT = 0,
GPIO0A0_MASK = 3 << GPIO0A0_SHIFT,
GPIO0A0_GPIO = 0,
GPIO0A0_I2C0_SCL,
};
/* GRF_GPIO0B_IOMUX */
enum {
GPIO0B7_SHIFT = 14,
GPIO0B7_MASK = 3 << GPIO0B7_SHIFT,
GPIO0B7_GPIO = 0,
GPIO0B7_HDMI_HDP,
GPIO0B6_SHIFT = 12,
GPIO0B6_MASK = 3 << GPIO0B6_SHIFT,
GPIO0B6_GPIO = 0,
GPIO0B6_I2S_SDI,
GPIO0B6_SPI_CSN0,
GPIO0B5_SHIFT = 10,
GPIO0B5_MASK = 3 << GPIO0B5_SHIFT,
GPIO0B5_GPIO = 0,
GPIO0B5_I2S_SDO,
GPIO0B5_SPI_RXD,
GPIO0B3_SHIFT = 6,
GPIO0B3_MASK = 3 << GPIO0B3_SHIFT,
GPIO0B3_GPIO = 0,
GPIO0B3_I2S1_LRCKRX,
GPIO0B3_SPI_TXD,
GPIO0B1_SHIFT = 2,
GPIO0B1_MASK = 3 << GPIO0B1_SHIFT,
GPIO0B1_GPIO = 0,
GPIO0B1_I2S_SCLK,
GPIO0B1_SPI_CLK,
GPIO0B0_SHIFT = 0,
GPIO0B0_MASK = 3,
GPIO0B0_GPIO = 0,
GPIO0B0_I2S_MCLK,
};
/* GRF_GPIO0C_IOMUX */
enum {
GPIO0C4_SHIFT = 8,
GPIO0C4_MASK = 3 << GPIO0C4_SHIFT,
GPIO0C4_GPIO = 0,
GPIO0C4_HDMI_CECSDA,
GPIO0C1_SHIFT = 2,
GPIO0C1_MASK = 3 << GPIO0C1_SHIFT,
GPIO0C1_GPIO = 0,
GPIO0C1_UART0_RSTN,
GPIO0C1_CLK_OUT1,
};
/* GRF_GPIO0D_IOMUX */
enum {
GPIO0D6_SHIFT = 12,
GPIO0D6_MASK = 3 << GPIO0D6_SHIFT,
GPIO0D6_GPIO = 0,
GPIO0D6_SDIO_PWREN,
GPIO0D6_PWM11,
GPIO0D4_SHIFT = 8,
GPIO0D4_MASK = 3 << GPIO0D4_SHIFT,
GPIO0D4_GPIO = 0,
GPIO0D4_PWM2,
GPIO0D3_SHIFT = 6,
GPIO0D3_MASK = 3 << GPIO0D3_SHIFT,
GPIO0D3_GPIO = 0,
GPIO0D3_PWM1,
GPIO0D2_SHIFT = 4,
GPIO0D2_MASK = 3 << GPIO0D2_SHIFT,
GPIO0D2_GPIO = 0,
GPIO0D2_PWM0,
};
/* GRF_GPIO1A_IOMUX */
enum {
GPIO1A7_SHIFT = 14,
GPIO1A7_MASK = 1,
GPIO1A7_GPIO = 0,
GPIO1A7_SDMMC_WRPRT,
};
/* GRF_GPIO1B_IOMUX */
enum {
GPIO1B7_SHIFT = 14,
GPIO1B7_MASK = 3 << GPIO1B7_SHIFT,
GPIO1B7_GPIO = 0,
GPIO1B7_SDMMC_CMD,
GPIO1B6_SHIFT = 12,
GPIO1B6_MASK = 3 << GPIO1B6_SHIFT,
GPIO1B6_GPIO = 0,
GPIO1B6_SDMMC_PWREN,
GPIO1B4_SHIFT = 8,
GPIO1B4_MASK = 3 << GPIO1B4_SHIFT,
GPIO1B4_GPIO = 0,
GPIO1B4_SPI_CSN1,
GPIO1B4_PWM12,
GPIO1B3_SHIFT = 6,
GPIO1B3_MASK = 3 << GPIO1B3_SHIFT,
GPIO1B3_GPIO = 0,
GPIO1B3_UART1_RSTN,
GPIO1B3_PWM13,
GPIO1B2_SHIFT = 4,
GPIO1B2_MASK = 3 << GPIO1B2_SHIFT,
GPIO1B2_GPIO = 0,
GPIO1B2_UART1_SIN,
GPIO1B2_UART21_SIN,
GPIO1B1_SHIFT = 2,
GPIO1B1_MASK = 3 << GPIO1B1_SHIFT,
GPIO1B1_GPIO = 0,
GPIO1B1_UART1_SOUT,
GPIO1B1_UART21_SOUT,
};
/* GRF_GPIO1C_IOMUX */
enum {
GPIO1C7_SHIFT = 14,
GPIO1C7_MASK = 3 << GPIO1C7_SHIFT,
GPIO1C7_GPIO = 0,
GPIO1C7_NAND_CS3,
GPIO1C7_EMMC_RSTNOUT,
GPIO1C6_SHIFT = 12,
GPIO1C6_MASK = 3 << GPIO1C6_SHIFT,
GPIO1C6_GPIO = 0,
GPIO1C6_NAND_CS2,
GPIO1C6_EMMC_CMD,
GPIO1C5_SHIFT = 10,
GPIO1C5_MASK = 3 << GPIO1C5_SHIFT,
GPIO1C5_GPIO = 0,
GPIO1C5_SDMMC_D3,
GPIO1C5_JTAG_TMS,
GPIO1C4_SHIFT = 8,
GPIO1C4_MASK = 3 << GPIO1C4_SHIFT,
GPIO1C4_GPIO = 0,
GPIO1C4_SDMMC_D2,
GPIO1C4_JTAG_TCK,
GPIO1C3_SHIFT = 6,
GPIO1C3_MASK = 3 << GPIO1C3_SHIFT,
GPIO1C3_GPIO = 0,
GPIO1C3_SDMMC_D1,
GPIO1C3_UART2_SIN,
GPIO1C2_SHIFT = 4,
GPIO1C2_MASK = 3 << GPIO1C2_SHIFT ,
GPIO1C2_GPIO = 0,
GPIO1C2_SDMMC_D0,
GPIO1C2_UART2_SOUT,
GPIO1C1_SHIFT = 2,
GPIO1C1_MASK = 3 << GPIO1C1_SHIFT,
GPIO1C1_GPIO = 0,
GPIO1C1_SDMMC_DETN,
GPIO1C0_SHIFT = 0,
GPIO1C0_MASK = 3 << GPIO1C0_SHIFT,
GPIO1C0_GPIO = 0,
GPIO1C0_SDMMC_CLKOUT,
};
/* GRF_GPIO1D_IOMUX */
enum {
GPIO1D7_SHIFT = 14,
GPIO1D7_MASK = 3 << GPIO1D7_SHIFT,
GPIO1D7_GPIO = 0,
GPIO1D7_NAND_D7,
GPIO1D7_EMMC_D7,
GPIO1D6_SHIFT = 12,
GPIO1D6_MASK = 3 << GPIO1D6_SHIFT,
GPIO1D6_GPIO = 0,
GPIO1D6_NAND_D6,
GPIO1D6_EMMC_D6,
GPIO1D5_SHIFT = 10,
GPIO1D5_MASK = 3 << GPIO1D5_SHIFT,
GPIO1D5_GPIO = 0,
GPIO1D5_NAND_D5,
GPIO1D5_EMMC_D5,
GPIO1D4_SHIFT = 8,
GPIO1D4_MASK = 3 << GPIO1D4_SHIFT,
GPIO1D4_GPIO = 0,
GPIO1D4_NAND_D4,
GPIO1D4_EMMC_D4,
GPIO1D3_SHIFT = 6,
GPIO1D3_MASK = 3 << GPIO1D3_SHIFT,
GPIO1D3_GPIO = 0,
GPIO1D3_NAND_D3,
GPIO1D3_EMMC_D3,
GPIO1D2_SHIFT = 4,
GPIO1D2_MASK = 3 << GPIO1D2_SHIFT,
GPIO1D2_GPIO = 0,
GPIO1D2_NAND_D2,
GPIO1D2_EMMC_D2,
GPIO1D1_SHIFT = 2,
GPIO1D1_MASK = 3 << GPIO1D1_SHIFT,
GPIO1D1_GPIO = 0,
GPIO1D1_NAND_D1,
GPIO1D1_EMMC_D1,
GPIO1D0_SHIFT = 0,
GPIO1D0_MASK = 3 << GPIO1D0_SHIFT,
GPIO1D0_GPIO = 0,
GPIO1D0_NAND_D0,
GPIO1D0_EMMC_D0,
};
/* GRF_GPIO2A_IOMUX */
enum {
GPIO2A7_SHIFT = 14,
GPIO2A7_MASK = 3 << GPIO2A7_SHIFT,
GPIO2A7_GPIO = 0,
GPIO2A7_NAND_DQS,
GPIO2A7_EMMC_CLKOUT,
GPIO2A5_SHIFT = 10,
GPIO2A5_MASK = 3 << GPIO2A5_SHIFT,
GPIO2A5_GPIO = 0,
GPIO2A5_NAND_WP,
GPIO2A5_EMMC_PWREN,
GPIO2A4_SHIFT = 8,
GPIO2A4_MASK = 3 << GPIO2A4_SHIFT,
GPIO2A4_GPIO = 0,
GPIO2A4_NAND_RDY,
GPIO2A4_EMMC_CMD,
GPIO2A3_SHIFT = 6,
GPIO2A3_MASK = 3 << GPIO2A3_SHIFT,
GPIO2A3_GPIO = 0,
GPIO2A3_NAND_RDN,
GPIO2A4_SPI1_CSN1,
GPIO2A2_SHIFT = 4,
GPIO2A2_MASK = 3 << GPIO2A2_SHIFT,
GPIO2A2_GPIO = 0,
GPIO2A2_NAND_WRN,
GPIO2A4_SPI1_CSN0,
GPIO2A1_SHIFT = 2,
GPIO2A1_MASK = 3 << GPIO2A1_SHIFT,
GPIO2A1_GPIO = 0,
GPIO2A1_NAND_CLE,
GPIO2A1_SPI1_TXD,
GPIO2A0_SHIFT = 0,
GPIO2A0_MASK = 3 << GPIO2A0_SHIFT,
GPIO2A0_GPIO = 0,
GPIO2A0_NAND_ALE,
GPIO2A0_SPI1_RXD,
};
/* GRF_GPIO2B_IOMUX */
enum {
GPIO2B7_SHIFT = 14,
GPIO2B7_MASK = 3 << GPIO2B7_SHIFT,
GPIO2B7_GPIO = 0,
GPIO2B7_GMAC_RXER,
GPIO2B6_SHIFT = 12,
GPIO2B6_MASK = 3 << GPIO2B6_SHIFT,
GPIO2B6_GPIO = 0,
GPIO2B6_GMAC_CLK,
GPIO2B6_MAC_LINK,
GPIO2B5_SHIFT = 10,
GPIO2B5_MASK = 3 << GPIO2B5_SHIFT,
GPIO2B5_GPIO = 0,
GPIO2B5_GMAC_TXEN,
GPIO2B4_SHIFT = 8,
GPIO2B4_MASK = 3 << GPIO2B4_SHIFT,
GPIO2B4_GPIO = 0,
GPIO2B4_GMAC_MDIO,
GPIO2B3_SHIFT = 6,
GPIO2B3_MASK = 3 << GPIO2B3_SHIFT,
GPIO2B3_GPIO = 0,
GPIO2B3_GMAC_RXCLK,
GPIO2B2_SHIFT = 4,
GPIO2B2_MASK = 3 << GPIO2B2_SHIFT,
GPIO2B2_GPIO = 0,
GPIO2B2_GMAC_CRS,
GPIO2B1_SHIFT = 2,
GPIO2B1_MASK = 3 << GPIO2B1_SHIFT,
GPIO2B1_GPIO = 0,
GPIO2B1_GMAC_TXCLK,
GPIO2B0_SHIFT = 0,
GPIO2B0_MASK = 3 << GPIO2B0_SHIFT,
GPIO2B0_GPIO = 0,
GPIO2B0_GMAC_RXDV,
GPIO2B0_MAC_SPEED_IOUT,
};
/* GRF_GPIO2C_IOMUX */
enum {
GPIO2C7_SHIFT = 14,
GPIO2C7_MASK = 3 << GPIO2C7_SHIFT,
GPIO2C7_GPIO = 0,
GPIO2C7_GMAC_TXD3,
GPIO2C6_SHIFT = 12,
GPIO2C6_MASK = 3 << GPIO2C6_SHIFT,
GPIO2C6_GPIO = 0,
GPIO2C6_GMAC_TXD2,
GPIO2C5_SHIFT = 10,
GPIO2C5_MASK = 3 << GPIO2C5_SHIFT,
GPIO2C5_GPIO = 0,
GPIO2C5_I2C2_SCL,
GPIO2C5_GMAC_RXD2,
GPIO2C4_SHIFT = 8,
GPIO2C4_MASK = 3 << GPIO2C4_SHIFT,
GPIO2C4_GPIO = 0,
GPIO2C4_I2C2_SDA,
GPIO2C4_GMAC_RXD3,
GPIO2C3_SHIFT = 6,
GPIO2C3_MASK = 3 << GPIO2C3_SHIFT,
GPIO2C3_GPIO = 0,
GPIO2C3_GMAC_TXD0,
GPIO2C2_SHIFT = 4,
GPIO2C2_MASK = 3 << GPIO2C2_SHIFT,
GPIO2C2_GPIO = 0,
GPIO2C2_GMAC_TXD1,
GPIO2C1_SHIFT = 2,
GPIO2C1_MASK = 3 << GPIO2C1_SHIFT,
GPIO2C1_GPIO = 0,
GPIO2C1_GMAC_RXD0,
GPIO2C0_SHIFT = 0,
GPIO2C0_MASK = 3 << GPIO2C0_SHIFT,
GPIO2C0_GPIO = 0,
GPIO2C0_GMAC_RXD1,
};
/* GRF_GPIO2D_IOMUX */
enum {
GPIO2D1_SHIFT = 2,
GPIO2D1_MASK = 3 << GPIO2D1_SHIFT,
GPIO2D1_GPIO = 0,
GPIO2D1_GMAC_MDC,
GPIO2D0_SHIFT = 0,
GPIO2D0_MASK = 3,
GPIO2D0_GPIO = 0,
GPIO2D0_GMAC_COL,
};
/* GRF_GPIO3C_IOMUX */
enum {
GPIO3C6_SHIFT = 12,
GPIO3C6_MASK = 3 << GPIO3C6_SHIFT,
GPIO3C6_GPIO = 0,
GPIO3C6_DRV_VBUS1,
GPIO3C5_SHIFT = 10,
GPIO3C5_MASK = 3 << GPIO3C5_SHIFT,
GPIO3C5_GPIO = 0,
GPIO3C5_PWM10,
GPIO3C1_SHIFT = 2,
GPIO3C1_MASK = 3 << GPIO3C1_SHIFT,
GPIO3C1_GPIO = 0,
GPIO3C1_DRV_VBUS,
};
/* GRF_GPIO3D_IOMUX */
enum {
GPIO3D2_SHIFT = 4,
GPIO3D2_MASK = 3 << GPIO3D2_SHIFT,
GPIO3D2_GPIO = 0,
GPIO3D2_PWM3,
};
/* GRF_CON_IOMUX */
enum {
CON_IOMUX_GMAC_SHIFT = 15,
CON_IOMUX_GMAC_MASK = 1 << CON_IOMUX_GMAC_SHIFT,
CON_IOMUX_UART1SEL_SHIFT = 11,
CON_IOMUX_UART1SEL_MASK = 1 << CON_IOMUX_UART1SEL_SHIFT,
CON_IOMUX_UART2SEL_SHIFT = 8,
CON_IOMUX_UART2SEL_MASK = 1 << CON_IOMUX_UART2SEL_SHIFT,
CON_IOMUX_UART2SEL_2 = 0,
CON_IOMUX_UART2SEL_21,
CON_IOMUX_EMMCSEL_SHIFT = 7,
CON_IOMUX_EMMCSEL_MASK = 1 << CON_IOMUX_EMMCSEL_SHIFT,
CON_IOMUX_PWM3SEL_SHIFT = 3,
CON_IOMUX_PWM3SEL_MASK = 1 << CON_IOMUX_PWM3SEL_SHIFT,
CON_IOMUX_PWM2SEL_SHIFT = 2,
CON_IOMUX_PWM2SEL_MASK = 1 << CON_IOMUX_PWM2SEL_SHIFT,
CON_IOMUX_PWM1SEL_SHIFT = 1,
CON_IOMUX_PWM1SEL_MASK = 1 << CON_IOMUX_PWM1SEL_SHIFT,
CON_IOMUX_PWM0SEL_SHIFT = 0,
CON_IOMUX_PWM0SEL_MASK = 1 << CON_IOMUX_PWM0SEL_SHIFT,
};
/* GRF_MACPHY_CON0 */
enum {
MACPHY_CFG_ENABLE_SHIFT = 0,

114
arch/arm/include/asm/arch-rockchip/grf_rk3328.h
View File

@@ -131,118 +131,4 @@ struct rk3328_sgrf_regs {
};
check_member(rk3328_sgrf_regs, hdcp_key_access_mask, 0x2a0);
enum {
/* GPIO0A_IOMUX */
GPIO0A5_SEL_SHIFT = 10,
GPIO0A5_SEL_MASK = 3 << GPIO0A5_SEL_SHIFT,
GPIO0A5_I2C3_SCL = 2,
GPIO0A6_SEL_SHIFT = 12,
GPIO0A6_SEL_MASK = 3 << GPIO0A6_SEL_SHIFT,
GPIO0A6_I2C3_SDA = 2,
GPIO0A7_SEL_SHIFT = 14,
GPIO0A7_SEL_MASK = 3 << GPIO0A7_SEL_SHIFT,
GPIO0A7_EMMC_DATA0 = 2,
/* GPIO0D_IOMUX*/
GPIO0D6_SEL_SHIFT = 12,
GPIO0D6_SEL_MASK = 3 << GPIO0D6_SEL_SHIFT,
GPIO0D6_GPIO = 0,
GPIO0D6_SDMMC0_PWRENM1 = 3,
/* GPIO1A_IOMUX */
GPIO1A0_SEL_SHIFT = 0,
GPIO1A0_SEL_MASK = 0x3fff << GPIO1A0_SEL_SHIFT,
GPIO1A0_CARD_DATA_CLK_CMD_DETN = 0x1555,
/* GPIO2A_IOMUX */
GPIO2A0_SEL_SHIFT = 0,
GPIO2A0_SEL_MASK = 3 << GPIO2A0_SEL_SHIFT,
GPIO2A0_UART2_TX_M1 = 1,
GPIO2A1_SEL_SHIFT = 2,
GPIO2A1_SEL_MASK = 3 << GPIO2A1_SEL_SHIFT,
GPIO2A1_UART2_RX_M1 = 1,
GPIO2A2_SEL_SHIFT = 4,
GPIO2A2_SEL_MASK = 3 << GPIO2A2_SEL_SHIFT,
GPIO2A2_PWM_IR = 1,
GPIO2A4_SEL_SHIFT = 8,
GPIO2A4_SEL_MASK = 3 << GPIO2A4_SEL_SHIFT,
GPIO2A4_PWM_0 = 1,
GPIO2A4_I2C1_SDA,
GPIO2A5_SEL_SHIFT = 10,
GPIO2A5_SEL_MASK = 3 << GPIO2A5_SEL_SHIFT,
GPIO2A5_PWM_1 = 1,
GPIO2A5_I2C1_SCL,
GPIO2A6_SEL_SHIFT = 12,
GPIO2A6_SEL_MASK = 3 << GPIO2A6_SEL_SHIFT,
GPIO2A6_PWM_2 = 1,
GPIO2A7_SEL_SHIFT = 14,
GPIO2A7_SEL_MASK = 3 << GPIO2A7_SEL_SHIFT,
GPIO2A7_GPIO = 0,
GPIO2A7_SDMMC0_PWRENM0,
/* GPIO2BL_IOMUX */
GPIO2BL0_SEL_SHIFT = 0,
GPIO2BL0_SEL_MASK = 0x3f << GPIO2BL0_SEL_SHIFT,
GPIO2BL0_SPI_CLK_TX_RX_M0 = 0x15,
GPIO2BL3_SEL_SHIFT = 6,
GPIO2BL3_SEL_MASK = 3 << GPIO2BL3_SEL_SHIFT,
GPIO2BL3_SPI_CSN0_M0 = 1,
GPIO2BL4_SEL_SHIFT = 8,
GPIO2BL4_SEL_MASK = 3 << GPIO2BL4_SEL_SHIFT,
GPIO2BL4_SPI_CSN1_M0 = 1,
GPIO2BL5_SEL_SHIFT = 10,
GPIO2BL5_SEL_MASK = 3 << GPIO2BL5_SEL_SHIFT,
GPIO2BL5_I2C2_SDA = 1,
GPIO2BL6_SEL_SHIFT = 12,
GPIO2BL6_SEL_MASK = 3 << GPIO2BL6_SEL_SHIFT,
GPIO2BL6_I2C2_SCL = 1,
/* GPIO2D_IOMUX */
GPIO2D0_SEL_SHIFT = 0,
GPIO2D0_SEL_MASK = 3 << GPIO2D0_SEL_SHIFT,
GPIO2D0_I2C0_SCL = 1,
GPIO2D1_SEL_SHIFT = 2,
GPIO2D1_SEL_MASK = 3 << GPIO2D1_SEL_SHIFT,
GPIO2D1_I2C0_SDA = 1,
GPIO2D4_SEL_SHIFT = 8,
GPIO2D4_SEL_MASK = 0xff << GPIO2D4_SEL_SHIFT,
GPIO2D4_EMMC_DATA1234 = 0xaa,
/* GPIO3C_IOMUX */
GPIO3C0_SEL_SHIFT = 0,
GPIO3C0_SEL_MASK = 0x3fff << GPIO3C0_SEL_SHIFT,
GPIO3C0_EMMC_DATA567_PWR_CLK_RSTN_CMD = 0x2aaa,
/* COM_IOMUX */
IOMUX_SEL_UART2_SHIFT = 0,
IOMUX_SEL_UART2_MASK = 3 << IOMUX_SEL_UART2_SHIFT,
IOMUX_SEL_UART2_M0 = 0,
IOMUX_SEL_UART2_M1,
IOMUX_SEL_SPI_SHIFT = 4,
IOMUX_SEL_SPI_MASK = 3 << IOMUX_SEL_SPI_SHIFT,
IOMUX_SEL_SPI_M0 = 0,
IOMUX_SEL_SPI_M1,
IOMUX_SEL_SPI_M2,
IOMUX_SEL_SDMMC_SHIFT = 7,
IOMUX_SEL_SDMMC_MASK = 1 << IOMUX_SEL_SDMMC_SHIFT,
IOMUX_SEL_SDMMC_M0 = 0,
IOMUX_SEL_SDMMC_M1,
};
#endif /* __SOC_ROCKCHIP_RK3328_GRF_H__ */

405
arch/arm/include/asm/arch-rockchip/grf_rv1108.h
View File

@@ -100,410 +100,15 @@ struct rv1108_grf {
u32 reserved14[2];
u32 dma_con0;
u32 dma_con1;
u32 reserved15[539];
u32 reserved15[59];
u32 uoc_status;
u32 reserved16[2];
u32 host_status;
u32 reserved17[59];
u32 gmac_con0;
u32 reserved18[191];
u32 chip_id;
};
check_member(rv1108_grf, chip_id, 0xf90);
/* GRF_GPIO1B_IOMUX */
enum {
GPIO1B7_SHIFT = 14,
GPIO1B7_MASK = 3 << GPIO1B7_SHIFT,
GPIO1B7_GPIO = 0,
GPIO1B7_LCDC_D12,
GPIO1B7_I2S_SDIO2_M0,
GPIO1B7_GMAC_RXDV,
GPIO1B6_SHIFT = 12,
GPIO1B6_MASK = 3 << GPIO1B6_SHIFT,
GPIO1B6_GPIO = 0,
GPIO1B6_LCDC_D13,
GPIO1B6_I2S_LRCLKTX_M0,
GPIO1B6_GMAC_RXD1,
GPIO1B5_SHIFT = 10,
GPIO1B5_MASK = 3 << GPIO1B5_SHIFT,
GPIO1B5_GPIO = 0,
GPIO1B5_LCDC_D14,
GPIO1B5_I2S_SDIO1_M0,
GPIO1B5_GMAC_RXD0,
GPIO1B4_SHIFT = 8,
GPIO1B4_MASK = 3 << GPIO1B4_SHIFT,
GPIO1B4_GPIO = 0,
GPIO1B4_LCDC_D15,
GPIO1B4_I2S_MCLK_M0,
GPIO1B4_GMAC_TXEN,
GPIO1B3_SHIFT = 6,
GPIO1B3_MASK = 3 << GPIO1B3_SHIFT,
GPIO1B3_GPIO = 0,
GPIO1B3_LCDC_D16,
GPIO1B3_I2S_SCLK_M0,
GPIO1B3_GMAC_TXD1,
GPIO1B2_SHIFT = 4,
GPIO1B2_MASK = 3 << GPIO1B2_SHIFT,
GPIO1B2_GPIO = 0,
GPIO1B2_LCDC_D17,
GPIO1B2_I2S_SDIO_M0,
GPIO1B2_GMAC_TXD0,
GPIO1B1_SHIFT = 2,
GPIO1B1_MASK = 3 << GPIO1B1_SHIFT,
GPIO1B1_GPIO = 0,
GPIO1B1_LCDC_D9,
GPIO1B1_PWM7,
GPIO1B0_SHIFT = 0,
GPIO1B0_MASK = 3,
GPIO1B0_GPIO = 0,
GPIO1B0_LCDC_D8,
GPIO1B0_PWM6,
};
/* GRF_GPIO1C_IOMUX */
enum {
GPIO1C7_SHIFT = 14,
GPIO1C7_MASK = 3 << GPIO1C7_SHIFT,
GPIO1C7_GPIO = 0,
GPIO1C7_CIF_D5,
GPIO1C7_I2S_SDIO2_M1,
GPIO1C6_SHIFT = 12,
GPIO1C6_MASK = 3 << GPIO1C6_SHIFT,
GPIO1C6_GPIO = 0,
GPIO1C6_CIF_D4,
GPIO1C6_I2S_LRCLKTX_M1,
GPIO1C5_SHIFT = 10,
GPIO1C5_MASK = 3 << GPIO1C5_SHIFT,
GPIO1C5_GPIO = 0,
GPIO1C5_LCDC_CLK,
GPIO1C5_GMAC_CLK,
GPIO1C4_SHIFT = 8,
GPIO1C4_MASK = 3 << GPIO1C4_SHIFT,
GPIO1C4_GPIO = 0,
GPIO1C4_LCDC_HSYNC,
GPIO1C4_GMAC_MDC,
GPIO1C3_SHIFT = 6,
GPIO1C3_MASK = 3 << GPIO1C3_SHIFT,
GPIO1C3_GPIO = 0,
GPIO1C3_LCDC_VSYNC,
GPIO1C3_GMAC_MDIO,
GPIO1C2_SHIFT = 4,
GPIO1C2_MASK = 3 << GPIO1C2_SHIFT,
GPIO1C2_GPIO = 0,
GPIO1C2_LCDC_EN,
GPIO1C2_I2S_SDIO3_M0,
GPIO1C2_GMAC_RXER,
GPIO1C1_SHIFT = 2,
GPIO1C1_MASK = 3 << GPIO1C1_SHIFT,
GPIO1C1_GPIO = 0,
GPIO1C1_LCDC_D10,
GPIO1C1_I2S_SDI_M0,
GPIO1C1_PWM4,
GPIO1C0_SHIFT = 0,
GPIO1C0_MASK = 3,
GPIO1C0_GPIO = 0,
GPIO1C0_LCDC_D11,
GPIO1C0_I2S_LRCLKRX_M0,
};
/* GRF_GPIO1D_OIMUX */
enum {
GPIO1D7_SHIFT = 14,
GPIO1D7_MASK = 3 << GPIO1D7_SHIFT,
GPIO1D7_GPIO = 0,
GPIO1D7_HDMI_CEC,
GPIO1D7_DSP_RTCK,
GPIO1D6_SHIFT = 12,
GPIO1D6_MASK = 1 << GPIO1D6_SHIFT,
GPIO1D6_GPIO = 0,
GPIO1D6_HDMI_HPD_M0,
GPIO1D5_SHIFT = 10,
GPIO1D5_MASK = 3 << GPIO1D5_SHIFT,
GPIO1D5_GPIO = 0,
GPIO1D5_UART2_RTSN,
GPIO1D5_HDMI_SDA_M0,
GPIO1D4_SHIFT = 8,
GPIO1D4_MASK = 3 << GPIO1D4_SHIFT,
GPIO1D4_GPIO = 0,
GPIO1D4_UART2_CTSN,
GPIO1D4_HDMI_SCL_M0,
GPIO1D3_SHIFT = 6,
GPIO1D3_MASK = 3 << GPIO1D3_SHIFT,
GPIO1D3_GPIO = 0,
GPIO1D3_UART0_SOUT,
GPIO1D3_SPI_TXD_M0,
GPIO1D2_SHIFT = 4,
GPIO1D2_MASK = 3 << GPIO1D2_SHIFT,
GPIO1D2_GPIO = 0,
GPIO1D2_UART0_SIN,
GPIO1D2_SPI_RXD_M0,
GPIO1D2_DSP_TDI,
GPIO1D1_SHIFT = 2,
GPIO1D1_MASK = 3 << GPIO1D1_SHIFT,
GPIO1D1_GPIO = 0,
GPIO1D1_UART0_RTSN,
GPIO1D1_SPI_CSN0_M0,
GPIO1D1_DSP_TMS,
GPIO1D0_SHIFT = 0,
GPIO1D0_MASK = 3,
GPIO1D0_GPIO = 0,
GPIO1D0_UART0_CTSN,
GPIO1D0_SPI_CLK_M0,
GPIO1D0_DSP_TCK,
};
/* GRF_GPIO2A_IOMUX */
enum {
GPIO2A7_SHIFT = 14,
GPIO2A7_MASK = 3 << GPIO2A7_SHIFT,
GPIO2A7_GPIO = 0,
GPIO2A7_FLASH_D7,
GPIO2A7_EMMC_D7,
GPIO2A6_SHIFT = 12,
GPIO2A6_MASK = 3 << GPIO2A6_SHIFT,
GPIO2A6_GPIO = 0,
GPIO2A6_FLASH_D6,
GPIO2A6_EMMC_D6,
GPIO2A5_SHIFT = 10,
GPIO2A5_MASK = 3 << GPIO2A5_SHIFT,
GPIO2A5_GPIO = 0,
GPIO2A5_FLASH_D5,
GPIO2A5_EMMC_D5,
GPIO2A4_SHIFT = 8,
GPIO2A4_MASK = 3 << GPIO2A4_SHIFT,
GPIO2A4_GPIO = 0,
GPIO2A4_FLASH_D4,
GPIO2A4_EMMC_D4,
GPIO2A3_SHIFT = 6,
GPIO2A3_MASK = 3 << GPIO2A3_SHIFT,
GPIO2A3_GPIO = 0,
GPIO2A3_FLASH_D3,
GPIO2A3_EMMC_D3,
GPIO2A3_SFC_HOLD_IO3,
GPIO2A2_SHIFT = 4,
GPIO2A2_MASK = 3 << GPIO2A2_SHIFT,
GPIO2A2_GPIO = 0,
GPIO2A2_FLASH_D2,
GPIO2A2_EMMC_D2,
GPIO2A2_SFC_WP_IO2,
GPIO2A1_SHIFT = 2,
GPIO2A1_MASK = 3 << GPIO2A1_SHIFT,
GPIO2A1_GPIO = 0,
GPIO2A1_FLASH_D1,
GPIO2A1_EMMC_D1,
GPIO2A1_SFC_SO_IO1,
GPIO2A0_SHIFT = 0,
GPIO2A0_MASK = 3 << GPIO2A0_SHIFT,
GPIO2A0_GPIO = 0,
GPIO2A0_FLASH_D0,
GPIO2A0_EMMC_D0,
GPIO2A0_SFC_SI_IO0,
};
/* GRF_GPIO2D_IOMUX */
enum {
GPIO2B7_SHIFT = 14,
GPIO2B7_MASK = 3 << GPIO2B7_SHIFT,
GPIO2B7_GPIO = 0,
GPIO2B7_FLASH_CS1,
GPIO2B7_SFC_CLK,
GPIO2B6_SHIFT = 12,
GPIO2B6_MASK = 1 << GPIO2B6_SHIFT,
GPIO2B6_GPIO = 0,
GPIO2B6_EMMC_CLKO,
GPIO2B5_SHIFT = 10,
GPIO2B5_MASK = 1 << GPIO2B5_SHIFT,
GPIO2B5_GPIO = 0,
GPIO2B5_FLASH_CS0,
GPIO2B4_SHIFT = 8,
GPIO2B4_MASK = 3 << GPIO2B4_SHIFT,
GPIO2B4_GPIO = 0,
GPIO2B4_FLASH_RDY,
GPIO2B4_EMMC_CMD,
GPIO2B4_SFC_CSN0,
GPIO2B3_SHIFT = 6,
GPIO2B3_MASK = 1 << GPIO2B3_SHIFT,
GPIO2B3_GPIO = 0,
GPIO2B3_FLASH_RDN,
GPIO2B2_SHIFT = 4,
GPIO2B2_MASK = 1 << GPIO2B2_SHIFT,
GPIO2B2_GPIO = 0,
GPIO2B2_FLASH_WRN,
GPIO2B1_SHIFT = 2,
GPIO2B1_MASK = 1 << GPIO2B1_SHIFT,
GPIO2B1_GPIO = 0,
GPIO2B1_FLASH_CLE,
GPIO2B0_SHIFT = 0,
GPIO2B0_MASK = 1 << GPIO2B0_SHIFT,
GPIO2B0_GPIO = 0,
GPIO2B0_FLASH_ALE,
};
/* GRF_GPIO2D_IOMUX */
enum {
GPIO2D7_SHIFT = 14,
GPIO2D7_MASK = 1 << GPIO2D7_SHIFT,
GPIO2D7_GPIO = 0,
GPIO2D7_SDIO_D0,
GPIO2D6_SHIFT = 12,
GPIO2D6_MASK = 1 << GPIO2D6_SHIFT,
GPIO2D6_GPIO = 0,
GPIO2D6_SDIO_CMD,
GPIO2D5_SHIFT = 10,
GPIO2D5_MASK = 1 << GPIO2D5_SHIFT,
GPIO2D5_GPIO = 0,
GPIO2D5_SDIO_CLKO,
GPIO2D4_SHIFT = 8,
GPIO2D4_MASK = 1 << GPIO2D4_SHIFT,
GPIO2D4_GPIO = 0,
GPIO2D4_I2C1_SCL,
GPIO2D3_SHIFT = 6,
GPIO2D3_MASK = 1 << GPIO2D3_SHIFT,
GPIO2D3_GPIO = 0,
GPIO2D3_I2C1_SDA,
GPIO2D2_SHIFT = 4,
GPIO2D2_MASK = 3 << GPIO2D2_SHIFT,
GPIO2D2_GPIO = 0,
GPIO2D2_UART2_SOUT_M0,
GPIO2D2_JTAG_TCK,
GPIO2D1_SHIFT = 2,
GPIO2D1_MASK = 3 << GPIO2D1_SHIFT,
GPIO2D1_GPIO = 0,
GPIO2D1_UART2_SIN_M0,
GPIO2D1_JTAG_TMS,
GPIO2D1_DSP_TMS,
GPIO2D0_SHIFT = 0,
GPIO2D0_MASK = 3,
GPIO2D0_GPIO = 0,
GPIO2D0_UART0_CTSN,
GPIO2D0_SPI_CLK_M0,
GPIO2D0_DSP_TCK,
};
/* GRF_GPIO3A_IOMUX */
enum {
GPIO3A7_SHIFT = 14,
GPIO3A7_MASK = 1 << GPIO3A7_SHIFT,
GPIO3A7_GPIO = 0,
GPIO3A6_SHIFT = 12,
GPIO3A6_MASK = 1 << GPIO3A6_SHIFT,
GPIO3A6_GPIO = 0,
GPIO3A6_UART1_SOUT,
GPIO3A5_SHIFT = 10,
GPIO3A5_MASK = 1 << GPIO3A5_SHIFT,
GPIO3A5_GPIO = 0,
GPIO3A5_UART1_SIN,
GPIO3A4_SHIFT = 8,
GPIO3A4_MASK = 1 << GPIO3A4_SHIFT,
GPIO3A4_GPIO = 0,
GPIO3A4_UART1_CTSN,
GPIO3A3_SHIFT = 6,
GPIO3A3_MASK = 1 << GPIO3A3_SHIFT,
GPIO3A3_GPIO = 0,
GPIO3A3_UART1_RTSN,
GPIO3A2_SHIFT = 4,
GPIO3A2_MASK = 1 << GPIO3A2_SHIFT,
GPIO3A2_GPIO = 0,
GPIO3A2_SDIO_D3,
GPIO3A1_SHIFT = 2,
GPIO3A1_MASK = 1 << GPIO3A1_SHIFT,
GPIO3A1_GPIO = 0,
GPIO3A1_SDIO_D2,
GPIO3A0_SHIFT = 0,
GPIO3A0_MASK = 1,
GPIO3A0_GPIO = 0,
GPIO3A0_SDIO_D1,
};
/* GRF_GPIO3C_IOMUX */
enum {
GPIO3C7_SHIFT = 14,
GPIO3C7_MASK = 1 << GPIO3C7_SHIFT,
GPIO3C7_GPIO = 0,
GPIO3C7_CIF_CLKI,
GPIO3C6_SHIFT = 12,
GPIO3C6_MASK = 1 << GPIO3C6_SHIFT,
GPIO3C6_GPIO = 0,
GPIO3C6_CIF_VSYNC,
GPIO3C5_SHIFT = 10,
GPIO3C5_MASK = 1 << GPIO3C5_SHIFT,
GPIO3C5_GPIO = 0,
GPIO3C5_SDMMC_CMD,
GPIO3C4_SHIFT = 8,
GPIO3C4_MASK = 1 << GPIO3C4_SHIFT,
GPIO3C4_GPIO = 0,
GPIO3C4_SDMMC_CLKO,
GPIO3C3_SHIFT = 6,
GPIO3C3_MASK = 3 << GPIO3C3_SHIFT,
GPIO3C3_GPIO = 0,
GPIO3C3_SDMMC_D0,
GPIO3C3_UART2_SOUT_M1,
GPIO3C2_SHIFT = 4,
GPIO3C2_MASK = 3 << GPIO3C2_SHIFT,
GPIO3C2_GPIO = 0,
GPIO3C2_SDMMC_D1,
GPIO3C2_UART2_SIN_M1,
GPIOC1_SHIFT = 2,
GPIOC1_MASK = 1 << GPIOC1_SHIFT,
GPIOC1_GPIO = 0,
GPIOC1_SDMMC_D2,
GPIOC0_SHIFT = 0,
GPIOC0_MASK = 1,
GPIO3C0_GPIO = 0,
GPIO3C0_SDMMC_D3,
};
check_member(rv1108_grf, chip_id, 0x0c00);
#endif

2
arch/arm/mach-rockchip/Kconfig
View File

@@ -5,6 +5,8 @@ config ROCKCHIP_RK3036
select CPU_V7
select SUPPORT_SPL
select SPL
imply USB_FUNCTION_ROCKUSB
imply CMD_ROCKUSB
help
The Rockchip RK3036 is a ARM-based SoC with a dual-core Cortex-A7
including NEON and GPU, Mali-400 graphics, several DDR3 options

22
arch/arm/mach-rockchip/rk322x-board-spl.c
View File

@@ -30,7 +30,27 @@ DECLARE_GLOBAL_DATA_PTR;
void board_debug_uart_init(void)
{
static struct rk322x_grf * const grf = (void *)GRF_BASE;
static struct rk322x_grf * const grf = (void *)GRF_BASE;
enum {
GPIO1B2_SHIFT = 4,
GPIO1B2_MASK = 3 << GPIO1B2_SHIFT,
GPIO1B2_GPIO = 0,
GPIO1B2_UART1_SIN,
GPIO1B2_UART21_SIN,
GPIO1B1_SHIFT = 2,
GPIO1B1_MASK = 3 << GPIO1B1_SHIFT,
GPIO1B1_GPIO = 0,
GPIO1B1_UART1_SOUT,
GPIO1B1_UART21_SOUT,
};
enum {
CON_IOMUX_UART2SEL_SHIFT= 8,
CON_IOMUX_UART2SEL_MASK = 1 << CON_IOMUX_UART2SEL_SHIFT,
CON_IOMUX_UART2SEL_2 = 0,
CON_IOMUX_UART2SEL_21,
};
/* Enable early UART2 channel 1 on the RK322x */
rk_clrsetreg(&grf->gpio1b_iomux,
GPIO1B1_MASK | GPIO1B2_MASK,

18
arch/arm/mach-rockchip/rk322x-board.c
View File

@@ -34,6 +34,24 @@ int board_init(void)
/* Enable early UART2 channel 1 on the RK322x */
#define GRF_BASE 0x11000000
struct rk322x_grf * const grf = (void *)GRF_BASE;
enum {
GPIO1B2_SHIFT = 4,
GPIO1B2_MASK = 3 << GPIO1B2_SHIFT,
GPIO1B2_GPIO = 0,
GPIO1B2_UART21_SIN,
GPIO1B1_SHIFT = 2,
GPIO1B1_MASK = 3 << GPIO1B1_SHIFT,
GPIO1B1_GPIO = 0,
GPIO1B1_UART1_SOUT,
GPIO1B1_UART21_SOUT,
};
enum {
CON_IOMUX_UART2SEL_SHIFT= 8,
CON_IOMUX_UART2SEL_MASK = 1 << CON_IOMUX_UART2SEL_SHIFT,
CON_IOMUX_UART2SEL_2 = 0,
CON_IOMUX_UART2SEL_21,
};
rk_clrsetreg(&grf->gpio1b_iomux,
GPIO1B1_MASK | GPIO1B2_MASK,