Merge branch 'master' of git://git.denx.de/u-boot
This commit is contained in:
Stefano Babic
commit
f2465934b4
32
.travis.yml
32
.travis.yml
@ -10,8 +10,6 @@ language: c
|
||||
|
||||
addons:
|
||||
apt:
|
||||
sources:
|
||||
- sourceline: 'ppa:gns3/qemu'
|
||||
packages:
|
||||
- cppcheck
|
||||
- sloccount
|
||||
@ -21,10 +19,6 @@ addons:
|
||||
- libsdl1.2-dev
|
||||
- python
|
||||
- python-virtualenv
|
||||
- qemu-system-arm
|
||||
- qemu-system-mips
|
||||
- qemu-system-ppc
|
||||
- qemu-system-x86
|
||||
- gcc-powerpc-linux-gnu
|
||||
- gcc-arm-linux-gnueabihf
|
||||
- gcc-aarch64-linux-gnu
|
||||
@ -54,7 +48,7 @@ install:
|
||||
|
||||
env:
|
||||
global:
|
||||
- PATH=/tmp/dtc:/tmp/uboot-test-hooks/bin:$PATH
|
||||
- PATH=/tmp/dtc:/tmp/qemu-install/bin:/tmp/uboot-test-hooks/bin:$PATH
|
||||
- PYTHONPATH=/tmp/uboot-test-hooks/py/travis-ci
|
||||
- BUILD_DIR=build
|
||||
- HOSTCC="cc"
|
||||
@ -74,6 +68,15 @@ before_script:
|
||||
echo -e "\n[toolchain-prefix]\nx86 = ${HOME}/.buildman-toolchains/gcc-4.9.0-nolibc/x86_64-linux/bin/x86_64-linux-" >> ~/.buildman;
|
||||
fi
|
||||
- if [[ "${TOOLCHAIN}" == *xtensa* ]]; then ./tools/buildman/buildman --fetch-arch xtensa ; fi
|
||||
- if [[ "${QEMU_TARGET}" != "" ]]; then
|
||||
git clone git://git.qemu.org/qemu.git /tmp/qemu;
|
||||
pushd /tmp/qemu;
|
||||
git submodule update --init dtc &&
|
||||
git checkout v2.8.0-rc3 &&
|
||||
./configure --prefix=/tmp/qemu-install --target-list=${QEMU_TARGET} &&
|
||||
make -j4 all install;
|
||||
popd;
|
||||
fi
|
||||
|
||||
script:
|
||||
# Comments must be outside the command strings below, or the Travis parser
|
||||
@ -151,12 +154,14 @@ matrix:
|
||||
- BUILDMAN="sun50i"
|
||||
- env:
|
||||
- JOB="Catch-all ARM"
|
||||
BUILDMAN="arm -x arm11,arm7,arm9,aarch64,atmel,denx,freescale,kirkwood,siemens,tegra,uniphier,mx,samsung,sunxi,am33xx,omap3,omap4,omap5,pxa,rockchip"
|
||||
BUILDMAN="arm -x arm11,arm7,arm9,aarch64,atmel,denx,freescale,kirkwood,mvebu,siemens,tegra,uniphier,mx,samsung,sunxi,am33xx,omap3,omap4,omap5,pxa,rockchip"
|
||||
- env:
|
||||
- BUILDMAN="sandbox x86"
|
||||
TOOLCHAIN="x86_64"
|
||||
- env:
|
||||
- BUILDMAN="kirkwood"
|
||||
- env:
|
||||
- BUILDMAN="mvebu"
|
||||
- env:
|
||||
- BUILDMAN="pxa"
|
||||
- env:
|
||||
@ -208,7 +213,7 @@ matrix:
|
||||
- env:
|
||||
- BUILDMAN="uniphier"
|
||||
- env:
|
||||
- BUILDMAN="aarch64 -x tegra,freescale,uniphier,sunxi,samsung,rockchip"
|
||||
- BUILDMAN="aarch64 -x tegra,freescale,mvebu,uniphier,sunxi,samsung,rockchip"
|
||||
TOOLCHAIN="aarch64"
|
||||
- env:
|
||||
- BUILDMAN="rockchip"
|
||||
@ -252,43 +257,52 @@ matrix:
|
||||
- env:
|
||||
- TEST_PY_BD="vexpress_ca15_tc2"
|
||||
TEST_PY_ID="--id qemu"
|
||||
QEMU_TARGET="arm-softmmu"
|
||||
BUILDMAN="^vexpress_ca15_tc2$"
|
||||
- env:
|
||||
- TEST_PY_BD="vexpress_ca9x4"
|
||||
TEST_PY_ID="--id qemu"
|
||||
QEMU_TARGET="arm-softmmu"
|
||||
BUILDMAN="^vexpress_ca9x4$"
|
||||
- env:
|
||||
- TEST_PY_BD="integratorcp_cm926ejs"
|
||||
TEST_PY_TEST_SPEC="not sleep"
|
||||
TEST_PY_ID="--id qemu"
|
||||
QEMU_TARGET="arm-softmmu"
|
||||
BUILDMAN="^integratorcp_cm926ejs$"
|
||||
- env:
|
||||
- TEST_PY_BD="qemu_mips"
|
||||
TEST_PY_TEST_SPEC="not sleep"
|
||||
QEMU_TARGET="mips-softmmu"
|
||||
BUILDMAN="^qemu_mips$"
|
||||
TOOLCHAIN="mips"
|
||||
- env:
|
||||
- TEST_PY_BD="qemu_mipsel"
|
||||
TEST_PY_TEST_SPEC="not sleep"
|
||||
QEMU_TARGET="mipsel-softmmu"
|
||||
BUILDMAN="^qemu_mipsel$"
|
||||
TOOLCHAIN="mips"
|
||||
- env:
|
||||
- TEST_PY_BD="qemu_mips64"
|
||||
TEST_PY_TEST_SPEC="not sleep"
|
||||
QEMU_TARGET="mips64-softmmu"
|
||||
BUILDMAN="^qemu_mips64$"
|
||||
TOOLCHAIN="mips"
|
||||
- env:
|
||||
- TEST_PY_BD="qemu_mips64el"
|
||||
TEST_PY_TEST_SPEC="not sleep"
|
||||
QEMU_TARGET="mips64el-softmmu"
|
||||
BUILDMAN="^qemu_mips64el$"
|
||||
TOOLCHAIN="mips"
|
||||
- env:
|
||||
- TEST_PY_BD="qemu-ppce500"
|
||||
TEST_PY_TEST_SPEC="not sleep"
|
||||
QEMU_TARGET="ppc-softmmu"
|
||||
BUILDMAN="^qemu-ppce500$"
|
||||
- env:
|
||||
- TEST_PY_BD="qemu-x86"
|
||||
TEST_PY_TEST_SPEC="not sleep"
|
||||
QEMU_TARGET="i386-softmmu"
|
||||
BUILDMAN="^qemu-x86$"
|
||||
TOOLCHAIN="x86_64"
|
||||
BUILD_ROM="yes"
|
||||
|
||||
@ -69,8 +69,7 @@ ARM ALTERA SOCFPGA
|
||||
M: Marek Vasut <marex@denx.de>
|
||||
S: Maintainted
|
||||
T: git git://git.denx.de/u-boot-socfpga.git
|
||||
F: arch/arm/cpu/armv7/socfpga/
|
||||
F: board/altera/socfpga/
|
||||
F: arch/arm/mach-socfpga/
|
||||
|
||||
ARM ATMEL AT91
|
||||
M: Andreas Bießmann <andreas@biessmann.org>
|
||||
@ -243,7 +242,7 @@ T: git git://git.denx.de/u-boot-coldfire.git
|
||||
F: arch/m68k/
|
||||
|
||||
DFU
|
||||
M: Lukasz Majewski <l.majewski@samsung.com>
|
||||
M: Lukasz Majewski <l.majewski@majess.pl>
|
||||
S: Maintained
|
||||
T: git git://git.denx.de/u-boot-dfu.git
|
||||
F: drivers/dfu/
|
||||
@ -393,8 +392,8 @@ T: git git://git.denx.de/u-boot-nios.git
|
||||
F: arch/nios2/
|
||||
|
||||
ONENAND
|
||||
M: Lukasz Majewski <l.majewski@samsung.com>
|
||||
S: Maintained
|
||||
#M: Lukasz Majewski <l.majewski@majess.pl>
|
||||
S: Orphaned (Since 2017-01)
|
||||
T: git git://git.denx.de/u-boot-onenand.git
|
||||
F: drivers/mtd/onenand/
|
||||
|
||||
|
||||
6
Makefile
6
Makefile
@ -2,10 +2,10 @@
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
|
||||
VERSION = 2016
|
||||
PATCHLEVEL = 11
|
||||
VERSION = 2017
|
||||
PATCHLEVEL = 01
|
||||
SUBLEVEL =
|
||||
EXTRAVERSION =
|
||||
EXTRAVERSION = -rc1
|
||||
NAME =
|
||||
|
||||
# *DOCUMENTATION*
|
||||
|
||||
@ -406,6 +406,7 @@ config TARGET_BCMNSP
|
||||
config ARCH_EXYNOS
|
||||
bool "Samsung EXYNOS"
|
||||
select DM
|
||||
select DM_I2C
|
||||
select DM_SPI_FLASH
|
||||
select DM_SERIAL
|
||||
select DM_SPI
|
||||
@ -418,6 +419,7 @@ config ARCH_S5PC1XX
|
||||
select DM
|
||||
select DM_SERIAL
|
||||
select DM_GPIO
|
||||
select DM_I2C
|
||||
|
||||
config ARCH_HIGHBANK
|
||||
bool "Calxeda Highbank"
|
||||
@ -540,6 +542,7 @@ config ARCH_SOCFPGA
|
||||
select DM
|
||||
select DM_SPI_FLASH
|
||||
select DM_SPI
|
||||
select ENABLE_ARM_SOC_BOOT0_HOOK
|
||||
|
||||
config TARGET_CM_T43
|
||||
bool "Support cm_t43"
|
||||
@ -826,7 +829,6 @@ config TARGET_COLIBRI_PXA270
|
||||
|
||||
config ARCH_UNIPHIER
|
||||
bool "Socionext UniPhier SoCs"
|
||||
select BLK
|
||||
select CLK_UNIPHIER
|
||||
select DM
|
||||
select DM_GPIO
|
||||
|
||||
@ -8,6 +8,7 @@
|
||||
#include <common.h>
|
||||
#include <asm/io.h>
|
||||
#include <div64.h>
|
||||
#include <bootstage.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
@ -17,7 +18,6 @@ int timer_init(void)
|
||||
gd->arch.tbu = 0;
|
||||
|
||||
gd->arch.timer_rate_hz = CONFIG_SYS_HZ_CLOCK / CONFIG_SYS_HZ;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
@ -39,6 +39,11 @@ ulong get_timer(ulong base)
|
||||
return lldiv(get_ticks(), gd->arch.timer_rate_hz) - base;
|
||||
}
|
||||
|
||||
ulong timer_get_boot_us(void)
|
||||
{
|
||||
return lldiv(get_ticks(), CONFIG_SYS_HZ_CLOCK / (CONFIG_SYS_HZ * 1000));
|
||||
}
|
||||
|
||||
void __udelay(unsigned long usec)
|
||||
{
|
||||
unsigned long long endtime;
|
||||
|
||||
@ -76,6 +76,13 @@ config SECURE_BOOT
|
||||
help
|
||||
Enable Freescale Secure Boot feature
|
||||
|
||||
config QSPI_AHB_INIT
|
||||
bool "Init the QSPI AHB bus"
|
||||
help
|
||||
The default setting for QSPI AHB bus just support 3bytes addressing.
|
||||
But some QSPI flash size up to 64MBytes, so initialize the QSPI AHB
|
||||
bus for those flashes to support the full QSPI flash size.
|
||||
|
||||
config SYS_FSL_IFC_BANK_COUNT
|
||||
int "Maximum banks of Integrated flash controller"
|
||||
depends on ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A
|
||||
|
||||
@ -26,6 +26,9 @@
|
||||
#ifdef CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT
|
||||
#include <asm/armv8/sec_firmware.h>
|
||||
#endif
|
||||
#ifdef CONFIG_SYS_FSL_DDR
|
||||
#include <fsl_ddr.h>
|
||||
#endif
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
@ -403,7 +406,9 @@ int arch_early_init_r(void)
|
||||
#ifdef CONFIG_SYS_FSL_ERRATUM_A009635
|
||||
erratum_a009635();
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_SYS_FSL_ERRATUM_A009942) && defined(CONFIG_SYS_FSL_DDR)
|
||||
erratum_a009942_check_cpo();
|
||||
#endif
|
||||
#ifdef CONFIG_MP
|
||||
#if defined(CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT) && defined(CONFIG_ARMV8_PSCI)
|
||||
/* Check the psci version to determine if the psci is supported */
|
||||
|
||||
@ -36,6 +36,7 @@ static struct serdes_config serdes1_cfg_tbl[] = {
|
||||
{0x35, {QSGMII_D, QSGMII_C, QSGMII_B, PCIE2, XFI4, XFI3, XFI2, XFI1 } },
|
||||
{0x39, {SGMII8, SGMII7, SGMII6, PCIE2, SGMII4, SGMII3, SGMII2,
|
||||
PCIE1 } },
|
||||
{0x3B, {XFI8, XFI7, XFI6, PCIE2, XFI4, XFI3, XFI2, PCIE1 } },
|
||||
{0x4B, {PCIE2, PCIE2, PCIE2, PCIE2, XFI4, XFI3, XFI2, XFI1 } },
|
||||
{0x4C, {XFI8, XFI7, XFI6, XFI5, PCIE1, PCIE1, PCIE1, PCIE1 } },
|
||||
{0x4D, {SGMII8, SGMII7, PCIE2, PCIE2, SGMII4, SGMII3, PCIE1, PCIE1 } },
|
||||
|
||||
@ -373,6 +373,45 @@ void fsl_lsch2_early_init_f(void)
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_QSPI_AHB_INIT
|
||||
/* Enable 4bytes address support and fast read */
|
||||
int qspi_ahb_init(void)
|
||||
{
|
||||
u32 *qspi_lut, lut_key, *qspi_key;
|
||||
|
||||
qspi_key = (void *)SYS_FSL_QSPI_ADDR + 0x300;
|
||||
qspi_lut = (void *)SYS_FSL_QSPI_ADDR + 0x310;
|
||||
|
||||
lut_key = in_be32(qspi_key);
|
||||
|
||||
if (lut_key == 0x5af05af0) {
|
||||
/* That means the register is BE */
|
||||
out_be32(qspi_key, 0x5af05af0);
|
||||
/* Unlock the lut table */
|
||||
out_be32(qspi_key + 1, 0x00000002);
|
||||
out_be32(qspi_lut, 0x0820040c);
|
||||
out_be32(qspi_lut + 1, 0x1c080c08);
|
||||
out_be32(qspi_lut + 2, 0x00002400);
|
||||
/* Lock the lut table */
|
||||
out_be32(qspi_key, 0x5af05af0);
|
||||
out_be32(qspi_key + 1, 0x00000001);
|
||||
} else {
|
||||
/* That means the register is LE */
|
||||
out_le32(qspi_key, 0x5af05af0);
|
||||
/* Unlock the lut table */
|
||||
out_le32(qspi_key + 1, 0x00000002);
|
||||
out_le32(qspi_lut, 0x0820040c);
|
||||
out_le32(qspi_lut + 1, 0x1c080c08);
|
||||
out_le32(qspi_lut + 2, 0x00002400);
|
||||
/* Lock the lut table */
|
||||
out_le32(qspi_key, 0x5af05af0);
|
||||
out_le32(qspi_key + 1, 0x00000001);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_BOARD_LATE_INIT
|
||||
int board_late_init(void)
|
||||
{
|
||||
@ -382,6 +421,9 @@ int board_late_init(void)
|
||||
#ifdef CONFIG_CHAIN_OF_TRUST
|
||||
fsl_setenv_chain_of_trust();
|
||||
#endif
|
||||
#ifdef CONFIG_QSPI_AHB_INIT
|
||||
qspi_ahb_init();
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
@ -75,6 +75,7 @@ dtb-$(CONFIG_ARCH_MVEBU) += \
|
||||
armada-388-gp.dtb \
|
||||
armada-385-amc.dtb \
|
||||
armada-7040-db.dtb \
|
||||
armada-8040-db.dtb \
|
||||
armada-xp-gp.dtb \
|
||||
armada-xp-maxbcm.dtb \
|
||||
armada-xp-synology-ds414.dtb \
|
||||
@ -132,6 +133,7 @@ dtb-$(CONFIG_ARCH_SOCFPGA) += \
|
||||
socfpga_cyclone5_mcvevk.dtb \
|
||||
socfpga_cyclone5_socdk.dtb \
|
||||
socfpga_cyclone5_de0_nano_soc.dtb \
|
||||
socfpga_cyclone5_de1_soc.dtb \
|
||||
socfpga_cyclone5_sockit.dtb \
|
||||
socfpga_cyclone5_socrates.dtb \
|
||||
socfpga_cyclone5_sr1500.dtb \
|
||||
|
||||
@ -66,36 +66,14 @@
|
||||
};
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
status = "okay";
|
||||
clock-frequency = <100000>;
|
||||
};
|
||||
|
||||
&spi0 {
|
||||
status = "okay";
|
||||
|
||||
spi-flash@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "jedec,spi-nor";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <10000000>;
|
||||
|
||||
partitions {
|
||||
compatible = "fixed-partitions";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
partition@0 {
|
||||
label = "U-Boot";
|
||||
reg = <0 0x200000>;
|
||||
};
|
||||
partition@400000 {
|
||||
label = "Filesystem";
|
||||
reg = <0x200000 0xce0000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
&ap_pinctl {
|
||||
/* MPP Bus:
|
||||
* SDIO [0-5]
|
||||
* UART0 [11,19]
|
||||
*/
|
||||
/* 0 1 2 3 4 5 6 7 8 9 */
|
||||
pin-func = < 1 1 1 1 1 1 0 0 0 0
|
||||
0 3 0 0 0 0 0 0 0 3 >;
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
@ -108,11 +86,37 @@
|
||||
};
|
||||
|
||||
&cpm_i2c0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&cpm_i2c0_pins>;
|
||||
status = "okay";
|
||||
clock-frequency = <100000>;
|
||||
};
|
||||
|
||||
&cpm_pinctl {
|
||||
/* MPP Bus:
|
||||
* TDM [0-11]
|
||||
* SPI [13-16]
|
||||
* SATA1 [28]
|
||||
* UART0 [29-30]
|
||||
* SMI [32,34]
|
||||
* XSMI [35-36]
|
||||
* I2C [37-38]
|
||||
* RGMII1[44-55]
|
||||
* SD [56-62]
|
||||
*/
|
||||
/* 0 1 2 3 4 5 6 7 8 9 */
|
||||
pin-func = < 4 4 4 4 4 4 4 4 4 4
|
||||
4 4 0 3 3 3 3 0 0 0
|
||||
0 0 0 0 0 0 0 0 9 0xA
|
||||
0xA 0 7 0 7 7 7 2 2 0
|
||||
0 0 0 0 1 1 1 1 1 1
|
||||
1 1 1 1 1 1 0xE 0xE 0xE 0xE
|
||||
0xE 0xE 0xE >;
|
||||
};
|
||||
|
||||
&cpm_spi1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&cpm_spi0_pins>;
|
||||
status = "okay";
|
||||
|
||||
spi-flash@0 {
|
||||
@ -152,7 +156,7 @@
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&comphy_cp110 {
|
||||
&cpm_comphy {
|
||||
phy0 {
|
||||
phy-type = <PHY_TYPE_SGMII2>;
|
||||
phy-speed = <PHY_SPEED_3_125G>;
|
||||
@ -184,10 +188,10 @@
|
||||
};
|
||||
};
|
||||
|
||||
&utmi0 {
|
||||
&cpm_utmi0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&utmi1 {
|
||||
&cpm_utmi1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
56
arch/arm/dts/armada-8020.dtsi
Normal file
56
arch/arm/dts/armada-8020.dtsi
Normal file
@ -0,0 +1,56 @@
|
||||
/*
|
||||
* Copyright (C) 2016 Marvell Technology Group Ltd.
|
||||
*
|
||||
* This file is dual-licensed: you can use it either under the terms
|
||||
* of the GPLv2 or the X11 license, at your option. Note that this dual
|
||||
* licensing only applies to this file, and not this project as a
|
||||
* whole.
|
||||
*
|
||||
* a) This library is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of the
|
||||
* License, or (at your option) any later version.
|
||||
*
|
||||
* This library is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* Or, alternatively,
|
||||
*
|
||||
* b) Permission is hereby granted, free of charge, to any person
|
||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without
|
||||
* restriction, including without limitation the rights to use,
|
||||
* copy, modify, merge, publish, distribute, sublicense, and/or
|
||||
* sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following
|
||||
* conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Device Tree file for the Armada 8020 SoC, made of an AP806 Dual and
|
||||
* two CP110.
|
||||
*/
|
||||
|
||||
#include "armada-ap806-dual.dtsi"
|
||||
#include "armada-cp110-master.dtsi"
|
||||
#include "armada-cp110-slave.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Marvell Armada 8020";
|
||||
compatible = "marvell,armada8020", "marvell,armada-ap806-dual",
|
||||
"marvell,armada-ap806";
|
||||
};
|
||||
285
arch/arm/dts/armada-8040-db.dts
Normal file
285
arch/arm/dts/armada-8040-db.dts
Normal file
@ -0,0 +1,285 @@
|
||||
/*
|
||||
* Copyright (C) 2016 Marvell Technology Group Ltd.
|
||||
*
|
||||
* This file is dual-licensed: you can use it either under the terms
|
||||
* of the GPLv2 or the X11 license, at your option. Note that this dual
|
||||
* licensing only applies to this file, and not this project as a
|
||||
* whole.
|
||||
*
|
||||
* a) This library is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of the
|
||||
* License, or (at your option) any later version.
|
||||
*
|
||||
* This library is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* Or, alternatively,
|
||||
*
|
||||
* b) Permission is hereby granted, free of charge, to any person
|
||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without
|
||||
* restriction, including without limitation the rights to use,
|
||||
* copy, modify, merge, publish, distribute, sublicense, and/or
|
||||
* sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following
|
||||
* conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Device Tree file for Marvell Armada 8040 Development board platform
|
||||
*/
|
||||
|
||||
#include "armada-8040.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Marvell Armada 8040 DB board";
|
||||
compatible = "marvell,armada8040-db", "marvell,armada8040",
|
||||
"marvell,armada-ap806-quad", "marvell,armada-ap806";
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
aliases {
|
||||
i2c0 = &cpm_i2c0;
|
||||
spi0 = &cps_spi1;
|
||||
};
|
||||
|
||||
memory@00000000 {
|
||||
device_type = "memory";
|
||||
reg = <0x0 0x0 0x0 0x80000000>;
|
||||
};
|
||||
};
|
||||
|
||||
/* Accessible over the mini-USB CON9 connector on the main board */
|
||||
&uart0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ap_pinctl {
|
||||
/* MPP Bus:
|
||||
* SDIO [0-10]
|
||||
* UART0 [11,19]
|
||||
*/
|
||||
/* 0 1 2 3 4 5 6 7 8 9 */
|
||||
pin-func = < 1 1 1 1 1 1 1 1 1 1
|
||||
1 3 0 0 0 0 0 0 0 3 >;
|
||||
};
|
||||
|
||||
&cpm_pinctl {
|
||||
/* MPP Bus:
|
||||
* [0-31] = 0xff: Keep default CP0_shared_pins:
|
||||
* [11] CLKOUT_MPP_11 (out)
|
||||
* [23] LINK_RD_IN_CP2CP (in)
|
||||
* [25] CLKOUT_MPP_25 (out)
|
||||
* [29] AVS_FB_IN_CP2CP (in)
|
||||
* [32,34] SMI
|
||||
* [31] GPIO: push button/Wake
|
||||
* [35-36] GPIO
|
||||
* [37-38] I2C
|
||||
* [40-41] SATA[0/1]_PRESENT_ACTIVEn
|
||||
* [42-43] XSMI
|
||||
* [44-55] RGMII1
|
||||
* [56-62] SD
|
||||
*/
|
||||
/* 0 1 2 3 4 5 6 7 8 9 */
|
||||
pin-func = < 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
|
||||
0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
|
||||
0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
|
||||
0xff 0 7 0 7 0 0 2 2 0
|
||||
0 0 8 8 1 1 1 1 1 1
|
||||
1 1 1 1 1 1 0xe 0xe 0xe 0xe
|
||||
0xe 0xe 0xe >;
|
||||
};
|
||||
|
||||
/* CON5 on CP0 expansion */
|
||||
&cpm_pcie2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cpm_i2c0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&cpm_i2c0_pins>;
|
||||
status = "okay";
|
||||
clock-frequency = <100000>;
|
||||
};
|
||||
|
||||
/* CON4 on CP0 expansion */
|
||||
&cpm_sata0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* CON9 on CP0 expansion */
|
||||
&cpm_usb3_0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* CON10 on CP0 expansion */
|
||||
&cpm_usb3_1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cps_pinctl {
|
||||
/* MPP Bus:
|
||||
* [0-11] RGMII0
|
||||
* [13-16] SPI1
|
||||
* [27,31] GE_MDIO/MDC
|
||||
* [32-62] = 0xff: Keep default CP1_shared_pins:
|
||||
*/
|
||||
/* 0 1 2 3 4 5 6 7 8 9 */
|
||||
pin-func = < 0x3 0x3 0x3 0x3 0x3 0x3 0x3 0x3 0x3 0x3
|
||||
0x3 0x3 0xff 0x3 0x3 0x3 0x3 0xff 0xff 0xff
|
||||
0xff 0xff 0xff 0xff 0xff 0xff 0xff 0x8 0xff 0xff
|
||||
0xff 0x8 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
|
||||
0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
|
||||
0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
|
||||
0xff 0xff 0xff >;
|
||||
};
|
||||
|
||||
/* CON5 on CP1 expansion */
|
||||
&cps_pcie2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cps_spi1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&cps_spi1_pins>;
|
||||
status = "okay";
|
||||
|
||||
spi-flash@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "jedec,spi-nor";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <10000000>;
|
||||
|
||||
partitions {
|
||||
compatible = "fixed-partitions";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
partition@0 {
|
||||
label = "U-Boot";
|
||||
reg = <0 0x200000>;
|
||||
};
|
||||
partition@400000 {
|
||||
label = "Filesystem";
|
||||
reg = <0x200000 0xce0000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/* CON4 on CP1 expansion */
|
||||
&cps_sata0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* CON9 on CP1 expansion */
|
||||
&cps_usb3_0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* CON10 on CP1 expansion */
|
||||
&cps_usb3_1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cpm_comphy {
|
||||
/*
|
||||
* Serdes Configuration:
|
||||
* Lane 0: SGMII2
|
||||
* Lane 1: USB3_HOST0
|
||||
* Lane 2: KR (10G)
|
||||
* Lane 3: SATA1
|
||||
* Lane 4: USB3_HOST1
|
||||
* Lane 5: PEX2x1
|
||||
*/
|
||||
phy0 {
|
||||
phy-type = <PHY_TYPE_SGMII2>;
|
||||
phy-speed = <PHY_SPEED_3_125G>;
|
||||
};
|
||||
|
||||
phy1 {
|
||||
phy-type = <PHY_TYPE_USB3_HOST0>;
|
||||
};
|
||||
|
||||
phy2 {
|
||||
phy-type = <PHY_TYPE_KR>;
|
||||
};
|
||||
|
||||
phy3 {
|
||||
phy-type = <PHY_TYPE_SATA1>;
|
||||
};
|
||||
|
||||
phy4 {
|
||||
phy-type = <PHY_TYPE_USB3_HOST1>;
|
||||
};
|
||||
|
||||
phy5 {
|
||||
phy-type = <PHY_TYPE_PEX2>;
|
||||
};
|
||||
};
|
||||
|
||||
&cps_comphy {
|
||||
/*
|
||||
* Serdes Configuration:
|
||||
* Lane 0: SGMII2
|
||||
* Lane 1: USB3_HOST0
|
||||
* Lane 2: KR (10G)
|
||||
* Lane 3: SATA1
|
||||
* Lane 4: Unconnected
|
||||
* Lane 5: PEX2x1
|
||||
*/
|
||||
phy0 {
|
||||
phy-type = <PHY_TYPE_SGMII2>;
|
||||
phy-speed = <PHY_SPEED_3_125G>;
|
||||
};
|
||||
|
||||
phy1 {
|
||||
phy-type = <PHY_TYPE_USB3_HOST0>;
|
||||
};
|
||||
|
||||
phy2 {
|
||||
phy-type = <PHY_TYPE_KR>;
|
||||
};
|
||||
|
||||
phy3 {
|
||||
phy-type = <PHY_TYPE_SATA1>;
|
||||
};
|
||||
|
||||
phy4 {
|
||||
phy-type = <PHY_TYPE_UNCONNECTED>;
|
||||
};
|
||||
|
||||
phy5 {
|
||||
phy-type = <PHY_TYPE_PEX2>;
|
||||
};
|
||||
};
|
||||
|
||||
&cpm_utmi0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cpm_utmi1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cps_utmi0 {
|
||||
status = "okay";
|
||||
};
|
||||
56
arch/arm/dts/armada-8040.dtsi
Normal file
56
arch/arm/dts/armada-8040.dtsi
Normal file
@ -0,0 +1,56 @@
|
||||
/*
|
||||
* Copyright (C) 2016 Marvell Technology Group Ltd.
|
||||
*
|
||||
* This file is dual-licensed: you can use it either under the terms
|
||||
* of the GPLv2 or the X11 license, at your option. Note that this dual
|
||||
* licensing only applies to this file, and not this project as a
|
||||
* whole.
|
||||
*
|
||||
* a) This library is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of the
|
||||
* License, or (at your option) any later version.
|
||||
*
|
||||
* This library is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* Or, alternatively,
|
||||
*
|
||||
* b) Permission is hereby granted, free of charge, to any person
|
||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without
|
||||
* restriction, including without limitation the rights to use,
|
||||
* copy, modify, merge, publish, distribute, sublicense, and/or
|
||||
* sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following
|
||||
* conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Device Tree file for the Armada 8040 SoC, made of an AP806 Quad and
|
||||
* two CP110.
|
||||
*/
|
||||
|
||||
#include "armada-ap806-quad.dtsi"
|
||||
#include "armada-cp110-master.dtsi"
|
||||
#include "armada-cp110-slave.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Marvell Armada 8040";
|
||||
compatible = "marvell,armada8040", "marvell,armada-ap806-quad",
|
||||
"marvell,armada-ap806";
|
||||
};
|
||||
@ -140,6 +140,24 @@
|
||||
marvell,spi-base = <128>, <136>, <144>, <152>;
|
||||
};
|
||||
|
||||
ap_pinctl: ap-pinctl@6F4000 {
|
||||
compatible = "marvell,armada-ap806-pinctrl";
|
||||
bank-name ="apn-806";
|
||||
reg = <0x6F4000 0x10>;
|
||||
pin-count = <20>;
|
||||
max-func = <3>;
|
||||
|
||||
ap_i2c0_pins: i2c-pins-0 {
|
||||
marvell,pins = < 4 5 >;
|
||||
marvell,function = <3>;
|
||||
};
|
||||
ap_emmc_pins: emmc-pins-0 {
|
||||
marvell,pins = < 0 1 2 3 4 5 6 7
|
||||
8 9 10 >;
|
||||
marvell,function = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
xor@400000 {
|
||||
compatible = "marvell,mv-xor-v2";
|
||||
reg = <0x400000 0x1000>,
|
||||
|
||||
@ -81,6 +81,38 @@
|
||||
"cpm-usb3dev", "cpm-eip150", "cpm-eip197";
|
||||
};
|
||||
|
||||
cpm_pinctl: cpm-pinctl@440000 {
|
||||
compatible = "marvell,mvebu-pinctrl",
|
||||
"marvell,a70x0-pinctrl",
|
||||
"marvell,a80x0-cp0-pinctrl";
|
||||
bank-name ="cp0-110";
|
||||
reg = <0x440000 0x20>;
|
||||
pin-count = <63>;
|
||||
max-func = <0xf>;
|
||||
|
||||
cpm_i2c0_pins: cpm-i2c-pins-0 {
|
||||
marvell,pins = < 37 38 >;
|
||||
marvell,function = <2>;
|
||||
};
|
||||
cpm_ge2_rgmii_pins: cpm-ge-rgmii-pins-0 {
|
||||
marvell,pins = < 44 45 46 47 48 49 50 51
|
||||
52 53 54 55 >;
|
||||
marvell,function = <1>;
|
||||
};
|
||||
pca0_pins: cpm-pca0_pins {
|
||||
marvell,pins = <62>;
|
||||
marvell,function = <0>;
|
||||
};
|
||||
cpm_sdhci_pins: cpm-sdhi-pins-0 {
|
||||
marvell,pins = < 56 57 58 59 60 61 >;
|
||||
marvell,function = <14>;
|
||||
};
|
||||
cpm_spi0_pins: cpm-spi-pins-0 {
|
||||
marvell,pins = < 13 14 15 16 >;
|
||||
marvell,function = <3>;
|
||||
};
|
||||
};
|
||||
|
||||
cpm_sata0: sata@540000 {
|
||||
compatible = "marvell,armada-8k-ahci";
|
||||
reg = <0x540000 0x30000>;
|
||||
@ -149,7 +181,7 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
comphy_cp110: comphy@441000 {
|
||||
cpm_comphy: comphy@441000 {
|
||||
compatible = "marvell,mvebu-comphy", "marvell,comphy-cp110";
|
||||
reg = <0x441000 0x8>,
|
||||
<0x120000 0x8>;
|
||||
@ -157,7 +189,7 @@
|
||||
max-lanes = <6>;
|
||||
};
|
||||
|
||||
utmi0: utmi@580000 {
|
||||
cpm_utmi0: utmi@580000 {
|
||||
compatible = "marvell,mvebu-utmi-2.6.0";
|
||||
reg = <0x580000 0x1000>, /* utmi-unit */
|
||||
<0x440420 0x4>, /* usb-cfg */
|
||||
@ -166,7 +198,7 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
utmi1: utmi@581000 {
|
||||
cpm_utmi1: utmi@581000 {
|
||||
compatible = "marvell,mvebu-utmi-2.6.0";
|
||||
reg = <0x581000 0x1000>, /* utmi-unit */
|
||||
<0x440420 0x4>, /* usb-cfg */
|
||||
|
||||
287
arch/arm/dts/armada-cp110-slave.dtsi
Normal file
287
arch/arm/dts/armada-cp110-slave.dtsi
Normal file
@ -0,0 +1,287 @@
|
||||
/*
|
||||
* Copyright (C) 2016 Marvell Technology Group Ltd.
|
||||
*
|
||||
* This file is dual-licensed: you can use it either under the terms
|
||||
* of the GPLv2 or the X11 license, at your option. Note that this dual
|
||||
* licensing only applies to this file, and not this project as a
|
||||
* whole.
|
||||
*
|
||||
* a) This library is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of the
|
||||
* License, or (at your option) any later version.
|
||||
*
|
||||
* This library is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* Or, alternatively,
|
||||
*
|
||||
* b) Permission is hereby granted, free of charge, to any person
|
||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without
|
||||
* restriction, including without limitation the rights to use,
|
||||
* copy, modify, merge, publish, distribute, sublicense, and/or
|
||||
* sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following
|
||||
* conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Device Tree file for Marvell Armada CP110 Slave.
|
||||
*/
|
||||
|
||||
#include <dt-bindings/comphy/comphy_data.h>
|
||||
|
||||
/ {
|
||||
cp110-slave {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
compatible = "simple-bus";
|
||||
interrupt-parent = <&gic>;
|
||||
ranges;
|
||||
|
||||
config-space {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "simple-bus";
|
||||
interrupt-parent = <&gic>;
|
||||
ranges = <0x0 0x0 0xf4000000 0x2000000>;
|
||||
|
||||
cps_syscon0: system-controller@440000 {
|
||||
compatible = "marvell,cp110-system-controller0",
|
||||
"syscon";
|
||||
reg = <0x440000 0x1000>;
|
||||
#clock-cells = <2>;
|
||||
core-clock-output-names =
|
||||
"cps-apll", "cps-ppv2-core", "cps-eip",
|
||||
"cps-core", "cps-nand-core";
|
||||
gate-clock-output-names =
|
||||
"cps-audio", "cps-communit", "cps-nand",
|
||||
"cps-ppv2", "cps-sdio", "cps-mg-domain",
|
||||
"cps-mg-core", "cps-xor1", "cps-xor0",
|
||||
"cps-gop-dp", "none", "cps-pcie_x10",
|
||||
"cps-pcie_x11", "cps-pcie_x4", "cps-pcie-xor",
|
||||
"cps-sata", "cps-sata-usb", "cps-main",
|
||||
"cps-sd-mmc", "none", "none",
|
||||
"cps-slow-io", "cps-usb3h0", "cps-usb3h1",
|
||||
"cps-usb3dev", "cps-eip150", "cps-eip197";
|
||||
};
|
||||
|
||||
cps_pinctl: cps-pinctl@440000 {
|
||||
compatible = "marvell,mvebu-pinctrl",
|
||||
"marvell,a80x0-cp1-pinctrl";
|
||||
bank-name ="cp1-110";
|
||||
reg = <0x440000 0x20>;
|
||||
pin-count = <63>;
|
||||
max-func = <0xf>;
|
||||
|
||||
cps_ge1_rgmii_pins: cps-ge-rgmii-pins-0 {
|
||||
marvell,pins = < 0 1 2 3 4 5 6 7
|
||||
8 9 10 11 >;
|
||||
marvell,function = <3>;
|
||||
};
|
||||
cps_spi1_pins: cps-spi-pins-1 {
|
||||
marvell,pins = < 13 14 15 16 >;
|
||||
marvell,function = <3>;
|
||||
};
|
||||
};
|
||||
|
||||
cps_sata0: sata@540000 {
|
||||
compatible = "marvell,armada-8k-ahci";
|
||||
reg = <0x540000 0x30000>;
|
||||
interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cps_syscon0 1 15>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
cps_usb3_0: usb3@500000 {
|
||||
compatible = "marvell,armada-8k-xhci",
|
||||
"generic-xhci";
|
||||
reg = <0x500000 0x4000>;
|
||||
dma-coherent;
|
||||
interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cps_syscon0 1 22>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
cps_usb3_1: usb3@510000 {
|
||||
compatible = "marvell,armada-8k-xhci",
|
||||
"generic-xhci";
|
||||
reg = <0x510000 0x4000>;
|
||||
dma-coherent;
|
||||
interrupts = <GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cps_syscon0 1 23>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
cps_xor0: xor@6a0000 {
|
||||
compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
|
||||
reg = <0x6a0000 0x1000>,
|
||||
<0x6b0000 0x1000>;
|
||||
dma-coherent;
|
||||
msi-parent = <&gic_v2m0>;
|
||||
clocks = <&cps_syscon0 1 8>;
|
||||
};
|
||||
|
||||
cps_xor1: xor@6c0000 {
|
||||
compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
|
||||
reg = <0x6c0000 0x1000>,
|
||||
<0x6d0000 0x1000>;
|
||||
dma-coherent;
|
||||
msi-parent = <&gic_v2m0>;
|
||||
clocks = <&cps_syscon0 1 7>;
|
||||
};
|
||||
|
||||
cps_spi0: spi@700600 {
|
||||
compatible = "marvell,armada-380-spi";
|
||||
reg = <0x700600 0x50>;
|
||||
#address-cells = <0x1>;
|
||||
#size-cells = <0x0>;
|
||||
cell-index = <1>;
|
||||
clocks = <&cps_syscon0 0 3>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
cps_spi1: spi@700680 {
|
||||
compatible = "marvell,armada-380-spi";
|
||||
reg = <0x700680 0x50>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
cell-index = <2>;
|
||||
clocks = <&cps_syscon0 1 21>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
cps_i2c0: i2c@701000 {
|
||||
compatible = "marvell,mv78230-i2c";
|
||||
reg = <0x701000 0x20>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cps_syscon0 1 21>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
cps_i2c1: i2c@701100 {
|
||||
compatible = "marvell,mv78230-i2c";
|
||||
reg = <0x701100 0x20>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cps_syscon0 1 21>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
cps_comphy: comphy@441000 {
|
||||
compatible = "marvell,mvebu-comphy", "marvell,comphy-cp110";
|
||||
reg = <0x441000 0x8>,
|
||||
<0x120000 0x8>;
|
||||
mux-bitcount = <4>;
|
||||
max-lanes = <6>;
|
||||
};
|
||||
|
||||
cps_utmi0: utmi@580000 {
|
||||
compatible = "marvell,mvebu-utmi-2.6.0";
|
||||
reg = <0x580000 0x1000>, /* utmi-unit */
|
||||
<0x440420 0x4>, /* usb-cfg */
|
||||
<0x440440 0x4>; /* utmi-cfg */
|
||||
utmi-port = <UTMI_PHY_TO_USB_HOST0>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
cps_pcie0: pcie@f4600000 {
|
||||
compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
|
||||
reg = <0 0xf4600000 0 0x10000>,
|
||||
<0 0xfaf00000 0 0x80000>;
|
||||
reg-names = "ctrl", "config";
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
device_type = "pci";
|
||||
dma-coherent;
|
||||
msi-parent = <&gic_v2m0>;
|
||||
|
||||
bus-range = <0 0xff>;
|
||||
ranges =
|
||||
/* downstream I/O */
|
||||
<0x81000000 0 0xfd000000 0 0xfd000000 0 0x10000
|
||||
/* non-prefetchable memory */
|
||||
0x82000000 0 0xfa000000 0 0xfa000000 0 0xf00000>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
|
||||
num-lanes = <1>;
|
||||
clocks = <&cps_syscon0 1 13>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
cps_pcie1: pcie@f4620000 {
|
||||
compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
|
||||
reg = <0 0xf4620000 0 0x10000>,
|
||||
<0 0xfbf00000 0 0x80000>;
|
||||
reg-names = "ctrl", "config";
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
device_type = "pci";
|
||||
dma-coherent;
|
||||
msi-parent = <&gic_v2m0>;
|
||||
|
||||
bus-range = <0 0xff>;
|
||||
ranges =
|
||||
/* downstream I/O */
|
||||
<0x81000000 0 0xfd010000 0 0xfd010000 0 0x10000
|
||||
/* non-prefetchable memory */
|
||||
0x82000000 0 0xfb000000 0 0xfb000000 0 0xf00000>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
num-lanes = <1>;
|
||||
clocks = <&cps_syscon0 1 11>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
cps_pcie2: pcie@f4640000 {
|
||||
compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
|
||||
reg = <0 0xf4640000 0 0x10000>,
|
||||
<0 0xfcf00000 0 0x80000>;
|
||||
reg-names = "ctrl", "config";
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
device_type = "pci";
|
||||
dma-coherent;
|
||||
msi-parent = <&gic_v2m0>;
|
||||
|
||||
bus-range = <0 0xff>;
|
||||
ranges =
|
||||
/* downstream I/O */
|
||||
<0x81000000 0 0xfd020000 0 0xfd020000 0 0x10000
|
||||
/* non-prefetchable memory */
|
||||
0x82000000 0 0xfc000000 0 0xfc000000 0 0xf00000>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupts = <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
num-lanes = <1>;
|
||||
clocks = <&cps_syscon0 1 12>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
@ -176,6 +176,7 @@
|
||||
#size-cells = <0>;
|
||||
reg = <0x1550000 0x10000>,
|
||||
<0x40000000 0x4000000>;
|
||||
reg-names = "QuadSPI", "QuadSPI-memory";
|
||||
num-cs = <2>;
|
||||
big-endian;
|
||||
status = "disabled";
|
||||
|
||||
66
arch/arm/dts/socfpga_cyclone5_de1_soc.dts
Normal file
66
arch/arm/dts/socfpga_cyclone5_de1_soc.dts
Normal file
@ -0,0 +1,66 @@
|
||||
/*
|
||||
* Copyright Altera Corporation (C) 2015
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#include "socfpga_cyclone5.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Terasic DE1-SoC";
|
||||
compatible = "altr,socfpga-cyclone5", "altr,socfpga";
|
||||
|
||||
chosen {
|
||||
bootargs = "console=ttyS0,115200";
|
||||
};
|
||||
|
||||
aliases {
|
||||
ethernet0 = &gmac1;
|
||||
udc0 = &usb1;
|
||||
};
|
||||
|
||||
memory {
|
||||
name = "memory";
|
||||
device_type = "memory";
|
||||
reg = <0x0 0x40000000>; /* 1GB */
|
||||
};
|
||||
|
||||
soc {
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
};
|
||||
|
||||
&gmac1 {
|
||||
status = "okay";
|
||||
phy-mode = "rgmii";
|
||||
|
||||
rxd0-skew-ps = <420>;
|
||||
rxd1-skew-ps = <420>;
|
||||
rxd2-skew-ps = <420>;
|
||||
rxd3-skew-ps = <420>;
|
||||
txen-skew-ps = <0>;
|
||||
txc-skew-ps = <1860>;
|
||||
rxdv-skew-ps = <420>;
|
||||
rxc-skew-ps = <1680>;
|
||||
};
|
||||
|
||||
&gpio0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gpio1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gpio2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&mmc0 {
|
||||
status = "okay";
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
&usb1 {
|
||||
status = "okay";
|
||||
};
|
||||
@ -1,177 +0,0 @@
|
||||
/*
|
||||
* Device Tree Source commonly used by UniPhier ARM SoCs
|
||||
*
|
||||
* Copyright (C) 2015-2016 Socionext Inc.
|
||||
* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+ X11
|
||||
*/
|
||||
|
||||
/include/ "skeleton.dtsi"
|
||||
|
||||
/ {
|
||||
psci {
|
||||
compatible = "arm,psci-0.2";
|
||||
method = "smc";
|
||||
};
|
||||
|
||||
clocks {
|
||||
refclk: ref {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
};
|
||||
};
|
||||
|
||||
soc: soc {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
interrupt-parent = <&intc>;
|
||||
u-boot,dm-pre-reloc;
|
||||
|
||||
serial0: serial@54006800 {
|
||||
compatible = "socionext,uniphier-uart";
|
||||
status = "disabled";
|
||||
reg = <0x54006800 0x40>;
|
||||
interrupts = <0 33 4>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart0>;
|
||||
clocks = <&peri_clk 0>;
|
||||
};
|
||||
|
||||
serial1: serial@54006900 {
|
||||
compatible = "socionext,uniphier-uart";
|
||||
status = "disabled";
|
||||
reg = <0x54006900 0x40>;
|
||||
interrupts = <0 35 4>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart1>;
|
||||
clocks = <&peri_clk 1>;
|
||||
};
|
||||
|
||||
serial2: serial@54006a00 {
|
||||
compatible = "socionext,uniphier-uart";
|
||||
status = "disabled";
|
||||
reg = <0x54006a00 0x40>;
|
||||
interrupts = <0 37 4>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart2>;
|
||||
clocks = <&peri_clk 2>;
|
||||
};
|
||||
|
||||
serial3: serial@54006b00 {
|
||||
compatible = "socionext,uniphier-uart";
|
||||
status = "disabled";
|
||||
reg = <0x54006b00 0x40>;
|
||||
interrupts = <0 177 4>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart3>;
|
||||
clocks = <&peri_clk 3>;
|
||||
};
|
||||
|
||||
system_bus: system-bus@58c00000 {
|
||||
compatible = "socionext,uniphier-system-bus";
|
||||
status = "disabled";
|
||||
reg = <0x58c00000 0x400>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_system_bus>;
|
||||
};
|
||||
|
||||
smpctrl@59800000 {
|
||||
compatible = "socionext,uniphier-smpctrl";
|
||||
reg = <0x59801000 0x400>;
|
||||
};
|
||||
|
||||
mioctrl@59810000 {
|
||||
compatible = "socionext,uniphier-mioctrl",
|
||||
"simple-mfd", "syscon";
|
||||
reg = <0x59810000 0x800>;
|
||||
u-boot,dm-pre-reloc;
|
||||
|
||||
mio_clk: clock {
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
mio_rst: reset {
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
perictrl@59820000 {
|
||||
compatible = "socionext,uniphier-perictrl",
|
||||
"simple-mfd", "syscon";
|
||||
reg = <0x59820000 0x200>;
|
||||
|
||||
peri_clk: clock {
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
peri_rst: reset {
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
timer@60000200 {
|
||||
compatible = "arm,cortex-a9-global-timer";
|
||||
reg = <0x60000200 0x20>;
|
||||
interrupts = <1 11 0x104>;
|
||||
clocks = <&arm_timer_clk>;
|
||||
};
|
||||
|
||||
timer@60000600 {
|
||||
compatible = "arm,cortex-a9-twd-timer";
|
||||
reg = <0x60000600 0x20>;
|
||||
interrupts = <1 13 0x104>;
|
||||
clocks = <&arm_timer_clk>;
|
||||
};
|
||||
|
||||
intc: interrupt-controller@60001000 {
|
||||
compatible = "arm,cortex-a9-gic";
|
||||
reg = <0x60001000 0x1000>,
|
||||
<0x60000100 0x100>;
|
||||
#interrupt-cells = <3>;
|
||||
interrupt-controller;
|
||||
};
|
||||
|
||||
soc-glue@5f800000 {
|
||||
compatible = "socionext,uniphier-soc-glue",
|
||||
"simple-mfd", "syscon";
|
||||
reg = <0x5f800000 0x2000>;
|
||||
u-boot,dm-pre-reloc;
|
||||
|
||||
pinctrl: pinctrl {
|
||||
/* specify compatible in each SoC DTSI */
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
};
|
||||
|
||||
sysctrl@61840000 {
|
||||
compatible = "socionext,uniphier-sysctrl",
|
||||
"simple-mfd", "syscon";
|
||||
reg = <0x61840000 0x4000>;
|
||||
|
||||
sys_clk: clock {
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
sys_rst: reset {
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
nand: nand@68000000 {
|
||||
compatible = "denali,denali-nand-dt";
|
||||
status = "disabled";
|
||||
reg-names = "nand_data", "denali_reg";
|
||||
reg = <0x68000000 0x20>, <0x68100000 0x1000>;
|
||||
interrupts = <0 65 4>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_nand>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/include/ "uniphier-pinctrl.dtsi"
|
||||
@ -7,7 +7,7 @@
|
||||
* SPDX-License-Identifier: GPL-2.0+ X11
|
||||
*/
|
||||
|
||||
/memreserve/ 0x80000000 0x00000008; /* cpu-release-addr */
|
||||
/memreserve/ 0x80000000 0x00080000;
|
||||
|
||||
/ {
|
||||
compatible = "socionext,uniphier-ld11";
|
||||
@ -34,31 +34,66 @@
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a53", "arm,armv8";
|
||||
reg = <0 0x000>;
|
||||
enable-method = "spin-table";
|
||||
cpu-release-addr = <0 0x80000000>;
|
||||
clocks = <&sys_clk 33>;
|
||||
enable-method = "psci";
|
||||
operating-points-v2 = <&cluster0_opp>;
|
||||
};
|
||||
|
||||
cpu1: cpu@1 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a53", "arm,armv8";
|
||||
reg = <0 0x001>;
|
||||
enable-method = "spin-table";
|
||||
cpu-release-addr = <0 0x80000000>;
|
||||
clocks = <&sys_clk 33>;
|
||||
enable-method = "psci";
|
||||
operating-points-v2 = <&cluster0_opp>;
|
||||
};
|
||||
};
|
||||
|
||||
cluster0_opp: opp_table {
|
||||
compatible = "operating-points-v2";
|
||||
opp-shared;
|
||||
|
||||
opp@245000000 {
|
||||
opp-hz = /bits/ 64 <245000000>;
|
||||
clock-latency-ns = <300>;
|
||||
};
|
||||
opp@250000000 {
|
||||
opp-hz = /bits/ 64 <250000000>;
|
||||
clock-latency-ns = <300>;
|
||||
};
|
||||
opp@490000000 {
|
||||
opp-hz = /bits/ 64 <490000000>;
|
||||
clock-latency-ns = <300>;
|
||||
};
|
||||
opp@500000000 {
|
||||
opp-hz = /bits/ 64 <500000000>;
|
||||
clock-latency-ns = <300>;
|
||||
};
|
||||
opp@653334000 {
|
||||
opp-hz = /bits/ 64 <653334000>;
|
||||
clock-latency-ns = <300>;
|
||||
};
|
||||
opp@666667000 {
|
||||
opp-hz = /bits/ 64 <666667000>;
|
||||
clock-latency-ns = <300>;
|
||||
};
|
||||
opp@980000000 {
|
||||
opp-hz = /bits/ 64 <980000000>;
|
||||
clock-latency-ns = <300>;
|
||||
};
|
||||
};
|
||||
|
||||
psci {
|
||||
compatible = "arm,psci-1.0";
|
||||
method = "smc";
|
||||
};
|
||||
|
||||
clocks {
|
||||
refclk: ref {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <25000000>;
|
||||
};
|
||||
|
||||
i2c_clk: i2c_clk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <50000000>;
|
||||
};
|
||||
};
|
||||
|
||||
timer {
|
||||
@ -129,7 +164,7 @@
|
||||
interrupts = <0 41 4>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c0>;
|
||||
clocks = <&i2c_clk>;
|
||||
clocks = <&peri_clk 4>;
|
||||
clock-frequency = <100000>;
|
||||
};
|
||||
|
||||
@ -142,7 +177,7 @@
|
||||
interrupts = <0 42 4>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c1>;
|
||||
clocks = <&i2c_clk>;
|
||||
clocks = <&peri_clk 5>;
|
||||
clock-frequency = <100000>;
|
||||
};
|
||||
|
||||
@ -152,7 +187,7 @@
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <0 43 4>;
|
||||
clocks = <&i2c_clk>;
|
||||
clocks = <&peri_clk 6>;
|
||||
clock-frequency = <400000>;
|
||||
};
|
||||
|
||||
@ -165,7 +200,7 @@
|
||||
interrupts = <0 44 4>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c3>;
|
||||
clocks = <&i2c_clk>;
|
||||
clocks = <&peri_clk 7>;
|
||||
clock-frequency = <100000>;
|
||||
};
|
||||
|
||||
@ -178,7 +213,7 @@
|
||||
interrupts = <0 45 4>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c4>;
|
||||
clocks = <&i2c_clk>;
|
||||
clocks = <&peri_clk 8>;
|
||||
clock-frequency = <100000>;
|
||||
};
|
||||
|
||||
@ -188,7 +223,7 @@
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <0 25 4>;
|
||||
clocks = <&i2c_clk>;
|
||||
clocks = <&peri_clk 9>;
|
||||
clock-frequency = <400000>;
|
||||
};
|
||||
|
||||
@ -207,8 +242,19 @@
|
||||
reg = <0x59801000 0x400>;
|
||||
};
|
||||
|
||||
sdctrl@59810000 {
|
||||
compatible = "socionext,uniphier-ld11-sdctrl",
|
||||
"simple-mfd", "syscon";
|
||||
reg = <0x59810000 0x400>;
|
||||
|
||||
sd_rst: reset {
|
||||
compatible = "socionext,uniphier-ld11-sd-reset";
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
perictrl@59820000 {
|
||||
compatible = "socionext,uniphier-perictrl",
|
||||
compatible = "socionext,uniphier-ld11-perictrl",
|
||||
"simple-mfd", "syscon";
|
||||
reg = <0x59820000 0x200>;
|
||||
|
||||
@ -223,6 +269,19 @@
|
||||
};
|
||||
};
|
||||
|
||||
emmc: sdhc@5a000000 {
|
||||
compatible = "cdns,sd4hc";
|
||||
reg = <0x5a000000 0x400>;
|
||||
interrupts = <0 78 4>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_emmc_1v8>;
|
||||
clocks = <&sys_clk 4>;
|
||||
bus-width = <8>;
|
||||
mmc-ddr-1_8v;
|
||||
mmc-hs200-1_8v;
|
||||
/* mmc-hs400-1_8v; support depends on board design */
|
||||
};
|
||||
|
||||
usb0: usb@5a800100 {
|
||||
compatible = "socionext,uniphier-ehci", "generic-ehci";
|
||||
status = "disabled";
|
||||
@ -277,7 +336,7 @@
|
||||
};
|
||||
|
||||
soc-glue@5f800000 {
|
||||
compatible = "socionext,uniphier-soc-glue",
|
||||
compatible = "socionext,uniphier-ld11-soc-glue",
|
||||
"simple-mfd", "syscon";
|
||||
reg = <0x5f800000 0x2000>;
|
||||
u-boot,dm-pre-reloc;
|
||||
@ -305,7 +364,7 @@
|
||||
sysctrl@61840000 {
|
||||
compatible = "socionext,uniphier-ld11-sysctrl",
|
||||
"simple-mfd", "syscon";
|
||||
reg = <0x61840000 0x4000>;
|
||||
reg = <0x61840000 0x10000>;
|
||||
|
||||
sys_clk: clock {
|
||||
compatible = "socionext,uniphier-ld11-clock";
|
||||
@ -317,6 +376,18 @@
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
nand: nand@68000000 {
|
||||
compatible = "socionext,denali-nand-v5b";
|
||||
status = "disabled";
|
||||
reg-names = "nand_data", "denali_reg";
|
||||
reg = <0x68000000 0x20>, <0x68100000 0x1000>;
|
||||
interrupts = <0 65 4>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_nand>;
|
||||
clocks = <&sys_clk 2>;
|
||||
nand-ecc-strength = <8>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
@ -7,7 +7,7 @@
|
||||
* SPDX-License-Identifier: GPL-2.0+ X11
|
||||
*/
|
||||
|
||||
/memreserve/ 0x80000000 0x00000008; /* cpu-release-addr */
|
||||
/memreserve/ 0x80000000 0x00080000;
|
||||
|
||||
/ {
|
||||
compatible = "socionext,uniphier-ld20";
|
||||
@ -43,47 +43,126 @@
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a72", "arm,armv8";
|
||||
reg = <0 0x000>;
|
||||
enable-method = "spin-table";
|
||||
cpu-release-addr = <0 0x80000000>;
|
||||
clocks = <&sys_clk 32>;
|
||||
enable-method = "psci";
|
||||
operating-points-v2 = <&cluster0_opp>;
|
||||
};
|
||||
|
||||
cpu1: cpu@1 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a72", "arm,armv8";
|
||||
reg = <0 0x001>;
|
||||
enable-method = "spin-table";
|
||||
cpu-release-addr = <0 0x80000000>;
|
||||
clocks = <&sys_clk 32>;
|
||||
enable-method = "psci";
|
||||
operating-points-v2 = <&cluster0_opp>;
|
||||
};
|
||||
|
||||
cpu2: cpu@100 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a53", "arm,armv8";
|
||||
reg = <0 0x100>;
|
||||
enable-method = "spin-table";
|
||||
cpu-release-addr = <0 0x80000000>;
|
||||
clocks = <&sys_clk 33>;
|
||||
enable-method = "psci";
|
||||
operating-points-v2 = <&cluster1_opp>;
|
||||
};
|
||||
|
||||
cpu3: cpu@101 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a53", "arm,armv8";
|
||||
reg = <0 0x101>;
|
||||
enable-method = "spin-table";
|
||||
cpu-release-addr = <0 0x80000000>;
|
||||
clocks = <&sys_clk 33>;
|
||||
enable-method = "psci";
|
||||
operating-points-v2 = <&cluster1_opp>;
|
||||
};
|
||||
};
|
||||
|
||||
cluster0_opp: opp_table0 {
|
||||
compatible = "operating-points-v2";
|
||||
opp-shared;
|
||||
|
||||
opp@250000000 {
|
||||
opp-hz = /bits/ 64 <250000000>;
|
||||
clock-latency-ns = <300>;
|
||||
};
|
||||
opp@275000000 {
|
||||
opp-hz = /bits/ 64 <275000000>;
|
||||
clock-latency-ns = <300>;
|
||||
};
|
||||
opp@500000000 {
|
||||
opp-hz = /bits/ 64 <500000000>;
|
||||
clock-latency-ns = <300>;
|
||||
};
|
||||
opp@550000000 {
|
||||
opp-hz = /bits/ 64 <550000000>;
|
||||
clock-latency-ns = <300>;
|
||||
};
|
||||
opp@666667000 {
|
||||
opp-hz = /bits/ 64 <666667000>;
|
||||
clock-latency-ns = <300>;
|
||||
};
|
||||
opp@733334000 {
|
||||
opp-hz = /bits/ 64 <733334000>;
|
||||
clock-latency-ns = <300>;
|
||||
};
|
||||
opp@1000000000 {
|
||||
opp-hz = /bits/ 64 <1000000000>;
|
||||
clock-latency-ns = <300>;
|
||||
};
|
||||
opp@1100000000 {
|
||||
opp-hz = /bits/ 64 <1100000000>;
|
||||
clock-latency-ns = <300>;
|
||||
};
|
||||
};
|
||||
|
||||
cluster1_opp: opp_table1 {
|
||||
compatible = "operating-points-v2";
|
||||
opp-shared;
|
||||
|
||||
opp@250000000 {
|
||||
opp-hz = /bits/ 64 <250000000>;
|
||||
clock-latency-ns = <300>;
|
||||
};
|
||||
opp@275000000 {
|
||||
opp-hz = /bits/ 64 <275000000>;
|
||||
clock-latency-ns = <300>;
|
||||
};
|
||||
opp@500000000 {
|
||||
opp-hz = /bits/ 64 <500000000>;
|
||||
clock-latency-ns = <300>;
|
||||
};
|
||||
opp@550000000 {
|
||||
opp-hz = /bits/ 64 <550000000>;
|
||||
clock-latency-ns = <300>;
|
||||
};
|
||||
opp@666667000 {
|
||||
opp-hz = /bits/ 64 <666667000>;
|
||||
clock-latency-ns = <300>;
|
||||
};
|
||||
opp@733334000 {
|
||||
opp-hz = /bits/ 64 <733334000>;
|
||||
clock-latency-ns = <300>;
|
||||
};
|
||||
opp@1000000000 {
|
||||
opp-hz = /bits/ 64 <1000000000>;
|
||||
clock-latency-ns = <300>;
|
||||
};
|
||||
opp@1100000000 {
|
||||
opp-hz = /bits/ 64 <1100000000>;
|
||||
clock-latency-ns = <300>;
|
||||
};
|
||||
};
|
||||
|
||||
psci {
|
||||
compatible = "arm,psci-1.0";
|
||||
method = "smc";
|
||||
};
|
||||
|
||||
clocks {
|
||||
refclk: ref {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <25000000>;
|
||||
};
|
||||
|
||||
i2c_clk: i2c_clk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <50000000>;
|
||||
};
|
||||
};
|
||||
|
||||
timer {
|
||||
@ -154,7 +233,7 @@
|
||||
interrupts = <0 41 4>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c0>;
|
||||
clocks = <&i2c_clk>;
|
||||
clocks = <&peri_clk 4>;
|
||||
clock-frequency = <100000>;
|
||||
};
|
||||
|
||||
@ -167,7 +246,7 @@
|
||||
interrupts = <0 42 4>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c1>;
|
||||
clocks = <&i2c_clk>;
|
||||
clocks = <&peri_clk 5>;
|
||||
clock-frequency = <100000>;
|
||||
};
|
||||
|
||||
@ -177,7 +256,7 @@
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <0 43 4>;
|
||||
clocks = <&i2c_clk>;
|
||||
clocks = <&peri_clk 6>;
|
||||
clock-frequency = <400000>;
|
||||
};
|
||||
|
||||
@ -190,7 +269,7 @@
|
||||
interrupts = <0 44 4>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c3>;
|
||||
clocks = <&i2c_clk>;
|
||||
clocks = <&peri_clk 7>;
|
||||
clock-frequency = <100000>;
|
||||
};
|
||||
|
||||
@ -203,7 +282,7 @@
|
||||
interrupts = <0 45 4>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c4>;
|
||||
clocks = <&i2c_clk>;
|
||||
clocks = <&peri_clk 8>;
|
||||
clock-frequency = <100000>;
|
||||
};
|
||||
|
||||
@ -213,7 +292,7 @@
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <0 25 4>;
|
||||
clocks = <&i2c_clk>;
|
||||
clocks = <&peri_clk 9>;
|
||||
clock-frequency = <400000>;
|
||||
};
|
||||
|
||||
@ -232,24 +311,24 @@
|
||||
reg = <0x59801000 0x400>;
|
||||
};
|
||||
|
||||
mioctrl@59810000 {
|
||||
compatible = "socionext,uniphier-mioctrl",
|
||||
sdctrl@59810000 {
|
||||
compatible = "socionext,uniphier-ld20-sdctrl",
|
||||
"simple-mfd", "syscon";
|
||||
reg = <0x59810000 0x800>;
|
||||
|
||||
mio_clk: clock {
|
||||
compatible = "socionext,uniphier-ld20-mio-clock";
|
||||
sd_clk: clock {
|
||||
compatible = "socionext,uniphier-ld20-sd-clock";
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
mio_rst: reset {
|
||||
compatible = "socionext,uniphier-ld20-mio-reset";
|
||||
sd_rst: reset {
|
||||
compatible = "socionext,uniphier-ld20-sd-reset";
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
perictrl@59820000 {
|
||||
compatible = "socionext,uniphier-perictrl",
|
||||
compatible = "socionext,uniphier-ld20-perictrl",
|
||||
"simple-mfd", "syscon";
|
||||
reg = <0x59820000 0x200>;
|
||||
|
||||
@ -264,6 +343,19 @@
|
||||
};
|
||||
};
|
||||
|
||||
emmc: sdhc@5a000000 {
|
||||
compatible = "cdns,sd4hc";
|
||||
reg = <0x5a000000 0x400>;
|
||||
interrupts = <0 78 4>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_emmc_1v8>;
|
||||
clocks = <&sys_clk 4>;
|
||||
bus-width = <8>;
|
||||
mmc-ddr-1_8v;
|
||||
mmc-hs200-1_8v;
|
||||
/* mmc-hs400-1_8v; support depends on board design */
|
||||
};
|
||||
|
||||
sd: sdhc@5a400000 {
|
||||
compatible = "socionext,uniphier-sdhc";
|
||||
status = "disabled";
|
||||
@ -271,14 +363,15 @@
|
||||
interrupts = <0 76 4>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_sd>;
|
||||
clocks = <&mio_clk 0>;
|
||||
clocks = <&sd_clk 0>;
|
||||
reset-names = "host";
|
||||
resets = <&mio_rst 0>;
|
||||
resets = <&sd_rst 0>;
|
||||
bus-width = <4>;
|
||||
cap-sd-highspeed;
|
||||
};
|
||||
|
||||
soc-glue@5f800000 {
|
||||
compatible = "socionext,uniphier-soc-glue",
|
||||
compatible = "socionext,uniphier-ld20-soc-glue",
|
||||
"simple-mfd", "syscon";
|
||||
reg = <0x5f800000 0x2000>;
|
||||
u-boot,dm-pre-reloc;
|
||||
@ -304,9 +397,9 @@
|
||||
};
|
||||
|
||||
sysctrl@61840000 {
|
||||
compatible = "socionext,uniphier-sysctrl",
|
||||
compatible = "socionext,uniphier-ld20-sysctrl",
|
||||
"simple-mfd", "syscon";
|
||||
reg = <0x61840000 0x4000>;
|
||||
reg = <0x61840000 0x10000>;
|
||||
|
||||
sys_clk: clock {
|
||||
compatible = "socionext,uniphier-ld20-clock";
|
||||
@ -318,6 +411,35 @@
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
usb: usb@65b00000 {
|
||||
compatible = "socionext,uniphier-ld20-dwc3";
|
||||
reg = <0x65b00000 0x1000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb1>,
|
||||
<&pinctrl_usb2>, <&pinctrl_usb3>;
|
||||
dwc3@65a00000 {
|
||||
compatible = "snps,dwc3";
|
||||
reg = <0x65a00000 0x10000>;
|
||||
interrupts = <0 134 4>;
|
||||
tx-fifo-resize;
|
||||
};
|
||||
};
|
||||
|
||||
nand: nand@68000000 {
|
||||
compatible = "socionext,denali-nand-v5b";
|
||||
status = "disabled";
|
||||
reg-names = "nand_data", "denali_reg";
|
||||
reg = <0x68000000 0x20>, <0x68100000 0x1000>;
|
||||
interrupts = <0 65 4>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_nand>;
|
||||
clocks = <&sys_clk 2>;
|
||||
nand-ecc-strength = <8>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
@ -7,7 +7,7 @@
|
||||
* SPDX-License-Identifier: GPL-2.0+ X11
|
||||
*/
|
||||
|
||||
/include/ "uniphier-common32.dtsi"
|
||||
/include/ "skeleton.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "socionext,uniphier-ld4";
|
||||
@ -25,313 +25,438 @@
|
||||
};
|
||||
};
|
||||
|
||||
psci {
|
||||
compatible = "arm,psci-0.2";
|
||||
method = "smc";
|
||||
};
|
||||
|
||||
clocks {
|
||||
refclk: ref {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <24576000>;
|
||||
};
|
||||
|
||||
arm_timer_clk: arm_timer_clk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <50000000>;
|
||||
};
|
||||
};
|
||||
|
||||
iobus_clk: iobus_clk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <100000000>;
|
||||
soc {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
interrupt-parent = <&intc>;
|
||||
u-boot,dm-pre-reloc;
|
||||
|
||||
l2: l2-cache@500c0000 {
|
||||
compatible = "socionext,uniphier-system-cache";
|
||||
reg = <0x500c0000 0x2000>, <0x503c0100 0x4>,
|
||||
<0x506c0000 0x400>;
|
||||
interrupts = <0 174 4>, <0 175 4>;
|
||||
cache-unified;
|
||||
cache-size = <(512 * 1024)>;
|
||||
cache-sets = <256>;
|
||||
cache-line-size = <128>;
|
||||
cache-level = <2>;
|
||||
};
|
||||
|
||||
serial0: serial@54006800 {
|
||||
compatible = "socionext,uniphier-uart";
|
||||
status = "disabled";
|
||||
reg = <0x54006800 0x40>;
|
||||
interrupts = <0 33 4>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart0>;
|
||||
clocks = <&peri_clk 0>;
|
||||
clock-frequency = <36864000>;
|
||||
};
|
||||
|
||||
serial1: serial@54006900 {
|
||||
compatible = "socionext,uniphier-uart";
|
||||
status = "disabled";
|
||||
reg = <0x54006900 0x40>;
|
||||
interrupts = <0 35 4>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart1>;
|
||||
clocks = <&peri_clk 1>;
|
||||
clock-frequency = <36864000>;
|
||||
};
|
||||
|
||||
serial2: serial@54006a00 {
|
||||
compatible = "socionext,uniphier-uart";
|
||||
status = "disabled";
|
||||
reg = <0x54006a00 0x40>;
|
||||
interrupts = <0 37 4>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart2>;
|
||||
clocks = <&peri_clk 2>;
|
||||
clock-frequency = <36864000>;
|
||||
};
|
||||
|
||||
serial3: serial@54006b00 {
|
||||
compatible = "socionext,uniphier-uart";
|
||||
status = "disabled";
|
||||
reg = <0x54006b00 0x40>;
|
||||
interrupts = <0 29 4>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart3>;
|
||||
clocks = <&peri_clk 3>;
|
||||
clock-frequency = <36864000>;
|
||||
};
|
||||
|
||||
port0x: gpio@55000008 {
|
||||
compatible = "socionext,uniphier-gpio";
|
||||
reg = <0x55000008 0x8>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
port1x: gpio@55000010 {
|
||||
compatible = "socionext,uniphier-gpio";
|
||||
reg = <0x55000010 0x8>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
port2x: gpio@55000018 {
|
||||
compatible = "socionext,uniphier-gpio";
|
||||
reg = <0x55000018 0x8>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
port3x: gpio@55000020 {
|
||||
compatible = "socionext,uniphier-gpio";
|
||||
reg = <0x55000020 0x8>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
port4: gpio@55000028 {
|
||||
compatible = "socionext,uniphier-gpio";
|
||||
reg = <0x55000028 0x8>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
port5x: gpio@55000030 {
|
||||
compatible = "socionext,uniphier-gpio";
|
||||
reg = <0x55000030 0x8>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
port6x: gpio@55000038 {
|
||||
compatible = "socionext,uniphier-gpio";
|
||||
reg = <0x55000038 0x8>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
port7x: gpio@55000040 {
|
||||
compatible = "socionext,uniphier-gpio";
|
||||
reg = <0x55000040 0x8>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
port8x: gpio@55000048 {
|
||||
compatible = "socionext,uniphier-gpio";
|
||||
reg = <0x55000048 0x8>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
port9x: gpio@55000050 {
|
||||
compatible = "socionext,uniphier-gpio";
|
||||
reg = <0x55000050 0x8>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
port10x: gpio@55000058 {
|
||||
compatible = "socionext,uniphier-gpio";
|
||||
reg = <0x55000058 0x8>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
port11x: gpio@55000060 {
|
||||
compatible = "socionext,uniphier-gpio";
|
||||
reg = <0x55000060 0x8>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
port12x: gpio@55000068 {
|
||||
compatible = "socionext,uniphier-gpio";
|
||||
reg = <0x55000068 0x8>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
port13x: gpio@55000070 {
|
||||
compatible = "socionext,uniphier-gpio";
|
||||
reg = <0x55000070 0x8>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
port14x: gpio@55000078 {
|
||||
compatible = "socionext,uniphier-gpio";
|
||||
reg = <0x55000078 0x8>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
port16x: gpio@55000088 {
|
||||
compatible = "socionext,uniphier-gpio";
|
||||
reg = <0x55000088 0x8>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
i2c0: i2c@58400000 {
|
||||
compatible = "socionext,uniphier-i2c";
|
||||
status = "disabled";
|
||||
reg = <0x58400000 0x40>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <0 41 1>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c0>;
|
||||
clocks = <&peri_clk 4>;
|
||||
clock-frequency = <100000>;
|
||||
};
|
||||
|
||||
i2c1: i2c@58480000 {
|
||||
compatible = "socionext,uniphier-i2c";
|
||||
status = "disabled";
|
||||
reg = <0x58480000 0x40>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <0 42 1>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c1>;
|
||||
clocks = <&peri_clk 5>;
|
||||
clock-frequency = <100000>;
|
||||
};
|
||||
|
||||
/* chip-internal connection for DMD */
|
||||
i2c2: i2c@58500000 {
|
||||
compatible = "socionext,uniphier-i2c";
|
||||
reg = <0x58500000 0x40>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <0 43 1>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c2>;
|
||||
clocks = <&peri_clk 6>;
|
||||
clock-frequency = <400000>;
|
||||
};
|
||||
|
||||
i2c3: i2c@58580000 {
|
||||
compatible = "socionext,uniphier-i2c";
|
||||
status = "disabled";
|
||||
reg = <0x58580000 0x40>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <0 44 1>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c3>;
|
||||
clocks = <&peri_clk 7>;
|
||||
clock-frequency = <100000>;
|
||||
};
|
||||
|
||||
system_bus: system-bus@58c00000 {
|
||||
compatible = "socionext,uniphier-system-bus";
|
||||
status = "disabled";
|
||||
reg = <0x58c00000 0x400>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_system_bus>;
|
||||
};
|
||||
|
||||
smpctrl@59800000 {
|
||||
compatible = "socionext,uniphier-smpctrl";
|
||||
reg = <0x59801000 0x400>;
|
||||
};
|
||||
|
||||
mioctrl@59810000 {
|
||||
compatible = "socionext,uniphier-ld4-mioctrl",
|
||||
"simple-mfd", "syscon";
|
||||
reg = <0x59810000 0x800>;
|
||||
|
||||
mio_clk: clock {
|
||||
compatible = "socionext,uniphier-ld4-mio-clock";
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
mio_rst: reset {
|
||||
compatible = "socionext,uniphier-ld4-mio-reset";
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
perictrl@59820000 {
|
||||
compatible = "socionext,uniphier-ld4-perictrl",
|
||||
"simple-mfd", "syscon";
|
||||
reg = <0x59820000 0x200>;
|
||||
|
||||
peri_clk: clock {
|
||||
compatible = "socionext,uniphier-ld4-peri-clock";
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
peri_rst: reset {
|
||||
compatible = "socionext,uniphier-ld4-peri-reset";
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
sd: sdhc@5a400000 {
|
||||
compatible = "socionext,uniphier-sdhc";
|
||||
status = "disabled";
|
||||
reg = <0x5a400000 0x200>;
|
||||
interrupts = <0 76 4>;
|
||||
pinctrl-names = "default", "1.8v";
|
||||
pinctrl-0 = <&pinctrl_sd>;
|
||||
pinctrl-1 = <&pinctrl_sd_1v8>;
|
||||
clocks = <&mio_clk 0>;
|
||||
reset-names = "host", "bridge";
|
||||
resets = <&mio_rst 0>, <&mio_rst 3>;
|
||||
bus-width = <4>;
|
||||
cap-sd-highspeed;
|
||||
sd-uhs-sdr12;
|
||||
sd-uhs-sdr25;
|
||||
sd-uhs-sdr50;
|
||||
};
|
||||
|
||||
emmc: sdhc@5a500000 {
|
||||
compatible = "socionext,uniphier-sdhc";
|
||||
status = "disabled";
|
||||
reg = <0x5a500000 0x200>;
|
||||
interrupts = <0 78 4>;
|
||||
pinctrl-names = "default", "1.8v";
|
||||
pinctrl-0 = <&pinctrl_emmc>;
|
||||
pinctrl-1 = <&pinctrl_emmc_1v8>;
|
||||
clocks = <&mio_clk 1>;
|
||||
reset-names = "host", "bridge";
|
||||
resets = <&mio_rst 1>, <&mio_rst 4>;
|
||||
bus-width = <8>;
|
||||
non-removable;
|
||||
cap-mmc-highspeed;
|
||||
cap-mmc-hw-reset;
|
||||
};
|
||||
|
||||
usb0: usb@5a800100 {
|
||||
compatible = "socionext,uniphier-ehci", "generic-ehci";
|
||||
status = "disabled";
|
||||
reg = <0x5a800100 0x100>;
|
||||
interrupts = <0 80 4>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usb0>;
|
||||
clocks = <&mio_clk 7>, <&mio_clk 8>, <&mio_clk 12>;
|
||||
resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>,
|
||||
<&mio_rst 12>;
|
||||
};
|
||||
|
||||
usb1: usb@5a810100 {
|
||||
compatible = "socionext,uniphier-ehci", "generic-ehci";
|
||||
status = "disabled";
|
||||
reg = <0x5a810100 0x100>;
|
||||
interrupts = <0 81 4>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usb1>;
|
||||
clocks = <&mio_clk 7>, <&mio_clk 9>, <&mio_clk 13>;
|
||||
resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>,
|
||||
<&mio_rst 13>;
|
||||
};
|
||||
|
||||
usb2: usb@5a820100 {
|
||||
compatible = "socionext,uniphier-ehci", "generic-ehci";
|
||||
status = "disabled";
|
||||
reg = <0x5a820100 0x100>;
|
||||
interrupts = <0 82 4>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usb2>;
|
||||
clocks = <&mio_clk 7>, <&mio_clk 10>, <&mio_clk 14>;
|
||||
resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 10>,
|
||||
<&mio_rst 14>;
|
||||
};
|
||||
|
||||
soc-glue@5f800000 {
|
||||
compatible = "socionext,uniphier-ld4-soc-glue",
|
||||
"simple-mfd", "syscon";
|
||||
reg = <0x5f800000 0x2000>;
|
||||
u-boot,dm-pre-reloc;
|
||||
|
||||
pinctrl: pinctrl {
|
||||
compatible = "socionext,uniphier-ld4-pinctrl";
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
};
|
||||
|
||||
timer@60000200 {
|
||||
compatible = "arm,cortex-a9-global-timer";
|
||||
reg = <0x60000200 0x20>;
|
||||
interrupts = <1 11 0x104>;
|
||||
clocks = <&arm_timer_clk>;
|
||||
};
|
||||
|
||||
timer@60000600 {
|
||||
compatible = "arm,cortex-a9-twd-timer";
|
||||
reg = <0x60000600 0x20>;
|
||||
interrupts = <1 13 0x104>;
|
||||
clocks = <&arm_timer_clk>;
|
||||
};
|
||||
|
||||
intc: interrupt-controller@60001000 {
|
||||
compatible = "arm,cortex-a9-gic";
|
||||
reg = <0x60001000 0x1000>,
|
||||
<0x60000100 0x100>;
|
||||
#interrupt-cells = <3>;
|
||||
interrupt-controller;
|
||||
};
|
||||
|
||||
aidet@61830000 {
|
||||
compatible = "simple-mfd", "syscon";
|
||||
reg = <0x61830000 0x200>;
|
||||
};
|
||||
|
||||
sysctrl@61840000 {
|
||||
compatible = "socionext,uniphier-ld4-sysctrl",
|
||||
"simple-mfd", "syscon";
|
||||
reg = <0x61840000 0x10000>;
|
||||
|
||||
sys_clk: clock {
|
||||
compatible = "socionext,uniphier-ld4-clock";
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
sys_rst: reset {
|
||||
compatible = "socionext,uniphier-ld4-reset";
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
nand: nand@68000000 {
|
||||
compatible = "socionext,denali-nand-v5a";
|
||||
status = "disabled";
|
||||
reg-names = "nand_data", "denali_reg";
|
||||
reg = <0x68000000 0x20>, <0x68100000 0x1000>;
|
||||
interrupts = <0 65 4>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_nand>;
|
||||
clocks = <&sys_clk 2>;
|
||||
nand-ecc-strength = <8>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&soc {
|
||||
l2: l2-cache@500c0000 {
|
||||
compatible = "socionext,uniphier-system-cache";
|
||||
reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, <0x506c0000 0x400>;
|
||||
interrupts = <0 174 4>, <0 175 4>;
|
||||
cache-unified;
|
||||
cache-size = <(512 * 1024)>;
|
||||
cache-sets = <256>;
|
||||
cache-line-size = <128>;
|
||||
cache-level = <2>;
|
||||
};
|
||||
|
||||
port0x: gpio@55000008 {
|
||||
compatible = "socionext,uniphier-gpio";
|
||||
reg = <0x55000008 0x8>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
port1x: gpio@55000010 {
|
||||
compatible = "socionext,uniphier-gpio";
|
||||
reg = <0x55000010 0x8>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
port2x: gpio@55000018 {
|
||||
compatible = "socionext,uniphier-gpio";
|
||||
reg = <0x55000018 0x8>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
port3x: gpio@55000020 {
|
||||
compatible = "socionext,uniphier-gpio";
|
||||
reg = <0x55000020 0x8>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
port4: gpio@55000028 {
|
||||
compatible = "socionext,uniphier-gpio";
|
||||
reg = <0x55000028 0x8>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
port5x: gpio@55000030 {
|
||||
compatible = "socionext,uniphier-gpio";
|
||||
reg = <0x55000030 0x8>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
port6x: gpio@55000038 {
|
||||
compatible = "socionext,uniphier-gpio";
|
||||
reg = <0x55000038 0x8>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
port7x: gpio@55000040 {
|
||||
compatible = "socionext,uniphier-gpio";
|
||||
reg = <0x55000040 0x8>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
port8x: gpio@55000048 {
|
||||
compatible = "socionext,uniphier-gpio";
|
||||
reg = <0x55000048 0x8>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
port9x: gpio@55000050 {
|
||||
compatible = "socionext,uniphier-gpio";
|
||||
reg = <0x55000050 0x8>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
port10x: gpio@55000058 {
|
||||
compatible = "socionext,uniphier-gpio";
|
||||
reg = <0x55000058 0x8>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
port11x: gpio@55000060 {
|
||||
compatible = "socionext,uniphier-gpio";
|
||||
reg = <0x55000060 0x8>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
port12x: gpio@55000068 {
|
||||
compatible = "socionext,uniphier-gpio";
|
||||
reg = <0x55000068 0x8>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
port13x: gpio@55000070 {
|
||||
compatible = "socionext,uniphier-gpio";
|
||||
reg = <0x55000070 0x8>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
port14x: gpio@55000078 {
|
||||
compatible = "socionext,uniphier-gpio";
|
||||
reg = <0x55000078 0x8>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
port16x: gpio@55000088 {
|
||||
compatible = "socionext,uniphier-gpio";
|
||||
reg = <0x55000088 0x8>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
i2c0: i2c@58400000 {
|
||||
compatible = "socionext,uniphier-i2c";
|
||||
status = "disabled";
|
||||
reg = <0x58400000 0x40>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <0 41 1>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c0>;
|
||||
clocks = <&iobus_clk>;
|
||||
clock-frequency = <100000>;
|
||||
};
|
||||
|
||||
i2c1: i2c@58480000 {
|
||||
compatible = "socionext,uniphier-i2c";
|
||||
status = "disabled";
|
||||
reg = <0x58480000 0x40>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <0 42 1>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c1>;
|
||||
clocks = <&iobus_clk>;
|
||||
clock-frequency = <100000>;
|
||||
};
|
||||
|
||||
/* chip-internal connection for DMD */
|
||||
i2c2: i2c@58500000 {
|
||||
compatible = "socionext,uniphier-i2c";
|
||||
reg = <0x58500000 0x40>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <0 43 1>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c2>;
|
||||
clocks = <&iobus_clk>;
|
||||
clock-frequency = <400000>;
|
||||
};
|
||||
|
||||
i2c3: i2c@58580000 {
|
||||
compatible = "socionext,uniphier-i2c";
|
||||
status = "disabled";
|
||||
reg = <0x58580000 0x40>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <0 44 1>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c3>;
|
||||
clocks = <&iobus_clk>;
|
||||
clock-frequency = <100000>;
|
||||
};
|
||||
|
||||
sd: sdhc@5a400000 {
|
||||
compatible = "socionext,uniphier-sdhc";
|
||||
status = "disabled";
|
||||
reg = <0x5a400000 0x200>;
|
||||
interrupts = <0 76 4>;
|
||||
pinctrl-names = "default", "1.8v";
|
||||
pinctrl-0 = <&pinctrl_sd>;
|
||||
pinctrl-1 = <&pinctrl_sd_1v8>;
|
||||
clocks = <&mio_clk 0>;
|
||||
reset-names = "host", "bridge";
|
||||
resets = <&mio_rst 0>, <&mio_rst 3>;
|
||||
bus-width = <4>;
|
||||
};
|
||||
|
||||
emmc: sdhc@5a500000 {
|
||||
compatible = "socionext,uniphier-sdhc";
|
||||
status = "disabled";
|
||||
reg = <0x5a500000 0x200>;
|
||||
interrupts = <0 78 4>;
|
||||
pinctrl-names = "default", "1.8v";
|
||||
pinctrl-0 = <&pinctrl_emmc>;
|
||||
pinctrl-1 = <&pinctrl_emmc_1v8>;
|
||||
clocks = <&mio_clk 1>;
|
||||
reset-names = "host", "bridge", "hw-reset";
|
||||
resets = <&mio_rst 1>, <&mio_rst 4>, <&mio_rst 6>;
|
||||
bus-width = <8>;
|
||||
non-removable;
|
||||
};
|
||||
|
||||
usb0: usb@5a800100 {
|
||||
compatible = "socionext,uniphier-ehci", "generic-ehci";
|
||||
status = "disabled";
|
||||
reg = <0x5a800100 0x100>;
|
||||
interrupts = <0 80 4>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usb0>;
|
||||
clocks = <&mio_clk 7>, <&mio_clk 8>, <&mio_clk 12>;
|
||||
resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>,
|
||||
<&mio_rst 12>;
|
||||
};
|
||||
|
||||
usb1: usb@5a810100 {
|
||||
compatible = "socionext,uniphier-ehci", "generic-ehci";
|
||||
status = "disabled";
|
||||
reg = <0x5a810100 0x100>;
|
||||
interrupts = <0 81 4>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usb1>;
|
||||
clocks = <&mio_clk 7>, <&mio_clk 9>, <&mio_clk 13>;
|
||||
resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>,
|
||||
<&mio_rst 13>;
|
||||
};
|
||||
|
||||
usb2: usb@5a820100 {
|
||||
compatible = "socionext,uniphier-ehci", "generic-ehci";
|
||||
status = "disabled";
|
||||
reg = <0x5a820100 0x100>;
|
||||
interrupts = <0 82 4>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usb2>;
|
||||
clocks = <&mio_clk 7>, <&mio_clk 10>, <&mio_clk 14>;
|
||||
resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 10>,
|
||||
<&mio_rst 14>;
|
||||
};
|
||||
|
||||
aidet@61830000 {
|
||||
compatible = "simple-mfd", "syscon";
|
||||
reg = <0x61830000 0x200>;
|
||||
};
|
||||
};
|
||||
|
||||
&refclk {
|
||||
clock-frequency = <24576000>;
|
||||
};
|
||||
|
||||
&serial0 {
|
||||
clock-frequency = <36864000>;
|
||||
};
|
||||
|
||||
&serial1 {
|
||||
clock-frequency = <36864000>;
|
||||
};
|
||||
|
||||
&serial2 {
|
||||
clock-frequency = <36864000>;
|
||||
};
|
||||
|
||||
&serial3 {
|
||||
interrupts = <0 29 4>;
|
||||
clock-frequency = <36864000>;
|
||||
};
|
||||
|
||||
&mio_clk {
|
||||
compatible = "socionext,uniphier-ld4-mio-clock";
|
||||
};
|
||||
|
||||
&mio_rst {
|
||||
compatible = "socionext,uniphier-ld4-mio-reset";
|
||||
};
|
||||
|
||||
&peri_clk {
|
||||
compatible = "socionext,uniphier-ld4-peri-clock";
|
||||
};
|
||||
|
||||
&peri_rst {
|
||||
compatible = "socionext,uniphier-ld4-peri-reset";
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
compatible = "socionext,uniphier-ld4-pinctrl";
|
||||
};
|
||||
|
||||
&sys_clk {
|
||||
compatible = "socionext,uniphier-ld4-clock";
|
||||
};
|
||||
|
||||
&sys_rst {
|
||||
compatible = "socionext,uniphier-ld4-reset";
|
||||
};
|
||||
/include/ "uniphier-pinctrl.dtsi"
|
||||
|
||||
@ -68,10 +68,6 @@
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2 {
|
||||
status = "okay";
|
||||
};
|
||||
@ -80,6 +76,14 @@
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* for U-Boot only */
|
||||
&serial0 {
|
||||
u-boot,dm-pre-reloc;
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@ -71,7 +71,7 @@
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
&mio_clk {
|
||||
&sd_clk {
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
|
||||
@ -55,7 +55,7 @@
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
&mio_clk {
|
||||
&sd_clk {
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -50,12 +50,6 @@
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <50000000>;
|
||||
};
|
||||
|
||||
iobus_clk: iobus_clk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <100000000>;
|
||||
};
|
||||
};
|
||||
|
||||
soc {
|
||||
@ -251,7 +245,7 @@
|
||||
interrupts = <0 41 1>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c0>;
|
||||
clocks = <&iobus_clk>;
|
||||
clocks = <&sys_clk 1>;
|
||||
clock-frequency = <100000>;
|
||||
};
|
||||
|
||||
@ -262,7 +256,7 @@
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <0 42 1>;
|
||||
clocks = <&iobus_clk>;
|
||||
clocks = <&sys_clk 1>;
|
||||
clock-frequency = <100000>;
|
||||
};
|
||||
|
||||
@ -273,7 +267,7 @@
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <0 43 1>;
|
||||
clocks = <&iobus_clk>;
|
||||
clocks = <&sys_clk 1>;
|
||||
clock-frequency = <100000>;
|
||||
};
|
||||
|
||||
@ -284,7 +278,7 @@
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <0 44 1>;
|
||||
clocks = <&iobus_clk>;
|
||||
clocks = <&sys_clk 1>;
|
||||
clock-frequency = <100000>;
|
||||
};
|
||||
|
||||
@ -295,7 +289,7 @@
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <0 45 1>;
|
||||
clocks = <&iobus_clk>;
|
||||
clocks = <&sys_clk 1>;
|
||||
clock-frequency = <400000>;
|
||||
};
|
||||
|
||||
@ -339,9 +333,12 @@
|
||||
pinctrl-0 = <&pinctrl_emmc>;
|
||||
pinctrl-1 = <&pinctrl_emmc_1v8>;
|
||||
clocks = <&mio_clk 1>;
|
||||
reset-names = "host", "bridge";
|
||||
resets = <&mio_rst 1>, <&mio_rst 4>;
|
||||
bus-width = <8>;
|
||||
non-removable;
|
||||
cap-mmc-highspeed;
|
||||
cap-mmc-hw-reset;
|
||||
};
|
||||
|
||||
sd: sdhc@5a500000 {
|
||||
@ -353,8 +350,13 @@
|
||||
pinctrl-0 = <&pinctrl_sd>;
|
||||
pinctrl-1 = <&pinctrl_sd_1v8>;
|
||||
clocks = <&mio_clk 0>;
|
||||
reset-names = "host", "bridge";
|
||||
resets = <&mio_rst 0>, <&mio_rst 3>;
|
||||
bus-width = <4>;
|
||||
cap-sd-highspeed;
|
||||
sd-uhs-sdr12;
|
||||
sd-uhs-sdr25;
|
||||
sd-uhs-sdr50;
|
||||
};
|
||||
|
||||
usb0: usb@5a800100 {
|
||||
@ -406,7 +408,8 @@
|
||||
};
|
||||
|
||||
soc-glue@5f800000 {
|
||||
compatible = "simple-mfd", "syscon";
|
||||
compatible = "socionext,uniphier-sld3-soc-glue",
|
||||
"simple-mfd", "syscon";
|
||||
reg = <0x5f800000 0x2000>;
|
||||
u-boot,dm-pre-reloc;
|
||||
|
||||
@ -422,7 +425,7 @@
|
||||
};
|
||||
|
||||
sysctrl@f1840000 {
|
||||
compatible = "socionext,uniphier-sysctrl",
|
||||
compatible = "socionext,uniphier-sld3-sysctrl",
|
||||
"simple-mfd", "syscon";
|
||||
reg = <0xf1840000 0x4000>;
|
||||
|
||||
@ -438,9 +441,13 @@
|
||||
};
|
||||
|
||||
nand: nand@f8000000 {
|
||||
compatible = "denali,denali-nand-dt";
|
||||
reg = <0xf8000000 0x20>, <0xf8100000 0x1000>;
|
||||
compatible = "socionext,denali-nand-v5a";
|
||||
status = "disabled";
|
||||
reg-names = "nand_data", "denali_reg";
|
||||
reg = <0xf8000000 0x20>, <0xf8100000 0x1000>;
|
||||
interrupts = <0 65 4>;
|
||||
clocks = <&sys_clk 2>;
|
||||
nand-ecc-strength = <8>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
@ -7,7 +7,7 @@
|
||||
* SPDX-License-Identifier: GPL-2.0+ X11
|
||||
*/
|
||||
|
||||
/include/ "uniphier-common32.dtsi"
|
||||
/include/ "skeleton.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "socionext,uniphier-sld8";
|
||||
@ -25,313 +25,438 @@
|
||||
};
|
||||
};
|
||||
|
||||
psci {
|
||||
compatible = "arm,psci-0.2";
|
||||
method = "smc";
|
||||
};
|
||||
|
||||
clocks {
|
||||
refclk: ref {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <25000000>;
|
||||
};
|
||||
|
||||
arm_timer_clk: arm_timer_clk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <50000000>;
|
||||
};
|
||||
};
|
||||
|
||||
iobus_clk: iobus_clk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <100000000>;
|
||||
soc {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
interrupt-parent = <&intc>;
|
||||
u-boot,dm-pre-reloc;
|
||||
|
||||
l2: l2-cache@500c0000 {
|
||||
compatible = "socionext,uniphier-system-cache";
|
||||
reg = <0x500c0000 0x2000>, <0x503c0100 0x4>,
|
||||
<0x506c0000 0x400>;
|
||||
interrupts = <0 174 4>, <0 175 4>;
|
||||
cache-unified;
|
||||
cache-size = <(256 * 1024)>;
|
||||
cache-sets = <256>;
|
||||
cache-line-size = <128>;
|
||||
cache-level = <2>;
|
||||
};
|
||||
|
||||
serial0: serial@54006800 {
|
||||
compatible = "socionext,uniphier-uart";
|
||||
status = "disabled";
|
||||
reg = <0x54006800 0x40>;
|
||||
interrupts = <0 33 4>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart0>;
|
||||
clocks = <&peri_clk 0>;
|
||||
clock-frequency = <80000000>;
|
||||
};
|
||||
|
||||
serial1: serial@54006900 {
|
||||
compatible = "socionext,uniphier-uart";
|
||||
status = "disabled";
|
||||
reg = <0x54006900 0x40>;
|
||||
interrupts = <0 35 4>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart1>;
|
||||
clocks = <&peri_clk 1>;
|
||||
clock-frequency = <80000000>;
|
||||
};
|
||||
|
||||
serial2: serial@54006a00 {
|
||||
compatible = "socionext,uniphier-uart";
|
||||
status = "disabled";
|
||||
reg = <0x54006a00 0x40>;
|
||||
interrupts = <0 37 4>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart2>;
|
||||
clocks = <&peri_clk 2>;
|
||||
clock-frequency = <80000000>;
|
||||
};
|
||||
|
||||
serial3: serial@54006b00 {
|
||||
compatible = "socionext,uniphier-uart";
|
||||
status = "disabled";
|
||||
reg = <0x54006b00 0x40>;
|
||||
interrupts = <0 29 4>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart3>;
|
||||
clocks = <&peri_clk 3>;
|
||||
clock-frequency = <80000000>;
|
||||
};
|
||||
|
||||
port0x: gpio@55000008 {
|
||||
compatible = "socionext,uniphier-gpio";
|
||||
reg = <0x55000008 0x8>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
port1x: gpio@55000010 {
|
||||
compatible = "socionext,uniphier-gpio";
|
||||
reg = <0x55000010 0x8>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
port2x: gpio@55000018 {
|
||||
compatible = "socionext,uniphier-gpio";
|
||||
reg = <0x55000018 0x8>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
port3x: gpio@55000020 {
|
||||
compatible = "socionext,uniphier-gpio";
|
||||
reg = <0x55000020 0x8>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
port4: gpio@55000028 {
|
||||
compatible = "socionext,uniphier-gpio";
|
||||
reg = <0x55000028 0x8>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
port5x: gpio@55000030 {
|
||||
compatible = "socionext,uniphier-gpio";
|
||||
reg = <0x55000030 0x8>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
port6x: gpio@55000038 {
|
||||
compatible = "socionext,uniphier-gpio";
|
||||
reg = <0x55000038 0x8>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
port7x: gpio@55000040 {
|
||||
compatible = "socionext,uniphier-gpio";
|
||||
reg = <0x55000040 0x8>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
port8x: gpio@55000048 {
|
||||
compatible = "socionext,uniphier-gpio";
|
||||
reg = <0x55000048 0x8>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
port9x: gpio@55000050 {
|
||||
compatible = "socionext,uniphier-gpio";
|
||||
reg = <0x55000050 0x8>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
port10x: gpio@55000058 {
|
||||
compatible = "socionext,uniphier-gpio";
|
||||
reg = <0x55000058 0x8>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
port11x: gpio@55000060 {
|
||||
compatible = "socionext,uniphier-gpio";
|
||||
reg = <0x55000060 0x8>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
port12x: gpio@55000068 {
|
||||
compatible = "socionext,uniphier-gpio";
|
||||
reg = <0x55000068 0x8>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
port13x: gpio@55000070 {
|
||||
compatible = "socionext,uniphier-gpio";
|
||||
reg = <0x55000070 0x8>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
port14x: gpio@55000078 {
|
||||
compatible = "socionext,uniphier-gpio";
|
||||
reg = <0x55000078 0x8>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
port16x: gpio@55000088 {
|
||||
compatible = "socionext,uniphier-gpio";
|
||||
reg = <0x55000088 0x8>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
i2c0: i2c@58400000 {
|
||||
compatible = "socionext,uniphier-i2c";
|
||||
status = "disabled";
|
||||
reg = <0x58400000 0x40>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <0 41 1>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c0>;
|
||||
clocks = <&peri_clk 4>;
|
||||
clock-frequency = <100000>;
|
||||
};
|
||||
|
||||
i2c1: i2c@58480000 {
|
||||
compatible = "socionext,uniphier-i2c";
|
||||
status = "disabled";
|
||||
reg = <0x58480000 0x40>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <0 42 1>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c1>;
|
||||
clocks = <&peri_clk 5>;
|
||||
clock-frequency = <100000>;
|
||||
};
|
||||
|
||||
/* chip-internal connection for DMD */
|
||||
i2c2: i2c@58500000 {
|
||||
compatible = "socionext,uniphier-i2c";
|
||||
reg = <0x58500000 0x40>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <0 43 1>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c2>;
|
||||
clocks = <&peri_clk 6>;
|
||||
clock-frequency = <400000>;
|
||||
};
|
||||
|
||||
i2c3: i2c@58580000 {
|
||||
compatible = "socionext,uniphier-i2c";
|
||||
status = "disabled";
|
||||
reg = <0x58580000 0x40>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <0 44 1>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c3>;
|
||||
clocks = <&peri_clk 7>;
|
||||
clock-frequency = <100000>;
|
||||
};
|
||||
|
||||
system_bus: system-bus@58c00000 {
|
||||
compatible = "socionext,uniphier-system-bus";
|
||||
status = "disabled";
|
||||
reg = <0x58c00000 0x400>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_system_bus>;
|
||||
};
|
||||
|
||||
smpctrl@59800000 {
|
||||
compatible = "socionext,uniphier-smpctrl";
|
||||
reg = <0x59801000 0x400>;
|
||||
};
|
||||
|
||||
mioctrl@59810000 {
|
||||
compatible = "socionext,uniphier-sld8-mioctrl",
|
||||
"simple-mfd", "syscon";
|
||||
reg = <0x59810000 0x800>;
|
||||
|
||||
mio_clk: clock {
|
||||
compatible = "socionext,uniphier-sld8-mio-clock";
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
mio_rst: reset {
|
||||
compatible = "socionext,uniphier-sld8-mio-reset";
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
perictrl@59820000 {
|
||||
compatible = "socionext,uniphier-sld8-perictrl",
|
||||
"simple-mfd", "syscon";
|
||||
reg = <0x59820000 0x200>;
|
||||
|
||||
peri_clk: clock {
|
||||
compatible = "socionext,uniphier-sld8-peri-clock";
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
peri_rst: reset {
|
||||
compatible = "socionext,uniphier-sld8-peri-reset";
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
sd: sdhc@5a400000 {
|
||||
compatible = "socionext,uniphier-sdhc";
|
||||
status = "disabled";
|
||||
reg = <0x5a400000 0x200>;
|
||||
interrupts = <0 76 4>;
|
||||
pinctrl-names = "default", "1.8v";
|
||||
pinctrl-0 = <&pinctrl_sd>;
|
||||
pinctrl-1 = <&pinctrl_sd_1v8>;
|
||||
clocks = <&mio_clk 0>;
|
||||
reset-names = "host", "bridge";
|
||||
resets = <&mio_rst 0>, <&mio_rst 3>;
|
||||
bus-width = <4>;
|
||||
cap-sd-highspeed;
|
||||
sd-uhs-sdr12;
|
||||
sd-uhs-sdr25;
|
||||
sd-uhs-sdr50;
|
||||
};
|
||||
|
||||
emmc: sdhc@5a500000 {
|
||||
compatible = "socionext,uniphier-sdhc";
|
||||
status = "disabled";
|
||||
reg = <0x5a500000 0x200>;
|
||||
interrupts = <0 78 4>;
|
||||
pinctrl-names = "default", "1.8v";
|
||||
pinctrl-0 = <&pinctrl_emmc>;
|
||||
pinctrl-1 = <&pinctrl_emmc_1v8>;
|
||||
clocks = <&mio_clk 1>;
|
||||
reset-names = "host", "bridge";
|
||||
resets = <&mio_rst 1>, <&mio_rst 4>;
|
||||
bus-width = <8>;
|
||||
non-removable;
|
||||
cap-mmc-highspeed;
|
||||
cap-mmc-hw-reset;
|
||||
};
|
||||
|
||||
usb0: usb@5a800100 {
|
||||
compatible = "socionext,uniphier-ehci", "generic-ehci";
|
||||
status = "disabled";
|
||||
reg = <0x5a800100 0x100>;
|
||||
interrupts = <0 80 4>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usb0>;
|
||||
clocks = <&mio_clk 7>, <&mio_clk 8>, <&mio_clk 12>;
|
||||
resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>,
|
||||
<&mio_rst 12>;
|
||||
};
|
||||
|
||||
usb1: usb@5a810100 {
|
||||
compatible = "socionext,uniphier-ehci", "generic-ehci";
|
||||
status = "disabled";
|
||||
reg = <0x5a810100 0x100>;
|
||||
interrupts = <0 81 4>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usb1>;
|
||||
clocks = <&mio_clk 7>, <&mio_clk 9>, <&mio_clk 13>;
|
||||
resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>,
|
||||
<&mio_rst 13>;
|
||||
};
|
||||
|
||||
usb2: usb@5a820100 {
|
||||
compatible = "socionext,uniphier-ehci", "generic-ehci";
|
||||
status = "disabled";
|
||||
reg = <0x5a820100 0x100>;
|
||||
interrupts = <0 82 4>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usb2>;
|
||||
clocks = <&mio_clk 7>, <&mio_clk 10>, <&mio_clk 14>;
|
||||
resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 10>,
|
||||
<&mio_rst 14>;
|
||||
};
|
||||
|
||||
soc-glue@5f800000 {
|
||||
compatible = "socionext,uniphier-sld8-soc-glue",
|
||||
"simple-mfd", "syscon";
|
||||
reg = <0x5f800000 0x2000>;
|
||||
u-boot,dm-pre-reloc;
|
||||
|
||||
pinctrl: pinctrl {
|
||||
compatible = "socionext,uniphier-sld8-pinctrl";
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
};
|
||||
|
||||
timer@60000200 {
|
||||
compatible = "arm,cortex-a9-global-timer";
|
||||
reg = <0x60000200 0x20>;
|
||||
interrupts = <1 11 0x104>;
|
||||
clocks = <&arm_timer_clk>;
|
||||
};
|
||||
|
||||
timer@60000600 {
|
||||
compatible = "arm,cortex-a9-twd-timer";
|
||||
reg = <0x60000600 0x20>;
|
||||
interrupts = <1 13 0x104>;
|
||||
clocks = <&arm_timer_clk>;
|
||||
};
|
||||
|
||||
intc: interrupt-controller@60001000 {
|
||||
compatible = "arm,cortex-a9-gic";
|
||||
reg = <0x60001000 0x1000>,
|
||||
<0x60000100 0x100>;
|
||||
#interrupt-cells = <3>;
|
||||
interrupt-controller;
|
||||
};
|
||||
|
||||
aidet@61830000 {
|
||||
compatible = "simple-mfd", "syscon";
|
||||
reg = <0x61830000 0x200>;
|
||||
};
|
||||
|
||||
sysctrl@61840000 {
|
||||
compatible = "socionext,uniphier-sld8-sysctrl",
|
||||
"simple-mfd", "syscon";
|
||||
reg = <0x61840000 0x10000>;
|
||||
|
||||
sys_clk: clock {
|
||||
compatible = "socionext,uniphier-sld8-clock";
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
sys_rst: reset {
|
||||
compatible = "socionext,uniphier-sld8-reset";
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
nand: nand@68000000 {
|
||||
compatible = "socionext,denali-nand-v5a";
|
||||
status = "disabled";
|
||||
reg-names = "nand_data", "denali_reg";
|
||||
reg = <0x68000000 0x20>, <0x68100000 0x1000>;
|
||||
interrupts = <0 65 4>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_nand>;
|
||||
clocks = <&sys_clk 2>;
|
||||
nand-ecc-strength = <8>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&soc {
|
||||
l2: l2-cache@500c0000 {
|
||||
compatible = "socionext,uniphier-system-cache";
|
||||
reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, <0x506c0000 0x400>;
|
||||
interrupts = <0 174 4>, <0 175 4>;
|
||||
cache-unified;
|
||||
cache-size = <(256 * 1024)>;
|
||||
cache-sets = <256>;
|
||||
cache-line-size = <128>;
|
||||
cache-level = <2>;
|
||||
};
|
||||
|
||||
port0x: gpio@55000008 {
|
||||
compatible = "socionext,uniphier-gpio";
|
||||
reg = <0x55000008 0x8>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
port1x: gpio@55000010 {
|
||||
compatible = "socionext,uniphier-gpio";
|
||||
reg = <0x55000010 0x8>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
port2x: gpio@55000018 {
|
||||
compatible = "socionext,uniphier-gpio";
|
||||
reg = <0x55000018 0x8>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
port3x: gpio@55000020 {
|
||||
compatible = "socionext,uniphier-gpio";
|
||||
reg = <0x55000020 0x8>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
port4: gpio@55000028 {
|
||||
compatible = "socionext,uniphier-gpio";
|
||||
reg = <0x55000028 0x8>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
port5x: gpio@55000030 {
|
||||
compatible = "socionext,uniphier-gpio";
|
||||
reg = <0x55000030 0x8>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
port6x: gpio@55000038 {
|
||||
compatible = "socionext,uniphier-gpio";
|
||||
reg = <0x55000038 0x8>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
port7x: gpio@55000040 {
|
||||
compatible = "socionext,uniphier-gpio";
|
||||
reg = <0x55000040 0x8>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
port8x: gpio@55000048 {
|
||||
compatible = "socionext,uniphier-gpio";
|
||||
reg = <0x55000048 0x8>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
port9x: gpio@55000050 {
|
||||
compatible = "socionext,uniphier-gpio";
|
||||
reg = <0x55000050 0x8>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
port10x: gpio@55000058 {
|
||||
compatible = "socionext,uniphier-gpio";
|
||||
reg = <0x55000058 0x8>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
port11x: gpio@55000060 {
|
||||
compatible = "socionext,uniphier-gpio";
|
||||
reg = <0x55000060 0x8>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
port12x: gpio@55000068 {
|
||||
compatible = "socionext,uniphier-gpio";
|
||||
reg = <0x55000068 0x8>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
port13x: gpio@55000070 {
|
||||
compatible = "socionext,uniphier-gpio";
|
||||
reg = <0x55000070 0x8>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
port14x: gpio@55000078 {
|
||||
compatible = "socionext,uniphier-gpio";
|
||||
reg = <0x55000078 0x8>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
port16x: gpio@55000088 {
|
||||
compatible = "socionext,uniphier-gpio";
|
||||
reg = <0x55000088 0x8>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
i2c0: i2c@58400000 {
|
||||
compatible = "socionext,uniphier-i2c";
|
||||
status = "disabled";
|
||||
reg = <0x58400000 0x40>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <0 41 1>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c0>;
|
||||
clocks = <&iobus_clk>;
|
||||
clock-frequency = <100000>;
|
||||
};
|
||||
|
||||
i2c1: i2c@58480000 {
|
||||
compatible = "socionext,uniphier-i2c";
|
||||
status = "disabled";
|
||||
reg = <0x58480000 0x40>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <0 42 1>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c1>;
|
||||
clocks = <&iobus_clk>;
|
||||
clock-frequency = <100000>;
|
||||
};
|
||||
|
||||
/* chip-internal connection for DMD */
|
||||
i2c2: i2c@58500000 {
|
||||
compatible = "socionext,uniphier-i2c";
|
||||
reg = <0x58500000 0x40>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <0 43 1>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c2>;
|
||||
clocks = <&iobus_clk>;
|
||||
clock-frequency = <400000>;
|
||||
};
|
||||
|
||||
i2c3: i2c@58580000 {
|
||||
compatible = "socionext,uniphier-i2c";
|
||||
status = "disabled";
|
||||
reg = <0x58580000 0x40>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <0 44 1>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c3>;
|
||||
clocks = <&iobus_clk>;
|
||||
clock-frequency = <100000>;
|
||||
};
|
||||
|
||||
sd: sdhc@5a400000 {
|
||||
compatible = "socionext,uniphier-sdhc";
|
||||
status = "disabled";
|
||||
reg = <0x5a400000 0x200>;
|
||||
interrupts = <0 76 4>;
|
||||
pinctrl-names = "default", "1.8v";
|
||||
pinctrl-0 = <&pinctrl_sd>;
|
||||
pinctrl-1 = <&pinctrl_sd_1v8>;
|
||||
clocks = <&mio_clk 0>;
|
||||
reset-names = "host", "bridge";
|
||||
resets = <&mio_rst 0>, <&mio_rst 3>;
|
||||
bus-width = <4>;
|
||||
};
|
||||
|
||||
emmc: sdhc@5a500000 {
|
||||
compatible = "socionext,uniphier-sdhc";
|
||||
status = "disabled";
|
||||
interrupts = <0 78 4>;
|
||||
reg = <0x5a500000 0x200>;
|
||||
pinctrl-names = "default", "1.8v";
|
||||
pinctrl-0 = <&pinctrl_emmc>;
|
||||
pinctrl-1 = <&pinctrl_emmc_1v8>;
|
||||
clocks = <&mio_clk 1>;
|
||||
reset-names = "host", "bridge", "hw-reset";
|
||||
resets = <&mio_rst 1>, <&mio_rst 4>, <&mio_rst 6>;
|
||||
bus-width = <8>;
|
||||
non-removable;
|
||||
};
|
||||
|
||||
usb0: usb@5a800100 {
|
||||
compatible = "socionext,uniphier-ehci", "generic-ehci";
|
||||
status = "disabled";
|
||||
reg = <0x5a800100 0x100>;
|
||||
interrupts = <0 80 4>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usb0>;
|
||||
clocks = <&mio_clk 7>, <&mio_clk 8>, <&mio_clk 12>;
|
||||
resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>,
|
||||
<&mio_rst 12>;
|
||||
};
|
||||
|
||||
usb1: usb@5a810100 {
|
||||
compatible = "socionext,uniphier-ehci", "generic-ehci";
|
||||
status = "disabled";
|
||||
reg = <0x5a810100 0x100>;
|
||||
interrupts = <0 81 4>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usb1>;
|
||||
clocks = <&mio_clk 7>, <&mio_clk 9>, <&mio_clk 13>;
|
||||
resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>,
|
||||
<&mio_rst 13>;
|
||||
};
|
||||
|
||||
usb2: usb@5a820100 {
|
||||
compatible = "socionext,uniphier-ehci", "generic-ehci";
|
||||
status = "disabled";
|
||||
reg = <0x5a820100 0x100>;
|
||||
interrupts = <0 82 4>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usb2>;
|
||||
clocks = <&mio_clk 7>, <&mio_clk 10>, <&mio_clk 14>;
|
||||
resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 10>,
|
||||
<&mio_rst 14>;
|
||||
};
|
||||
|
||||
aidet@61830000 {
|
||||
compatible = "simple-mfd", "syscon";
|
||||
reg = <0x61830000 0x200>;
|
||||
};
|
||||
};
|
||||
|
||||
&refclk {
|
||||
clock-frequency = <25000000>;
|
||||
};
|
||||
|
||||
&serial0 {
|
||||
clock-frequency = <80000000>;
|
||||
};
|
||||
|
||||
&serial1 {
|
||||
clock-frequency = <80000000>;
|
||||
};
|
||||
|
||||
&serial2 {
|
||||
clock-frequency = <80000000>;
|
||||
};
|
||||
|
||||
&serial3 {
|
||||
interrupts = <0 29 4>;
|
||||
clock-frequency = <80000000>;
|
||||
};
|
||||
|
||||
&mio_clk {
|
||||
compatible = "socionext,uniphier-sld8-mio-clock";
|
||||
};
|
||||
|
||||
&mio_rst {
|
||||
compatible = "socionext,uniphier-sld8-mio-reset";
|
||||
};
|
||||
|
||||
&peri_clk {
|
||||
compatible = "socionext,uniphier-sld8-peri-clock";
|
||||
};
|
||||
|
||||
&peri_rst {
|
||||
compatible = "socionext,uniphier-sld8-peri-reset";
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
compatible = "socionext,uniphier-sld8-pinctrl";
|
||||
};
|
||||
|
||||
&sys_clk {
|
||||
compatible = "socionext,uniphier-sld8-clock";
|
||||
};
|
||||
|
||||
&sys_rst {
|
||||
compatible = "socionext,uniphier-sld8-reset";
|
||||
};
|
||||
/include/ "uniphier-pinctrl.dtsi"
|
||||
|
||||
21
arch/arm/include/asm/arch-armada8k/cache_llc.h
Normal file
21
arch/arm/include/asm/arch-armada8k/cache_llc.h
Normal file
@ -0,0 +1,21 @@
|
||||
/*
|
||||
* Copyright (C) 2016 Marvell International Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0
|
||||
* https://spdx.org/licenses
|
||||
*/
|
||||
|
||||
#ifndef _CACHE_LLC_H_
|
||||
#define _CACHE_LLC_H_
|
||||
|
||||
/* Armada-7K/8K last level cache */
|
||||
|
||||
#define MVEBU_A8K_REGS_BASE_MSB 0xf000
|
||||
#define LLC_BASE_ADDR 0x8000
|
||||
#define LLC_CACHE_SYNC 0x700
|
||||
#define LLC_CACHE_SYNC_COMPLETE 0x730
|
||||
#define LLC_FLUSH_BY_WAY 0x7fc
|
||||
#define LLC_WAY_MASK 0xffffffff
|
||||
#define LLC_CACHE_SYNC_MASK 0x1
|
||||
|
||||
#endif /* _CACHE_LLC_H_ */
|
||||
17
arch/arm/include/asm/arch-armada8k/soc-info.h
Normal file
17
arch/arm/include/asm/arch-armada8k/soc-info.h
Normal file
@ -0,0 +1,17 @@
|
||||
/*
|
||||
* Copyright (C) 2016 Marvell International Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0
|
||||
* https://spdx.org/licenses
|
||||
*/
|
||||
|
||||
#ifndef _SOC_INFO_H_
|
||||
#define _SOC_INFO_H_
|
||||
|
||||
/* Pin Ctrl driver definitions */
|
||||
#define BITS_PER_PIN 4
|
||||
#define PIN_FUNC_MASK ((1 << BITS_PER_PIN) - 1)
|
||||
#define PIN_REG_SHIFT 3
|
||||
#define PIN_FIELD_MASK ((1 << PIN_REG_SHIFT) - 1)
|
||||
|
||||
#endif /* _SOC_INFO_H_ */
|
||||
@ -18,6 +18,7 @@
|
||||
#define CONFIG_SYS_CCI400_ADDR (CONFIG_SYS_IMMR + 0x00180000)
|
||||
#define CONFIG_SYS_GIC400_ADDR (CONFIG_SYS_IMMR + 0x00400000)
|
||||
#define CONFIG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x00530000)
|
||||
#define SYS_FSL_QSPI_ADDR (CONFIG_SYS_IMMR + 0x00550000)
|
||||
#define CONFIG_SYS_FSL_ESDHC_ADDR (CONFIG_SYS_IMMR + 0x00560000)
|
||||
#define CONFIG_SYS_FSL_CSU_ADDR (CONFIG_SYS_IMMR + 0x00510000)
|
||||
#define CONFIG_SYS_FSL_GUTS_ADDR (CONFIG_SYS_IMMR + 0x00ee0000)
|
||||
|
||||
@ -19,6 +19,7 @@
|
||||
#define CONFIG_SYS_FSL_CH3_CLK_GRPA_ADDR (CONFIG_SYS_IMMR + 0x00300000)
|
||||
#define CONFIG_SYS_FSL_CH3_CLK_GRPB_ADDR (CONFIG_SYS_IMMR + 0x00310000)
|
||||
#define CONFIG_SYS_FSL_CH3_CLK_CTRL_ADDR (CONFIG_SYS_IMMR + 0x00370000)
|
||||
#define SYS_FSL_QSPI_ADDR (CONFIG_SYS_IMMR + 0x010c0000)
|
||||
#define CONFIG_SYS_FSL_ESDHC_ADDR (CONFIG_SYS_IMMR + 0x01140000)
|
||||
#define CONFIG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x01240000)
|
||||
#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x011C0500)
|
||||
|
||||
@ -1171,6 +1171,7 @@ struct emif_regs {
|
||||
u32 sdram_tim1;
|
||||
u32 sdram_tim2;
|
||||
u32 sdram_tim3;
|
||||
u32 ocp_config;
|
||||
u32 read_idle_ctrl;
|
||||
u32 zq_config;
|
||||
u32 temp_alert_config;
|
||||
|
||||
@ -83,8 +83,8 @@ config TARGET_DB_88F6820_AMC
|
||||
bool "Support DB-88F6820-AMC"
|
||||
select 88F6820
|
||||
|
||||
config TARGET_MVEBU_DB_88F7040
|
||||
bool "Support DB-88F7040 Armada 7040"
|
||||
config TARGET_MVEBU_ARMADA_8K
|
||||
bool "Support Armada 7k/8k platforms"
|
||||
select ARMADA_8K
|
||||
|
||||
config TARGET_DB_MV784MP_GP
|
||||
@ -111,7 +111,7 @@ config SYS_BOARD
|
||||
default "db-88f6720" if TARGET_DB_88F6720
|
||||
default "db-88f6820-gp" if TARGET_DB_88F6820_GP
|
||||
default "db-88f6820-amc" if TARGET_DB_88F6820_AMC
|
||||
default "mvebu_db-88f7040" if TARGET_MVEBU_DB_88F7040
|
||||
default "mvebu_armada-8k" if TARGET_MVEBU_ARMADA_8K
|
||||
default "db-mv784mp-gp" if TARGET_DB_MV784MP_GP
|
||||
default "ds414" if TARGET_DS414
|
||||
default "maxbcm" if TARGET_MAXBCM
|
||||
@ -123,7 +123,7 @@ config SYS_CONFIG_NAME
|
||||
default "db-88f6720" if TARGET_DB_88F6720
|
||||
default "db-88f6820-gp" if TARGET_DB_88F6820_GP
|
||||
default "db-88f6820-amc" if TARGET_DB_88F6820_AMC
|
||||
default "mvebu_db-88f7040" if TARGET_MVEBU_DB_88F7040
|
||||
default "mvebu_armada-8k" if TARGET_MVEBU_ARMADA_8K
|
||||
default "db-mv784mp-gp" if TARGET_DB_MV784MP_GP
|
||||
default "ds414" if TARGET_DS414
|
||||
default "maxbcm" if TARGET_MAXBCM
|
||||
@ -135,7 +135,7 @@ config SYS_VENDOR
|
||||
default "Marvell" if TARGET_DB_88F6720
|
||||
default "Marvell" if TARGET_DB_88F6820_GP
|
||||
default "Marvell" if TARGET_DB_88F6820_AMC
|
||||
default "Marvell" if TARGET_MVEBU_DB_88F7040
|
||||
default "Marvell" if TARGET_MVEBU_ARMADA_8K
|
||||
default "solidrun" if TARGET_CLEARFOG
|
||||
default "Synology" if TARGET_DS414
|
||||
|
||||
|
||||
@ -16,6 +16,23 @@
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
/*
|
||||
* Not all memory is mapped in the MMU. So we need to restrict the
|
||||
* memory size so that U-Boot does not try to access it. Also, the
|
||||
* internal registers are located at 0xf000.0000 - 0xffff.ffff.
|
||||
* Currently only 2GiB are mapped for system memory. This is what
|
||||
* we pass to the U-Boot subsystem here.
|
||||
*/
|
||||
#define USABLE_RAM_SIZE 0x80000000
|
||||
|
||||
ulong board_get_usable_ram_top(ulong total_size)
|
||||
{
|
||||
if (gd->ram_size > USABLE_RAM_SIZE)
|
||||
return USABLE_RAM_SIZE;
|
||||
|
||||
return gd->ram_size;
|
||||
}
|
||||
|
||||
/*
|
||||
* On ARMv8, MBus is not configured in U-Boot. To enable compilation
|
||||
* of the already implemented drivers, lets add a dummy version of
|
||||
@ -109,12 +126,20 @@ int arch_early_init_r(void)
|
||||
{
|
||||
struct udevice *dev;
|
||||
int ret;
|
||||
int i;
|
||||
|
||||
/* Call the comphy code via the MISC uclass driver */
|
||||
ret = uclass_get_device(UCLASS_MISC, 0, &dev);
|
||||
if (ret) {
|
||||
debug("COMPHY init failed: %d\n", ret);
|
||||
return -ENODEV;
|
||||
/*
|
||||
* Loop over all MISC uclass drivers to call the comphy code
|
||||
* and init all CP110 devices enabled in the DT
|
||||
*/
|
||||
i = 0;
|
||||
while (1) {
|
||||
/* Call the comphy code via the MISC uclass driver */
|
||||
ret = uclass_get_device(UCLASS_MISC, i++, &dev);
|
||||
|
||||
/* We're done, once no further CP110 device is found */
|
||||
if (ret)
|
||||
break;
|
||||
}
|
||||
|
||||
/* Cause the SATA device to do its early init */
|
||||
|
||||
@ -5,3 +5,4 @@
|
||||
#
|
||||
|
||||
obj-y = cpu.o
|
||||
obj-y += cache_llc.o
|
||||
|
||||
39
arch/arm/mach-mvebu/armada8k/cache_llc.S
Normal file
39
arch/arm/mach-mvebu/armada8k/cache_llc.S
Normal file
@ -0,0 +1,39 @@
|
||||
/*
|
||||
* Copyright (C) 2016 Marvell International Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0
|
||||
* https://spdx.org/licenses
|
||||
*/
|
||||
|
||||
#include <asm/arch-armada8k/cache_llc.h>
|
||||
#include <linux/linkage.h>
|
||||
|
||||
/*
|
||||
* int __asm_flush_l3_dcache
|
||||
*
|
||||
* flush Armada-8K last level cache.
|
||||
*
|
||||
*/
|
||||
ENTRY(__asm_flush_l3_dcache)
|
||||
/* flush cache */
|
||||
mov x0, #LLC_BASE_ADDR
|
||||
add x0, x0, #LLC_FLUSH_BY_WAY
|
||||
movk x0, #MVEBU_A8K_REGS_BASE_MSB, lsl #16
|
||||
mov w1, #LLC_WAY_MASK
|
||||
str w1, [x0]
|
||||
/* sync cache */
|
||||
mov x0, #LLC_BASE_ADDR
|
||||
add x0, x0, #LLC_CACHE_SYNC
|
||||
movk x0, #MVEBU_A8K_REGS_BASE_MSB, lsl #16
|
||||
str wzr, [x0]
|
||||
/* check that cache sync completed */
|
||||
mov x0, #LLC_BASE_ADDR
|
||||
add x0, x0, #LLC_CACHE_SYNC_COMPLETE
|
||||
movk x0, #MVEBU_A8K_REGS_BASE_MSB, lsl #16
|
||||
1: ldr w1, [x0]
|
||||
and w1, w1, #LLC_CACHE_SYNC_MASK
|
||||
cbnz w1, 1b
|
||||
/* return success */
|
||||
mov x0, #0
|
||||
ret
|
||||
ENDPROC(__asm_flush_l3_dcache)
|
||||
@ -39,13 +39,29 @@ static struct mm_region mvebu_mem_map[] = {
|
||||
PTE_BLOCK_NON_SHARE
|
||||
},
|
||||
{
|
||||
/* SRAM, MMIO regions - CP110 region */
|
||||
/* SRAM, MMIO regions - CP110 master region */
|
||||
.phys = 0xf2000000UL,
|
||||
.virt = 0xf2000000UL,
|
||||
.size = 0x02000000UL, /* 32MiB internal registers */
|
||||
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
|
||||
PTE_BLOCK_NON_SHARE
|
||||
},
|
||||
{
|
||||
/* SRAM, MMIO regions - CP110 slave region */
|
||||
.phys = 0xf4000000UL,
|
||||
.virt = 0xf4000000UL,
|
||||
.size = 0x02000000UL, /* 32MiB internal registers */
|
||||
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
|
||||
PTE_BLOCK_NON_SHARE
|
||||
},
|
||||
{
|
||||
/* PCI regions */
|
||||
.phys = 0xf8000000UL,
|
||||
.virt = 0xf8000000UL,
|
||||
.size = 0x08000000UL, /* 128MiB PCI space (master & slave) */
|
||||
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
|
||||
PTE_BLOCK_NON_SHARE
|
||||
},
|
||||
{
|
||||
/* List terminator */
|
||||
0,
|
||||
|
||||
@ -180,6 +180,10 @@ void config_sdram(const struct emif_regs *regs, int nr)
|
||||
writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl);
|
||||
writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl_shdw);
|
||||
writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config);
|
||||
|
||||
/* Write REG_COS_COUNT_1, REG_COS_COUNT_2, and REG_PR_OLD_COUNT. */
|
||||
if (regs->ocp_config)
|
||||
writel(regs->ocp_config, &emif_reg[nr]->emif_l3_config);
|
||||
}
|
||||
|
||||
/**
|
||||
|
||||
@ -74,6 +74,10 @@ config TARGET_SOCFPGA_TERASIC_DE0_NANO
|
||||
bool "Terasic DE0-Nano-Atlas (Cyclone V)"
|
||||
select TARGET_SOCFPGA_CYCLONE5
|
||||
|
||||
config TARGET_SOCFPGA_TERASIC_DE1_SOC
|
||||
bool "Terasic DE1-SoC (Cyclone V)"
|
||||
select TARGET_SOCFPGA_CYCLONE5
|
||||
|
||||
config TARGET_SOCFPGA_TERASIC_SOCKIT
|
||||
bool "Terasic SoCkit (Cyclone V)"
|
||||
select TARGET_SOCFPGA_CYCLONE5
|
||||
@ -84,6 +88,7 @@ config SYS_BOARD
|
||||
default "arria5-socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
|
||||
default "cyclone5-socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
|
||||
default "de0-nano-soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
|
||||
default "de1-soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC
|
||||
default "is1" if TARGET_SOCFPGA_IS1
|
||||
default "mcvevk" if TARGET_SOCFPGA_DENX_MCVEVK
|
||||
default "sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
|
||||
@ -98,6 +103,7 @@ config SYS_VENDOR
|
||||
default "ebv" if TARGET_SOCFPGA_EBV_SOCRATES
|
||||
default "samtec" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
|
||||
default "terasic" if TARGET_SOCFPGA_TERASIC_DE0_NANO
|
||||
default "terasic" if TARGET_SOCFPGA_TERASIC_DE1_SOC
|
||||
default "terasic" if TARGET_SOCFPGA_TERASIC_SOCKIT
|
||||
|
||||
config SYS_SOC
|
||||
@ -107,6 +113,7 @@ config SYS_CONFIG_NAME
|
||||
default "socfpga_arria5_socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
|
||||
default "socfpga_cyclone5_socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
|
||||
default "socfpga_de0_nano_soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
|
||||
default "socfpga_de1_soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC
|
||||
default "socfpga_is1" if TARGET_SOCFPGA_IS1
|
||||
default "socfpga_mcvevk" if TARGET_SOCFPGA_DENX_MCVEVK
|
||||
default "socfpga_sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
|
||||
|
||||
28
arch/arm/mach-socfpga/include/mach/boot0.h
Normal file
28
arch/arm/mach-socfpga/include/mach/boot0.h
Normal file
@ -0,0 +1,28 @@
|
||||
/*
|
||||
* Specialty padding for the Altera SoCFPGA preloader image
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef __BOOT0_H
|
||||
#define __BOOT0_H
|
||||
|
||||
#ifdef CONFIG_SPL_BUILD
|
||||
#define ARM_SOC_BOOT0_HOOK \
|
||||
.balignl 64,0xf33db33f; \
|
||||
\
|
||||
.word 0x1337c0d3; /* SoCFPGA preloader validation word */ \
|
||||
.word 0xc01df00d; /* Version, flags, length */ \
|
||||
.word 0xcafec0d3; /* Checksum, zero-pad */ \
|
||||
nop; \
|
||||
\
|
||||
b reset; /* SoCFPGA jumps here */ \
|
||||
nop; \
|
||||
nop; \
|
||||
nop;
|
||||
#else
|
||||
#define ARM_SOC_BOOT0_HOOK
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* __BOOT0_H */
|
||||
@ -1,5 +1,13 @@
|
||||
#!/bin/sh
|
||||
|
||||
#
|
||||
# helper function to convert from DOS to Unix, if necessary, and handle
|
||||
# lines ending in '\'.
|
||||
#
|
||||
fix_newlines_in_macros() {
|
||||
sed -n ':next;s/\r$//;/[^\\]\\$/ {N;s/\\\n//;b next};p' $1
|
||||
}
|
||||
|
||||
#
|
||||
# Process iocsr_config_*.[ch]
|
||||
# $1: SoC type
|
||||
@ -27,14 +35,16 @@ process_iocsr_config() {
|
||||
EOF
|
||||
|
||||
# Retrieve the scan chain lengths
|
||||
grep 'CONFIG_HPS_IOCSR_SCANCHAIN[0-9]\+_LENGTH' \
|
||||
${in_bsp_dir}/generated/iocsr_config_${soc}.h | tr -d "()"
|
||||
fix_newlines_in_macros \
|
||||
${in_bsp_dir}/generated/iocsr_config_${soc}.h |
|
||||
grep 'CONFIG_HPS_IOCSR_SCANCHAIN[0-9]\+_LENGTH' | tr -d "()"
|
||||
|
||||
echo ""
|
||||
|
||||
# Retrieve the scan chain config and zap the ad-hoc length encoding
|
||||
sed -n '/^const/ !b; :next {/^const/ s/(.*)//;p;n;b next}' \
|
||||
${in_bsp_dir}/generated/iocsr_config_${soc}.c
|
||||
fix_newlines_in_macros \
|
||||
${in_bsp_dir}/generated/iocsr_config_${soc}.c |
|
||||
sed -n '/^const/ !b; :next {/^const/ s/(.*)//;p;n;b next}'
|
||||
|
||||
cat << EOF
|
||||
|
||||
@ -69,8 +79,9 @@ process_pinmux_config() {
|
||||
EOF
|
||||
|
||||
# Retrieve the pinmux config and zap the ad-hoc length encoding
|
||||
sed -n '/^unsigned/ !b; :next {/^unsigned/ {s/\[.*\]/[]/;s/unsigned long/const u8/};p;n;b next}' \
|
||||
${in_bsp_dir}/generated/pinmux_config_${soc}.c
|
||||
fix_newlines_in_macros \
|
||||
${in_bsp_dir}/generated/pinmux_config_${soc}.c |
|
||||
sed -n '/^unsigned/ !b; :next {/^unsigned/ {s/\[.*\]/[]/;s/unsigned long/const u8/};p;n;b next}'
|
||||
|
||||
cat << EOF
|
||||
|
||||
@ -105,8 +116,9 @@ process_pll_config() {
|
||||
EOF
|
||||
|
||||
# Retrieve the pll config and zap parenthesis
|
||||
sed -n '/CONFIG_HPS/ !b; :next {/CONFIG_HPS/ s/[()]//g;/endif/ b;p;n;b next}' \
|
||||
${in_bsp_dir}/generated/pll_config.h
|
||||
fix_newlines_in_macros \
|
||||
${in_bsp_dir}/generated/pll_config.h |
|
||||
sed -n '/CONFIG_HPS/ !b; :next {/CONFIG_HPS/ s/[()]//g;/endif/ b;p;n;b next}'
|
||||
|
||||
cat << EOF
|
||||
|
||||
@ -149,32 +161,37 @@ EOF
|
||||
|
||||
echo "/* SDRAM configuration */"
|
||||
# Retrieve the sdram config, zap broken lines and zap parenthesis
|
||||
sed -n "/\\\\$/ {N;s/ \\\\\n/\t/};p" \
|
||||
fix_newlines_in_macros \
|
||||
${in_bsp_dir}/generated/sdram/sdram_config.h |
|
||||
sed -n "/\\\\$/ {N;s/ \\\\\n/\t/};p" |
|
||||
sed -n '/CONFIG_HPS/ !b; :next {/CONFIG_HPS/ s/[()]//g;/endif/ b;p;n;b next}' |
|
||||
sort -u | grep_sdram_config
|
||||
|
||||
echo ""
|
||||
echo "/* Sequencer auto configuration */"
|
||||
sed -n "/__RW_MGR/ {s/__//;s/ \+\([^ ]\+\)$/\t\1/p}" \
|
||||
fix_newlines_in_macros \
|
||||
${in_qts_dir}/hps_isw_handoff/*/sequencer_auto.h |
|
||||
sed -n "/__RW_MGR/ {s/__//;s/ \+\([^ ]\+\)$/\t\1/p}" |
|
||||
sort -u | grep_sdram_config
|
||||
|
||||
echo ""
|
||||
echo "/* Sequencer defines configuration */"
|
||||
sed -n "/^#define [^_]/ {s/__//;s/ \+\([^ ]\+\)$/\t\1/p}" \
|
||||
fix_newlines_in_macros \
|
||||
${in_qts_dir}/hps_isw_handoff/*/sequencer_defines.h |
|
||||
sed -n "/^#define [^_]/ {s/__//;s/ \+\([^ ]\+\)$/\t\1/p}" |
|
||||
sort -u | grep_sdram_config
|
||||
|
||||
echo ""
|
||||
echo "/* Sequencer ac_rom_init configuration */"
|
||||
sed -n '/^const.*\[/ !b; :next {/^const.*\[/ {N;s/\n//;s/alt_u32/u32/;s/\[.*\]/[]/};/endif/ b;p;n;b next}'\
|
||||
${in_qts_dir}/hps_isw_handoff/*/sequencer_auto_ac_init.c
|
||||
fix_newlines_in_macros \
|
||||
${in_qts_dir}/hps_isw_handoff/*/sequencer_auto_ac_init.c |
|
||||
sed -n '/^const.*\[/ !b; :next {/^const.*\[/ {N;s/\n//;s/alt_u32/u32/;s/\[.*\]/[]/};/endif/ b;p;n;b next}'
|
||||
|
||||
echo ""
|
||||
echo "/* Sequencer inst_rom_init configuration */"
|
||||
sed -n '/^const.*\[/ !b; :next {/^const.*\[/ {N;s/\n//;s/alt_u32/u32/;s/\[.*\]/[]/};/endif/ b;p;n;b next}'\
|
||||
${in_qts_dir}/hps_isw_handoff/*/sequencer_auto_inst_init.c
|
||||
fix_newlines_in_macros \
|
||||
${in_qts_dir}/hps_isw_handoff/*/sequencer_auto_inst_init.c |
|
||||
sed -n '/^const.*\[/ !b; :next {/^const.*\[/ {N;s/\n//;s/alt_u32/u32/;s/\[.*\]/[]/};/endif/ b;p;n;b next}'
|
||||
|
||||
cat << EOF
|
||||
|
||||
|
||||
@ -142,7 +142,7 @@ static int spl_board_load_image(struct spl_image_info *spl_image,
|
||||
|
||||
return 0;
|
||||
}
|
||||
SPL_LOAD_IMAGE_METHOD(0, BOOT_DEVICE_BOARD, spl_board_load_image);
|
||||
SPL_LOAD_IMAGE_METHOD("FEL", 0, BOOT_DEVICE_BOARD, spl_board_load_image);
|
||||
#endif
|
||||
|
||||
void s_init(void)
|
||||
@ -247,15 +247,6 @@ u32 spl_boot_device(void)
|
||||
return -1; /* Never reached */
|
||||
}
|
||||
|
||||
/*
|
||||
* Properly announce BOOT_DEVICE_BOARD as "FEL".
|
||||
* Overrides weak function from common/spl/spl.c
|
||||
*/
|
||||
void spl_board_announce_boot_device(void)
|
||||
{
|
||||
printf("FEL");
|
||||
}
|
||||
|
||||
/* No confirmation data available in SPL yet. Hardcode bootmode */
|
||||
u32 spl_boot_mode(const u32 boot_device)
|
||||
{
|
||||
|
||||
@ -12,11 +12,6 @@
|
||||
|
||||
#include "../soc-info.h"
|
||||
|
||||
void spl_board_announce_boot_device(void)
|
||||
{
|
||||
printf("eMMC");
|
||||
}
|
||||
|
||||
struct uniphier_romfunc_table {
|
||||
void *mmc_send_cmd;
|
||||
void *mmc_card_blockaddr;
|
||||
@ -127,4 +122,4 @@ static int spl_board_load_image(struct spl_image_info *spl_image,
|
||||
|
||||
return 0;
|
||||
}
|
||||
SPL_LOAD_IMAGE_METHOD(0, BOOT_DEVICE_BOARD, spl_board_load_image);
|
||||
SPL_LOAD_IMAGE_METHOD("eMMC", 0, BOOT_DEVICE_BOARD, spl_board_load_image);
|
||||
|
||||
@ -1,7 +1,7 @@
|
||||
/*
|
||||
* Copyright (C) 2016 Socionext Inc.
|
||||
*
|
||||
* based on commit a7a36122aa072fe1bb06e02b73b3634b7a6c555a of Diag
|
||||
* based on commit 5e1cb0f1caeabc6c99469dd997cb6b4f46834443 of Diag
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
@ -264,8 +264,8 @@ static int ddrphy_ip_dq_shift_val[DRAM_BOARD_NR][DRAM_CH_NR][32] = {
|
||||
static void ddrphy_select_lane(void __iomem *phy_base, unsigned int lane,
|
||||
unsigned int bit)
|
||||
{
|
||||
WARN_ON(lane >= (1 << PHY_LANE_SEL_LANE_WIDTH));
|
||||
WARN_ON(bit >= (1 << PHY_LANE_SEL_BIT_WIDTH));
|
||||
WARN_ON(lane >= 1 << PHY_LANE_SEL_LANE_WIDTH);
|
||||
WARN_ON(bit >= 1 << PHY_LANE_SEL_BIT_WIDTH);
|
||||
|
||||
writel((bit << PHY_LANE_SEL_BIT_SHIFT) |
|
||||
(lane << PHY_LANE_SEL_LANE_SHIFT),
|
||||
|
||||
@ -1,5 +1,7 @@
|
||||
/*
|
||||
* Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
|
||||
* Copyright (C) 2011-2015 Panasonic Corporation
|
||||
* Copyright (C) 2016 Socionext Inc.
|
||||
* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
@ -14,7 +16,7 @@
|
||||
|
||||
int memconf_init(const struct uniphier_board_data *bd)
|
||||
{
|
||||
u32 tmp = 0;
|
||||
u32 tmp;
|
||||
unsigned long size_per_word;
|
||||
|
||||
tmp = readl(SG_MEMCONF);
|
||||
|
||||
@ -45,7 +45,9 @@
|
||||
#include <nand.h>
|
||||
#include <errno.h>
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_ARCH_QEMU_E500
|
||||
#include <fsl_ddr.h>
|
||||
#endif
|
||||
#include "../../../../drivers/block/fsl_sata.h"
|
||||
#ifdef CONFIG_U_QE
|
||||
#include <fsl_qe.h>
|
||||
@ -947,6 +949,10 @@ int cpu_init_r(void)
|
||||
|
||||
#endif /* CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE */
|
||||
|
||||
#ifdef CONFIG_SYS_FSL_ERRATUM_A009942
|
||||
erratum_a009942_check_cpo();
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_FMAN_ENET
|
||||
fman_enet_init();
|
||||
#endif
|
||||
|
||||
@ -512,7 +512,6 @@
|
||||
#define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
|
||||
#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
|
||||
#define CONFIG_SYS_FSL_ERRATUM_A004468
|
||||
#define CONFIG_SYS_FSL_ERRATUM_A_004934
|
||||
#define CONFIG_SYS_FSL_ERRATUM_A005871
|
||||
#define CONFIG_SYS_FSL_ERRATUM_A006379
|
||||
#define CONFIG_SYS_FSL_ERRATUM_A007186
|
||||
@ -549,7 +548,6 @@
|
||||
#define CONFIG_SYS_FSL_TBCLK_DIV 16
|
||||
#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
|
||||
#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
|
||||
#define CONFIG_SYS_FSL_ERRATUM_A_004934
|
||||
#define CONFIG_SYS_FSL_ERRATUM_A005871
|
||||
#define CONFIG_SYS_FSL_ERRATUM_A006379
|
||||
#define CONFIG_SYS_FSL_ERRATUM_A007186
|
||||
|
||||
@ -25,19 +25,6 @@ u32 spl_boot_device(void)
|
||||
return BOOT_DEVICE_BOARD;
|
||||
}
|
||||
|
||||
void spl_board_announce_boot_device(void)
|
||||
{
|
||||
char fname[256];
|
||||
int ret;
|
||||
|
||||
ret = os_find_u_boot(fname, sizeof(fname));
|
||||
if (ret) {
|
||||
printf("(%s not found, error %d)\n", fname, ret);
|
||||
return;
|
||||
}
|
||||
printf("%s\n", fname);
|
||||
}
|
||||
|
||||
static int spl_board_load_image(struct spl_image_info *spl_image,
|
||||
struct spl_boot_device *bootdev)
|
||||
{
|
||||
@ -45,13 +32,15 @@ static int spl_board_load_image(struct spl_image_info *spl_image,
|
||||
int ret;
|
||||
|
||||
ret = os_find_u_boot(fname, sizeof(fname));
|
||||
if (ret)
|
||||
if (ret) {
|
||||
printf("(%s not found, error %d)\n", fname, ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
/* Hopefully this will not return */
|
||||
return os_spl_to_uboot(fname);
|
||||
}
|
||||
SPL_LOAD_IMAGE_METHOD(0, BOOT_DEVICE_BOARD, spl_board_load_image);
|
||||
SPL_LOAD_IMAGE_METHOD("sandbox", 0, BOOT_DEVICE_BOARD, spl_board_load_image);
|
||||
|
||||
void spl_board_init(void)
|
||||
{
|
||||
|
||||
7
board/Marvell/mvebu_armada-8k/MAINTAINERS
Normal file
7
board/Marvell/mvebu_armada-8k/MAINTAINERS
Normal file
@ -0,0 +1,7 @@
|
||||
MVEBU_ARMADA_8K BOARD
|
||||
M: Stefan Roese <sr@denx.de>
|
||||
S: Maintained
|
||||
F: board/Marvell/mvebu_armada-8k/
|
||||
F: include/configs/mvebu_armada-8k.h
|
||||
F: configs/mvebu_db-88f7040_defconfig
|
||||
F: configs/mvebu_db-88f8040_defconfig
|
||||
162
board/Marvell/mvebu_armada-8k/board.c
Normal file
162
board/Marvell/mvebu_armada-8k/board.c
Normal file
@ -0,0 +1,162 @@
|
||||
/*
|
||||
* Copyright (C) 2016 Stefan Roese <sr@denx.de>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <dm.h>
|
||||
#include <i2c.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/arch/cpu.h>
|
||||
#include <asm/arch/soc.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
/*
|
||||
* Information specific to the DB-88F7040 eval board. We strive to use
|
||||
* DT for such platform specfic configurations. At some point, this
|
||||
* might be removed here and implemented via DT.
|
||||
*/
|
||||
/* IO expander I2C device */
|
||||
#define I2C_IO_EXP_ADDR 0x21
|
||||
#define I2C_IO_CFG_REG_0 0x6
|
||||
#define I2C_IO_DATA_OUT_REG_0 0x2
|
||||
/* VBus enable */
|
||||
#define I2C_IO_REG_0_USB_H0_OFF 0
|
||||
#define I2C_IO_REG_0_USB_H1_OFF 1
|
||||
#define I2C_IO_REG_VBUS ((1 << I2C_IO_REG_0_USB_H0_OFF) | \
|
||||
(1 << I2C_IO_REG_0_USB_H1_OFF))
|
||||
/* Current limit */
|
||||
#define I2C_IO_REG_0_USB_H0_CL 4
|
||||
#define I2C_IO_REG_0_USB_H1_CL 5
|
||||
#define I2C_IO_REG_CL ((1 << I2C_IO_REG_0_USB_H0_CL) | \
|
||||
(1 << I2C_IO_REG_0_USB_H1_CL))
|
||||
|
||||
static int usb_enabled = 0;
|
||||
|
||||
/* Board specific xHCI dis-/enable code */
|
||||
|
||||
/*
|
||||
* Set USB VBUS signals (via I2C IO expander/GPIO) as output and set
|
||||
* output value as disabled
|
||||
*
|
||||
* Set USB Current Limit signals (via I2C IO expander/GPIO) as output
|
||||
* and set output value as enabled
|
||||
*/
|
||||
int board_xhci_config(void)
|
||||
{
|
||||
struct udevice *dev;
|
||||
int ret;
|
||||
u8 buf[8];
|
||||
|
||||
if (of_machine_is_compatible("marvell,armada7040-db")) {
|
||||
/* Configure IO exander PCA9555: 7bit address 0x21 */
|
||||
ret = i2c_get_chip_for_busnum(0, I2C_IO_EXP_ADDR, 1, &dev);
|
||||
if (ret) {
|
||||
printf("Cannot find PCA9555: %d\n", ret);
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* Read configuration (direction) and set VBUS pin as output
|
||||
* (reset pin = output)
|
||||
*/
|
||||
ret = dm_i2c_read(dev, I2C_IO_CFG_REG_0, buf, 1);
|
||||
if (ret) {
|
||||
printf("Failed to read IO expander value via I2C\n");
|
||||
return -EIO;
|
||||
}
|
||||
buf[0] &= ~I2C_IO_REG_VBUS;
|
||||
buf[0] &= ~I2C_IO_REG_CL;
|
||||
ret = dm_i2c_write(dev, I2C_IO_CFG_REG_0, buf, 1);
|
||||
if (ret) {
|
||||
printf("Failed to set IO expander via I2C\n");
|
||||
return -EIO;
|
||||
}
|
||||
|
||||
/* Read output value and configure it */
|
||||
ret = dm_i2c_read(dev, I2C_IO_DATA_OUT_REG_0, buf, 1);
|
||||
if (ret) {
|
||||
printf("Failed to read IO expander value via I2C\n");
|
||||
return -EIO;
|
||||
}
|
||||
buf[0] &= ~I2C_IO_REG_VBUS;
|
||||
buf[0] |= I2C_IO_REG_CL;
|
||||
ret = dm_i2c_write(dev, I2C_IO_DATA_OUT_REG_0, buf, 1);
|
||||
if (ret) {
|
||||
printf("Failed to set IO expander via I2C\n");
|
||||
return -EIO;
|
||||
}
|
||||
|
||||
mdelay(500); /* required delay to let output value settle */
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_xhci_enable(void)
|
||||
{
|
||||
struct udevice *dev;
|
||||
int ret;
|
||||
u8 buf[8];
|
||||
|
||||
if (of_machine_is_compatible("marvell,armada7040-db")) {
|
||||
/*
|
||||
* This function enables all USB ports simultaniously,
|
||||
* it only needs to get called once
|
||||
*/
|
||||
if (usb_enabled)
|
||||
return 0;
|
||||
|
||||
/* Configure IO exander PCA9555: 7bit address 0x21 */
|
||||
ret = i2c_get_chip_for_busnum(0, I2C_IO_EXP_ADDR, 1, &dev);
|
||||
if (ret) {
|
||||
printf("Cannot find PCA9555: %d\n", ret);
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Read VBUS output value */
|
||||
ret = dm_i2c_read(dev, I2C_IO_DATA_OUT_REG_0, buf, 1);
|
||||
if (ret) {
|
||||
printf("Failed to read IO expander value via I2C\n");
|
||||
return -EIO;
|
||||
}
|
||||
|
||||
/* Enable VBUS power: Set output value of VBUS pin as enabled */
|
||||
buf[0] |= I2C_IO_REG_VBUS;
|
||||
ret = dm_i2c_write(dev, I2C_IO_DATA_OUT_REG_0, buf, 1);
|
||||
if (ret) {
|
||||
printf("Failed to set IO expander via I2C\n");
|
||||
return -EIO;
|
||||
}
|
||||
|
||||
mdelay(500); /* required delay to let output value settle */
|
||||
usb_enabled = 1;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_early_init_f(void)
|
||||
{
|
||||
/* Nothing to do (yet), perhaps later some pin-muxing etc */
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_init(void)
|
||||
{
|
||||
/* adress of boot parameters */
|
||||
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_late_init(void)
|
||||
{
|
||||
/* Pre-configure the USB ports (overcurrent, VBus) */
|
||||
board_xhci_config();
|
||||
|
||||
return 0;
|
||||
}
|
||||
@ -1,6 +0,0 @@
|
||||
MVEBU_DB_88F7040 BOARD
|
||||
M: Stefan Roese <sr@denx.de>
|
||||
S: Maintained
|
||||
F: board/Marvell/mvebu_db-88f7040/
|
||||
F: include/configs/mvebu_db-88f7040.h
|
||||
F: configs/mvebu_db-88f7040_defconfig
|
||||
@ -1,152 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) 2016 Stefan Roese <sr@denx.de>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <i2c.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/arch/cpu.h>
|
||||
#include <asm/arch/soc.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
/* IO expander I2C device */
|
||||
#define I2C_IO_EXP_ADDR 0x21
|
||||
#define I2C_IO_CFG_REG_0 0x6
|
||||
#define I2C_IO_DATA_OUT_REG_0 0x2
|
||||
/* VBus enable */
|
||||
#define I2C_IO_REG_0_USB_H0_OFF 0
|
||||
#define I2C_IO_REG_0_USB_H1_OFF 1
|
||||
#define I2C_IO_REG_VBUS ((1 << I2C_IO_REG_0_USB_H0_OFF) | \
|
||||
(1 << I2C_IO_REG_0_USB_H1_OFF))
|
||||
/* Current limit */
|
||||
#define I2C_IO_REG_0_USB_H0_CL 4
|
||||
#define I2C_IO_REG_0_USB_H1_CL 5
|
||||
#define I2C_IO_REG_CL ((1 << I2C_IO_REG_0_USB_H0_CL) | \
|
||||
(1 << I2C_IO_REG_0_USB_H1_CL))
|
||||
|
||||
static int usb_enabled = 0;
|
||||
|
||||
/* Board specific xHCI dis-/enable code */
|
||||
|
||||
/*
|
||||
* Set USB VBUS signals (via I2C IO expander/GPIO) as output and set
|
||||
* output value as disabled
|
||||
*
|
||||
* Set USB Current Limit signals (via I2C IO expander/GPIO) as output
|
||||
* and set output value as enabled
|
||||
*/
|
||||
int board_xhci_config(void)
|
||||
{
|
||||
struct udevice *dev;
|
||||
int ret;
|
||||
u8 buf[8];
|
||||
|
||||
/* Configure IO exander PCA9555: 7bit address 0x21 */
|
||||
ret = i2c_get_chip_for_busnum(0, I2C_IO_EXP_ADDR, 1, &dev);
|
||||
if (ret) {
|
||||
printf("Cannot find PCA9555: %d\n", ret);
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* Read configuration (direction) and set VBUS pin as output
|
||||
* (reset pin = output)
|
||||
*/
|
||||
ret = dm_i2c_read(dev, I2C_IO_CFG_REG_0, buf, 1);
|
||||
if (ret) {
|
||||
printf("Failed to read IO expander value via I2C\n");
|
||||
return -EIO;
|
||||
}
|
||||
buf[0] &= ~I2C_IO_REG_VBUS;
|
||||
buf[0] &= ~I2C_IO_REG_CL;
|
||||
ret = dm_i2c_write(dev, I2C_IO_CFG_REG_0, buf, 1);
|
||||
if (ret) {
|
||||
printf("Failed to set IO expander via I2C\n");
|
||||
return -EIO;
|
||||
}
|
||||
|
||||
/* Read output value and configure it */
|
||||
ret = dm_i2c_read(dev, I2C_IO_DATA_OUT_REG_0, buf, 1);
|
||||
if (ret) {
|
||||
printf("Failed to read IO expander value via I2C\n");
|
||||
return -EIO;
|
||||
}
|
||||
buf[0] &= ~I2C_IO_REG_VBUS;
|
||||
buf[0] |= I2C_IO_REG_CL;
|
||||
ret = dm_i2c_write(dev, I2C_IO_DATA_OUT_REG_0, buf, 1);
|
||||
if (ret) {
|
||||
printf("Failed to set IO expander via I2C\n");
|
||||
return -EIO;
|
||||
}
|
||||
|
||||
mdelay(500); /* required delay to let output value settle */
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_xhci_enable(void)
|
||||
{
|
||||
struct udevice *dev;
|
||||
int ret;
|
||||
u8 buf[8];
|
||||
|
||||
/*
|
||||
* This function enables all USB ports simultaniously,
|
||||
* it only needs to get called once
|
||||
*/
|
||||
if (usb_enabled)
|
||||
return 0;
|
||||
|
||||
/* Configure IO exander PCA9555: 7bit address 0x21 */
|
||||
ret = i2c_get_chip_for_busnum(0, I2C_IO_EXP_ADDR, 1, &dev);
|
||||
if (ret) {
|
||||
printf("Cannot find PCA9555: %d\n", ret);
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Read VBUS output value */
|
||||
ret = dm_i2c_read(dev, I2C_IO_DATA_OUT_REG_0, buf, 1);
|
||||
if (ret) {
|
||||
printf("Failed to read IO expander value via I2C\n");
|
||||
return -EIO;
|
||||
}
|
||||
|
||||
/* Enable VBUS power: Set output value of VBUS pin as enabled */
|
||||
buf[0] |= I2C_IO_REG_VBUS;
|
||||
ret = dm_i2c_write(dev, I2C_IO_DATA_OUT_REG_0, buf, 1);
|
||||
if (ret) {
|
||||
printf("Failed to set IO expander via I2C\n");
|
||||
return -EIO;
|
||||
}
|
||||
|
||||
mdelay(500); /* required delay to let output value settle */
|
||||
usb_enabled = 1;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_early_init_f(void)
|
||||
{
|
||||
/* Nothing to do (yet), perhaps later some pin-muxing etc */
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_init(void)
|
||||
{
|
||||
/* adress of boot parameters */
|
||||
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_late_init(void)
|
||||
{
|
||||
/* Pre-configure the USB ports (overcurrent, VBus) */
|
||||
board_xhci_config();
|
||||
|
||||
return 0;
|
||||
}
|
||||
@ -1,5 +1,5 @@
|
||||
SOCFPGA BOARD
|
||||
M: Dinh Nguyen <dinguyen@opensource.altera.com>
|
||||
M: Dinh Nguyen <dinguyen@kernel.org>
|
||||
M: Chin-Liang See <clsee@altera.com>
|
||||
S: Maintained
|
||||
F: board/altera/arria5-socdk/
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
SOCFPGA BOARD
|
||||
M: Dinh Nguyen <dinguyen@opensource.altera.com>
|
||||
M: Dinh Nguyen <dinguyen@kernel.org>
|
||||
M: Chin-Liang See <clsee@altera.com>
|
||||
S: Maintained
|
||||
F: board/altera/cyclone5-socdk/
|
||||
|
||||
@ -22,7 +22,7 @@
|
||||
#include <spl.h>
|
||||
#include <fsl_devdis.h>
|
||||
#include <fsl_validate.h>
|
||||
|
||||
#include <fsl_ddr.h>
|
||||
#include "../common/sleep.h"
|
||||
#include "../common/qixis.h"
|
||||
#include "ls1021aqds_qixis.h"
|
||||
@ -433,7 +433,9 @@ int board_init(void)
|
||||
#ifdef CONFIG_SYS_FSL_ERRATUM_A010315
|
||||
erratum_a010315();
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SYS_FSL_ERRATUM_A009942
|
||||
erratum_a009942_check_cpo();
|
||||
#endif
|
||||
major = get_soc_major_rev();
|
||||
if (major == SOC_MAJOR_VER_1_0) {
|
||||
/* Set CCI-400 control override register to
|
||||
|
||||
@ -3,4 +3,7 @@ M: Paul Burton <paul.burton@imgtec.com>
|
||||
S: Maintained
|
||||
F: board/imgtec/boston/
|
||||
F: include/configs/boston.h
|
||||
F: configs/boston_defconfig
|
||||
F: configs/boston32r2_defconfig
|
||||
F: configs/boston32r2el_defconfig
|
||||
F: configs/boston64r2_defconfig
|
||||
F: configs/boston64r2el_defconfig
|
||||
|
||||
@ -3,5 +3,7 @@ M: Paul Burton <paul.burton@imgtec.com>
|
||||
S: Maintained
|
||||
F: board/imgtec/malta/
|
||||
F: include/configs/malta.h
|
||||
F: configs/malta64_defconfig
|
||||
F: configs/malta64el_defconfig
|
||||
F: configs/malta_defconfig
|
||||
F: configs/maltael_defconfig
|
||||
|
||||
@ -1,6 +1,6 @@
|
||||
CALIMAIN BOARD
|
||||
M: Manfred Rudigier <manfred.rudigier@omicron.at>
|
||||
M: Christian Riesch <christian.riesch@omicron.at>
|
||||
M: Manfred Rudigier <manfred.rudigier@omicronenergy.com>
|
||||
M: Christoph Rüdisser <christoph.ruedisser@omicronenergy.com>
|
||||
S: Maintained
|
||||
F: board/omicron/calimain/
|
||||
F: include/configs/calimain.h
|
||||
|
||||
@ -101,6 +101,7 @@ void set_board_info(void)
|
||||
#ifdef CONFIG_LCD_MENU
|
||||
static int power_key_pressed(u32 reg)
|
||||
{
|
||||
#ifndef CONFIG_DM_I2C /* TODO(maintainer): Convert to driver model */
|
||||
struct pmic *pmic;
|
||||
u32 status;
|
||||
u32 mask;
|
||||
@ -123,6 +124,9 @@ static int power_key_pressed(u32 reg)
|
||||
return 0;
|
||||
|
||||
return !!(status & mask);
|
||||
#else
|
||||
return 0;
|
||||
#endif
|
||||
}
|
||||
|
||||
static int key_pressed(int key)
|
||||
|
||||
@ -45,11 +45,15 @@ void i2c_init_board(void)
|
||||
|
||||
int power_init_board(void)
|
||||
{
|
||||
#ifndef CONFIG_DM_I2C /* TODO(maintainer): Convert to driver model */
|
||||
/*
|
||||
* For PMIC the I2C bus is named as I2C5, but it is connected
|
||||
* to logical I2C adapter 0
|
||||
*/
|
||||
return pmic_init(I2C_0);
|
||||
#else
|
||||
return 0;
|
||||
#endif
|
||||
}
|
||||
|
||||
int dram_init(void)
|
||||
@ -142,6 +146,7 @@ int board_mmc_init(bd_t *bis)
|
||||
#ifdef CONFIG_USB_GADGET
|
||||
static int s5pc1xx_phy_control(int on)
|
||||
{
|
||||
#ifndef CONFIG_DM_I2C /* TODO(maintainer): Convert to driver model */
|
||||
int ret;
|
||||
static int status;
|
||||
struct pmic *p = pmic_get("MAX8998_PMIC");
|
||||
@ -173,7 +178,7 @@ static int s5pc1xx_phy_control(int on)
|
||||
status = 0;
|
||||
}
|
||||
udelay(10000);
|
||||
|
||||
#endif
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
@ -53,6 +53,7 @@ int exynos_init(void)
|
||||
|
||||
void i2c_init_board(void)
|
||||
{
|
||||
#ifndef CONFIG_DM_I2C /* TODO(maintainer): Convert to driver model */
|
||||
int err;
|
||||
|
||||
/* I2C_5 -> PMIC */
|
||||
@ -67,8 +68,10 @@ void i2c_init_board(void)
|
||||
gpio_request(EXYNOS4_GPIO_Y41, "i2c_data");
|
||||
gpio_direction_output(EXYNOS4_GPIO_Y40, 1);
|
||||
gpio_direction_output(EXYNOS4_GPIO_Y41, 1);
|
||||
#endif
|
||||
}
|
||||
|
||||
#ifndef CONFIG_DM_I2C /* TODO(maintainer): Convert to driver model */
|
||||
static void trats_low_power_mode(void)
|
||||
{
|
||||
struct exynos4_clock *clk =
|
||||
@ -273,11 +276,14 @@ static int pmic_init_max8997(void)
|
||||
puts("MAX8997 PMIC setting error!\n");
|
||||
return -1;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
int exynos_power_init(void)
|
||||
{
|
||||
#ifndef CONFIG_DM_I2C /* TODO(maintainer): Convert to driver model */
|
||||
int chrg, ret;
|
||||
struct power_battery *pb;
|
||||
struct pmic *p_fg, *p_chrg, *p_muic, *p_bat;
|
||||
@ -341,6 +347,7 @@ int exynos_power_init(void)
|
||||
|
||||
if (pb->bat->state == CHARGE && chrg == CHARGER_USB)
|
||||
puts("CHARGE Battery !\n");
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
@ -384,6 +391,7 @@ static void check_hw_revision(void)
|
||||
#ifdef CONFIG_USB_GADGET
|
||||
static int s5pc210_phy_control(int on)
|
||||
{
|
||||
#ifndef CONFIG_DM_I2C /* TODO(maintainer): Convert to driver model */
|
||||
int ret = 0;
|
||||
u32 val = 0;
|
||||
struct pmic *p = pmic_get("MAX8997_PMIC");
|
||||
@ -415,6 +423,7 @@ static int s5pc210_phy_control(int on)
|
||||
puts("MAX8997 LDO setting error!\n");
|
||||
return -1;
|
||||
}
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
@ -435,11 +444,16 @@ int board_usb_init(int index, enum usb_init_type init)
|
||||
|
||||
int g_dnl_board_usb_cable_connected(void)
|
||||
{
|
||||
#ifndef CONFIG_DM_I2C /* TODO(maintainer): Convert to driver model */
|
||||
struct pmic *muic = pmic_get("MAX8997_MUIC");
|
||||
if (!muic)
|
||||
return 0;
|
||||
|
||||
return !!muic->chrg->chrg_type(muic);
|
||||
#else
|
||||
return false;
|
||||
#endif
|
||||
|
||||
}
|
||||
#endif
|
||||
|
||||
@ -552,6 +566,7 @@ void exynos_reset_lcd(void)
|
||||
|
||||
int lcd_power(void)
|
||||
{
|
||||
#ifndef CONFIG_DM_I2C /* TODO(maintainer): Convert to driver model */
|
||||
int ret = 0;
|
||||
struct pmic *p = pmic_get("MAX8997_PMIC");
|
||||
if (!p)
|
||||
@ -569,12 +584,13 @@ int lcd_power(void)
|
||||
puts("MAX8997 LDO setting error!\n");
|
||||
return -1;
|
||||
}
|
||||
|
||||
#endif
|
||||
return 0;
|
||||
}
|
||||
|
||||
int mipi_power(void)
|
||||
{
|
||||
#ifndef CONFIG_DM_I2C /* TODO(maintainer): Convert to driver model */
|
||||
int ret = 0;
|
||||
struct pmic *p = pmic_get("MAX8997_PMIC");
|
||||
if (!p)
|
||||
@ -592,7 +608,7 @@ int mipi_power(void)
|
||||
puts("MAX8997 LDO setting error!\n");
|
||||
return -1;
|
||||
}
|
||||
|
||||
#endif
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
@ -151,8 +151,6 @@ int exynos_early_init_f(void)
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int pmic_init_max77686(void);
|
||||
|
||||
int exynos_init(void)
|
||||
{
|
||||
struct exynos4_power *pwr =
|
||||
@ -176,6 +174,7 @@ int exynos_init(void)
|
||||
|
||||
int exynos_power_init(void)
|
||||
{
|
||||
#ifndef CONFIG_DM_I2C /* TODO(maintainer): Convert to driver model */
|
||||
int chrg;
|
||||
struct power_battery *pb;
|
||||
struct pmic *p_chrg, *p_muic, *p_fg, *p_bat;
|
||||
@ -236,13 +235,14 @@ int exynos_power_init(void)
|
||||
|
||||
if (pb->bat->state == CHARGE && chrg == CHARGER_USB)
|
||||
puts("CHARGE Battery !\n");
|
||||
|
||||
#endif
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_USB_GADGET
|
||||
static int s5pc210_phy_control(int on)
|
||||
{
|
||||
#ifndef CONFIG_DM_I2C /* TODO(maintainer): Convert to driver model */
|
||||
int ret = 0;
|
||||
unsigned int val;
|
||||
struct pmic *p, *p_pmic, *p_muic;
|
||||
@ -299,7 +299,7 @@ static int s5pc210_phy_control(int on)
|
||||
|
||||
if (ret)
|
||||
return -1;
|
||||
|
||||
#endif
|
||||
return 0;
|
||||
}
|
||||
|
||||
@ -319,14 +319,19 @@ int board_usb_init(int index, enum usb_init_type init)
|
||||
|
||||
int g_dnl_board_usb_cable_connected(void)
|
||||
{
|
||||
#ifndef CONFIG_DM_I2C /* TODO(maintainer): Convert to driver model */
|
||||
struct pmic *muic = pmic_get("MAX77693_MUIC");
|
||||
if (!muic)
|
||||
return 0;
|
||||
|
||||
return !!muic->chrg->chrg_type(muic);
|
||||
#else
|
||||
return false;
|
||||
#endif
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_DM_I2C /* TODO(maintainer): Convert to driver model */
|
||||
static int pmic_init_max77686(void)
|
||||
{
|
||||
struct pmic *p = pmic_get("MAX77686_PMIC");
|
||||
@ -379,6 +384,7 @@ static int pmic_init_max77686(void)
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
/*
|
||||
* LCD
|
||||
@ -387,18 +393,21 @@ static int pmic_init_max77686(void)
|
||||
#ifdef CONFIG_LCD
|
||||
int mipi_power(void)
|
||||
{
|
||||
#ifndef CONFIG_DM_I2C /* TODO(maintainer): Convert to driver model */
|
||||
struct pmic *p = pmic_get("MAX77686_PMIC");
|
||||
|
||||
/* LDO8 VMIPI_1.0V_AP */
|
||||
max77686_set_ldo_mode(p, 8, OPMODE_ON);
|
||||
/* LDO10 VMIPI_1.8V_AP */
|
||||
max77686_set_ldo_mode(p, 10, OPMODE_ON);
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void exynos_lcd_power_on(void)
|
||||
{
|
||||
#ifndef CONFIG_DM_I2C /* TODO(maintainer): Convert to driver model */
|
||||
struct pmic *p = pmic_get("MAX77686_PMIC");
|
||||
|
||||
/* LCD_2.2V_EN: GPC0[1] */
|
||||
@ -410,6 +419,7 @@ void exynos_lcd_power_on(void)
|
||||
pmic_probe(p);
|
||||
max77686_set_ldo_voltage(p, 25, 3100000);
|
||||
max77686_set_ldo_mode(p, 25, OPMODE_LPM);
|
||||
#endif
|
||||
}
|
||||
|
||||
void exynos_reset_lcd(void)
|
||||
|
||||
@ -38,10 +38,9 @@ static int get_hwrev(void)
|
||||
return board_rev & 0xFF;
|
||||
}
|
||||
|
||||
static void init_pmic_lcd(void);
|
||||
|
||||
int exynos_power_init(void)
|
||||
{
|
||||
#ifndef CONFIG_DM_I2C /* TODO(maintainer): Convert to driver model */
|
||||
int ret;
|
||||
|
||||
/*
|
||||
@ -53,7 +52,7 @@ int exynos_power_init(void)
|
||||
return ret;
|
||||
|
||||
init_pmic_lcd();
|
||||
|
||||
#endif
|
||||
return 0;
|
||||
}
|
||||
|
||||
@ -84,6 +83,7 @@ static unsigned short get_adc_value(int channel)
|
||||
|
||||
static int adc_power_control(int on)
|
||||
{
|
||||
#ifndef CONFIG_DM_I2C /* TODO(maintainer): Convert to driver model */
|
||||
int ret;
|
||||
struct pmic *p = pmic_get("MAX8998_PMIC");
|
||||
if (!p)
|
||||
@ -97,6 +97,9 @@ static int adc_power_control(int on)
|
||||
MAX8998_LDO4, !!on);
|
||||
|
||||
return ret;
|
||||
#else
|
||||
return 0;
|
||||
#endif
|
||||
}
|
||||
|
||||
static unsigned int get_hw_revision(void)
|
||||
@ -144,6 +147,7 @@ static void check_hw_revision(void)
|
||||
#ifdef CONFIG_USB_GADGET
|
||||
static int s5pc210_phy_control(int on)
|
||||
{
|
||||
#ifndef CONFIG_DM_I2C /* TODO(maintainer): Convert to driver model */
|
||||
int ret = 0;
|
||||
struct pmic *p = pmic_get("MAX8998_PMIC");
|
||||
if (!p)
|
||||
@ -175,7 +179,7 @@ static int s5pc210_phy_control(int on)
|
||||
puts("MAX8998 LDO setting error!\n");
|
||||
return -1;
|
||||
}
|
||||
|
||||
#endif
|
||||
return 0;
|
||||
}
|
||||
|
||||
@ -201,6 +205,7 @@ int exynos_early_init_f(void)
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifndef CONFIG_DM_I2C /* TODO(maintainer): Convert to driver model */
|
||||
static void init_pmic_lcd(void)
|
||||
{
|
||||
unsigned char val;
|
||||
@ -248,6 +253,7 @@ static void init_pmic_lcd(void)
|
||||
if (ret)
|
||||
puts("LCD pmic initialisation error!\n");
|
||||
}
|
||||
#endif
|
||||
|
||||
void exynos_cfg_lcd_gpio(void)
|
||||
{
|
||||
@ -304,6 +310,7 @@ void exynos_reset_lcd(void)
|
||||
|
||||
void exynos_lcd_power_on(void)
|
||||
{
|
||||
#ifndef CONFIG_DM_I2C /* TODO(maintainer): Convert to driver model */
|
||||
struct pmic *p = pmic_get("MAX8998_PMIC");
|
||||
|
||||
if (!p)
|
||||
@ -314,6 +321,7 @@ void exynos_lcd_power_on(void)
|
||||
|
||||
pmic_set_output(p, MAX8998_REG_ONOFF3, MAX8998_LDO17, LDO_ON);
|
||||
pmic_set_output(p, MAX8998_REG_ONOFF2, MAX8998_LDO7, LDO_ON);
|
||||
#endif
|
||||
}
|
||||
|
||||
void exynos_cfg_ldo(void)
|
||||
@ -328,8 +336,9 @@ void exynos_enable_ldo(unsigned int onoff)
|
||||
|
||||
int exynos_init(void)
|
||||
{
|
||||
#ifndef CONFIG_DM_I2C /* TODO(maintainer): Convert to driver model */
|
||||
char buf[16];
|
||||
|
||||
#endif
|
||||
gd->bd->bi_arch_number = MACH_TYPE_UNIVERSAL_C210;
|
||||
|
||||
switch (get_hwrev()) {
|
||||
@ -354,13 +363,14 @@ int exynos_init(void)
|
||||
break;
|
||||
}
|
||||
|
||||
#ifndef CONFIG_DM_I2C /* TODO(maintainer): Convert to driver model */
|
||||
/* Request soft I2C gpios */
|
||||
strcpy(buf, "soft_i2c_scl");
|
||||
gpio_request(CONFIG_SOFT_I2C_GPIO_SCL, buf);
|
||||
|
||||
strcpy(buf, "soft_i2c_sda");
|
||||
gpio_request(CONFIG_SOFT_I2C_GPIO_SDA, buf);
|
||||
|
||||
#endif
|
||||
check_hw_revision();
|
||||
printf("HW Revision:\t0x%x\n", board_rev);
|
||||
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
SOCFPGA ATLAS BOARD
|
||||
M: Dinh Nguyen <dinguyen@opensource.altera.com>
|
||||
M: Dinh Nguyen <dinguyen@kernel.org>
|
||||
S: Maintained
|
||||
F: include/configs/socfpga_de0_nano_soc.h
|
||||
F: configs/socfpga_de0_nano_soc_defconfig
|
||||
|
||||
5
board/terasic/de1-soc/MAINTAINERS
Normal file
5
board/terasic/de1-soc/MAINTAINERS
Normal file
@ -0,0 +1,5 @@
|
||||
DE1-SoC BOARD
|
||||
M: Anatolij Gustschin <agust@denx.de>
|
||||
S: Maintained
|
||||
F: include/configs/socfpga_de1_soc.h
|
||||
F: configs/socfpga_de1_soc_defconfig
|
||||
9
board/terasic/de1-soc/Makefile
Normal file
9
board/terasic/de1-soc/Makefile
Normal file
@ -0,0 +1,9 @@
|
||||
#
|
||||
# (C) Copyright 2001-2006
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
# (C) Copyright 2010, Thomas Chou <thomas@wytron.com.tw>
|
||||
#
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
|
||||
obj-y := socfpga.o
|
||||
660
board/terasic/de1-soc/qts/iocsr_config.h
Normal file
660
board/terasic/de1-soc/qts/iocsr_config.h
Normal file
@ -0,0 +1,660 @@
|
||||
/*
|
||||
* Altera SoCFPGA IOCSR configuration
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef __SOCFPGA_IOCSR_CONFIG_H__
|
||||
#define __SOCFPGA_IOCSR_CONFIG_H__
|
||||
|
||||
#define CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH 764
|
||||
#define CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH 1719
|
||||
#define CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH 955
|
||||
#define CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH 16766
|
||||
|
||||
const unsigned long iocsr_scan_chain0_table[] = {
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x0FF00000,
|
||||
0xC0000000,
|
||||
0x0000003F,
|
||||
0x00008000,
|
||||
0x00060180,
|
||||
0x18060000,
|
||||
0x18000000,
|
||||
0x00018060,
|
||||
0x00000000,
|
||||
0x00004000,
|
||||
0x000300C0,
|
||||
0x0C030000,
|
||||
0x0C000000,
|
||||
0x00000030,
|
||||
0x0000C030,
|
||||
0x00002000,
|
||||
0x00020000,
|
||||
0x06018000,
|
||||
0x06000000,
|
||||
0x00000018,
|
||||
0x00006018,
|
||||
0x00001000,
|
||||
};
|
||||
|
||||
const unsigned long iocsr_scan_chain1_table[] = {
|
||||
0x00100000,
|
||||
0x300C0000,
|
||||
0x300000C0,
|
||||
0x000000C0,
|
||||
0x000300C0,
|
||||
0x00008000,
|
||||
0x00060180,
|
||||
0x20000000,
|
||||
0x00000000,
|
||||
0x00000080,
|
||||
0x00020000,
|
||||
0x00004000,
|
||||
0x000300C0,
|
||||
0x10000000,
|
||||
0x0C000000,
|
||||
0x00000030,
|
||||
0x0000C030,
|
||||
0x00002000,
|
||||
0x06018060,
|
||||
0x06018000,
|
||||
0x01FE0000,
|
||||
0xF8000000,
|
||||
0x00000007,
|
||||
0x00001000,
|
||||
0x0000C030,
|
||||
0x0300C000,
|
||||
0x03000000,
|
||||
0x0000300C,
|
||||
0x0000300C,
|
||||
0x00000800,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x01800000,
|
||||
0x00000006,
|
||||
0x00002000,
|
||||
0x00000400,
|
||||
0x00000000,
|
||||
0x00C03000,
|
||||
0x00000003,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000200,
|
||||
0x00601806,
|
||||
0x00000000,
|
||||
0x80600000,
|
||||
0x80000601,
|
||||
0x00000601,
|
||||
0x00000100,
|
||||
0x00300C03,
|
||||
0xC0300C00,
|
||||
0xC0300000,
|
||||
0xC0000300,
|
||||
0x000C0300,
|
||||
0x00000080,
|
||||
};
|
||||
|
||||
const unsigned long iocsr_scan_chain2_table[] = {
|
||||
0x300C0300,
|
||||
0x00000000,
|
||||
0x0FF00000,
|
||||
0x00000000,
|
||||
0x000300C0,
|
||||
0x00008000,
|
||||
0x00080000,
|
||||
0x18060000,
|
||||
0x18000000,
|
||||
0x00018060,
|
||||
0x00020000,
|
||||
0x00004000,
|
||||
0x200300C0,
|
||||
0x10000000,
|
||||
0x00000000,
|
||||
0x00000040,
|
||||
0x00010000,
|
||||
0x00002000,
|
||||
0x10018060,
|
||||
0x06018000,
|
||||
0x06000000,
|
||||
0x00010018,
|
||||
0x00006018,
|
||||
0x00001000,
|
||||
0x0000C030,
|
||||
0x00000000,
|
||||
0x03000000,
|
||||
0x0000800C,
|
||||
0x00C0300C,
|
||||
0x00000800,
|
||||
};
|
||||
|
||||
const unsigned long iocsr_scan_chain3_table[] = {
|
||||
0x0C420D80,
|
||||
0x082000FF,
|
||||
0x0A804001,
|
||||
0x07900000,
|
||||
0x08020000,
|
||||
0x00100000,
|
||||
0x0A800000,
|
||||
0x07900000,
|
||||
0x08020000,
|
||||
0x00100000,
|
||||
0xC8800000,
|
||||
0x00003001,
|
||||
0x00C00722,
|
||||
0x00000000,
|
||||
0x00000021,
|
||||
0x82000004,
|
||||
0x05400000,
|
||||
0x03C80000,
|
||||
0x04010000,
|
||||
0x00080000,
|
||||
0x05400000,
|
||||
0x03C80000,
|
||||
0x05400000,
|
||||
0x03C80000,
|
||||
0xE4400000,
|
||||
0x00001800,
|
||||
0x00600391,
|
||||
0x800E4400,
|
||||
0x00000001,
|
||||
0x40000002,
|
||||
0x02A00000,
|
||||
0x01E40000,
|
||||
0x02A00000,
|
||||
0x01E40000,
|
||||
0x02A00000,
|
||||
0x01E40000,
|
||||
0x02A00000,
|
||||
0x01E40000,
|
||||
0x72200000,
|
||||
0x80000C00,
|
||||
0x003001C8,
|
||||
0xC0072200,
|
||||
0x1C880000,
|
||||
0x20000300,
|
||||
0x00040000,
|
||||
0x50670000,
|
||||
0x00000010,
|
||||
0x24590000,
|
||||
0x00001000,
|
||||
0xA0000034,
|
||||
0x0D000001,
|
||||
0x40680208,
|
||||
0x41034051,
|
||||
0x02081A00,
|
||||
0x802080D0,
|
||||
0x34010406,
|
||||
0x01A02490,
|
||||
0x080D0000,
|
||||
0x51406802,
|
||||
0x00410340,
|
||||
0xD000001A,
|
||||
0x06802080,
|
||||
0x10040000,
|
||||
0x00200000,
|
||||
0x10040000,
|
||||
0x00200000,
|
||||
0x15000000,
|
||||
0x0F200000,
|
||||
0x15000000,
|
||||
0x0F200000,
|
||||
0x01FE0000,
|
||||
0x00000000,
|
||||
0x01800E44,
|
||||
0x00391000,
|
||||
0x007F8006,
|
||||
0x00000000,
|
||||
0x0A800001,
|
||||
0x07900000,
|
||||
0x0A800000,
|
||||
0x07900000,
|
||||
0x0A800000,
|
||||
0x07900000,
|
||||
0x08020000,
|
||||
0x00100000,
|
||||
0xC8800000,
|
||||
0x00003001,
|
||||
0x00C00722,
|
||||
0x00000FF0,
|
||||
0x72200000,
|
||||
0x80000C00,
|
||||
0x05400000,
|
||||
0x02480000,
|
||||
0x04000000,
|
||||
0x00080000,
|
||||
0x05400000,
|
||||
0x03C80000,
|
||||
0x05400000,
|
||||
0x03C80000,
|
||||
0x6A1C0000,
|
||||
0x00001800,
|
||||
0x00600391,
|
||||
0x800E4400,
|
||||
0x1A870001,
|
||||
0x40000600,
|
||||
0x02A00040,
|
||||
0x01E40000,
|
||||
0x02A00000,
|
||||
0x01E40000,
|
||||
0x02A00000,
|
||||
0x01E40000,
|
||||
0x02A00000,
|
||||
0x01E40000,
|
||||
0x72200000,
|
||||
0x80000C00,
|
||||
0x003001C8,
|
||||
0xC0072200,
|
||||
0x1C880000,
|
||||
0x20000300,
|
||||
0x00040000,
|
||||
0x50670000,
|
||||
0x00000010,
|
||||
0x24590000,
|
||||
0x00001000,
|
||||
0xA0000034,
|
||||
0x0D000001,
|
||||
0x40680C30,
|
||||
0x49034010,
|
||||
0x12481A02,
|
||||
0x802080D0,
|
||||
0x34051406,
|
||||
0x01A00040,
|
||||
0x080D0002,
|
||||
0x51406802,
|
||||
0x02490340,
|
||||
0xD012481A,
|
||||
0x06802080,
|
||||
0x10040000,
|
||||
0x00200000,
|
||||
0x10040000,
|
||||
0x00200000,
|
||||
0x15000000,
|
||||
0x0F200000,
|
||||
0x15000000,
|
||||
0x0F200000,
|
||||
0x01FE0000,
|
||||
0x00000000,
|
||||
0x01800E44,
|
||||
0x00391000,
|
||||
0x007F8006,
|
||||
0x00000000,
|
||||
0x99300001,
|
||||
0x34343400,
|
||||
0xAA0D4000,
|
||||
0x01C3A800,
|
||||
0xAA0D4000,
|
||||
0x01C3A800,
|
||||
0xAA0D4000,
|
||||
0x01C3A800,
|
||||
0x00040100,
|
||||
0x00000800,
|
||||
0x00000000,
|
||||
0x00001208,
|
||||
0x00482000,
|
||||
0x01000000,
|
||||
0x00000000,
|
||||
0x00410482,
|
||||
0x0006A000,
|
||||
0x0001B400,
|
||||
0x00020000,
|
||||
0x00000400,
|
||||
0x0002A000,
|
||||
0x0001E400,
|
||||
0x5506A000,
|
||||
0x00E1D400,
|
||||
0x00000000,
|
||||
0xC880090C,
|
||||
0x00003001,
|
||||
0x90400000,
|
||||
0x00000000,
|
||||
0x2020C243,
|
||||
0x2A835000,
|
||||
0x0070EA00,
|
||||
0x2A835000,
|
||||
0x0070EA00,
|
||||
0x2A835000,
|
||||
0x0070EA00,
|
||||
0x00010040,
|
||||
0x00000200,
|
||||
0x00000000,
|
||||
0x00000482,
|
||||
0x00120800,
|
||||
0x00002000,
|
||||
0x80000000,
|
||||
0x00104120,
|
||||
0x00000200,
|
||||
0xAC0D5F80,
|
||||
0xFFFFFFFF,
|
||||
0x14F3690D,
|
||||
0x1A041414,
|
||||
0x00D00000,
|
||||
0x18864000,
|
||||
0x49247A06,
|
||||
0xE3CF23DA,
|
||||
0xF796591E,
|
||||
0x0344E388,
|
||||
0x821A0000,
|
||||
0x0000D000,
|
||||
0x01040680,
|
||||
0xD271C47A,
|
||||
0x1EE3CF23,
|
||||
0x88F79659,
|
||||
0x000344E3,
|
||||
0x00080200,
|
||||
0x00001000,
|
||||
0x00080200,
|
||||
0x00001000,
|
||||
0x000A8000,
|
||||
0x00075000,
|
||||
0x541A8000,
|
||||
0x03875001,
|
||||
0x10000000,
|
||||
0x00000000,
|
||||
0x0080C000,
|
||||
0x41000000,
|
||||
0x00003FC2,
|
||||
0x00820000,
|
||||
0xAA0D4000,
|
||||
0x01C3A800,
|
||||
0xAA0D4000,
|
||||
0x01C3A800,
|
||||
0xAA0D4000,
|
||||
0x01C3A800,
|
||||
0x00040100,
|
||||
0x00000800,
|
||||
0x00000000,
|
||||
0x00001208,
|
||||
0x00482000,
|
||||
0x00008000,
|
||||
0x00000000,
|
||||
0x00410482,
|
||||
0x0006A000,
|
||||
0x0001B400,
|
||||
0x00020000,
|
||||
0x00000400,
|
||||
0x00020080,
|
||||
0x00000400,
|
||||
0x5506A000,
|
||||
0x00E1D400,
|
||||
0x00000000,
|
||||
0x0000090C,
|
||||
0x00000010,
|
||||
0x90400000,
|
||||
0x00000000,
|
||||
0x2020C243,
|
||||
0x2A835000,
|
||||
0x0070EA00,
|
||||
0x2A835000,
|
||||
0x0070EA00,
|
||||
0x2A835000,
|
||||
0x0070EA00,
|
||||
0x00015000,
|
||||
0x0000F200,
|
||||
0x00000000,
|
||||
0x00000482,
|
||||
0x00120800,
|
||||
0x00600391,
|
||||
0x80000000,
|
||||
0x00104120,
|
||||
0x00000200,
|
||||
0xAC0D5F80,
|
||||
0xFFFFFFFF,
|
||||
0x14F3690D,
|
||||
0x1A041414,
|
||||
0x00D00000,
|
||||
0x18864000,
|
||||
0x49247A06,
|
||||
0xA3CF23DA,
|
||||
0xF796591E,
|
||||
0x0344E388,
|
||||
0x821A028A,
|
||||
0x0000D000,
|
||||
0x00000680,
|
||||
0xD271C47A,
|
||||
0x1EA2CB23,
|
||||
0x88F79A69,
|
||||
0x000344E3,
|
||||
0x00080200,
|
||||
0x00001000,
|
||||
0x00080200,
|
||||
0x00001000,
|
||||
0x000A8000,
|
||||
0x00075000,
|
||||
0x541A8000,
|
||||
0x03875001,
|
||||
0x10000000,
|
||||
0x00000000,
|
||||
0x0080C000,
|
||||
0x41000000,
|
||||
0x04000002,
|
||||
0x00820000,
|
||||
0xAA0D4000,
|
||||
0x01C3A800,
|
||||
0xAA0D4000,
|
||||
0x01C3A800,
|
||||
0xAA0D4000,
|
||||
0x01C3A800,
|
||||
0x00040100,
|
||||
0x00000800,
|
||||
0x00000000,
|
||||
0x00001208,
|
||||
0x00482000,
|
||||
0x00008000,
|
||||
0x00000000,
|
||||
0x00410482,
|
||||
0x0006A000,
|
||||
0x0001B400,
|
||||
0x00020000,
|
||||
0x00000400,
|
||||
0x0002A000,
|
||||
0x0001E400,
|
||||
0x5506A000,
|
||||
0x00E1D400,
|
||||
0x00000000,
|
||||
0xC880090C,
|
||||
0x00003001,
|
||||
0x90400000,
|
||||
0x00000000,
|
||||
0x2020C243,
|
||||
0x2A835000,
|
||||
0x0070EA00,
|
||||
0x2A835000,
|
||||
0x0070EA00,
|
||||
0x2A835000,
|
||||
0x0070EA00,
|
||||
0x00010040,
|
||||
0x00000200,
|
||||
0x00000000,
|
||||
0x00000482,
|
||||
0x00120800,
|
||||
0x00002000,
|
||||
0x80000000,
|
||||
0x00104120,
|
||||
0x00000200,
|
||||
0xAC0D5F80,
|
||||
0xFFFFFFFF,
|
||||
0x14F3690D,
|
||||
0x1A041414,
|
||||
0x00D00000,
|
||||
0x04864000,
|
||||
0x69A47A01,
|
||||
0x9228A3D6,
|
||||
0xF456591E,
|
||||
0x03549248,
|
||||
0x821A0000,
|
||||
0x0000D000,
|
||||
0x00000680,
|
||||
0xD669A47A,
|
||||
0x1EE3CF23,
|
||||
0x48F45659,
|
||||
0x00035492,
|
||||
0x00080200,
|
||||
0x00001000,
|
||||
0x00080200,
|
||||
0x00001000,
|
||||
0x000A8000,
|
||||
0x00075000,
|
||||
0x541A8000,
|
||||
0x03875001,
|
||||
0x10000000,
|
||||
0x00000000,
|
||||
0x0080C000,
|
||||
0x41000000,
|
||||
0x04000002,
|
||||
0x00820000,
|
||||
0xAA0D4000,
|
||||
0x01C3A800,
|
||||
0xAA0D4000,
|
||||
0x01C3A800,
|
||||
0xAA0D4000,
|
||||
0x01C3A800,
|
||||
0x00040100,
|
||||
0x00000800,
|
||||
0x00000000,
|
||||
0x00001208,
|
||||
0x00482000,
|
||||
0x00008000,
|
||||
0x00000000,
|
||||
0x00410482,
|
||||
0x0006A000,
|
||||
0x0001B400,
|
||||
0x00020000,
|
||||
0x00000400,
|
||||
0x00020080,
|
||||
0x00000400,
|
||||
0x5506A000,
|
||||
0x00E1D400,
|
||||
0x00000000,
|
||||
0x0000090C,
|
||||
0x00000010,
|
||||
0x90400000,
|
||||
0x00000000,
|
||||
0x2020C243,
|
||||
0x2A835000,
|
||||
0x0070EA00,
|
||||
0x2A835000,
|
||||
0x0070EA00,
|
||||
0x2A835000,
|
||||
0x0070EA00,
|
||||
0x00010040,
|
||||
0x00000200,
|
||||
0x00000000,
|
||||
0x00000482,
|
||||
0x00120800,
|
||||
0x00400000,
|
||||
0x80000000,
|
||||
0x00104120,
|
||||
0x00000200,
|
||||
0xAC0D5F80,
|
||||
0xFFFFFFFF,
|
||||
0x14F1690D,
|
||||
0x1A041414,
|
||||
0x00D00000,
|
||||
0x08864000,
|
||||
0x71C47A02,
|
||||
0xA2CB23D2,
|
||||
0xF796591E,
|
||||
0x0344A288,
|
||||
0x821A0000,
|
||||
0x0000D000,
|
||||
0x00000680,
|
||||
0xDA49247A,
|
||||
0x1EE3CF23,
|
||||
0x88F79659,
|
||||
0x000344E3,
|
||||
0x00080200,
|
||||
0x00001000,
|
||||
0x00080200,
|
||||
0x00001000,
|
||||
0x000A8000,
|
||||
0x00075000,
|
||||
0x541A8000,
|
||||
0x03875001,
|
||||
0x10000000,
|
||||
0x00000000,
|
||||
0x0080C000,
|
||||
0x41000000,
|
||||
0x04000002,
|
||||
0x00820000,
|
||||
0x00489800,
|
||||
0x801A1A1A,
|
||||
0x00000200,
|
||||
0x80000004,
|
||||
0x00000200,
|
||||
0x80000004,
|
||||
0x00000200,
|
||||
0x80000004,
|
||||
0x00000200,
|
||||
0x00000004,
|
||||
0x00040000,
|
||||
0x10000000,
|
||||
0x00000000,
|
||||
0x00000040,
|
||||
0x00010000,
|
||||
0x40002000,
|
||||
0x00000100,
|
||||
0x40000002,
|
||||
0x00000100,
|
||||
0x40000002,
|
||||
0x00000100,
|
||||
0x40000002,
|
||||
0x00000100,
|
||||
0x00000002,
|
||||
0x00020000,
|
||||
0x08000000,
|
||||
0x00000000,
|
||||
0x00000020,
|
||||
0x00008000,
|
||||
0x20001000,
|
||||
0x00000080,
|
||||
0x20000001,
|
||||
0x00000080,
|
||||
0x20000001,
|
||||
0x00000080,
|
||||
0x20000001,
|
||||
0x00000080,
|
||||
0x00000001,
|
||||
0x00010000,
|
||||
0x04000000,
|
||||
0x00FF0000,
|
||||
0x00000000,
|
||||
0x00004000,
|
||||
0x00000800,
|
||||
0xC0000001,
|
||||
0x00041419,
|
||||
0x40000000,
|
||||
0x04000816,
|
||||
0x000D0000,
|
||||
0x00006800,
|
||||
0x00000340,
|
||||
0xD000001A,
|
||||
0x06800000,
|
||||
0x00340000,
|
||||
0x0001A000,
|
||||
0x00000D00,
|
||||
0x40000068,
|
||||
0x1A000003,
|
||||
0x00D00000,
|
||||
0x00068000,
|
||||
0x00003400,
|
||||
0x000001A0,
|
||||
0x00000401,
|
||||
0x00000008,
|
||||
0x00000401,
|
||||
0x00000008,
|
||||
0x00000401,
|
||||
0x00000008,
|
||||
0x00000401,
|
||||
0x80000008,
|
||||
0x0000007F,
|
||||
0x20000000,
|
||||
0x00000000,
|
||||
0xE0000080,
|
||||
0x0000001F,
|
||||
0x00004000,
|
||||
};
|
||||
|
||||
|
||||
#endif /* __SOCFPGA_IOCSR_CONFIG_H__ */
|
||||
219
board/terasic/de1-soc/qts/pinmux_config.h
Normal file
219
board/terasic/de1-soc/qts/pinmux_config.h
Normal file
@ -0,0 +1,219 @@
|
||||
/*
|
||||
* Altera SoCFPGA PinMux configuration
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef __SOCFPGA_PINMUX_CONFIG_H__
|
||||
#define __SOCFPGA_PINMUX_CONFIG_H__
|
||||
|
||||
const u8 sys_mgr_init_table[] = {
|
||||
0, /* EMACIO0 */
|
||||
2, /* EMACIO1 */
|
||||
2, /* EMACIO2 */
|
||||
2, /* EMACIO3 */
|
||||
2, /* EMACIO4 */
|
||||
2, /* EMACIO5 */
|
||||
2, /* EMACIO6 */
|
||||
2, /* EMACIO7 */
|
||||
2, /* EMACIO8 */
|
||||
0, /* EMACIO9 */
|
||||
2, /* EMACIO10 */
|
||||
2, /* EMACIO11 */
|
||||
2, /* EMACIO12 */
|
||||
2, /* EMACIO13 */
|
||||
0, /* EMACIO14 */
|
||||
0, /* EMACIO15 */
|
||||
0, /* EMACIO16 */
|
||||
0, /* EMACIO17 */
|
||||
0, /* EMACIO18 */
|
||||
0, /* EMACIO19 */
|
||||
3, /* FLASHIO0 */
|
||||
0, /* FLASHIO1 */
|
||||
3, /* FLASHIO2 */
|
||||
3, /* FLASHIO3 */
|
||||
0, /* FLASHIO4 */
|
||||
0, /* FLASHIO5 */
|
||||
0, /* FLASHIO6 */
|
||||
0, /* FLASHIO7 */
|
||||
0, /* FLASHIO8 */
|
||||
3, /* FLASHIO9 */
|
||||
3, /* FLASHIO10 */
|
||||
3, /* FLASHIO11 */
|
||||
0, /* GENERALIO0 */
|
||||
1, /* GENERALIO1 */
|
||||
1, /* GENERALIO2 */
|
||||
1, /* GENERALIO3 */
|
||||
1, /* GENERALIO4 */
|
||||
0, /* GENERALIO5 */
|
||||
0, /* GENERALIO6 */
|
||||
1, /* GENERALIO7 */
|
||||
1, /* GENERALIO8 */
|
||||
0, /* GENERALIO9 */
|
||||
0, /* GENERALIO10 */
|
||||
0, /* GENERALIO11 */
|
||||
0, /* GENERALIO12 */
|
||||
0, /* GENERALIO13 */
|
||||
0, /* GENERALIO14 */
|
||||
1, /* GENERALIO15 */
|
||||
1, /* GENERALIO16 */
|
||||
1, /* GENERALIO17 */
|
||||
1, /* GENERALIO18 */
|
||||
0, /* GENERALIO19 */
|
||||
0, /* GENERALIO20 */
|
||||
0, /* GENERALIO21 */
|
||||
0, /* GENERALIO22 */
|
||||
0, /* GENERALIO23 */
|
||||
0, /* GENERALIO24 */
|
||||
0, /* GENERALIO25 */
|
||||
0, /* GENERALIO26 */
|
||||
0, /* GENERALIO27 */
|
||||
0, /* GENERALIO28 */
|
||||
0, /* GENERALIO29 */
|
||||
0, /* GENERALIO30 */
|
||||
0, /* GENERALIO31 */
|
||||
2, /* MIXED1IO0 */
|
||||
2, /* MIXED1IO1 */
|
||||
2, /* MIXED1IO2 */
|
||||
2, /* MIXED1IO3 */
|
||||
2, /* MIXED1IO4 */
|
||||
2, /* MIXED1IO5 */
|
||||
2, /* MIXED1IO6 */
|
||||
2, /* MIXED1IO7 */
|
||||
2, /* MIXED1IO8 */
|
||||
2, /* MIXED1IO9 */
|
||||
2, /* MIXED1IO10 */
|
||||
2, /* MIXED1IO11 */
|
||||
2, /* MIXED1IO12 */
|
||||
2, /* MIXED1IO13 */
|
||||
0, /* MIXED1IO14 */
|
||||
3, /* MIXED1IO15 */
|
||||
3, /* MIXED1IO16 */
|
||||
3, /* MIXED1IO17 */
|
||||
3, /* MIXED1IO18 */
|
||||
3, /* MIXED1IO19 */
|
||||
3, /* MIXED1IO20 */
|
||||
0, /* MIXED1IO21 */
|
||||
0, /* MIXED2IO0 */
|
||||
0, /* MIXED2IO1 */
|
||||
0, /* MIXED2IO2 */
|
||||
0, /* MIXED2IO3 */
|
||||
0, /* MIXED2IO4 */
|
||||
0, /* MIXED2IO5 */
|
||||
0, /* MIXED2IO6 */
|
||||
0, /* MIXED2IO7 */
|
||||
0, /* GPLINMUX48 */
|
||||
0, /* GPLINMUX49 */
|
||||
0, /* GPLINMUX50 */
|
||||
0, /* GPLINMUX51 */
|
||||
0, /* GPLINMUX52 */
|
||||
0, /* GPLINMUX53 */
|
||||
0, /* GPLINMUX54 */
|
||||
0, /* GPLINMUX55 */
|
||||
0, /* GPLINMUX56 */
|
||||
0, /* GPLINMUX57 */
|
||||
0, /* GPLINMUX58 */
|
||||
0, /* GPLINMUX59 */
|
||||
0, /* GPLINMUX60 */
|
||||
0, /* GPLINMUX61 */
|
||||
0, /* GPLINMUX62 */
|
||||
0, /* GPLINMUX63 */
|
||||
0, /* GPLINMUX64 */
|
||||
0, /* GPLINMUX65 */
|
||||
0, /* GPLINMUX66 */
|
||||
0, /* GPLINMUX67 */
|
||||
0, /* GPLINMUX68 */
|
||||
0, /* GPLINMUX69 */
|
||||
0, /* GPLINMUX70 */
|
||||
1, /* GPLMUX0 */
|
||||
1, /* GPLMUX1 */
|
||||
1, /* GPLMUX2 */
|
||||
1, /* GPLMUX3 */
|
||||
1, /* GPLMUX4 */
|
||||
1, /* GPLMUX5 */
|
||||
1, /* GPLMUX6 */
|
||||
1, /* GPLMUX7 */
|
||||
1, /* GPLMUX8 */
|
||||
1, /* GPLMUX9 */
|
||||
1, /* GPLMUX10 */
|
||||
1, /* GPLMUX11 */
|
||||
1, /* GPLMUX12 */
|
||||
1, /* GPLMUX13 */
|
||||
1, /* GPLMUX14 */
|
||||
1, /* GPLMUX15 */
|
||||
1, /* GPLMUX16 */
|
||||
1, /* GPLMUX17 */
|
||||
1, /* GPLMUX18 */
|
||||
1, /* GPLMUX19 */
|
||||
1, /* GPLMUX20 */
|
||||
1, /* GPLMUX21 */
|
||||
1, /* GPLMUX22 */
|
||||
1, /* GPLMUX23 */
|
||||
1, /* GPLMUX24 */
|
||||
1, /* GPLMUX25 */
|
||||
1, /* GPLMUX26 */
|
||||
1, /* GPLMUX27 */
|
||||
1, /* GPLMUX28 */
|
||||
1, /* GPLMUX29 */
|
||||
1, /* GPLMUX30 */
|
||||
1, /* GPLMUX31 */
|
||||
1, /* GPLMUX32 */
|
||||
1, /* GPLMUX33 */
|
||||
1, /* GPLMUX34 */
|
||||
1, /* GPLMUX35 */
|
||||
1, /* GPLMUX36 */
|
||||
1, /* GPLMUX37 */
|
||||
1, /* GPLMUX38 */
|
||||
1, /* GPLMUX39 */
|
||||
1, /* GPLMUX40 */
|
||||
1, /* GPLMUX41 */
|
||||
1, /* GPLMUX42 */
|
||||
1, /* GPLMUX43 */
|
||||
1, /* GPLMUX44 */
|
||||
1, /* GPLMUX45 */
|
||||
1, /* GPLMUX46 */
|
||||
1, /* GPLMUX47 */
|
||||
1, /* GPLMUX48 */
|
||||
1, /* GPLMUX49 */
|
||||
1, /* GPLMUX50 */
|
||||
1, /* GPLMUX51 */
|
||||
1, /* GPLMUX52 */
|
||||
1, /* GPLMUX53 */
|
||||
1, /* GPLMUX54 */
|
||||
1, /* GPLMUX55 */
|
||||
1, /* GPLMUX56 */
|
||||
1, /* GPLMUX57 */
|
||||
1, /* GPLMUX58 */
|
||||
1, /* GPLMUX59 */
|
||||
1, /* GPLMUX60 */
|
||||
1, /* GPLMUX61 */
|
||||
1, /* GPLMUX62 */
|
||||
1, /* GPLMUX63 */
|
||||
1, /* GPLMUX64 */
|
||||
1, /* GPLMUX65 */
|
||||
1, /* GPLMUX66 */
|
||||
1, /* GPLMUX67 */
|
||||
1, /* GPLMUX68 */
|
||||
1, /* GPLMUX69 */
|
||||
1, /* GPLMUX70 */
|
||||
0, /* NANDUSEFPGA */
|
||||
0, /* UART0USEFPGA */
|
||||
0, /* RGMII1USEFPGA */
|
||||
0, /* SPIS0USEFPGA */
|
||||
0, /* CAN0USEFPGA */
|
||||
0, /* I2C0USEFPGA */
|
||||
0, /* SDMMCUSEFPGA */
|
||||
0, /* QSPIUSEFPGA */
|
||||
0, /* SPIS1USEFPGA */
|
||||
0, /* RGMII0USEFPGA */
|
||||
0, /* UART1USEFPGA */
|
||||
0, /* CAN1USEFPGA */
|
||||
0, /* USB1USEFPGA */
|
||||
0, /* I2C3USEFPGA */
|
||||
0, /* I2C2USEFPGA */
|
||||
0, /* I2C1USEFPGA */
|
||||
0, /* SPIM1USEFPGA */
|
||||
0, /* USB0USEFPGA */
|
||||
0 /* SPIM0USEFPGA */
|
||||
};
|
||||
#endif /* __SOCFPGA_PINMUX_CONFIG_H__ */
|
||||
91
board/terasic/de1-soc/qts/pll_config.h
Normal file
91
board/terasic/de1-soc/qts/pll_config.h
Normal file
@ -0,0 +1,91 @@
|
||||
/*
|
||||
* Altera SoCFPGA Clock and PLL configuration
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef __SOCFPGA_PLL_CONFIG_H__
|
||||
#define __SOCFPGA_PLL_CONFIG_H__
|
||||
|
||||
#define CONFIG_HPS_DBCTRL_STAYOSC1 1
|
||||
|
||||
#define CONFIG_HPS_MAINPLLGRP_VCO_DENOM 0
|
||||
#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER 63
|
||||
#define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT 0
|
||||
#define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT 0
|
||||
#define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT 0
|
||||
#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 3
|
||||
#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511
|
||||
#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 15
|
||||
#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1
|
||||
#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1
|
||||
#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1
|
||||
#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1
|
||||
#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0
|
||||
#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1
|
||||
#define CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0
|
||||
#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP 1
|
||||
#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP 1
|
||||
|
||||
#define CONFIG_HPS_PERPLLGRP_VCO_DENOM 0
|
||||
#define CONFIG_HPS_PERPLLGRP_VCO_NUMER 39
|
||||
#define CONFIG_HPS_PERPLLGRP_VCO_PSRC 0
|
||||
#define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT 511
|
||||
#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 3
|
||||
#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT 511
|
||||
#define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4
|
||||
#define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT 4
|
||||
#define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 511
|
||||
#define CONFIG_HPS_PERPLLGRP_DIV_USBCLK 0
|
||||
#define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK 0
|
||||
#define CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK 4
|
||||
#define CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK 4
|
||||
#define CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249
|
||||
#define CONFIG_HPS_PERPLLGRP_SRC_SDMMC 2
|
||||
#define CONFIG_HPS_PERPLLGRP_SRC_NAND 2
|
||||
#define CONFIG_HPS_PERPLLGRP_SRC_QSPI 1
|
||||
|
||||
#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM 0
|
||||
#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER 31
|
||||
#define CONFIG_HPS_SDRPLLGRP_VCO_SSRC 0
|
||||
#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1
|
||||
#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0
|
||||
#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0
|
||||
#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0
|
||||
#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1
|
||||
#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4
|
||||
#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 5
|
||||
#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0
|
||||
|
||||
#define CONFIG_HPS_CLK_OSC1_HZ 25000000
|
||||
#define CONFIG_HPS_CLK_OSC2_HZ 25000000
|
||||
#define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0
|
||||
#define CONFIG_HPS_CLK_F2S_PER_REF_HZ 0
|
||||
#define CONFIG_HPS_CLK_MAINVCO_HZ 1600000000
|
||||
#define CONFIG_HPS_CLK_PERVCO_HZ 1000000000
|
||||
#define CONFIG_HPS_CLK_SDRVCO_HZ 800000000
|
||||
#define CONFIG_HPS_CLK_OSC1_HZ 25000000
|
||||
#define CONFIG_HPS_CLK_OSC2_HZ 25000000
|
||||
#define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0
|
||||
#define CONFIG_HPS_CLK_F2S_PER_REF_HZ 0
|
||||
#define CONFIG_HPS_CLK_MAINVCO_HZ 1600000000
|
||||
#define CONFIG_HPS_CLK_PERVCO_HZ 1000000000
|
||||
#define CONFIG_HPS_CLK_EMAC0_HZ 1953125
|
||||
#define CONFIG_HPS_CLK_EMAC1_HZ 250000000
|
||||
#define CONFIG_HPS_CLK_USBCLK_HZ 200000000
|
||||
#define CONFIG_HPS_CLK_NAND_HZ 50000000
|
||||
#define CONFIG_HPS_CLK_SDMMC_HZ 200000000
|
||||
#define CONFIG_HPS_CLK_QSPI_HZ 400000000
|
||||
#define CONFIG_HPS_CLK_SPIM_HZ 200000000
|
||||
#define CONFIG_HPS_CLK_CAN0_HZ 12500000
|
||||
#define CONFIG_HPS_CLK_CAN1_HZ 12500000
|
||||
#define CONFIG_HPS_CLK_GPIODB_HZ 32000
|
||||
#define CONFIG_HPS_CLK_L4_MP_HZ 100000000
|
||||
#define CONFIG_HPS_CLK_L4_SP_HZ 100000000
|
||||
|
||||
#define CONFIG_HPS_ALTERAGRP_MPUCLK 1
|
||||
#define CONFIG_HPS_ALTERAGRP_MAINCLK 3
|
||||
#define CONFIG_HPS_ALTERAGRP_DBGATCLK 3
|
||||
|
||||
|
||||
#endif /* __SOCFPGA_PLL_CONFIG_H__ */
|
||||
344
board/terasic/de1-soc/qts/sdram_config.h
Normal file
344
board/terasic/de1-soc/qts/sdram_config.h
Normal file
@ -0,0 +1,344 @@
|
||||
/*
|
||||
* Altera SoCFPGA SDRAM configuration
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef __SOCFPGA_SDRAM_CONFIG_H__
|
||||
#define __SOCFPGA_SDRAM_CONFIG_H__
|
||||
|
||||
/* SDRAM configuration */
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 0
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 0
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL 8
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE 2
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN 1
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT 10
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH 2
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS 3
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS 10
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS 1
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS 15
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH 8
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH 32
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK 3
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ 0
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE 1
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL 7
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 7
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 18
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 120
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 3
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 6
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 3120
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 6
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR 6
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR 4
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD 4
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD 4
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 15
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 20
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 3
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 200
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST 0x0
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES 0
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES 8
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 0x20820820
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 0x8208208
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 0
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 0x41041041
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 0x410410
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY 0x3FFD1088
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 0x01010101
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 0x01010101
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 0x0101
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 0x21084210
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 0x1EF84
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 0x2020
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 0x0
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 0xF800
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0 0x200
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN 0
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP 0x760210
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL 2
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA 0
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP 0x980543
|
||||
|
||||
/* Sequencer auto configuration */
|
||||
#define RW_MGR_ACTIVATE_0_AND_1 0x0D
|
||||
#define RW_MGR_ACTIVATE_0_AND_1_WAIT1 0x0E
|
||||
#define RW_MGR_ACTIVATE_0_AND_1_WAIT2 0x10
|
||||
#define RW_MGR_ACTIVATE_1 0x0F
|
||||
#define RW_MGR_CLEAR_DQS_ENABLE 0x49
|
||||
#define RW_MGR_GUARANTEED_READ 0x4C
|
||||
#define RW_MGR_GUARANTEED_READ_CONT 0x54
|
||||
#define RW_MGR_GUARANTEED_WRITE 0x18
|
||||
#define RW_MGR_GUARANTEED_WRITE_WAIT0 0x1B
|
||||
#define RW_MGR_GUARANTEED_WRITE_WAIT1 0x1F
|
||||
#define RW_MGR_GUARANTEED_WRITE_WAIT2 0x19
|
||||
#define RW_MGR_GUARANTEED_WRITE_WAIT3 0x1D
|
||||
#define RW_MGR_IDLE 0x00
|
||||
#define RW_MGR_IDLE_LOOP1 0x7B
|
||||
#define RW_MGR_IDLE_LOOP2 0x7A
|
||||
#define RW_MGR_INIT_RESET_0_CKE_0 0x6F
|
||||
#define RW_MGR_INIT_RESET_1_CKE_0 0x74
|
||||
#define RW_MGR_LFSR_WR_RD_BANK_0 0x22
|
||||
#define RW_MGR_LFSR_WR_RD_BANK_0_DATA 0x25
|
||||
#define RW_MGR_LFSR_WR_RD_BANK_0_DQS 0x24
|
||||
#define RW_MGR_LFSR_WR_RD_BANK_0_NOP 0x23
|
||||
#define RW_MGR_LFSR_WR_RD_BANK_0_WAIT 0x32
|
||||
#define RW_MGR_LFSR_WR_RD_BANK_0_WL_1 0x21
|
||||
#define RW_MGR_LFSR_WR_RD_DM_BANK_0 0x36
|
||||
#define RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA 0x39
|
||||
#define RW_MGR_LFSR_WR_RD_DM_BANK_0_DQS 0x38
|
||||
#define RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP 0x37
|
||||
#define RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT 0x46
|
||||
#define RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1 0x35
|
||||
#define RW_MGR_MRS0_DLL_RESET 0x02
|
||||
#define RW_MGR_MRS0_DLL_RESET_MIRR 0x08
|
||||
#define RW_MGR_MRS0_USER 0x07
|
||||
#define RW_MGR_MRS0_USER_MIRR 0x0C
|
||||
#define RW_MGR_MRS1 0x03
|
||||
#define RW_MGR_MRS1_MIRR 0x09
|
||||
#define RW_MGR_MRS2 0x04
|
||||
#define RW_MGR_MRS2_MIRR 0x0A
|
||||
#define RW_MGR_MRS3 0x05
|
||||
#define RW_MGR_MRS3_MIRR 0x0B
|
||||
#define RW_MGR_PRECHARGE_ALL 0x12
|
||||
#define RW_MGR_READ_B2B 0x59
|
||||
#define RW_MGR_READ_B2B_WAIT1 0x61
|
||||
#define RW_MGR_READ_B2B_WAIT2 0x6B
|
||||
#define RW_MGR_REFRESH_ALL 0x14
|
||||
#define RW_MGR_RETURN 0x01
|
||||
#define RW_MGR_SGLE_READ 0x7D
|
||||
#define RW_MGR_ZQCL 0x06
|
||||
|
||||
/* Sequencer defines configuration */
|
||||
#define AFI_RATE_RATIO 1
|
||||
#define CALIB_LFIFO_OFFSET 8
|
||||
#define CALIB_VFIFO_OFFSET 6
|
||||
#define ENABLE_SUPER_QUICK_CALIBRATION 0
|
||||
#define IO_DELAY_PER_DCHAIN_TAP 25
|
||||
#define IO_DELAY_PER_DQS_EN_DCHAIN_TAP 25
|
||||
#define IO_DELAY_PER_OPA_TAP 312
|
||||
#define IO_DLL_CHAIN_LENGTH 8
|
||||
#define IO_DQDQS_OUT_PHASE_MAX 0
|
||||
#define IO_DQS_EN_DELAY_MAX 31
|
||||
#define IO_DQS_EN_DELAY_OFFSET 0
|
||||
#define IO_DQS_EN_PHASE_MAX 7
|
||||
#define IO_DQS_IN_DELAY_MAX 31
|
||||
#define IO_DQS_IN_RESERVE 4
|
||||
#define IO_DQS_OUT_RESERVE 4
|
||||
#define IO_IO_IN_DELAY_MAX 31
|
||||
#define IO_IO_OUT1_DELAY_MAX 31
|
||||
#define IO_IO_OUT2_DELAY_MAX 0
|
||||
#define IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS 0
|
||||
#define MAX_LATENCY_COUNT_WIDTH 5
|
||||
#define READ_VALID_FIFO_SIZE 16
|
||||
#define REG_FILE_INIT_SEQ_SIGNATURE 0x5555048d
|
||||
#define RW_MGR_MEM_ADDRESS_MIRRORING 0
|
||||
#define RW_MGR_MEM_DATA_MASK_WIDTH 4
|
||||
#define RW_MGR_MEM_DATA_WIDTH 32
|
||||
#define RW_MGR_MEM_DQ_PER_READ_DQS 8
|
||||
#define RW_MGR_MEM_DQ_PER_WRITE_DQS 8
|
||||
#define RW_MGR_MEM_IF_READ_DQS_WIDTH 4
|
||||
#define RW_MGR_MEM_IF_WRITE_DQS_WIDTH 4
|
||||
#define RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM 1
|
||||
#define RW_MGR_MEM_NUMBER_OF_RANKS 1
|
||||
#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS 1
|
||||
#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS 1
|
||||
#define RW_MGR_TRUE_MEM_DATA_MASK_WIDTH 4
|
||||
#define TINIT_CNTR0_VAL 99
|
||||
#define TINIT_CNTR1_VAL 32
|
||||
#define TINIT_CNTR2_VAL 32
|
||||
#define TRESET_CNTR0_VAL 99
|
||||
#define TRESET_CNTR1_VAL 99
|
||||
#define TRESET_CNTR2_VAL 10
|
||||
|
||||
/* Sequencer ac_rom_init configuration */
|
||||
const u32 ac_rom_init[] = {
|
||||
0x20700000,
|
||||
0x20780000,
|
||||
0x10080431,
|
||||
0x10080530,
|
||||
0x10090044,
|
||||
0x100a0010,
|
||||
0x100b0000,
|
||||
0x10380400,
|
||||
0x10080449,
|
||||
0x100804c8,
|
||||
0x100a0024,
|
||||
0x10090008,
|
||||
0x100b0000,
|
||||
0x30780000,
|
||||
0x38780000,
|
||||
0x30780000,
|
||||
0x10680000,
|
||||
0x106b0000,
|
||||
0x10280400,
|
||||
0x10480000,
|
||||
0x1c980000,
|
||||
0x1c9b0000,
|
||||
0x1c980008,
|
||||
0x1c9b0008,
|
||||
0x38f80000,
|
||||
0x3cf80000,
|
||||
0x38780000,
|
||||
0x18180000,
|
||||
0x18980000,
|
||||
0x13580000,
|
||||
0x135b0000,
|
||||
0x13580008,
|
||||
0x135b0008,
|
||||
0x33780000,
|
||||
0x10580008,
|
||||
0x10780000
|
||||
};
|
||||
|
||||
/* Sequencer inst_rom_init configuration */
|
||||
const u32 inst_rom_init[] = {
|
||||
0x80000,
|
||||
0x80680,
|
||||
0x8180,
|
||||
0x8200,
|
||||
0x8280,
|
||||
0x8300,
|
||||
0x8380,
|
||||
0x8100,
|
||||
0x8480,
|
||||
0x8500,
|
||||
0x8580,
|
||||
0x8600,
|
||||
0x8400,
|
||||
0x800,
|
||||
0x8680,
|
||||
0x880,
|
||||
0xa680,
|
||||
0x80680,
|
||||
0x900,
|
||||
0x80680,
|
||||
0x980,
|
||||
0xa680,
|
||||
0x8680,
|
||||
0x80680,
|
||||
0xb68,
|
||||
0xcce8,
|
||||
0xae8,
|
||||
0x8ce8,
|
||||
0xb88,
|
||||
0xec88,
|
||||
0xa08,
|
||||
0xac88,
|
||||
0x80680,
|
||||
0xce00,
|
||||
0xcd80,
|
||||
0xe700,
|
||||
0xc00,
|
||||
0x20ce0,
|
||||
0x20ce0,
|
||||
0x20ce0,
|
||||
0x20ce0,
|
||||
0xd00,
|
||||
0x680,
|
||||
0x680,
|
||||
0x680,
|
||||
0x680,
|
||||
0x60e80,
|
||||
0x61080,
|
||||
0x61080,
|
||||
0x61080,
|
||||
0xa680,
|
||||
0x8680,
|
||||
0x80680,
|
||||
0xce00,
|
||||
0xcd80,
|
||||
0xe700,
|
||||
0xc00,
|
||||
0x30ce0,
|
||||
0x30ce0,
|
||||
0x30ce0,
|
||||
0x30ce0,
|
||||
0xd00,
|
||||
0x680,
|
||||
0x680,
|
||||
0x680,
|
||||
0x680,
|
||||
0x70e80,
|
||||
0x71080,
|
||||
0x71080,
|
||||
0x71080,
|
||||
0xa680,
|
||||
0x8680,
|
||||
0x80680,
|
||||
0x1158,
|
||||
0x6d8,
|
||||
0x80680,
|
||||
0x1168,
|
||||
0x7e8,
|
||||
0x7e8,
|
||||
0x87e8,
|
||||
0x40fe8,
|
||||
0x410e8,
|
||||
0x410e8,
|
||||
0x410e8,
|
||||
0x1168,
|
||||
0x7e8,
|
||||
0x7e8,
|
||||
0xa7e8,
|
||||
0x80680,
|
||||
0x40e88,
|
||||
0x41088,
|
||||
0x41088,
|
||||
0x41088,
|
||||
0x40f68,
|
||||
0x410e8,
|
||||
0x410e8,
|
||||
0x410e8,
|
||||
0xa680,
|
||||
0x40fe8,
|
||||
0x410e8,
|
||||
0x410e8,
|
||||
0x410e8,
|
||||
0x41008,
|
||||
0x41088,
|
||||
0x41088,
|
||||
0x41088,
|
||||
0x1100,
|
||||
0xc680,
|
||||
0x8680,
|
||||
0xe680,
|
||||
0x80680,
|
||||
0x0,
|
||||
0x8000,
|
||||
0xa000,
|
||||
0xc000,
|
||||
0x80000,
|
||||
0x80,
|
||||
0x8080,
|
||||
0xa080,
|
||||
0xc080,
|
||||
0x80080,
|
||||
0x9180,
|
||||
0x8680,
|
||||
0xa680,
|
||||
0x80680,
|
||||
0x40f08,
|
||||
0x80680
|
||||
};
|
||||
|
||||
#endif /* __SOCFPGA_SDRAM_CONFIG_H__ */
|
||||
19
board/terasic/de1-soc/socfpga.c
Normal file
19
board/terasic/de1-soc/socfpga.c
Normal file
@ -0,0 +1,19 @@
|
||||
/*
|
||||
* Copyright (C) 2012 Altera Corporation <www.altera.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
#include <common.h>
|
||||
#include <spl.h>
|
||||
|
||||
void board_boot_order(u32 *spl_boot_list)
|
||||
{
|
||||
spl_boot_list[0] = spl_boot_device();
|
||||
|
||||
switch (spl_boot_list[0]) {
|
||||
case BOOT_DEVICE_MMC1:
|
||||
spl_boot_list[0] = BOOT_DEVICE_MMC1;
|
||||
spl_boot_list[1] = BOOT_DEVICE_UART;
|
||||
break;
|
||||
}
|
||||
}
|
||||
@ -109,6 +109,16 @@ static const struct emif_regs ddr2_emif_reg_data = {
|
||||
.emif_ddr_phy_ctlr_1 = MT47H128M16RT25E_EMIF_READ_LATENCY,
|
||||
};
|
||||
|
||||
static const struct emif_regs ddr2_evm_emif_reg_data = {
|
||||
.sdram_config = MT47H128M16RT25E_EMIF_SDCFG,
|
||||
.ref_ctrl = MT47H128M16RT25E_EMIF_SDREF,
|
||||
.sdram_tim1 = MT47H128M16RT25E_EMIF_TIM1,
|
||||
.sdram_tim2 = MT47H128M16RT25E_EMIF_TIM2,
|
||||
.sdram_tim3 = MT47H128M16RT25E_EMIF_TIM3,
|
||||
.ocp_config = EMIF_OCP_CONFIG_AM335X_EVM,
|
||||
.emif_ddr_phy_ctlr_1 = MT47H128M16RT25E_EMIF_READ_LATENCY,
|
||||
};
|
||||
|
||||
static const struct ddr_data ddr3_data = {
|
||||
.datardsratio0 = MT41J128MJT125_RD_DQS,
|
||||
.datawdsratio0 = MT41J128MJT125_WR_DQS,
|
||||
@ -198,6 +208,7 @@ static struct emif_regs ddr3_beagleblack_emif_reg_data = {
|
||||
.sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
|
||||
.sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
|
||||
.sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
|
||||
.ocp_config = EMIF_OCP_CONFIG_BEAGLEBONE_BLACK,
|
||||
.zq_config = MT41K256M16HA125E_ZQ_CFG,
|
||||
.emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
|
||||
};
|
||||
@ -208,6 +219,7 @@ static struct emif_regs ddr3_evm_emif_reg_data = {
|
||||
.sdram_tim1 = MT41J512M8RH125_EMIF_TIM1,
|
||||
.sdram_tim2 = MT41J512M8RH125_EMIF_TIM2,
|
||||
.sdram_tim3 = MT41J512M8RH125_EMIF_TIM3,
|
||||
.ocp_config = EMIF_OCP_CONFIG_AM335X_EVM,
|
||||
.zq_config = MT41J512M8RH125_ZQ_CFG,
|
||||
.emif_ddr_phy_ctlr_1 = MT41J512M8RH125_EMIF_READ_LATENCY |
|
||||
PHY_EN_DYN_PWRDN,
|
||||
@ -486,6 +498,9 @@ void sdram_init(void)
|
||||
config_ddr(400, &ioregs_evmsk, &ddr3_icev2_data,
|
||||
&ddr3_icev2_cmd_ctrl_data, &ddr3_icev2_emif_reg_data,
|
||||
0);
|
||||
else if (board_is_gp_evm())
|
||||
config_ddr(266, &ioregs, &ddr2_data,
|
||||
&ddr2_cmd_ctrl_data, &ddr2_evm_emif_reg_data, 0);
|
||||
else
|
||||
config_ddr(266, &ioregs, &ddr2_data,
|
||||
&ddr2_cmd_ctrl_data, &ddr2_emif_reg_data, 0);
|
||||
|
||||
@ -11,6 +11,19 @@
|
||||
#ifndef _BOARD_H_
|
||||
#define _BOARD_H_
|
||||
|
||||
/**
|
||||
* AM335X (EMIF_4D) EMIF REG_COS_COUNT_1, REG_COS_COUNT_2, and
|
||||
* REG_PR_OLD_COUNT values to avoid LCDC DMA FIFO underflows and Frame
|
||||
* Synchronization Lost errors. The values are the biggest that work
|
||||
* reliably with offered video modes and the memory subsystem on the
|
||||
* boards. These register have are briefly documented in "7.3.3.5.2
|
||||
* Command Starvation" section of AM335x TRM. The REG_COS_COUNT_1 and
|
||||
* REG_COS_COUNT_2 do not have any effect on current versions of
|
||||
* AM335x.
|
||||
*/
|
||||
#define EMIF_OCP_CONFIG_BEAGLEBONE_BLACK 0x00141414
|
||||
#define EMIF_OCP_CONFIG_AM335X_EVM 0x003d3d3d
|
||||
|
||||
static inline int board_is_bone(void)
|
||||
{
|
||||
return board_ti_is("A335BONE");
|
||||
|
||||
@ -55,6 +55,9 @@ DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
#define SYSINFO_BOARD_NAME_MAX_LEN 45
|
||||
|
||||
#define TPS65903X_PRIMARY_SECONDARY_PAD2 0xFB
|
||||
#define TPS65903X_PAD2_POWERHOLD_MASK 0x20
|
||||
|
||||
const struct omap_sysinfo sysinfo = {
|
||||
"Board: UNKNOWN(BeagleBoard X15?) REV UNKNOWN\n"
|
||||
};
|
||||
@ -457,6 +460,7 @@ int board_init(void)
|
||||
int board_late_init(void)
|
||||
{
|
||||
setup_board_eeprom_env();
|
||||
u8 val;
|
||||
|
||||
/*
|
||||
* DEV_CTRL.DEV_ON = 1 please - else palmas switches off in 8 seconds
|
||||
@ -471,6 +475,18 @@ int board_late_init(void)
|
||||
if (get_device_type() == HS_DEVICE)
|
||||
setenv("boot_fit", "1");
|
||||
|
||||
/*
|
||||
* Set the GPIO7 Pad to POWERHOLD. This has higher priority
|
||||
* over DEV_CTRL.DEV_ON bit. This can be reset in case of
|
||||
* PMIC Power off. So to be on the safer side set it back
|
||||
* to POWERHOLD mode irrespective of the current state.
|
||||
*/
|
||||
palmas_i2c_read_u8(TPS65903X_CHIP_P1, TPS65903X_PRIMARY_SECONDARY_PAD2,
|
||||
&val);
|
||||
val = val | TPS65903X_PAD2_POWERHOLD_MASK;
|
||||
palmas_i2c_write_u8(TPS65903X_CHIP_P1, TPS65903X_PRIMARY_SECONDARY_PAD2,
|
||||
val);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
@ -123,8 +123,10 @@ int __maybe_unused ti_i2c_eeprom_am_get(int bus_addr, int dev_addr)
|
||||
struct ti_common_eeprom *ep;
|
||||
|
||||
ep = TI_EEPROM_DATA;
|
||||
#ifndef CONFIG_SPL_BUILD
|
||||
if (ep->header == TI_EEPROM_HEADER_MAGIC)
|
||||
goto already_read;
|
||||
return 0; /* EEPROM has already been read */
|
||||
#endif
|
||||
|
||||
/* Initialize with a known bad marker for i2c fails.. */
|
||||
ep->header = TI_DEAD_EEPROM_MAGIC;
|
||||
@ -157,7 +159,6 @@ int __maybe_unused ti_i2c_eeprom_am_get(int bus_addr, int dev_addr)
|
||||
memcpy(ep->mac_addr, am_ep.mac_addr,
|
||||
TI_EEPROM_HDR_NO_OF_MAC_ADDR * TI_EEPROM_HDR_ETH_ALEN);
|
||||
|
||||
already_read:
|
||||
return 0;
|
||||
}
|
||||
|
||||
@ -168,8 +169,10 @@ int __maybe_unused ti_i2c_eeprom_dra7_get(int bus_addr, int dev_addr)
|
||||
struct ti_common_eeprom *ep;
|
||||
|
||||
ep = TI_EEPROM_DATA;
|
||||
#ifndef CONFIG_SPL_BUILD
|
||||
if (ep->header == DRA7_EEPROM_HEADER_MAGIC)
|
||||
goto already_read;
|
||||
return 0; /* EEPROM has already been read */
|
||||
#endif
|
||||
|
||||
/* Initialize with a known bad marker for i2c fails.. */
|
||||
ep->header = TI_DEAD_EEPROM_MAGIC;
|
||||
@ -202,7 +205,6 @@ int __maybe_unused ti_i2c_eeprom_dra7_get(int bus_addr, int dev_addr)
|
||||
strlcpy(ep->config, dra7_ep.config, TI_EEPROM_HDR_CONFIG_LEN + 1);
|
||||
ti_eeprom_string_cleanup(ep->config);
|
||||
|
||||
already_read:
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
@ -39,6 +39,7 @@ DECLARE_GLOBAL_DATA_PTR;
|
||||
/* GPIO that controls power to DDR on EVM-SK */
|
||||
#define GPIO_DDR_VTT_EN 7
|
||||
#define DIP_S1 44
|
||||
#define MPCIE_SW 100
|
||||
|
||||
static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
|
||||
|
||||
@ -330,6 +331,11 @@ int ft_board_setup(void *blob, bd_t *bd)
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct module_pin_mux pcie_sw_pin_mux[] = {
|
||||
{OFFSET(mii1_rxdv), (MODE(7) | PULLUDEN )}, /* GPIO3_4 */
|
||||
{-1},
|
||||
};
|
||||
|
||||
static struct module_pin_mux dip_pin_mux[] = {
|
||||
{OFFSET(gpmc_ad12), (MODE(7) | RXACTIVE )}, /* GPIO1_12 */
|
||||
{OFFSET(gpmc_ad13), (MODE(7) | RXACTIVE )}, /* GPIO1_13 */
|
||||
@ -355,6 +361,18 @@ int board_late_init(void)
|
||||
baltos_set_console();
|
||||
}
|
||||
}
|
||||
|
||||
/* turn power for the mPCIe slot */
|
||||
configure_module_pin_mux(pcie_sw_pin_mux);
|
||||
if (gpio_request(MPCIE_SW, "mpcie_sw")) {
|
||||
printf("failed to export GPIO %d\n", MPCIE_SW);
|
||||
return -ENODEV;
|
||||
}
|
||||
if (gpio_direction_output(MPCIE_SW, 1)) {
|
||||
printf("failed to set GPIO %d direction\n", MPCIE_SW);
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
setenv("board_name", model);
|
||||
#endif
|
||||
|
||||
@ -415,7 +433,6 @@ int board_eth_init(bd_t *bis)
|
||||
int rv, n = 0;
|
||||
uint8_t mac_addr[6];
|
||||
uint32_t mac_hi, mac_lo;
|
||||
__maybe_unused struct am335x_baseboard_id header;
|
||||
|
||||
/*
|
||||
* Note here that we're using CPSW1 since that has a 1Gbit PHY while
|
||||
|
||||
@ -11,24 +11,6 @@
|
||||
#ifndef _BOARD_H_
|
||||
#define _BOARD_H_
|
||||
|
||||
/*
|
||||
* TI AM335x parts define a system EEPROM that defines certain sub-fields.
|
||||
* We use these fields to in turn see what board we are on, and what
|
||||
* that might require us to set or not set.
|
||||
*/
|
||||
#define HDR_NO_OF_MAC_ADDR 3
|
||||
#define HDR_ETH_ALEN 6
|
||||
#define HDR_NAME_LEN 8
|
||||
|
||||
struct am335x_baseboard_id {
|
||||
unsigned int magic;
|
||||
char name[HDR_NAME_LEN];
|
||||
char version[4];
|
||||
char serial[12];
|
||||
char config[32];
|
||||
char mac_addr[HDR_NO_OF_MAC_ADDR][HDR_ETH_ALEN];
|
||||
};
|
||||
|
||||
typedef struct _BSP_VS_HWPARAM // v1.0
|
||||
{
|
||||
uint32_t Magic;
|
||||
@ -41,37 +23,6 @@ typedef struct _BSP_VS_HWPARAM // v1.0
|
||||
uint8_t MAC3[6]; // WL1271 WLAN
|
||||
} __attribute__ ((packed)) BSP_VS_HWPARAM;
|
||||
|
||||
static inline int board_is_bone(struct am335x_baseboard_id *header)
|
||||
{
|
||||
return !strncmp(header->name, "A335BONE", HDR_NAME_LEN);
|
||||
}
|
||||
|
||||
static inline int board_is_bone_lt(struct am335x_baseboard_id *header)
|
||||
{
|
||||
return !strncmp(header->name, "A335BNLT", HDR_NAME_LEN);
|
||||
}
|
||||
|
||||
static inline int board_is_evm_sk(struct am335x_baseboard_id *header)
|
||||
{
|
||||
return !strncmp("A335X_SK", header->name, HDR_NAME_LEN);
|
||||
}
|
||||
|
||||
static inline int board_is_idk(struct am335x_baseboard_id *header)
|
||||
{
|
||||
return !strncmp(header->config, "SKU#02", 6);
|
||||
}
|
||||
|
||||
static inline int board_is_gp_evm(struct am335x_baseboard_id *header)
|
||||
{
|
||||
return !strncmp("A33515BB", header->name, HDR_NAME_LEN);
|
||||
}
|
||||
|
||||
static inline int board_is_evm_15_or_later(struct am335x_baseboard_id *header)
|
||||
{
|
||||
return (board_is_gp_evm(header) &&
|
||||
strncmp("1.5", header->version, 3) <= 0);
|
||||
}
|
||||
|
||||
/*
|
||||
* We have three pin mux functions that must exist. We must be able to enable
|
||||
* uart0, for initial output and i2c0 to read the main EEPROM. We then have a
|
||||
@ -79,12 +30,6 @@ static inline int board_is_evm_15_or_later(struct am335x_baseboard_id *header)
|
||||
* is required on the board.
|
||||
*/
|
||||
void enable_uart0_pin_mux(void);
|
||||
void enable_uart1_pin_mux(void);
|
||||
void enable_uart2_pin_mux(void);
|
||||
void enable_uart3_pin_mux(void);
|
||||
void enable_uart4_pin_mux(void);
|
||||
void enable_uart5_pin_mux(void);
|
||||
void enable_i2c0_pin_mux(void);
|
||||
void enable_i2c1_pin_mux(void);
|
||||
void enable_board_pin_mux(void);
|
||||
#endif
|
||||
|
||||
@ -27,36 +27,6 @@ static struct module_pin_mux uart0_pin_mux[] = {
|
||||
{-1},
|
||||
};
|
||||
|
||||
static struct module_pin_mux uart1_pin_mux[] = {
|
||||
{OFFSET(uart1_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART1_RXD */
|
||||
{OFFSET(uart1_txd), (MODE(0) | PULLUDEN)}, /* UART1_TXD */
|
||||
{-1},
|
||||
};
|
||||
|
||||
static struct module_pin_mux uart2_pin_mux[] = {
|
||||
{OFFSET(spi0_sclk), (MODE(1) | PULLUP_EN | RXACTIVE)}, /* UART2_RXD */
|
||||
{OFFSET(spi0_d0), (MODE(1) | PULLUDEN)}, /* UART2_TXD */
|
||||
{-1},
|
||||
};
|
||||
|
||||
static struct module_pin_mux uart3_pin_mux[] = {
|
||||
{OFFSET(spi0_cs1), (MODE(1) | PULLUP_EN | RXACTIVE)}, /* UART3_RXD */
|
||||
{OFFSET(ecap0_in_pwm0_out), (MODE(1) | PULLUDEN)}, /* UART3_TXD */
|
||||
{-1},
|
||||
};
|
||||
|
||||
static struct module_pin_mux uart4_pin_mux[] = {
|
||||
{OFFSET(gpmc_wait0), (MODE(6) | PULLUP_EN | RXACTIVE)}, /* UART4_RXD */
|
||||
{OFFSET(gpmc_wpn), (MODE(6) | PULLUDEN)}, /* UART4_TXD */
|
||||
{-1},
|
||||
};
|
||||
|
||||
static struct module_pin_mux uart5_pin_mux[] = {
|
||||
{OFFSET(lcd_data9), (MODE(4) | PULLUP_EN | RXACTIVE)}, /* UART5_RXD */
|
||||
{OFFSET(lcd_data8), (MODE(4) | PULLUDEN)}, /* UART5_TXD */
|
||||
{-1},
|
||||
};
|
||||
|
||||
static struct module_pin_mux mmc0_pin_mux[] = {
|
||||
{OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT3 */
|
||||
{OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT2 */
|
||||
@ -68,14 +38,6 @@ static struct module_pin_mux mmc0_pin_mux[] = {
|
||||
{-1},
|
||||
};
|
||||
|
||||
static struct module_pin_mux i2c0_pin_mux[] = {
|
||||
{OFFSET(i2c0_sda), (MODE(0) | RXACTIVE |
|
||||
PULLUDEN | SLEWCTRL)}, /* I2C_DATA */
|
||||
{OFFSET(i2c0_scl), (MODE(0) | RXACTIVE |
|
||||
PULLUDEN | SLEWCTRL)}, /* I2C_SCLK */
|
||||
{-1},
|
||||
};
|
||||
|
||||
static struct module_pin_mux i2c1_pin_mux[] = {
|
||||
{OFFSET(spi0_d1), (MODE(2) | RXACTIVE |
|
||||
PULLUDEN | SLEWCTRL)}, /* I2C_DATA */
|
||||
@ -144,36 +106,6 @@ void enable_uart0_pin_mux(void)
|
||||
configure_module_pin_mux(uart0_pin_mux);
|
||||
}
|
||||
|
||||
void enable_uart1_pin_mux(void)
|
||||
{
|
||||
configure_module_pin_mux(uart1_pin_mux);
|
||||
}
|
||||
|
||||
void enable_uart2_pin_mux(void)
|
||||
{
|
||||
configure_module_pin_mux(uart2_pin_mux);
|
||||
}
|
||||
|
||||
void enable_uart3_pin_mux(void)
|
||||
{
|
||||
configure_module_pin_mux(uart3_pin_mux);
|
||||
}
|
||||
|
||||
void enable_uart4_pin_mux(void)
|
||||
{
|
||||
configure_module_pin_mux(uart4_pin_mux);
|
||||
}
|
||||
|
||||
void enable_uart5_pin_mux(void)
|
||||
{
|
||||
configure_module_pin_mux(uart5_pin_mux);
|
||||
}
|
||||
|
||||
void enable_i2c0_pin_mux(void)
|
||||
{
|
||||
configure_module_pin_mux(i2c0_pin_mux);
|
||||
}
|
||||
|
||||
void enable_i2c1_pin_mux(void)
|
||||
{
|
||||
configure_module_pin_mux(i2c1_pin_mux);
|
||||
@ -181,7 +113,6 @@ void enable_i2c1_pin_mux(void)
|
||||
|
||||
void enable_board_pin_mux()
|
||||
{
|
||||
/* Baltos */
|
||||
configure_module_pin_mux(i2c1_pin_mux);
|
||||
configure_module_pin_mux(gpio0_7_pin_mux);
|
||||
configure_module_pin_mux(rgmii2_pin_mux);
|
||||
|
||||
@ -653,6 +653,9 @@ config CMD_QFW
|
||||
This provides access to the QEMU firmware interface. The main
|
||||
feature is to allow easy loading of files passed to qemu-system
|
||||
via -kernel / -initrd
|
||||
|
||||
source "cmd/mvebu/Kconfig"
|
||||
|
||||
endmenu
|
||||
|
||||
config CMD_BOOTSTAGE
|
||||
|
||||
@ -163,3 +163,5 @@ obj-$(CONFIG_CMD_BLOB) += blob.o
|
||||
|
||||
# core command
|
||||
obj-y += nvedit.o
|
||||
|
||||
obj-$(CONFIG_ARCH_MVEBU) += mvebu/
|
||||
|
||||
52
cmd/mvebu/Kconfig
Normal file
52
cmd/mvebu/Kconfig
Normal file
@ -0,0 +1,52 @@
|
||||
menu "MVEBU commands"
|
||||
depends on ARCH_MVEBU
|
||||
|
||||
config CMD_MVEBU_BUBT
|
||||
bool "bubt"
|
||||
default n
|
||||
help
|
||||
bubt - Burn a u-boot image to flash
|
||||
For details about bubt command please see the documentation
|
||||
in doc/mvebu/cmd/bubt.txt
|
||||
|
||||
choice
|
||||
prompt "Flash for image"
|
||||
default MVEBU_SPI_BOOT
|
||||
|
||||
config MVEBU_NAND_BOOT
|
||||
bool "NAND flash boot"
|
||||
depends on NAND_PXA3XX
|
||||
help
|
||||
Enable boot from NAND flash.
|
||||
Allow usage of NAND flash as a target for "bubt" command
|
||||
For details about bubt command please see the documentation
|
||||
in doc/mvebu/cmd/bubt.txt
|
||||
|
||||
config MVEBU_SPI_BOOT
|
||||
bool "SPI flash boot"
|
||||
depends on SPI_FLASH
|
||||
help
|
||||
Enable boot from SPI flash.
|
||||
Allow usage of SPI flash as a target for "bubt" command
|
||||
For details about bubt command please see the documentation
|
||||
in doc/mvebu/cmd/bubt.txt
|
||||
|
||||
config MVEBU_MMC_BOOT
|
||||
bool "eMMC flash boot"
|
||||
depends on MVEBU_MMC
|
||||
help
|
||||
Enable boot from eMMC boot partition
|
||||
Allow usage of eMMC/SD device as a target for "bubt" command
|
||||
For details about bubt command please see the documentation
|
||||
in doc/mvebu/cmd/bubt.txt
|
||||
|
||||
endchoice
|
||||
|
||||
config MVEBU_UBOOT_DFLT_NAME
|
||||
string "Default image name for bubt command"
|
||||
default "flash-image.bin"
|
||||
help
|
||||
This option should contain a default file name to be used with
|
||||
MVEBU "bubt" command if the source file name is omitted
|
||||
|
||||
endmenu
|
||||
8
cmd/mvebu/Makefile
Normal file
8
cmd/mvebu/Makefile
Normal file
@ -0,0 +1,8 @@
|
||||
#
|
||||
# Copyright (C) 2016 Marvell International Ltd.
|
||||
#
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
# https://spdx.org/licenses
|
||||
|
||||
|
||||
obj-$(CONFIG_CMD_MVEBU_BUBT) += bubt.o
|
||||
767
cmd/mvebu/bubt.c
Normal file
767
cmd/mvebu/bubt.c
Normal file
@ -0,0 +1,767 @@
|
||||
/*
|
||||
* Copyright (C) 2016 Marvell International Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0
|
||||
* https://spdx.org/licenses
|
||||
*/
|
||||
|
||||
#include <config.h>
|
||||
#include <common.h>
|
||||
#include <command.h>
|
||||
#include <vsprintf.h>
|
||||
#include <errno.h>
|
||||
#include <dm.h>
|
||||
|
||||
#include <spi_flash.h>
|
||||
#include <spi.h>
|
||||
#include <nand.h>
|
||||
#include <usb.h>
|
||||
#include <fs.h>
|
||||
#include <mmc.h>
|
||||
#include <u-boot/sha1.h>
|
||||
#include <u-boot/sha256.h>
|
||||
|
||||
#ifndef CONFIG_SYS_MMC_ENV_DEV
|
||||
#define CONFIG_SYS_MMC_ENV_DEV 0
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_ARMADA_8K)
|
||||
#define MAIN_HDR_MAGIC 0xB105B002
|
||||
|
||||
struct mvebu_image_header {
|
||||
u32 magic; /* 0-3 */
|
||||
u32 prolog_size; /* 4-7 */
|
||||
u32 prolog_checksum; /* 8-11 */
|
||||
u32 boot_image_size; /* 12-15 */
|
||||
u32 boot_image_checksum; /* 16-19 */
|
||||
u32 rsrvd0; /* 20-23 */
|
||||
u32 load_addr; /* 24-27 */
|
||||
u32 exec_addr; /* 28-31 */
|
||||
u8 uart_cfg; /* 32 */
|
||||
u8 baudrate; /* 33 */
|
||||
u8 ext_count; /* 34 */
|
||||
u8 aux_flags; /* 35 */
|
||||
u32 io_arg_0; /* 36-39 */
|
||||
u32 io_arg_1; /* 40-43 */
|
||||
u32 io_arg_2; /* 43-47 */
|
||||
u32 io_arg_3; /* 48-51 */
|
||||
u32 rsrvd1; /* 52-55 */
|
||||
u32 rsrvd2; /* 56-59 */
|
||||
u32 rsrvd3; /* 60-63 */
|
||||
};
|
||||
#elif defined(CONFIG_ARMADA_3700) /* A3700 */
|
||||
#define HASH_SUM_LEN 16
|
||||
#define IMAGE_VERSION_3_6_0 0x030600
|
||||
#define IMAGE_VERSION_3_5_0 0x030500
|
||||
|
||||
struct common_tim_data {
|
||||
u32 version;
|
||||
u32 identifier;
|
||||
u32 trusted;
|
||||
u32 issue_date;
|
||||
u32 oem_unique_id;
|
||||
u32 reserved[5]; /* Reserve 20 bytes */
|
||||
u32 boot_flash_sign;
|
||||
u32 num_images;
|
||||
u32 num_keys;
|
||||
u32 size_of_reserved;
|
||||
};
|
||||
|
||||
struct mvebu_image_info {
|
||||
u32 image_id;
|
||||
u32 next_image_id;
|
||||
u32 flash_entry_addr;
|
||||
u32 load_addr;
|
||||
u32 image_size;
|
||||
u32 image_size_to_hash;
|
||||
u32 hash_algorithm_id;
|
||||
u32 hash[HASH_SUM_LEN]; /* Reserve 512 bits for the hash */
|
||||
u32 partition_number;
|
||||
u32 enc_algorithm_id;
|
||||
u32 encrypt_start_offset;
|
||||
u32 encrypt_size;
|
||||
};
|
||||
#endif /* CONFIG_ARMADA_XXX */
|
||||
|
||||
struct bubt_dev {
|
||||
char name[8];
|
||||
size_t (*read)(const char *file_name);
|
||||
int (*write)(size_t image_size);
|
||||
int (*active)(void);
|
||||
};
|
||||
|
||||
static ulong get_load_addr(void)
|
||||
{
|
||||
const char *addr_str;
|
||||
unsigned long addr;
|
||||
|
||||
addr_str = getenv("loadaddr");
|
||||
if (addr_str)
|
||||
addr = simple_strtoul(addr_str, NULL, 16);
|
||||
else
|
||||
addr = CONFIG_SYS_LOAD_ADDR;
|
||||
|
||||
return addr;
|
||||
}
|
||||
|
||||
/********************************************************************
|
||||
* eMMC services
|
||||
********************************************************************/
|
||||
#ifdef CONFIG_DM_MMC
|
||||
static int mmc_burn_image(size_t image_size)
|
||||
{
|
||||
struct mmc *mmc;
|
||||
lbaint_t start_lba;
|
||||
lbaint_t blk_count;
|
||||
ulong blk_written;
|
||||
int err;
|
||||
const u8 mmc_dev_num = CONFIG_SYS_MMC_ENV_DEV;
|
||||
|
||||
mmc = find_mmc_device(mmc_dev_num);
|
||||
if (!mmc) {
|
||||
printf("No SD/MMC/eMMC card found\n");
|
||||
return -ENOMEDIUM;
|
||||
}
|
||||
|
||||
err = mmc_init(mmc);
|
||||
if (err) {
|
||||
printf("%s(%d) init failed\n", IS_SD(mmc) ? "SD" : "MMC",
|
||||
mmc_dev_num);
|
||||
return err;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_SYS_MMC_ENV_PART
|
||||
if (mmc->part_num != CONFIG_SYS_MMC_ENV_PART) {
|
||||
err = mmc_switch_part(mmc_dev_num, CONFIG_SYS_MMC_ENV_PART);
|
||||
if (err) {
|
||||
printf("MMC partition switch failed\n");
|
||||
return err;
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
/* SD reserves LBA-0 for MBR and boots from LBA-1,
|
||||
* MMC/eMMC boots from LBA-0
|
||||
*/
|
||||
start_lba = IS_SD(mmc) ? 1 : 0;
|
||||
blk_count = image_size / mmc->block_dev.blksz;
|
||||
if (image_size % mmc->block_dev.blksz)
|
||||
blk_count += 1;
|
||||
|
||||
blk_written = mmc->block_dev.block_write(mmc_dev_num,
|
||||
start_lba, blk_count,
|
||||
(void *)get_load_addr());
|
||||
if (blk_written != blk_count) {
|
||||
printf("Error - written %#lx blocks\n", blk_written);
|
||||
return -ENOSPC;
|
||||
}
|
||||
printf("Done!\n");
|
||||
|
||||
#ifdef CONFIG_SYS_MMC_ENV_PART
|
||||
if (mmc->part_num != CONFIG_SYS_MMC_ENV_PART)
|
||||
mmc_switch_part(mmc_dev_num, mmc->part_num);
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static size_t mmc_read_file(const char *file_name)
|
||||
{
|
||||
loff_t act_read = 0;
|
||||
int rc;
|
||||
struct mmc *mmc;
|
||||
const u8 mmc_dev_num = CONFIG_SYS_MMC_ENV_DEV;
|
||||
|
||||
mmc = find_mmc_device(mmc_dev_num);
|
||||
if (!mmc) {
|
||||
printf("No SD/MMC/eMMC card found\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
if (mmc_init(mmc)) {
|
||||
printf("%s(%d) init failed\n", IS_SD(mmc) ? "SD" : "MMC",
|
||||
mmc_dev_num);
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Load from data partition (0) */
|
||||
if (fs_set_blk_dev("mmc", "0", FS_TYPE_ANY)) {
|
||||
printf("Error: MMC 0 not found\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Perfrom file read */
|
||||
rc = fs_read(file_name, get_load_addr(), 0, 0, &act_read);
|
||||
if (rc)
|
||||
return 0;
|
||||
|
||||
return act_read;
|
||||
}
|
||||
|
||||
static int is_mmc_active(void)
|
||||
{
|
||||
return 1;
|
||||
}
|
||||
#else /* CONFIG_DM_MMC */
|
||||
static int mmc_burn_image(size_t image_size)
|
||||
{
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
static size_t mmc_read_file(const char *file_name)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int is_mmc_active(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
#endif /* CONFIG_DM_MMC */
|
||||
|
||||
/********************************************************************
|
||||
* SPI services
|
||||
********************************************************************/
|
||||
#ifdef CONFIG_SPI_FLASH
|
||||
static int spi_burn_image(size_t image_size)
|
||||
{
|
||||
int ret;
|
||||
struct spi_flash *flash;
|
||||
u32 erase_bytes;
|
||||
|
||||
/* Probe the SPI bus to get the flash device */
|
||||
flash = spi_flash_probe(CONFIG_ENV_SPI_BUS,
|
||||
CONFIG_ENV_SPI_CS,
|
||||
CONFIG_SF_DEFAULT_SPEED,
|
||||
CONFIG_SF_DEFAULT_MODE);
|
||||
if (!flash) {
|
||||
printf("Failed to probe SPI Flash\n");
|
||||
return -ENOMEDIUM;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_SPI_FLASH_PROTECTION
|
||||
spi_flash_protect(flash, 0);
|
||||
#endif
|
||||
erase_bytes = image_size +
|
||||
(flash->erase_size - image_size % flash->erase_size);
|
||||
printf("Erasing %d bytes (%d blocks) at offset 0 ...",
|
||||
erase_bytes, erase_bytes / flash->erase_size);
|
||||
ret = spi_flash_erase(flash, 0, erase_bytes);
|
||||
if (ret)
|
||||
printf("Error!\n");
|
||||
else
|
||||
printf("Done!\n");
|
||||
|
||||
printf("Writing %d bytes from 0x%lx to offset 0 ...",
|
||||
(int)image_size, get_load_addr());
|
||||
ret = spi_flash_write(flash, 0, image_size, (void *)get_load_addr());
|
||||
if (ret)
|
||||
printf("Error!\n");
|
||||
else
|
||||
printf("Done!\n");
|
||||
|
||||
#ifdef CONFIG_SPI_FLASH_PROTECTION
|
||||
spi_flash_protect(flash, 1);
|
||||
#endif
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int is_spi_active(void)
|
||||
{
|
||||
return 1;
|
||||
}
|
||||
|
||||
#else /* CONFIG_SPI_FLASH */
|
||||
static int spi_burn_image(size_t image_size)
|
||||
{
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
static int is_spi_active(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
#endif /* CONFIG_SPI_FLASH */
|
||||
|
||||
/********************************************************************
|
||||
* NAND services
|
||||
********************************************************************/
|
||||
#ifdef CONFIG_CMD_NAND
|
||||
static int nand_burn_image(size_t image_size)
|
||||
{
|
||||
int ret, block_size;
|
||||
nand_info_t *nand;
|
||||
int dev = nand_curr_device;
|
||||
|
||||
if ((dev < 0) || (dev >= CONFIG_SYS_MAX_NAND_DEVICE) ||
|
||||
(!nand_info[dev].name)) {
|
||||
puts("\nno devices available\n");
|
||||
return -ENOMEDIUM;
|
||||
}
|
||||
nand = &nand_info[dev];
|
||||
block_size = nand->erasesize;
|
||||
|
||||
/* Align U-Boot size to currently used blocksize */
|
||||
image_size = ((image_size + (block_size - 1)) & (~(block_size - 1)));
|
||||
|
||||
/* Erase the U-BOOT image space */
|
||||
printf("Erasing 0x%x - 0x%x:...", 0, (int)image_size);
|
||||
ret = nand_erase(nand, 0, image_size);
|
||||
if (ret) {
|
||||
printf("Error!\n");
|
||||
goto error;
|
||||
}
|
||||
printf("Done!\n");
|
||||
|
||||
/* Write the image to flash */
|
||||
printf("Writing image:...");
|
||||
printf("&image_size = 0x%p\n", (void *)&image_size);
|
||||
ret = nand_write(nand, 0, &image_size, (void *)get_load_addr());
|
||||
if (ret)
|
||||
printf("Error!\n");
|
||||
else
|
||||
printf("Done!\n");
|
||||
|
||||
error:
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int is_nand_active(void)
|
||||
{
|
||||
return 1;
|
||||
}
|
||||
|
||||
#else /* CONFIG_CMD_NAND */
|
||||
static int nand_burn_image(size_t image_size)
|
||||
{
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
static int is_nand_active(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
#endif /* CONFIG_CMD_NAND */
|
||||
|
||||
/********************************************************************
|
||||
* USB services
|
||||
********************************************************************/
|
||||
#if defined(CONFIG_USB_STORAGE) && defined(CONFIG_BLK)
|
||||
static size_t usb_read_file(const char *file_name)
|
||||
{
|
||||
loff_t act_read = 0;
|
||||
struct udevice *dev;
|
||||
int rc;
|
||||
|
||||
usb_stop();
|
||||
|
||||
if (usb_init() < 0) {
|
||||
printf("Error: usb_init failed\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Try to recognize storage devices immediately */
|
||||
blk_first_device(IF_TYPE_USB, &dev);
|
||||
if (!dev) {
|
||||
printf("Error: USB storage device not found\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Always load from usb 0 */
|
||||
if (fs_set_blk_dev("usb", "0", FS_TYPE_ANY)) {
|
||||
printf("Error: USB 0 not found\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Perfrom file read */
|
||||
rc = fs_read(file_name, get_load_addr(), 0, 0, &act_read);
|
||||
if (rc)
|
||||
return 0;
|
||||
|
||||
return act_read;
|
||||
}
|
||||
|
||||
static int is_usb_active(void)
|
||||
{
|
||||
return 1;
|
||||
}
|
||||
|
||||
#else /* defined(CONFIG_USB_STORAGE) && defined (CONFIG_BLK) */
|
||||
static size_t usb_read_file(const char *file_name)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int is_usb_active(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
#endif /* defined(CONFIG_USB_STORAGE) && defined (CONFIG_BLK) */
|
||||
|
||||
/********************************************************************
|
||||
* Network services
|
||||
********************************************************************/
|
||||
#ifdef CONFIG_CMD_NET
|
||||
static size_t tftp_read_file(const char *file_name)
|
||||
{
|
||||
/* update global variable load_addr before tftp file from network */
|
||||
load_addr = get_load_addr();
|
||||
return net_loop(TFTPGET);
|
||||
}
|
||||
|
||||
static int is_tftp_active(void)
|
||||
{
|
||||
return 1;
|
||||
}
|
||||
|
||||
#else
|
||||
static size_t tftp_read_file(const char *file_name)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int is_tftp_active(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
#endif /* CONFIG_CMD_NET */
|
||||
|
||||
enum bubt_devices {
|
||||
BUBT_DEV_NET = 0,
|
||||
BUBT_DEV_USB,
|
||||
BUBT_DEV_MMC,
|
||||
BUBT_DEV_SPI,
|
||||
BUBT_DEV_NAND,
|
||||
|
||||
BUBT_MAX_DEV
|
||||
};
|
||||
|
||||
struct bubt_dev bubt_devs[BUBT_MAX_DEV] = {
|
||||
{"tftp", tftp_read_file, NULL, is_tftp_active},
|
||||
{"usb", usb_read_file, NULL, is_usb_active},
|
||||
{"mmc", mmc_read_file, mmc_burn_image, is_mmc_active},
|
||||
{"spi", NULL, spi_burn_image, is_spi_active},
|
||||
{"nand", NULL, nand_burn_image, is_nand_active},
|
||||
};
|
||||
|
||||
static int bubt_write_file(struct bubt_dev *dst, size_t image_size)
|
||||
{
|
||||
if (!dst->write) {
|
||||
printf("Error: Write not supported on device %s\n", dst->name);
|
||||
return -ENOTSUPP;
|
||||
}
|
||||
|
||||
return dst->write(image_size);
|
||||
}
|
||||
|
||||
#if defined(CONFIG_ARMADA_8K)
|
||||
u32 do_checksum32(u32 *start, int32_t len)
|
||||
{
|
||||
u32 sum = 0;
|
||||
u32 *startp = start;
|
||||
|
||||
do {
|
||||
sum += *startp;
|
||||
startp++;
|
||||
len -= 4;
|
||||
} while (len > 0);
|
||||
|
||||
return sum;
|
||||
}
|
||||
|
||||
static int check_image_header(void)
|
||||
{
|
||||
struct mvebu_image_header *hdr =
|
||||
(struct mvebu_image_header *)get_load_addr();
|
||||
u32 header_len = hdr->prolog_size;
|
||||
u32 checksum;
|
||||
u32 checksum_ref = hdr->prolog_checksum;
|
||||
|
||||
/*
|
||||
* For now compare checksum, and magic. Later we can
|
||||
* verify more stuff on the header like interface type, etc
|
||||
*/
|
||||
if (hdr->magic != MAIN_HDR_MAGIC) {
|
||||
printf("ERROR: Bad MAGIC 0x%08x != 0x%08x\n",
|
||||
hdr->magic, MAIN_HDR_MAGIC);
|
||||
return -ENOEXEC;
|
||||
}
|
||||
|
||||
/* The checksum value is discarded from checksum calculation */
|
||||
hdr->prolog_checksum = 0;
|
||||
|
||||
checksum = do_checksum32((u32 *)hdr, header_len);
|
||||
if (checksum != checksum_ref) {
|
||||
printf("Error: Bad Image checksum. 0x%x != 0x%x\n",
|
||||
checksum, checksum_ref);
|
||||
return -ENOEXEC;
|
||||
}
|
||||
|
||||
/* Restore the checksum before writing */
|
||||
hdr->prolog_checksum = checksum_ref;
|
||||
printf("Image checksum...OK!\n");
|
||||
|
||||
return 0;
|
||||
}
|
||||
#elif defined(CONFIG_ARMADA_3700) /* Armada 3700 */
|
||||
static int check_image_header(void)
|
||||
{
|
||||
struct common_tim_data *hdr = (struct common_tim_data *)get_load_addr();
|
||||
int image_num;
|
||||
u8 hash_160_output[SHA1_SUM_LEN];
|
||||
u8 hash_256_output[SHA256_SUM_LEN];
|
||||
sha1_context hash1_text;
|
||||
sha256_context hash256_text;
|
||||
u8 *hash_output;
|
||||
u32 hash_algorithm_id;
|
||||
u32 image_size_to_hash;
|
||||
u32 flash_entry_addr;
|
||||
u32 *hash_value;
|
||||
u32 internal_hash[HASH_SUM_LEN];
|
||||
const u8 *buff;
|
||||
u32 num_of_image = hdr->num_images;
|
||||
u32 version = hdr->version;
|
||||
u32 trusted = hdr->trusted;
|
||||
|
||||
/* bubt checksum validation only supports nontrusted images */
|
||||
if (trusted == 1) {
|
||||
printf("bypass image validation, ");
|
||||
printf("only untrusted image is supported now\n");
|
||||
return 0;
|
||||
}
|
||||
/* only supports image version 3.5 and 3.6 */
|
||||
if (version != IMAGE_VERSION_3_5_0 && version != IMAGE_VERSION_3_6_0) {
|
||||
printf("Error: Unsupported Image version = 0x%08x\n", version);
|
||||
return -ENOEXEC;
|
||||
}
|
||||
/* validate images hash value */
|
||||
for (image_num = 0; image_num < num_of_image; image_num++) {
|
||||
struct mvebu_image_info *info =
|
||||
(struct mvebu_image_info *)(get_load_addr() +
|
||||
sizeof(struct common_tim_data) +
|
||||
image_num * sizeof(struct mvebu_image_info));
|
||||
hash_algorithm_id = info->hash_algorithm_id;
|
||||
image_size_to_hash = info->image_size_to_hash;
|
||||
flash_entry_addr = info->flash_entry_addr;
|
||||
hash_value = info->hash;
|
||||
buff = (const u8 *)(get_load_addr() + flash_entry_addr);
|
||||
|
||||
if (image_num == 0) {
|
||||
/*
|
||||
* The first image includes hash values in its content.
|
||||
* For hash calculation, we need to save the original
|
||||
* hash values to a local variable that will be
|
||||
* copied back for comparsion and set all zeros to
|
||||
* the orignal hash values for calculating new value.
|
||||
* First image original format :
|
||||
* x...x (datum1) x...x(orig. hash values) x...x(datum2)
|
||||
* Replaced first image format :
|
||||
* x...x (datum1) 0...0(hash values) x...x(datum2)
|
||||
*/
|
||||
memcpy(internal_hash, hash_value,
|
||||
sizeof(internal_hash));
|
||||
memset(hash_value, 0, sizeof(internal_hash));
|
||||
}
|
||||
if (image_size_to_hash == 0) {
|
||||
printf("Warning: Image_%d hash checksum is disabled, ",
|
||||
image_num);
|
||||
printf("skip the image validation.\n");
|
||||
continue;
|
||||
}
|
||||
switch (hash_algorithm_id) {
|
||||
case SHA1_SUM_LEN:
|
||||
sha1_starts(&hash1_text);
|
||||
sha1_update(&hash1_text, buff, image_size_to_hash);
|
||||
sha1_finish(&hash1_text, hash_160_output);
|
||||
hash_output = hash_160_output;
|
||||
break;
|
||||
case SHA256_SUM_LEN:
|
||||
sha256_starts(&hash256_text);
|
||||
sha256_update(&hash256_text, buff, image_size_to_hash);
|
||||
sha256_finish(&hash256_text, hash_256_output);
|
||||
hash_output = hash_256_output;
|
||||
break;
|
||||
default:
|
||||
printf("Error: Unsupported hash_algorithm_id = %d\n",
|
||||
hash_algorithm_id);
|
||||
return -ENOEXEC;
|
||||
}
|
||||
if (image_num == 0)
|
||||
memcpy(hash_value, internal_hash,
|
||||
sizeof(internal_hash));
|
||||
if (memcmp(hash_value, hash_output, hash_algorithm_id) != 0) {
|
||||
printf("Error: Image_%d checksum is not correct\n",
|
||||
image_num);
|
||||
return -ENOEXEC;
|
||||
}
|
||||
}
|
||||
printf("Image checksum...OK!\n");
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#else /* Not ARMADA? */
|
||||
static int check_image_header(void)
|
||||
{
|
||||
printf("bubt cmd does not support this SoC device or family!\n");
|
||||
return -ENOEXEC;
|
||||
}
|
||||
#endif
|
||||
|
||||
static int bubt_verify(size_t image_size)
|
||||
{
|
||||
int err;
|
||||
|
||||
/* Check a correct image header exists */
|
||||
err = check_image_header();
|
||||
if (err) {
|
||||
printf("Error: Image header verification failed\n");
|
||||
return err;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int bubt_read_file(struct bubt_dev *src)
|
||||
{
|
||||
size_t image_size;
|
||||
|
||||
if (!src->read) {
|
||||
printf("Error: Read not supported on device \"%s\"\n",
|
||||
src->name);
|
||||
return 0;
|
||||
}
|
||||
|
||||
image_size = src->read(net_boot_file_name);
|
||||
if (image_size <= 0) {
|
||||
printf("Error: Failed to read file %s from %s\n",
|
||||
net_boot_file_name, src->name);
|
||||
return 0;
|
||||
}
|
||||
|
||||
return image_size;
|
||||
}
|
||||
|
||||
static int bubt_is_dev_active(struct bubt_dev *dev)
|
||||
{
|
||||
if (!dev->active) {
|
||||
printf("Device \"%s\" not supported by U-BOOT image\n",
|
||||
dev->name);
|
||||
return 0;
|
||||
}
|
||||
|
||||
if (!dev->active()) {
|
||||
printf("Device \"%s\" is inactive\n", dev->name);
|
||||
return 0;
|
||||
}
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
struct bubt_dev *find_bubt_dev(char *dev_name)
|
||||
{
|
||||
int dev;
|
||||
|
||||
for (dev = 0; dev < BUBT_MAX_DEV; dev++) {
|
||||
if (strcmp(bubt_devs[dev].name, dev_name) == 0)
|
||||
return &bubt_devs[dev];
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#define DEFAULT_BUBT_SRC "tftp"
|
||||
|
||||
#ifndef DEFAULT_BUBT_DST
|
||||
#ifdef CONFIG_MVEBU_SPI_BOOT
|
||||
#define DEFAULT_BUBT_DST "spi"
|
||||
#elif defined(CONFIG_MVEBU_NAND_BOOT)
|
||||
#define DEFAULT_BUBT_DST "nand"
|
||||
#elif defined(CONFIG_MVEBU_MMC_BOOT)
|
||||
#define DEFAULT_BUBT_DST "mmc"
|
||||
else
|
||||
#define DEFAULT_BUBT_DST "error"
|
||||
#endif
|
||||
#endif /* DEFAULT_BUBT_DST */
|
||||
|
||||
int do_bubt_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
|
||||
{
|
||||
struct bubt_dev *src, *dst;
|
||||
size_t image_size;
|
||||
char src_dev_name[8];
|
||||
char dst_dev_name[8];
|
||||
char *name;
|
||||
int err;
|
||||
|
||||
if (argc < 2)
|
||||
copy_filename(net_boot_file_name,
|
||||
CONFIG_MVEBU_UBOOT_DFLT_NAME,
|
||||
sizeof(net_boot_file_name));
|
||||
else
|
||||
copy_filename(net_boot_file_name, argv[1],
|
||||
sizeof(net_boot_file_name));
|
||||
|
||||
if (argc >= 3) {
|
||||
strncpy(dst_dev_name, argv[2], 8);
|
||||
} else {
|
||||
name = DEFAULT_BUBT_DST;
|
||||
strncpy(dst_dev_name, name, 8);
|
||||
}
|
||||
|
||||
if (argc >= 4)
|
||||
strncpy(src_dev_name, argv[3], 8);
|
||||
else
|
||||
strncpy(src_dev_name, DEFAULT_BUBT_SRC, 8);
|
||||
|
||||
/* Figure out the destination device */
|
||||
dst = find_bubt_dev(dst_dev_name);
|
||||
if (!dst) {
|
||||
printf("Error: Unknown destination \"%s\"\n", dst_dev_name);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
if (!bubt_is_dev_active(dst))
|
||||
return -ENODEV;
|
||||
|
||||
/* Figure out the source device */
|
||||
src = find_bubt_dev(src_dev_name);
|
||||
if (!src) {
|
||||
printf("Error: Unknown source \"%s\"\n", src_dev_name);
|
||||
return 1;
|
||||
}
|
||||
|
||||
if (!bubt_is_dev_active(src))
|
||||
return -ENODEV;
|
||||
|
||||
printf("Burning U-BOOT image \"%s\" from \"%s\" to \"%s\"\n",
|
||||
net_boot_file_name, src->name, dst->name);
|
||||
|
||||
image_size = bubt_read_file(src);
|
||||
if (!image_size)
|
||||
return -EIO;
|
||||
|
||||
err = bubt_verify(image_size);
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
err = bubt_write_file(dst, image_size);
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
U_BOOT_CMD(
|
||||
bubt, 4, 0, do_bubt_cmd,
|
||||
"Burn a u-boot image to flash",
|
||||
"[file-name] [destination [source]]\n"
|
||||
"\t-file-name The image file name to burn. Default = flash-image.bin\n"
|
||||
"\t-destination Flash to burn to [spi, nand, mmc]. Default = active boot device\n"
|
||||
"\t-source The source to load image from [tftp, usb, mmc]. Default = tftp\n"
|
||||
"Examples:\n"
|
||||
"\tbubt - Burn flash-image.bin from tftp to active boot device\n"
|
||||
"\tbubt flash-image-new.bin nand - Burn flash-image-new.bin from tftp to NAND flash\n"
|
||||
"\tbubt backup-flash-image.bin mmc usb - Burn backup-flash-image.bin from usb to MMC\n"
|
||||
|
||||
);
|
||||
83
cmd/pci.c
83
cmd/pci.c
@ -92,6 +92,77 @@ static void pci_show_regs(pci_dev_t dev, struct pci_reg_info *regs)
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_DM_PCI
|
||||
int pci_bar_show(struct udevice *dev)
|
||||
{
|
||||
u8 header_type;
|
||||
int bar_cnt, bar_id, mem_type;
|
||||
bool is_64, is_io;
|
||||
u32 base_low, base_high;
|
||||
u32 size_low, size_high;
|
||||
u64 base, size;
|
||||
u32 reg_addr;
|
||||
int prefetchable;
|
||||
|
||||
dm_pci_read_config8(dev, PCI_HEADER_TYPE, &header_type);
|
||||
|
||||
if (header_type == PCI_HEADER_TYPE_CARDBUS) {
|
||||
printf("CardBus doesn't support BARs\n");
|
||||
return -ENOSYS;
|
||||
}
|
||||
|
||||
bar_cnt = (header_type == PCI_HEADER_TYPE_NORMAL) ? 6 : 2;
|
||||
|
||||
printf("ID Base Size Width Type\n");
|
||||
printf("----------------------------------------------------------\n");
|
||||
|
||||
bar_id = 0;
|
||||
reg_addr = PCI_BASE_ADDRESS_0;
|
||||
while (bar_cnt) {
|
||||
dm_pci_read_config32(dev, reg_addr, &base_low);
|
||||
dm_pci_write_config32(dev, reg_addr, 0xffffffff);
|
||||
dm_pci_read_config32(dev, reg_addr, &size_low);
|
||||
dm_pci_write_config32(dev, reg_addr, base_low);
|
||||
reg_addr += 4;
|
||||
|
||||
base = base_low & ~0xf;
|
||||
size = size_low & ~0xf;
|
||||
base_high = 0x0;
|
||||
size_high = 0xffffffff;
|
||||
is_64 = 0;
|
||||
prefetchable = base_low & PCI_BASE_ADDRESS_MEM_PREFETCH;
|
||||
is_io = base_low & PCI_BASE_ADDRESS_SPACE_IO;
|
||||
mem_type = base_low & PCI_BASE_ADDRESS_MEM_TYPE_MASK;
|
||||
|
||||
if (mem_type == PCI_BASE_ADDRESS_MEM_TYPE_64) {
|
||||
dm_pci_read_config32(dev, reg_addr, &base_high);
|
||||
dm_pci_write_config32(dev, reg_addr, 0xffffffff);
|
||||
dm_pci_read_config32(dev, reg_addr, &size_high);
|
||||
dm_pci_write_config32(dev, reg_addr, base_high);
|
||||
bar_cnt--;
|
||||
reg_addr += 4;
|
||||
is_64 = 1;
|
||||
}
|
||||
|
||||
base = base | ((u64)base_high << 32);
|
||||
size = size | ((u64)size_high << 32);
|
||||
|
||||
if ((!is_64 && size_low) || (is_64 && size)) {
|
||||
size = ~size + 1;
|
||||
printf(" %d %#016llx %#016llx %d %s %s\n",
|
||||
bar_id, base, size, is_64 ? 64 : 32,
|
||||
is_io ? "I/O" : "MEM",
|
||||
prefetchable ? "Prefetchable" : "");
|
||||
}
|
||||
|
||||
bar_id++;
|
||||
bar_cnt--;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
static struct pci_reg_info regs_start[] = {
|
||||
{ "vendor ID", PCI_SIZE_16, PCI_VENDOR_ID },
|
||||
{ "device ID", PCI_SIZE_16, PCI_DEVICE_ID },
|
||||
@ -573,6 +644,9 @@ static int do_pci(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
|
||||
if (argc > 4)
|
||||
value = simple_strtoul(argv[4], NULL, 16);
|
||||
case 'h': /* header */
|
||||
#ifdef CONFIG_DM_PCI
|
||||
case 'b': /* bars */
|
||||
#endif
|
||||
if (argc < 3)
|
||||
goto usage;
|
||||
if ((bdf = get_pci_dev(argv[2])) == -1)
|
||||
@ -641,6 +715,11 @@ static int do_pci(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
|
||||
ret = pci_cfg_write(dev, addr, size, value);
|
||||
#endif
|
||||
break;
|
||||
#ifdef CONFIG_DM_PCI
|
||||
|
||||
case 'b': /* bars */
|
||||
return pci_bar_show(dev);
|
||||
#endif
|
||||
default:
|
||||
ret = CMD_RET_USAGE;
|
||||
break;
|
||||
@ -663,6 +742,10 @@ static char pci_help_text[] =
|
||||
#endif
|
||||
"pci header b.d.f\n"
|
||||
" - show header of PCI device 'bus.device.function'\n"
|
||||
#ifdef CONFIG_DM_PCI
|
||||
"pci bar b.d.f\n"
|
||||
" - show BARs base and size for device b.d.f'\n"
|
||||
#endif
|
||||
"pci display[.b, .w, .l] b.d.f [address] [# of objects]\n"
|
||||
" - display PCI configuration space (CFG)\n"
|
||||
"pci next[.b, .w, .l] b.d.f address\n"
|
||||
|
||||
133
common/spl/spl.c
133
common/spl/spl.c
@ -221,10 +221,10 @@ static int spl_ram_load_image(struct spl_image_info *spl_image,
|
||||
return 0;
|
||||
}
|
||||
#if defined(CONFIG_SPL_RAM_DEVICE)
|
||||
SPL_LOAD_IMAGE_METHOD(0, BOOT_DEVICE_RAM, spl_ram_load_image);
|
||||
SPL_LOAD_IMAGE_METHOD("RAM", 0, BOOT_DEVICE_RAM, spl_ram_load_image);
|
||||
#endif
|
||||
#if defined(CONFIG_SPL_DFU_SUPPORT)
|
||||
SPL_LOAD_IMAGE_METHOD(0, BOOT_DEVICE_DFU, spl_ram_load_image);
|
||||
SPL_LOAD_IMAGE_METHOD("USB DFU", 0, BOOT_DEVICE_DFU, spl_ram_load_image);
|
||||
#endif
|
||||
#endif
|
||||
|
||||
@ -269,87 +269,6 @@ __weak void board_boot_order(u32 *spl_boot_list)
|
||||
spl_boot_list[0] = spl_boot_device();
|
||||
}
|
||||
|
||||
#ifdef CONFIG_SPL_BOARD_LOAD_IMAGE
|
||||
__weak void spl_board_announce_boot_device(void) { }
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
|
||||
struct boot_device_name {
|
||||
u32 boot_dev;
|
||||
const char *name;
|
||||
};
|
||||
|
||||
struct boot_device_name boot_name_table[] = {
|
||||
#ifdef CONFIG_SPL_RAM_DEVICE
|
||||
{ BOOT_DEVICE_RAM, "RAM" },
|
||||
#endif
|
||||
#ifdef CONFIG_SPL_MMC_SUPPORT
|
||||
{ BOOT_DEVICE_MMC1, "MMC1" },
|
||||
{ BOOT_DEVICE_MMC2, "MMC2" },
|
||||
{ BOOT_DEVICE_MMC2_2, "MMC2_2" },
|
||||
#endif
|
||||
#ifdef CONFIG_SPL_NAND_SUPPORT
|
||||
{ BOOT_DEVICE_NAND, "NAND" },
|
||||
#endif
|
||||
#ifdef CONFIG_SPL_ONENAND_SUPPORT
|
||||
{ BOOT_DEVICE_ONENAND, "OneNAND" },
|
||||
#endif
|
||||
#ifdef CONFIG_SPL_NOR_SUPPORT
|
||||
{ BOOT_DEVICE_NOR, "NOR" },
|
||||
#endif
|
||||
#ifdef CONFIG_SPL_YMODEM_SUPPORT
|
||||
{ BOOT_DEVICE_UART, "UART" },
|
||||
#endif
|
||||
#if defined(CONFIG_SPL_SPI_SUPPORT) || defined(CONFIG_SPL_SPI_FLASH_SUPPORT)
|
||||
{ BOOT_DEVICE_SPI, "SPI" },
|
||||
#endif
|
||||
#ifdef CONFIG_SPL_ETH_SUPPORT
|
||||
#ifdef CONFIG_SPL_ETH_DEVICE
|
||||
{ BOOT_DEVICE_CPGMAC, "eth device" },
|
||||
#else
|
||||
{ BOOT_DEVICE_CPGMAC, "net" },
|
||||
#endif
|
||||
#endif
|
||||
#ifdef CONFIG_SPL_USBETH_SUPPORT
|
||||
{ BOOT_DEVICE_USBETH, "USB eth" },
|
||||
#endif
|
||||
#ifdef CONFIG_SPL_USB_SUPPORT
|
||||
{ BOOT_DEVICE_USB, "USB" },
|
||||
#endif
|
||||
#ifdef CONFIG_SPL_DFU_SUPPORT
|
||||
{ BOOT_DEVICE_DFU, "USB DFU" },
|
||||
#endif
|
||||
#ifdef CONFIG_SPL_SATA_SUPPORT
|
||||
{ BOOT_DEVICE_SATA, "SATA" },
|
||||
#endif
|
||||
/* Keep this entry last */
|
||||
{ BOOT_DEVICE_NONE, "unknown boot device" },
|
||||
};
|
||||
|
||||
static void announce_boot_device(u32 boot_device)
|
||||
{
|
||||
int i;
|
||||
|
||||
puts("Trying to boot from ");
|
||||
|
||||
#ifdef CONFIG_SPL_BOARD_LOAD_IMAGE
|
||||
if (boot_device == BOOT_DEVICE_BOARD) {
|
||||
spl_board_announce_boot_device();
|
||||
puts("\n");
|
||||
return;
|
||||
}
|
||||
#endif
|
||||
for (i = 0; i < ARRAY_SIZE(boot_name_table) - 1; i++) {
|
||||
if (boot_name_table[i].boot_dev == boot_device)
|
||||
break;
|
||||
}
|
||||
|
||||
printf("%s\n", boot_name_table[i].name);
|
||||
}
|
||||
#else
|
||||
static inline void announce_boot_device(u32 boot_device) { }
|
||||
#endif
|
||||
|
||||
static struct spl_image_loader *spl_ll_find_loader(uint boot_device)
|
||||
{
|
||||
struct spl_image_loader *drv =
|
||||
@ -367,19 +286,44 @@ static struct spl_image_loader *spl_ll_find_loader(uint boot_device)
|
||||
return NULL;
|
||||
}
|
||||
|
||||
static int spl_load_image(struct spl_image_info *spl_image, u32 boot_device)
|
||||
static int spl_load_image(struct spl_image_info *spl_image,
|
||||
struct spl_image_loader *loader)
|
||||
{
|
||||
struct spl_boot_device bootdev;
|
||||
struct spl_image_loader *loader = spl_ll_find_loader(boot_device);
|
||||
|
||||
bootdev.boot_device = boot_device;
|
||||
bootdev.boot_device = loader->boot_device;
|
||||
bootdev.boot_device_name = NULL;
|
||||
if (loader)
|
||||
return loader->load_image(spl_image, &bootdev);
|
||||
|
||||
return loader->load_image(spl_image, &bootdev);
|
||||
}
|
||||
|
||||
/**
|
||||
* boot_from_devices() - Try loading an booting U-Boot from a list of devices
|
||||
*
|
||||
* @spl_image: Place to put the image details if successful
|
||||
* @spl_boot_list: List of boot devices to try
|
||||
* @count: Number of elements in spl_boot_list
|
||||
* @return 0 if OK, -ve on error
|
||||
*/
|
||||
static int boot_from_devices(struct spl_image_info *spl_image,
|
||||
u32 spl_boot_list[], int count)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = 0; i < count && spl_boot_list[i] != BOOT_DEVICE_NONE; i++) {
|
||||
struct spl_image_loader *loader;
|
||||
|
||||
loader = spl_ll_find_loader(spl_boot_list[i]);
|
||||
#if defined(CONFIG_SPL_SERIAL_SUPPORT) && defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
|
||||
puts("SPL: Unsupported Boot Device!\n");
|
||||
if (loader)
|
||||
printf("Trying to boot from %s", loader->name);
|
||||
else
|
||||
puts("SPL: Unsupported Boot Device!\n");
|
||||
#endif
|
||||
if (loader && !spl_load_image(spl_image, loader))
|
||||
return 0;
|
||||
}
|
||||
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
@ -393,7 +337,6 @@ void board_init_r(gd_t *dummy1, ulong dummy2)
|
||||
BOOT_DEVICE_NONE,
|
||||
};
|
||||
struct spl_image_info spl_image;
|
||||
int i;
|
||||
|
||||
debug(">>spl:board_init_r()\n");
|
||||
|
||||
@ -420,15 +363,9 @@ void board_init_r(gd_t *dummy1, ulong dummy2)
|
||||
|
||||
memset(&spl_image, '\0', sizeof(spl_image));
|
||||
board_boot_order(spl_boot_list);
|
||||
for (i = 0; i < ARRAY_SIZE(spl_boot_list) &&
|
||||
spl_boot_list[i] != BOOT_DEVICE_NONE; i++) {
|
||||
announce_boot_device(spl_boot_list[i]);
|
||||
if (!spl_load_image(&spl_image, spl_boot_list[i]))
|
||||
break;
|
||||
}
|
||||
|
||||
if (i == ARRAY_SIZE(spl_boot_list) ||
|
||||
spl_boot_list[i] == BOOT_DEVICE_NONE) {
|
||||
if (boot_from_devices(&spl_image, spl_boot_list,
|
||||
ARRAY_SIZE(spl_boot_list))) {
|
||||
puts("SPL: failed to boot from all boot devices\n");
|
||||
hang();
|
||||
}
|
||||
|
||||
@ -245,13 +245,13 @@ static int spl_mmc_do_fs_boot(struct spl_image_info *spl_image, struct mmc *mmc)
|
||||
#endif
|
||||
#ifdef CONFIG_SPL_EXT_SUPPORT
|
||||
if (!spl_start_uboot()) {
|
||||
err = spl_load_image_ext_os(spl_image, &mmc->block_dev,
|
||||
err = spl_load_image_ext_os(spl_image, mmc_get_blk_desc(mmc),
|
||||
CONFIG_SYS_MMCSD_FS_BOOT_PARTITION);
|
||||
if (!err)
|
||||
return err;
|
||||
}
|
||||
#ifdef CONFIG_SPL_FS_LOAD_PAYLOAD_NAME
|
||||
err = spl_load_image_ext(spl_image, &mmc->block_dev,
|
||||
err = spl_load_image_ext(spl_image, mmc_get_blk_desc(mmc),
|
||||
CONFIG_SYS_MMCSD_FS_BOOT_PARTITION,
|
||||
CONFIG_SPL_FS_LOAD_PAYLOAD_NAME);
|
||||
if (!err)
|
||||
@ -355,6 +355,6 @@ int spl_mmc_load_image(struct spl_image_info *spl_image,
|
||||
return err;
|
||||
}
|
||||
|
||||
SPL_LOAD_IMAGE_METHOD(0, BOOT_DEVICE_MMC1, spl_mmc_load_image);
|
||||
SPL_LOAD_IMAGE_METHOD(0, BOOT_DEVICE_MMC2, spl_mmc_load_image);
|
||||
SPL_LOAD_IMAGE_METHOD(0, BOOT_DEVICE_MMC2_2, spl_mmc_load_image);
|
||||
SPL_LOAD_IMAGE_METHOD("MMC1", 0, BOOT_DEVICE_MMC1, spl_mmc_load_image);
|
||||
SPL_LOAD_IMAGE_METHOD("MMC2", 0, BOOT_DEVICE_MMC2, spl_mmc_load_image);
|
||||
SPL_LOAD_IMAGE_METHOD("MMC2_2", 0, BOOT_DEVICE_MMC2_2, spl_mmc_load_image);
|
||||
|
||||
@ -151,4 +151,4 @@ static int spl_nand_load_image(struct spl_image_info *spl_image,
|
||||
}
|
||||
#endif
|
||||
/* Use priorty 1 so that Ubi can override this */
|
||||
SPL_LOAD_IMAGE_METHOD(1, BOOT_DEVICE_NAND, spl_nand_load_image);
|
||||
SPL_LOAD_IMAGE_METHOD("NAND", 1, BOOT_DEVICE_NAND, spl_nand_load_image);
|
||||
|
||||
@ -51,7 +51,8 @@ int spl_net_load_image_cpgmac(struct spl_image_info *spl_image,
|
||||
|
||||
return spl_net_load_image(spl_image, bootdev);
|
||||
}
|
||||
SPL_LOAD_IMAGE_METHOD(0, BOOT_DEVICE_CPGMAC, spl_net_load_image_cpgmac);
|
||||
SPL_LOAD_IMAGE_METHOD("eth device", 0, BOOT_DEVICE_CPGMAC,
|
||||
spl_net_load_image_cpgmac);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SPL_USBETH_SUPPORT
|
||||
@ -62,5 +63,5 @@ int spl_net_load_image_usb(struct spl_image_info *spl_image,
|
||||
|
||||
return spl_net_load_image(spl_image, bootdev);
|
||||
}
|
||||
SPL_LOAD_IMAGE_METHOD(0, BOOT_DEVICE_USBETH, spl_net_load_image_usb);
|
||||
SPL_LOAD_IMAGE_METHOD("USB eth", 0, BOOT_DEVICE_USBETH, spl_net_load_image_usb);
|
||||
#endif
|
||||
|
||||
@ -71,4 +71,4 @@ static int spl_nor_load_image(struct spl_image_info *spl_image,
|
||||
|
||||
return 0;
|
||||
}
|
||||
SPL_LOAD_IMAGE_METHOD(0, BOOT_DEVICE_NOR, spl_nor_load_image);
|
||||
SPL_LOAD_IMAGE_METHOD("NOR", 0, BOOT_DEVICE_NOR, spl_nor_load_image);
|
||||
|
||||
@ -36,4 +36,5 @@ static int spl_onenand_load_image(struct spl_image_info *spl_image,
|
||||
return 0;
|
||||
}
|
||||
/* Use priorty 1 so that Ubi can override this */
|
||||
SPL_LOAD_IMAGE_METHOD(1, BOOT_DEVICE_ONENAND, spl_onenand_load_image);
|
||||
SPL_LOAD_IMAGE_METHOD("OneNAND", 1, BOOT_DEVICE_ONENAND,
|
||||
spl_onenand_load_image);
|
||||
|
||||
@ -57,4 +57,4 @@ static int spl_sata_load_image(struct spl_image_info *spl_image,
|
||||
|
||||
return 0;
|
||||
}
|
||||
SPL_LOAD_IMAGE_METHOD(0, BOOT_DEVICE_SATA, spl_sata_load_image);
|
||||
SPL_LOAD_IMAGE_METHOD("SATA", 0, BOOT_DEVICE_SATA, spl_sata_load_image);
|
||||
|
||||
@ -125,4 +125,4 @@ static int spl_spi_load_image(struct spl_image_info *spl_image,
|
||||
return err;
|
||||
}
|
||||
/* Use priorty 1 so that boards can override this */
|
||||
SPL_LOAD_IMAGE_METHOD(1, BOOT_DEVICE_SPI, spl_spi_load_image);
|
||||
SPL_LOAD_IMAGE_METHOD("SPI", 1, BOOT_DEVICE_SPI, spl_spi_load_image);
|
||||
|
||||
@ -78,5 +78,5 @@ out:
|
||||
return ret;
|
||||
}
|
||||
/* Use priorty 0 so that Ubi will override NAND and ONENAND methods */
|
||||
SPL_LOAD_IMAGE_METHOD(0, BOOT_DEVICE_NAND, spl_ubi_load_image);
|
||||
SPL_LOAD_IMAGE_METHOD(0, BOOT_DEVICE_ONENAND, spl_ubi_load_image);
|
||||
SPL_LOAD_IMAGE_METHOD("NAND", 0, BOOT_DEVICE_NAND, spl_ubi_load_image);
|
||||
SPL_LOAD_IMAGE_METHOD("OneNAND", 0, BOOT_DEVICE_ONENAND, spl_ubi_load_image);
|
||||
|
||||
@ -65,4 +65,4 @@ static int spl_usb_load_image(struct spl_image_info *spl_image,
|
||||
|
||||
return 0;
|
||||
}
|
||||
SPL_LOAD_IMAGE_METHOD(0, BOOT_DEVICE_USB, spl_usb_load_image);
|
||||
SPL_LOAD_IMAGE_METHOD("USB", 0, BOOT_DEVICE_USB, spl_usb_load_image);
|
||||
|
||||
@ -132,4 +132,4 @@ end_stream:
|
||||
printf("Loaded %d bytes\n", size);
|
||||
return 0;
|
||||
}
|
||||
SPL_LOAD_IMAGE_METHOD(0, BOOT_DEVICE_UART, spl_ymodem_load_image);
|
||||
SPL_LOAD_IMAGE_METHOD("UART", 0, BOOT_DEVICE_UART, spl_ymodem_load_image);
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in New Issue
Block a user