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powerpc/85xx: Add the workaround for erratum ELBC-A001 (enable on P4080)

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Simultaneous FCM and GPCM or UPM operation may erroneously trigger bus
monitor timeout.  Set timeout to maximum to avoid.

Based on a patch from Lan Chunhe <b25806@freescale.com>

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This commit is contained in:
Kumar Gala 2011-01-13 02:58:23 -06:00
parent 868da5936e
commit f133796da8
4 changed files with 13 additions and 2 deletions
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3
arch/powerpc/cpu/mpc85xx/cmd_errata.c
View File

@ -65,6 +65,9 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
#ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A003
puts("Work-around for Erratum CPC-A003 enabled\n");
#endif
#ifdef CONFIG_SYS_FSL_ERRATUM_ELBC_A001
puts("Work-around for Erratum ELBC-A001 enabled\n");
#endif
return 0;
}

7
arch/powerpc/cpu/mpc8xxx/fsl_lbc.c
View File

@ -1,5 +1,5 @@
/*
* Copyright 2010 Freescale Semiconductor, Inc.
* Copyright 2010-2011 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
@ -34,6 +34,11 @@ void init_early_memctl_regs(void)
{
uint init_br1 = 1;
#ifdef CONFIG_SYS_FSL_ERRATUM_ELBC_A001
/* Set the local bus monitor timeout value to the maximum */
clrsetbits_be32(&(LBC_BASE_ADDR)->lbcr, LBCR_BMT|LBCR_BMTPS, 0xf);
#endif
#ifdef CONFIG_MPC85xx
/* if cs1 is already set via debugger, leave cs0/cs1 alone */
if (get_lbc_br(1) & BR_V)

4
arch/powerpc/include/asm/fsl_lbc.h
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@ -1,5 +1,5 @@
/*
* Copyright (C) 2004-2008,2010 Freescale Semiconductor, Inc.
* Copyright (C) 2004-2008,2010-2011 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
@ -295,6 +295,8 @@ void lbc_sdram_init(void);
#define LBCR_EPAR_SHIFT 16
#define LBCR_BMT 0x0000FF00
#define LBCR_BMT_SHIFT 8
#define LBCR_BMTPS 0x0000000F
#define LBCR_BMTPS_SHIFT 0
/* LCRR - Clock Ratio Register
*/

1
include/configs/P4080DS.h
View File

@ -43,5 +43,6 @@
#define CONFIG_SYS_FSL_ERRATUM_CPC_A002
#define CONFIG_SYS_FSL_ERRATUM_CPC_A003
#define CONFIG_SYS_P4080_ERRATUM_SERDES8
#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
#include "corenet_ds.h"