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Coding style cleanup, update CHANGELOG

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Signed-off-by: Wolfgang Denk <wd@denx.de>
This commit is contained in:
Wolfgang Denk
2008-09-13 02:23:05 +02:00
parent 0c32565f53
commit f12e4549b6
26 changed files with 979 additions and 215 deletions
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1
board/a3000/a3000.c
View File

@@ -115,4 +115,3 @@ int board_eth_init(bd_t *bis)
{
return pci_eth_init(bis);
}

1
board/amirix/ap1000/ap1000.c
View File

@@ -703,4 +703,3 @@ int board_eth_init(bd_t *bis)
{
return pci_eth_init(bis);
}

1
board/ap325rxa/u-boot.lds
View File

@@ -103,4 +103,3 @@ SECTIONS
PROVIDE (_end = .);
}

64
board/mucmc52/mucmc52.c
View File

@@ -192,22 +192,22 @@ phys_size_t initdram (int board_type)
#endif /* CFG_RAMBOOT */
/*
* On MPC5200B we need to set the special configuration delay in the
* DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM
* Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190:
*
* "The SDelay should be written to a value of 0x00000004. It is
* required to account for changes caused by normal wafer processing
* parameters."
*/
svr = get_svr();
pvr = get_pvr();
if ((SVR_MJREV(svr) >= 2) &&
(PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4)) {
* On MPC5200B we need to set the special configuration delay in the
* DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM
* Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190:
*
* "The SDelay should be written to a value of 0x00000004. It is
* required to account for changes caused by normal wafer processing
* parameters."
*/
svr = get_svr();
pvr = get_pvr();
if ((SVR_MJREV(svr) >= 2) &&
(PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4)) {
out_be32 ((unsigned __iomem *)MPC5XXX_SDRAM_SDELAY, 0x04);
__asm__ volatile ("sync");
}
out_be32 ((unsigned __iomem *)MPC5XXX_SDRAM_SDELAY, 0x04);
__asm__ volatile ("sync");
}
return dramsize + dramsize2;
}
@@ -339,14 +339,14 @@ int misc_init_r (void)
free (str);
#endif /* CONFIG_PREBOOT */
out_8 ((volatile uchar *)(CFG_DISPLAY_BASE + 0x38), ' ');
out_8 ((volatile uchar *)(CFG_DISPLAY_BASE + 0x39), ' ');
out_8 ((volatile uchar *)(CFG_DISPLAY_BASE + 0x3A), ' ');
out_8 ((volatile uchar *)(CFG_DISPLAY_BASE + 0x3B), ' ');
out_8 ((volatile uchar *)(CFG_DISPLAY_BASE + 0x3C), ' ');
out_8 ((volatile uchar *)(CFG_DISPLAY_BASE + 0x3D), ' ');
out_8 ((volatile uchar *)(CFG_DISPLAY_BASE + 0x3E), ' ');
out_8 ((volatile uchar *)(CFG_DISPLAY_BASE + 0x3F), ' ');
out_8 ((volatile uchar *)(CFG_DISPLAY_BASE + 0x38), ' ');
out_8 ((volatile uchar *)(CFG_DISPLAY_BASE + 0x39), ' ');
out_8 ((volatile uchar *)(CFG_DISPLAY_BASE + 0x3A), ' ');
out_8 ((volatile uchar *)(CFG_DISPLAY_BASE + 0x3B), ' ');
out_8 ((volatile uchar *)(CFG_DISPLAY_BASE + 0x3C), ' ');
out_8 ((volatile uchar *)(CFG_DISPLAY_BASE + 0x3D), ' ');
out_8 ((volatile uchar *)(CFG_DISPLAY_BASE + 0x3E), ' ');
out_8 ((volatile uchar *)(CFG_DISPLAY_BASE + 0x3F), ' ');
return 0;
}
@@ -365,16 +365,16 @@ int board_early_init_r (void)
int last_stage_init (void)
{
out_8 ((volatile uchar *)(CFG_DISPLAY_BASE + 0x38), 'M');
out_8 ((volatile uchar *)(CFG_DISPLAY_BASE + 0x39), 'U');
out_8 ((volatile uchar *)(CFG_DISPLAY_BASE + 0x3A), 'C');
out_8 ((volatile uchar *)(CFG_DISPLAY_BASE + 0x3B), '.');
out_8 ((volatile uchar *)(CFG_DISPLAY_BASE + 0x3C), 'M');
out_8 ((volatile uchar *)(CFG_DISPLAY_BASE + 0x3D), 'C');
out_8 ((volatile uchar *)(CFG_DISPLAY_BASE + 0x3E), '5');
out_8 ((volatile uchar *)(CFG_DISPLAY_BASE + 0x3F), '2');
out_8 ((volatile uchar *)(CFG_DISPLAY_BASE + 0x38), 'M');
out_8 ((volatile uchar *)(CFG_DISPLAY_BASE + 0x39), 'U');
out_8 ((volatile uchar *)(CFG_DISPLAY_BASE + 0x3A), 'C');
out_8 ((volatile uchar *)(CFG_DISPLAY_BASE + 0x3B), '.');
out_8 ((volatile uchar *)(CFG_DISPLAY_BASE + 0x3C), 'M');
out_8 ((volatile uchar *)(CFG_DISPLAY_BASE + 0x3D), 'C');
out_8 ((volatile uchar *)(CFG_DISPLAY_BASE + 0x3E), '5');
out_8 ((volatile uchar *)(CFG_DISPLAY_BASE + 0x3F), '2');
return 0;
return 0;
}
#if defined(CONFIG_HW_WATCHDOG)

1
board/purple/purple.c
View File

@@ -282,4 +282,3 @@ int board_eth_init(bd_t *bis)
return plb2800_eth_initialize(bis);
}
#endif

32
board/samsung/smdk6400/lowlevel_init.S
View File

@@ -2,7 +2,7 @@
* Memory Setup stuff - taken from blob memsetup.S
*
* Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and
* Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl)
* Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl)
*
* Modified for the Samsung SMDK2410 by
* (C) Copyright 2002
@@ -73,8 +73,8 @@ lowlevel_init:
ldr r1, [r0]
str r1, [r0]
ldr r0, =ELFIN_VIC0_BASE_ADDR @0x71200000
ldr r1, =ELFIN_VIC1_BASE_ADDR @0x71300000
ldr r0, =ELFIN_VIC0_BASE_ADDR @0x71200000
ldr r1, =ELFIN_VIC1_BASE_ADDR @0x71300000
/* Disable all interrupts (VIC0 and VIC1) */
mvn r3, #0x0
@@ -107,11 +107,11 @@ lowlevel_init:
bl mem_ctrl_asm_init
/* Wakeup support. Don't know if it's going to be used, untested. */
ldr r0, =(ELFIN_CLOCK_POWER_BASE + RST_STAT_OFFSET)
ldr r1, [r0]
bic r1, r1, #0xfffffff7
cmp r1, #0x8
beq wakeup_reset
ldr r0, =(ELFIN_CLOCK_POWER_BASE + RST_STAT_OFFSET)
ldr r1, [r0]
bic r1, r1, #0xfffffff7
cmp r1, #0x8
beq wakeup_reset
1:
mov lr, r12
@@ -124,10 +124,10 @@ wakeup_reset:
ldr r1, [r0]
str r1, [r0]
/* LED test */
ldr r0, =ELFIN_GPIO_BASE
ldr r1, =0x3000
str r1, [r0, #GPNDAT_OFFSET]
/* LED test */
ldr r0, =ELFIN_GPIO_BASE
ldr r1, =0x3000
str r1, [r0, #GPNDAT_OFFSET]
/* Load return address and jump to kernel */
ldr r0, =(ELFIN_CLOCK_POWER_BASE + INF_REG0_OFFSET)
@@ -201,7 +201,7 @@ wait_for_async:
str r1, [r0, #MPLL_LOCK_OFFSET]
/* Set Clock Divider */
ldr r1, [r0, #CLK_DIV0_OFFSET]
ldr r1, [r0, #CLK_DIV0_OFFSET]
bic r1, r1, #0x30000
bic r1, r1, #0xff00
bic r1, r1, #0xff
@@ -252,7 +252,7 @@ uart_asm_init:
/* set GPIO to enable UART */
ldr r0, =ELFIN_GPIO_BASE
ldr r1, =0x220022
str r1, [r0, #GPACON_OFFSET]
str r1, [r0, #GPACON_OFFSET]
mov pc, lr
#endif
@@ -265,11 +265,11 @@ nand_asm_init:
ldr r1, [r0, #NFCONF_OFFSET]
orr r1, r1, #0x70
orr r1, r1, #0x7700
str r1, [r0, #NFCONF_OFFSET]
str r1, [r0, #NFCONF_OFFSET]
ldr r1, [r0, #NFCONT_OFFSET]
orr r1, r1, #0x07
str r1, [r0, #NFCONT_OFFSET]
str r1, [r0, #NFCONT_OFFSET]
mov pc, lr
#endif

1
board/sh7785lcr/config.mk
View File

@@ -23,4 +23,3 @@
# NOTE: Must match value used in u-boot.lds (in this directory).
#
TEXT_BASE = 0x0ff80000

1
board/sh7785lcr/lowlevel_init.S
View File

@@ -315,4 +315,3 @@ CS_I2C_WCR_D: .long 0x00000003
CCR_A: .long 0xff00001c
CCR_D: .long 0x0000090b

1
board/sh7785lcr/rtl8169.h
View File

@@ -55,4 +55,3 @@ const unsigned short EEPROM_W_Data_8169_B[] = {
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000
};

1
board/sh7785lcr/rtl8169_mac.c
View File

@@ -346,4 +346,3 @@ U_BOOT_CMD(
"\n"
" - print MAC address for RTL8110\n"
);

1
board/sh7785lcr/selfcheck.c
View File

@@ -170,4 +170,3 @@ U_BOOT_CMD(
"hwtest sata - check SiI3512 ID\n"
"hwtest pci - output PCI slot device ID\n"
);

1
board/sh7785lcr/u-boot.lds
View File

@@ -94,4 +94,3 @@ SECTIONS
PROVIDE (_end = .);
}

1
board/sl8245/sl8245.c
View File

@@ -77,4 +77,3 @@ int board_eth_init(bd_t *bis)
#endif
return rc;
}

1
board/stxssa/stxssa.c
View File

@@ -407,4 +407,3 @@ int board_eth_init(bd_t *bis)
cpu_eth_init(bis); /* Initialize TSECs first */
return pci_eth_init(bis);
}