From 0ce3639d6f612d3fc215474a45075717d4e7aaa8 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Thu, 11 Jun 2020 10:53:49 +0200 Subject: [PATCH 01/79] board: amlogic: move boards doc into doc/board/amlogic Move the natural text Amlogic board README files to doc/board/amlogic into reStructuredText and : - add reStructuredText markup for bash code - fix secondary titles markup - move board support into global support matrix Signed-off-by: Neil Armstrong --- board/amlogic/p200/README.nanopi-k2 | 98 ------------- board/amlogic/p200/README.p200 | 102 ------------- board/amlogic/p201/README.p201 | 102 ------------- board/amlogic/p212/README.khadas-vim | 101 ------------- board/amlogic/p212/README.libretech-ac | 102 ------------- board/amlogic/p212/README.libretech-cc | 134 ----------------- board/amlogic/p212/README.p212 | 102 ------------- board/amlogic/q200/README.khadas-vim2 | 102 ------------- board/amlogic/q200/README.q200 | 101 ------------- board/amlogic/s400/README | 109 -------------- board/amlogic/sei510/README | 122 ---------------- board/amlogic/sei610/README | 118 --------------- board/amlogic/u200/README | 127 ---------------- board/amlogic/w400/README.khadas-vim3 | 131 ----------------- board/amlogic/w400/README.khadas-vim3l | 131 ----------------- board/amlogic/w400/README.odroid-n2 | 129 ----------------- board/amlogic/w400/README.w400 | 129 ----------------- doc/board/amlogic/index.rst | 95 ++++++++++++ doc/board/amlogic/khadas-vim.rst | 101 +++++++++++++ doc/board/amlogic/khadas-vim2.rst | 102 +++++++++++++ doc/board/amlogic/khadas-vim3.rst | 132 +++++++++++++++++ doc/board/amlogic/khadas-vim3l.rst | 130 +++++++++++++++++ doc/board/amlogic/libretech-ac.rst | 110 ++++++++++++++ doc/board/amlogic/libretech-cc.rst | 135 +++++++++++++++++ doc/board/amlogic/nanopi-k2.rst | 104 +++++++++++++ .../board/amlogic/odroid-c2.rst | 52 ++++--- doc/board/amlogic/odroid-n2.rst | 130 +++++++++++++++++ doc/board/amlogic/p200.rst | 102 +++++++++++++ doc/board/amlogic/p201.rst | 102 +++++++++++++ doc/board/amlogic/p212.rst | 102 +++++++++++++ doc/board/amlogic/q200.rst | 101 +++++++++++++ doc/board/amlogic/s400.rst | 109 ++++++++++++++ doc/board/amlogic/sei510.rst | 130 +++++++++++++++++ doc/board/amlogic/sei610.rst | 133 +++++++++++++++++ doc/board/amlogic/u200.rst | 135 +++++++++++++++++ doc/board/amlogic/w400.rst | 137 ++++++++++++++++++ doc/board/index.rst | 1 + 37 files changed, 2116 insertions(+), 1967 deletions(-) delete mode 100644 board/amlogic/p200/README.nanopi-k2 delete mode 100644 board/amlogic/p200/README.p200 delete mode 100644 board/amlogic/p201/README.p201 delete mode 100644 board/amlogic/p212/README.khadas-vim delete mode 100644 board/amlogic/p212/README.libretech-ac delete mode 100644 board/amlogic/p212/README.libretech-cc delete mode 100644 board/amlogic/p212/README.p212 delete mode 100644 board/amlogic/q200/README.khadas-vim2 delete mode 100644 board/amlogic/q200/README.q200 delete mode 100644 board/amlogic/s400/README delete mode 100644 board/amlogic/sei510/README delete mode 100644 board/amlogic/sei610/README delete mode 100644 board/amlogic/u200/README delete mode 100644 board/amlogic/w400/README.khadas-vim3 delete mode 100644 board/amlogic/w400/README.khadas-vim3l delete mode 100644 board/amlogic/w400/README.odroid-n2 delete mode 100644 board/amlogic/w400/README.w400 create mode 100644 doc/board/amlogic/index.rst create mode 100644 doc/board/amlogic/khadas-vim.rst create mode 100644 doc/board/amlogic/khadas-vim2.rst create mode 100644 doc/board/amlogic/khadas-vim3.rst create mode 100644 doc/board/amlogic/khadas-vim3l.rst create mode 100644 doc/board/amlogic/libretech-ac.rst create mode 100644 doc/board/amlogic/libretech-cc.rst create mode 100644 doc/board/amlogic/nanopi-k2.rst rename board/amlogic/p200/README.odroid-c2 => doc/board/amlogic/odroid-c2.rst (56%) create mode 100644 doc/board/amlogic/odroid-n2.rst create mode 100644 doc/board/amlogic/p200.rst create mode 100644 doc/board/amlogic/p201.rst create mode 100644 doc/board/amlogic/p212.rst create mode 100644 doc/board/amlogic/q200.rst create mode 100644 doc/board/amlogic/s400.rst create mode 100644 doc/board/amlogic/sei510.rst create mode 100644 doc/board/amlogic/sei610.rst create mode 100644 doc/board/amlogic/u200.rst create mode 100644 doc/board/amlogic/w400.rst diff --git a/board/amlogic/p200/README.nanopi-k2 b/board/amlogic/p200/README.nanopi-k2 deleted file mode 100644 index c8dec3569b..0000000000 --- a/board/amlogic/p200/README.nanopi-k2 +++ /dev/null @@ -1,98 +0,0 @@ -U-Boot for NanoPi-K2 -==================== - -NanoPi-K2 is a single board computer manufactured by FriendlyElec -with the following specifications: - - - Amlogic S905 ARM Cortex-A53 quad-core SoC @ 1.5GHz - - ARM Mali 450 GPU - - 2GB DDR3 SDRAM - - Gigabit Ethernet - - HDMI 2.0 4K/60Hz display - - 40-pin GPIO header - - 4 x USB 2.0 Host, 1 x USB OTG - - eMMC, microSD - - Infrared receiver - -Schematics are available on the manufacturer website. - -Currently the u-boot port supports the following devices: - - serial - - eMMC, microSD - - Ethernet - -u-boot compilation -================== - - > export CROSS_COMPILE=aarch64-none-elf- - > make nanopi-k2_defconfig - > make - -Image creation -============== - -Amlogic doesn't provide sources for the firmware and for tools needed -to create the bootloader image, so it is necessary to obtain them from -the git tree published by the board vendor: - - > wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz - > wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz - > tar xvfJ gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz - > tar xvfJ gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz - > export PATH=$PWD/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux/bin:$PWD/gcc-linaro-arm-none-eabi-4.8-2013.11_linux/bin:$PATH - > git clone https://github.com/BayLibre/u-boot.git -b libretech-cc amlogic-u-boot - > git clone https://github.com/friendlyarm/u-boot.git -b nanopi-k2-v2015.01 amlogic-u-boot - > cd amlogic-u-boot - > sed -i 's/aarch64-linux-gnu-/aarch64-none-elf-/' Makefile - > sed -i 's/arm-linux-/arm-none-eabi-/' arch/arm/cpu/armv8/gxb/firmware/scp_task/Makefile - > make nanopi-k2_defconfig - > make - > export FIPDIR=$PWD/fip - -Go back to mainline U-Boot source tree then : - > mkdir fip - - > cp $FIPDIR/gxb/bl2.bin fip/ - > cp $FIPDIR/gxb/acs.bin fip/ - > cp $FIPDIR/gxb/bl21.bin fip/ - > cp $FIPDIR/gxb/bl30.bin fip/ - > cp $FIPDIR/gxb/bl301.bin fip/ - > cp $FIPDIR/gxb/bl31.img fip/ - > cp u-boot.bin fip/bl33.bin - - > $FIPDIR/blx_fix.sh \ - fip/bl30.bin \ - fip/zero_tmp \ - fip/bl30_zero.bin \ - fip/bl301.bin \ - fip/bl301_zero.bin \ - fip/bl30_new.bin \ - bl30 - - > $FIPDIR/fip_create \ - --bl30 fip/bl30_new.bin \ - --bl31 fip/bl31.img \ - --bl33 fip/bl33.bin \ - fip/fip.bin - - > python $FIPDIR/acs_tool.pyc fip/bl2.bin fip/bl2_acs.bin fip/acs.bin 0 - - > $FIPDIR/blx_fix.sh \ - fip/bl2_acs.bin \ - fip/zero_tmp \ - fip/bl2_zero.bin \ - fip/bl21.bin \ - fip/bl21_zero.bin \ - fip/bl2_new.bin \ - bl2 - - > cat fip/bl2_new.bin fip/fip.bin > fip/boot_new.bin - - > $FIPDIR/gxb/aml_encrypt_gxb --bootsig \ - --input fip/boot_new.bin - --output fip/u-boot.bin - -and then write the image to SD with: - - > DEV=/dev/your_sd_device - > dd if=fip/u-boot.bin of=$DEV conv=fsync,notrunc bs=512 seek=1 diff --git a/board/amlogic/p200/README.p200 b/board/amlogic/p200/README.p200 deleted file mode 100644 index 84d5ca5356..0000000000 --- a/board/amlogic/p200/README.p200 +++ /dev/null @@ -1,102 +0,0 @@ -U-Boot for Amlogic P200 -======================= - -P200 is a reference board manufactured by Amlogic with the following -specifications: - - - Amlogic S905 ARM Cortex-A53 quad-core SoC @ 1.5GHz - - ARM Mali 450 GPU - - 2GB DDR3 SDRAM - - Gigabit Ethernet - - HDMI 2.0 4K/60Hz display - - 2 x USB 2.0 Host - - eMMC, microSD - - Infrared receiver - - SDIO WiFi Module - - CVBS+Stereo Audio Jack - -Schematics are available from Amlogic on demand. - -Currently the u-boot port supports the following devices: - - serial - - eMMC, microSD - - Ethernet - - I2C - - Regulators - - Reset controller - - Clock controller - - USB Host - - ADC - -u-boot compilation -================== - - > export CROSS_COMPILE=aarch64-none-elf- - > make p200_defconfig - > make - -Image creation -============== - -Amlogic doesn't provide sources for the firmware and for tools needed -to create the bootloader image, so it is necessary to obtain them from -the git tree published by the board vendor: - - > wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz - > wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz - > tar xvfJ gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz - > tar xvfJ gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz - > export PATH=$PWD/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux/bin:$PWD/gcc-linaro-arm-none-eabi-4.8-2013.11_linux/bin:$PATH - > git clone https://github.com/BayLibre/u-boot.git -b n-amlogic-openlinux-20170606 amlogic-u-boot - > cd amlogic-u-boot - > make gxb_p200_v1_defconfig - > make - > export FIPDIR=$PWD/fip - -Go back to mainline U-boot source tree then : - > mkdir fip - - > cp $FIPDIR/gxl/bl2.bin fip/ - > cp $FIPDIR/gxl/acs.bin fip/ - > cp $FIPDIR/gxl/bl21.bin fip/ - > cp $FIPDIR/gxl/bl30.bin fip/ - > cp $FIPDIR/gxl/bl301.bin fip/ - > cp $FIPDIR/gxl/bl31.img fip/ - > cp u-boot.bin fip/bl33.bin - - > $FIPDIR/blx_fix.sh \ - fip/bl30.bin \ - fip/zero_tmp \ - fip/bl30_zero.bin \ - fip/bl301.bin \ - fip/bl301_zero.bin \ - fip/bl30_new.bin \ - bl30 - - > $FIPDIR/acs_tool.pyc fip/bl2.bin fip/bl2_acs.bin fip/acs.bin 0 - - > $FIPDIR/blx_fix.sh \ - fip/bl2_acs.bin \ - fip/zero_tmp \ - fip/bl2_zero.bin \ - fip/bl21.bin \ - fip/bl21_zero.bin \ - fip/bl2_new.bin \ - bl2 - - > $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl30_new.bin - > $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl31.img - > $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl33.bin - > $FIPDIR/gxl/aml_encrypt_gxl --bl2sig --input fip/bl2_new.bin --output fip/bl2.n.bin.sig - > $FIPDIR/gxl/aml_encrypt_gxl --bootmk \ - --output fip/u-boot.bin \ - --bl2 fip/bl2.n.bin.sig \ - --bl30 fip/bl30_new.bin.enc \ - --bl31 fip/bl31.img.enc \ - --bl33 fip/bl33.bin.enc - -and then write the image to SD with: - - > DEV=/dev/your_sd_device - > dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1 - > dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444 diff --git a/board/amlogic/p201/README.p201 b/board/amlogic/p201/README.p201 deleted file mode 100644 index 4bb5e95905..0000000000 --- a/board/amlogic/p201/README.p201 +++ /dev/null @@ -1,102 +0,0 @@ -U-Boot for Amlogic P201 -======================= - -P201 is a reference board manufactured by Amlogic with the following -specifications: - - - Amlogic S905 ARM Cortex-A53 quad-core SoC @ 1.5GHz - - ARM Mali 450 GPU - - 2GB DDR3 SDRAM - - 10/100 Ethernet - - HDMI 2.0 4K/60Hz display - - 2 x USB 2.0 Host - - eMMC, microSD - - Infrared receiver - - SDIO WiFi Module - - CVBS+Stereo Audio Jack - -Schematics are available from Amlogic on demand. - -Currently the u-boot port supports the following devices: - - serial - - eMMC, microSD - - Ethernet - - I2C - - Regulators - - Reset controller - - Clock controller - - USB Host - - ADC - -u-boot compilation -================== - - > export CROSS_COMPILE=aarch64-none-elf- - > make p201_defconfig - > make - -Image creation -============== - -Amlogic doesn't provide sources for the firmware and for tools needed -to create the bootloader image, so it is necessary to obtain them from -the git tree published by the board vendor: - - > wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz - > wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz - > tar xvfJ gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz - > tar xvfJ gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz - > export PATH=$PWD/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux/bin:$PWD/gcc-linaro-arm-none-eabi-4.8-2013.11_linux/bin:$PATH - > git clone https://github.com/BayLibre/u-boot.git -b n-amlogic-openlinux-20170606 amlogic-u-boot - > cd amlogic-u-boot - > make gxb_p201_v1_defconfig - > make - > export FIPDIR=$PWD/fip - -Go back to mainline U-boot source tree then : - > mkdir fip - - > cp $FIPDIR/gxl/bl2.bin fip/ - > cp $FIPDIR/gxl/acs.bin fip/ - > cp $FIPDIR/gxl/bl21.bin fip/ - > cp $FIPDIR/gxl/bl30.bin fip/ - > cp $FIPDIR/gxl/bl301.bin fip/ - > cp $FIPDIR/gxl/bl31.img fip/ - > cp u-boot.bin fip/bl33.bin - - > $FIPDIR/blx_fix.sh \ - fip/bl30.bin \ - fip/zero_tmp \ - fip/bl30_zero.bin \ - fip/bl301.bin \ - fip/bl301_zero.bin \ - fip/bl30_new.bin \ - bl30 - - > $FIPDIR/acs_tool.pyc fip/bl2.bin fip/bl2_acs.bin fip/acs.bin 0 - - > $FIPDIR/blx_fix.sh \ - fip/bl2_acs.bin \ - fip/zero_tmp \ - fip/bl2_zero.bin \ - fip/bl21.bin \ - fip/bl21_zero.bin \ - fip/bl2_new.bin \ - bl2 - - > $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl30_new.bin - > $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl31.img - > $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl33.bin - > $FIPDIR/gxl/aml_encrypt_gxl --bl2sig --input fip/bl2_new.bin --output fip/bl2.n.bin.sig - > $FIPDIR/gxl/aml_encrypt_gxl --bootmk \ - --output fip/u-boot.bin \ - --bl2 fip/bl2.n.bin.sig \ - --bl30 fip/bl30_new.bin.enc \ - --bl31 fip/bl31.img.enc \ - --bl33 fip/bl33.bin.enc - -and then write the image to SD with: - - > DEV=/dev/your_sd_device - > dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1 - > dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444 diff --git a/board/amlogic/p212/README.khadas-vim b/board/amlogic/p212/README.khadas-vim deleted file mode 100644 index ccf933861b..0000000000 --- a/board/amlogic/p212/README.khadas-vim +++ /dev/null @@ -1,101 +0,0 @@ -U-Boot for Khadas VIM -======================= - -Khadas VIM is an Open Source DIY Box manufactured by Shenzhen Wesion -Technology Co., Ltd with the following specifications: - - - Amlogic S905X ARM Cortex-A53 quad-core SoC @ 1.5GHz - - ARM Mali 450 GPU - - 2GB DDR3 SDRAM - - 10/100 Ethernet - - HDMI 2.0 4K/60Hz display - - 40-pin GPIO header - - 2 x USB 2.0 Host, 1 x USB 2.0 Type-C OTG - - 8GB/16GBeMMC - - microSD - - SDIO Wifi Module, Bluetooth - - Two channels IR receiver - -Currently the u-boot port supports the following devices: - - serial - - eMMC, microSD - - Ethernet - - I2C - - Regulators - - Reset controller - - Clock controller - - USB Host - - ADC - -U-Boot compilation -================== - - > export CROSS_COMPILE=aarch64-none-elf- - > make khadas-vim_defconfig - > make - -Image creation -============== - -Amlogic doesn't provide sources for the firmware and for tools needed -to create the bootloader image, so it is necessary to obtain them from -the git tree published by the board vendor: - - > wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz - > wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz - > tar xvfJ gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz - > tar xvfJ gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz - > export PATH=$PWD/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux/bin:$PWD/gcc-linaro-arm-none-eabi-4.8-2013.11_linux/bin:$PATH - > git clone https://github.com/khadas/u-boot -b Vim vim-u-boot - > cd vim-u-boot - > make kvim_defconfig - > make CROSS_COMPILE=aarch64-none-elf- - > export FIPDIR=$PWD/fip - -Go back to mainline U-Boot source tree then : - > mkdir fip - - > cp $FIPDIR/gxl/bl2.bin fip/ - > cp $FIPDIR/gxl/acs.bin fip/ - > cp $FIPDIR/gxl/bl21.bin fip/ - > cp $FIPDIR/gxl/bl30.bin fip/ - > cp $FIPDIR/gxl/bl301.bin fip/ - > cp $FIPDIR/gxl/bl31.img fip/ - > cp u-boot.bin fip/bl33.bin - - > $FIPDIR/blx_fix.sh \ - fip/bl30.bin \ - fip/zero_tmp \ - fip/bl30_zero.bin \ - fip/bl301.bin \ - fip/bl301_zero.bin \ - fip/bl30_new.bin \ - bl30 - - > python $FIPDIR/acs_tool.pyc fip/bl2.bin fip/bl2_acs.bin fip/acs.bin 0 - - > $FIPDIR/blx_fix.sh \ - fip/bl2_acs.bin \ - fip/zero_tmp \ - fip/bl2_zero.bin \ - fip/bl21.bin \ - fip/bl21_zero.bin \ - fip/bl2_new.bin \ - bl2 - - > $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl30_new.bin - > $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl31.img - > $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl33.bin - > $FIPDIR/gxl/aml_encrypt_gxl --bl2sig --input fip/bl2_new.bin --output fip/bl2.n.bin.sig - > $FIPDIR/gxl/aml_encrypt_gxl --bootmk \ - --output fip/u-boot.bin \ - --bl2 fip/bl2.n.bin.sig \ - --bl30 fip/bl30_new.bin.enc \ - --bl31 fip/bl31.img.enc \ - --bl33 fip/bl33.bin.enc - -and then write the image to SD with: - - > DEV=/dev/your_sd_device - > dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1 - > dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444 diff --git a/board/amlogic/p212/README.libretech-ac b/board/amlogic/p212/README.libretech-ac deleted file mode 100644 index 3f713ec326..0000000000 --- a/board/amlogic/p212/README.libretech-ac +++ /dev/null @@ -1,102 +0,0 @@ -U-Boot for LibreTech AC -======================= - -LibreTech AC is a single board computer manufactured by Libre Technology -with the following specifications: - - - Amlogic S805X ARM Cortex-A53 quad-core SoC @ 1.2GHz - - ARM Mali 450 GPU - - 512MiB DDR4 SDRAM - - 10/100 Ethernet - - HDMI 2.0 4K/60Hz display - - 40-pin GPIO header - - 4 x USB 2.0 Host - - eMMC, SPI NOR Flash - - Infrared receiver - -Schematics are available on the manufacturer website. - -Currently the U-Boot port supports the following devices: - - serial - - eMMC - - Ethernet - - USB - -U-Boot compilation -================== - - > export CROSS_COMPILE=aarch64-none-elf- - > make libretech-ac_defconfig - > make - -Image creation -============== - -Amlogic doesn't provide sources for the firmware and for tools needed -to create the bootloader image, so it is necessary to obtain them from -the git tree published by the board vendor: - - > wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz - > wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz - > tar xvfJ gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz - > tar xvfJ gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz - > export PATH=$PWD/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux/bin:$PWD/gcc-linaro-arm-none-eabi-4.8-2013.11_linux/bin:$PATH - > git clone https://github.com/BayLibre/u-boot.git -b libretech-ac amlogic-u-boot - > cd amlogic-u-boot - > wget https://raw.githubusercontent.com/BayLibre/u-boot/libretech-cc/fip/blx_fix.sh - > make libretech_ac_defconfig - > make - > export UBOOTDIR=$PWD - -Download the latest Amlogic Buildroot package, and extract it : - > wget http://openlinux2.amlogic.com:8000/ARM/filesystem/Linux_BSP/buildroot_openlinux_kernel_4.9_fbdev_20180418.tar.gz - > tar xfz buildroot_openlinux_kernel_4.9_fbdev_20180418.tar.gz buildroot_openlinux_kernel_4.9_fbdev_20180418/bootloader - > export BRDIR=$PWD/buildroot_openlinux_kernel_4.9_fbdev_20180418 - -Go back to mainline U-Boot source tree then : - > mkdir fip - - > cp $UBOOTDIR/build/scp_task/bl301.bin fip/ - > cp $UBOOTDIR/build/board/amlogic/libretech_ac/firmware/bl21.bin fip/ - > cp $UBOOTDIR/build/board/amlogic/libretech_ac/firmware/acs.bin fip/ - > cp $BRDIR/bootloader/uboot-repo/bl2/bin/gxl/bl2.bin fip/ - > cp $BRDIR/bootloader/uboot-repo/bl30/bin/gxl/bl30.bin fip/ - > cp $BRDIR/bootloader/uboot-repo/bl31/bin/gxl/bl31.img fip/ - > cp u-boot.bin fip/bl33.bin - - > sh $UBOOTDIR/blx_fix.sh \ - fip/bl30.bin \ - fip/zero_tmp \ - fip/bl30_zero.bin \ - fip/bl301.bin \ - fip/bl301_zero.bin \ - fip/bl30_new.bin \ - bl30 - - > $BRDIR/bootloader/uboot-repo/fip/acs_tool.pyc fip/bl2.bin fip/bl2_acs.bin fip/acs.bin 0 - - > sh $UBOOTDIR/blx_fix.sh \ - fip/bl2_acs.bin \ - fip/zero_tmp \ - fip/bl2_zero.bin \ - fip/bl21.bin \ - fip/bl21_zero.bin \ - fip/bl2_new.bin \ - bl2 - - > $BRDIR/bootloader/uboot-repo/fip/gxl/aml_encrypt_gxl --bl3enc --input fip/bl30_new.bin - > $BRDIR/bootloader/uboot-repo/fip/gxl/aml_encrypt_gxl --bl3enc --input fip/bl31.img - > $BRDIR/bootloader/uboot-repo/fip/gxl/aml_encrypt_gxl --bl3enc --input fip/bl33.bin - > $BRDIR/bootloader/uboot-repo/fip/gxl/aml_encrypt_gxl --bl2sig --input fip/bl2_new.bin --output fip/bl2.n.bin.sig - > $BRDIR/bootloader/uboot-repo/fip/gxl/aml_encrypt_gxl --bootmk \ - --output fip/u-boot.bin \ - --bl2 fip/bl2.n.bin.sig \ - --bl30 fip/bl30_new.bin.enc \ - --bl31 fip/bl31.img.enc \ - --bl33 fip/bl33.bin.enc - -and then write the image to SD with: - - > DEV=/dev/your_sd_device - > dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1 - > dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444 diff --git a/board/amlogic/p212/README.libretech-cc b/board/amlogic/p212/README.libretech-cc deleted file mode 100644 index 74434d4435..0000000000 --- a/board/amlogic/p212/README.libretech-cc +++ /dev/null @@ -1,134 +0,0 @@ -U-Boot for LibreTech CC -======================= - -LibreTech CC is a single board computer manufactured by Libre Technology -with the following specifications: - - - Amlogic S905X ARM Cortex-A53 quad-core SoC @ 1.5GHz - - ARM Mali 450 GPU - - 2GB DDR3 SDRAM - - 10/100 Ethernet - - HDMI 2.0 4K/60Hz display - - 40-pin GPIO header - - 4 x USB 2.0 Host - - eMMC, microSD - - Infrared receiver - -Schematics are available on the manufacturer website. - -Currently the U-Boot port supports the following devices: - - serial - - eMMC, microSD - - Ethernet - - I2C - - Regulators - - Reset controller - - Clock controller - - USB Host - - ADC - -U-Boot compilation -================== - - > export CROSS_COMPILE=aarch64-none-elf- - > make libretech-cc_defconfig - > make - -Image creation -============== - -To boot the system, u-boot must be combined with several earlier stage -bootloaders: - -* bl2.bin: vendor-provided binary blob -* bl21.bin: built from vendor u-boot source -* bl30.bin: vendor-provided binary blob -* bl301.bin: built from vendor u-boot source -* bl31.bin: vendor-provided binary blob -* acs.bin: built from vendor u-boot source - -These binaries and the tools required below have been collected and prebuilt -for convenience at - -Download and extract the libretech-cc release from there, and set FIPDIR to -point to the `fip` subdirectory. - - > export FIPDIR=/path/to/extracted/fip - -Alternatively, you can obtain the original vendor u-boot tree which -contains the required blobs and sources, and build yourself. -Note that old compilers are required for this to build. The compilers here -are suggested by Amlogic, and they are 32-bit x86 binaries. - - > wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz - > wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz - > tar xvfJ gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz - > tar xvfJ gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz - > export PATH=$PWD/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux/bin:$PWD/gcc-linaro-arm-none-eabi-4.8-2013.11_linux/bin:$PATH - > git clone https://github.com/BayLibre/u-boot.git -b libretech-cc amlogic-u-boot - > cd amlogic-u-boot - > make libretech_cc_defconfig - > make - > export FIPDIR=$PWD/fip - -Once you have the binaries available (either through the prebuilt download, -or having built the vendor u-boot yourself), you can then proceed to glue -everything together. Go back to mainline U-Boot source tree then : - - > mkdir fip - - > cp $FIPDIR/gxl/bl2.bin fip/ - > cp $FIPDIR/gxl/acs.bin fip/ - > cp $FIPDIR/gxl/bl21.bin fip/ - > cp $FIPDIR/gxl/bl30.bin fip/ - > cp $FIPDIR/gxl/bl301.bin fip/ - > cp $FIPDIR/gxl/bl31.img fip/ - > cp u-boot.bin fip/bl33.bin - - > $FIPDIR/blx_fix.sh \ - fip/bl30.bin \ - fip/zero_tmp \ - fip/bl30_zero.bin \ - fip/bl301.bin \ - fip/bl301_zero.bin \ - fip/bl30_new.bin \ - bl30 - - > $FIPDIR/acs_tool.pyc fip/bl2.bin fip/bl2_acs.bin fip/acs.bin 0 - - > $FIPDIR/blx_fix.sh \ - fip/bl2_acs.bin \ - fip/zero_tmp \ - fip/bl2_zero.bin \ - fip/bl21.bin \ - fip/bl21_zero.bin \ - fip/bl2_new.bin \ - bl2 - - > $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl30_new.bin - > $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl31.img - > $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl33.bin - > $FIPDIR/gxl/aml_encrypt_gxl --bl2sig --input fip/bl2_new.bin --output fip/bl2.n.bin.sig - > $FIPDIR/gxl/aml_encrypt_gxl --bootmk \ - --output fip/u-boot.bin \ - --bl2 fip/bl2.n.bin.sig \ - --bl30 fip/bl30_new.bin.enc \ - --bl31 fip/bl31.img.enc \ - --bl33 fip/bl33.bin.enc - -and then write the image to SD with: - - > DEV=/dev/your_sd_device - > dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1 - > dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444 - -Note that Amlogic provides aml_encrypt_gxl as a 32-bit x86 binary with no -source code. Should you prefer to avoid that, there are open source reverse -engineered versions available: - -1. gxlimg , which comes with a handy - Makefile that automates the whole process. -2. meson-tools - -However, these community-developed alternatives are not endorsed by or -supported by Amlogic. diff --git a/board/amlogic/p212/README.p212 b/board/amlogic/p212/README.p212 deleted file mode 100644 index 3776f24493..0000000000 --- a/board/amlogic/p212/README.p212 +++ /dev/null @@ -1,102 +0,0 @@ -U-Boot for Amlogic P212 -======================= - -P212 is a reference board manufactured by Amlogic with the following -specifications: - - - Amlogic S905X ARM Cortex-A53 quad-core SoC @ 1.5GHz - - ARM Mali 450 GPU - - 2GB DDR3 SDRAM - - 10/100 Ethernet - - HDMI 2.0 4K/60Hz display - - 2 x USB 2.0 Host - - eMMC, microSD - - Infrared receiver - - SDIO WiFi Module - - CVBS+Stereo Audio Jack - -Schematics are available from Amlogic on demand. - -Currently the u-boot port supports the following devices: - - serial - - eMMC, microSD - - Ethernet - - I2C - - Regulators - - Reset controller - - Clock controller - - USB Host - - ADC - -u-boot compilation -================== - - > export CROSS_COMPILE=aarch64-none-elf- - > make p212_defconfig - > make - -Image creation -============== - -Amlogic doesn't provide sources for the firmware and for tools needed -to create the bootloader image, so it is necessary to obtain them from -the git tree published by the board vendor: - - > wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz - > wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz - > tar xvfJ gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz - > tar xvfJ gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz - > export PATH=$PWD/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux/bin:$PWD/gcc-linaro-arm-none-eabi-4.8-2013.11_linux/bin:$PATH - > git clone https://github.com/BayLibre/u-boot.git -b n-amlogic-openlinux-20170606 amlogic-u-boot - > cd amlogic-u-boot - > make gxl_p212_v1_defconfig - > make - > export FIPDIR=$PWD/fip - -Go back to mainline U-boot source tree then : - > mkdir fip - - > cp $FIPDIR/gxl/bl2.bin fip/ - > cp $FIPDIR/gxl/acs.bin fip/ - > cp $FIPDIR/gxl/bl21.bin fip/ - > cp $FIPDIR/gxl/bl30.bin fip/ - > cp $FIPDIR/gxl/bl301.bin fip/ - > cp $FIPDIR/gxl/bl31.img fip/ - > cp u-boot.bin fip/bl33.bin - - > $FIPDIR/blx_fix.sh \ - fip/bl30.bin \ - fip/zero_tmp \ - fip/bl30_zero.bin \ - fip/bl301.bin \ - fip/bl301_zero.bin \ - fip/bl30_new.bin \ - bl30 - - > $FIPDIR/acs_tool.pyc fip/bl2.bin fip/bl2_acs.bin fip/acs.bin 0 - - > $FIPDIR/blx_fix.sh \ - fip/bl2_acs.bin \ - fip/zero_tmp \ - fip/bl2_zero.bin \ - fip/bl21.bin \ - fip/bl21_zero.bin \ - fip/bl2_new.bin \ - bl2 - - > $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl30_new.bin - > $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl31.img - > $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl33.bin - > $FIPDIR/gxl/aml_encrypt_gxl --bl2sig --input fip/bl2_new.bin --output fip/bl2.n.bin.sig - > $FIPDIR/gxl/aml_encrypt_gxl --bootmk \ - --output fip/u-boot.bin \ - --bl2 fip/bl2.n.bin.sig \ - --bl30 fip/bl30_new.bin.enc \ - --bl31 fip/bl31.img.enc \ - --bl33 fip/bl33.bin.enc - -and then write the image to SD with: - - > DEV=/dev/your_sd_device - > dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1 - > dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444 diff --git a/board/amlogic/q200/README.khadas-vim2 b/board/amlogic/q200/README.khadas-vim2 deleted file mode 100644 index 595998c4fa..0000000000 --- a/board/amlogic/q200/README.khadas-vim2 +++ /dev/null @@ -1,102 +0,0 @@ -U-Boot for Khadas VIM2 -======================= - -Khadas VIM2 is an Open Source DIY Box manufactured by Shenzhen Wesion -Technology Co., Ltd with the following specifications: - - - Amlogic S912 ARM Cortex-A53 octo-core SoC @ 1.5GHz - - ARM Mali T860 GPU - - 2/3GB DDR4 SDRAM - - 10/100/1000 Ethernet - - HDMI 2.0 4K/60Hz display - - 40-pin GPIO header - - 2 x USB 2.0 Host, 1 x USB 2.0 Type-C OTG - - 16GB/32GB/64GB eMMC - - 2MB SPI Flash - - microSD - - SDIO Wifi Module, Bluetooth - - Two channels IR receiver - -Currently the u-boot port supports the following devices: - - serial - - eMMC, microSD - - Ethernet - - I2C - - Regulators - - Reset controller - - Clock controller - - USB Host - - ADC - -U-Boot compilation -================== - - > export CROSS_COMPILE=aarch64-none-elf- - > make khadas-vim2_defconfig - > make - -Image creation -============== - -Amlogic doesn't provide sources for the firmware and for tools needed -to create the bootloader image, so it is necessary to obtain them from -the git tree published by the board vendor: - - > wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz - > wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz - > tar xvfJ gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz - > tar xvfJ gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz - > export PATH=$PWD/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux/bin:$PWD/gcc-linaro-arm-none-eabi-4.8-2013.11_linux/bin:$PATH - > git clone https://github.com/khadas/u-boot -b khadas-vim-v2015.01 vim-u-boot - > cd vim-u-boot - > make kvim2_defconfig - > make - > export FIPDIR=$PWD/fip - -Go back to mainline U-Boot source tree then : - > mkdir fip - - > cp $FIPDIR/gxl/bl2.bin fip/ - > cp $FIPDIR/gxl/acs.bin fip/ - > cp $FIPDIR/gxl/bl21.bin fip/ - > cp $FIPDIR/gxl/bl30.bin fip/ - > cp $FIPDIR/gxl/bl301.bin fip/ - > cp $FIPDIR/gxl/bl31.img fip/ - > cp u-boot.bin fip/bl33.bin - - > $FIPDIR/blx_fix.sh \ - fip/bl30.bin \ - fip/zero_tmp \ - fip/bl30_zero.bin \ - fip/bl301.bin \ - fip/bl301_zero.bin \ - fip/bl30_new.bin \ - bl30 - - > python $FIPDIR/acs_tool.pyc fip/bl2.bin fip/bl2_acs.bin fip/acs.bin 0 - - > $FIPDIR/blx_fix.sh \ - fip/bl2_acs.bin \ - fip/zero_tmp \ - fip/bl2_zero.bin \ - fip/bl21.bin \ - fip/bl21_zero.bin \ - fip/bl2_new.bin \ - bl2 - - > $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl30_new.bin - > $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl31.img - > $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl33.bin - > $FIPDIR/gxl/aml_encrypt_gxl --bl2sig --input fip/bl2_new.bin --output fip/bl2.n.bin.sig - > $FIPDIR/gxl/aml_encrypt_gxl --bootmk \ - --output fip/u-boot.bin \ - --bl2 fip/bl2.n.bin.sig \ - --bl30 fip/bl30_new.bin.enc \ - --bl31 fip/bl31.img.enc \ - --bl33 fip/bl33.bin.enc - -and then write the image to SD with: - - > DEV=/dev/your_sd_device - > dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1 - > dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444 diff --git a/board/amlogic/q200/README.q200 b/board/amlogic/q200/README.q200 deleted file mode 100644 index d4142c88bd..0000000000 --- a/board/amlogic/q200/README.q200 +++ /dev/null @@ -1,101 +0,0 @@ -U-Boot for Amlogic Q200 -======================= - -Q200 is a reference board manufactured by Amlogic with the following -specifications: - - - Amlogic S912 ARM Cortex-A53 octo-core SoC @ 1.5GHz - - ARM Mali T860 GPU - - 2/3GB DDR4 SDRAM - - 10/100/1000 Ethernet - - HDMI 2.0 4K/60Hz display - - 2 x USB 2.0 Host, 1 x USB 2.0 Device - - 16GB/32GB/64GB eMMC - - 2MB SPI Flash - - microSD - - SDIO Wifi Module, Bluetooth - - IR receiver - -Currently the u-boot port supports the following devices: - - serial - - eMMC, microSD - - Ethernet - - I2C - - Regulators - - Reset controller - - Clock controller - - USB Host - - ADC - -U-Boot compilation -================== - - > export CROSS_COMPILE=aarch64-none-elf- - > make khadas-vim2_defconfig - > make - -Image creation -============== - -Amlogic doesn't provide sources for the firmware and for tools needed -to create the bootloader image, so it is necessary to obtain them from -the git tree published by the board vendor: - - > wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz - > wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz - > tar xvfJ gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz - > tar xvfJ gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz - > export PATH=$PWD/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux/bin:$PWD/gcc-linaro-arm-none-eabi-4.8-2013.11_linux/bin:$PATH - > git clone https://github.com/BayLibre/u-boot.git -b n-amlogic-openlinux-20170606 amlogic-u-boot - > cd amlogic-u-boot - > make gxm_q200_v1_defconfig - > make - > export FIPDIR=$PWD/fip - -Go back to mainline U-Boot source tree then : - > mkdir fip - - > cp $FIPDIR/gxl/bl2.bin fip/ - > cp $FIPDIR/gxl/acs.bin fip/ - > cp $FIPDIR/gxl/bl21.bin fip/ - > cp $FIPDIR/gxl/bl30.bin fip/ - > cp $FIPDIR/gxl/bl301.bin fip/ - > cp $FIPDIR/gxl/bl31.img fip/ - > cp u-boot.bin fip/bl33.bin - - > $FIPDIR/blx_fix.sh \ - fip/bl30.bin \ - fip/zero_tmp \ - fip/bl30_zero.bin \ - fip/bl301.bin \ - fip/bl301_zero.bin \ - fip/bl30_new.bin \ - bl30 - - > python $FIPDIR/acs_tool.pyc fip/bl2.bin fip/bl2_acs.bin fip/acs.bin 0 - - > $FIPDIR/blx_fix.sh \ - fip/bl2_acs.bin \ - fip/zero_tmp \ - fip/bl2_zero.bin \ - fip/bl21.bin \ - fip/bl21_zero.bin \ - fip/bl2_new.bin \ - bl2 - - > $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl30_new.bin - > $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl31.img - > $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl33.bin - > $FIPDIR/gxl/aml_encrypt_gxl --bl2sig --input fip/bl2_new.bin --output fip/bl2.n.bin.sig - > $FIPDIR/gxl/aml_encrypt_gxl --bootmk \ - --output fip/u-boot.bin \ - --bl2 fip/bl2.n.bin.sig \ - --bl30 fip/bl30_new.bin.enc \ - --bl31 fip/bl31.img.enc \ - --bl33 fip/bl33.bin.enc - -and then write the image to SD with: - - > DEV=/dev/your_sd_device - > dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1 - > dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444 diff --git a/board/amlogic/s400/README b/board/amlogic/s400/README deleted file mode 100644 index a48db22a42..0000000000 --- a/board/amlogic/s400/README +++ /dev/null @@ -1,109 +0,0 @@ -U-Boot for Amlogic S400 -======================= - -S400 is a reference board manufactured by Amlogic with the following -specifications: - - - Amlogic A113DX ARM Cortex-A53 quad-core SoC @ 1.2GHz - - 1GB DDR4 SDRAM - - 10/100 Ethernet - - 2 x USB 2.0 Host - - eMMC - - Infrared receiver - - SDIO WiFi Module - - MIPI DSI Connector - - Audio HAT Connector - - PCI-E M.2 Connectors - -Schematics are available from Amlogic on demand. - -Currently the u-boot port supports the following devices: - - serial - - eMMC - - Ethernet - - I2C - - Regulators - - Reset controller - - Clock controller - - USB Host - - ADC - -u-boot compilation -================== - - > export CROSS_COMPILE=aarch64-none-elf- - > make s400_defconfig - > make - -Image creation -============== - -Amlogic doesn't provide sources for the firmware and for tools needed -to create the bootloader image, so it is necessary to obtain them from -the git tree published by the board vendor: - - > wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz - > wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz - > tar xvfJ gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz - > tar xvfJ gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz - > export PATH=$PWD/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux/bin:$PWD/gcc-linaro-arm-none-eabi-4.8-2013.11_linux/bin:$PATH - > git clone https://github.com/BayLibre/u-boot.git -b n-amlogic-openlinux-20170606 amlogic-u-boot - > cd amlogic-u-boot - > make axg_s400_v1_defconfig - > make - > export FIPDIR=$PWD/fip - -Go back to mainline U-boot source tree then : - > mkdir fip - - > cp $FIPDIR/axg/bl2.bin fip/ - > cp $FIPDIR/axg/acs.bin fip/ - > cp $FIPDIR/axg/bl21.bin fip/ - > cp $FIPDIR/axg/bl30.bin fip/ - > cp $FIPDIR/axg/bl301.bin fip/ - > cp $FIPDIR/axg/bl31.img fip/ - > cp u-boot.bin fip/bl33.bin - - > $FIPDIR/blx_fix.sh \ - fip/bl30.bin \ - fip/zero_tmp \ - fip/bl30_zero.bin \ - fip/bl301.bin \ - fip/bl301_zero.bin \ - fip/bl30_new.bin \ - bl30 - - > $FIPDIR/acs_tool.pyc fip/bl2.bin fip/bl2_acs.bin fip/acs.bin 0 - - > $FIPDIR/blx_fix.sh \ - fip/bl2_acs.bin \ - fip/zero_tmp \ - fip/bl2_zero.bin \ - fip/bl21.bin \ - fip/bl21_zero.bin \ - fip/bl2_new.bin \ - bl2 - - > $FIPDIR/axg/aml_encrypt_axg --bl3sig --input fip/bl30_new.bin \ - --output fip/bl30_new.bin.enc \ - --level v3 --type bl30 - > $FIPDIR/axg/aml_encrypt_axg --bl3sig --input fip/bl31.img \ - --output fip/bl31.img.enc \ - --level v3 --type bl31 - > $FIPDIR/axg/aml_encrypt_axg --bl3sig --input fip/bl33.bin --compress lz4 \ - --output fip/bl33.bin.enc \ - --level v3 --type bl33 - > $FIPDIR/axg/aml_encrypt_axg --bl2sig --input fip/bl2_new.bin \ - --output fip/bl2.n.bin.sig - > $FIPDIR/axg/aml_encrypt_axg --bootmk \ - --output fip/u-boot.bin \ - --bl2 fip/bl2.n.bin.sig \ - --bl30 fip/bl30_new.bin.enc \ - --bl31 fip/bl31.img.enc \ - --bl33 fip/bl33.bin.enc --level v3 - -and then write the image to SD with: - - > DEV=/dev/your_sd_device - > dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1 - > dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444 diff --git a/board/amlogic/sei510/README b/board/amlogic/sei510/README deleted file mode 100644 index d9358aa501..0000000000 --- a/board/amlogic/sei510/README +++ /dev/null @@ -1,122 +0,0 @@ -U-Boot for Amlogic SEI510 -======================= - -SEI510 is a customer board manufactured by SEI Robotics with the following -specifications: - - - Amlogic S905X2 ARM Cortex-A53 quad-core SoC - - 2GB DDR4 SDRAM - - 10/100 Ethernet (Internal PHY) - - 1 x USB 3.0 Host - - eMMC - - SDcard - - Infrared receiver - - SDIO WiFi Module - -Currently the u-boot port supports the following devices: - - serial - - Ethernet - - Regulators - - Clock controller - -u-boot compilation -================== - - > export CROSS_COMPILE=aarch64-none-elf- - > make sei510_defconfig - > make - -Image creation -============== - -Amlogic doesn't provide sources for the firmware and for tools needed -to create the bootloader image, so it is necessary to obtain them from -the git tree published by the board vendor: - - > wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz - > wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz - > tar xvfJ gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz - > tar xvfJ gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz - > export PATH=$PWD/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux/bin:$PWD/gcc-linaro-arm-none-eabi-4.8-2013.11_linux/bin:$PATH - > git clone https://github.com/BayLibre/u-boot.git -b buildroot-openlinux-20180418 amlogic-u-boot - > cd amlogic-u-boot - > make g12a_u200_v1_defconfig - > make - > export UBOOTDIR=$PWD - -Download the latest Amlogic Buildroot package, and extract it : - > wget http://openlinux2.amlogic.com:8000/ARM/filesystem/Linux_BSP/buildroot_openlinux_kernel_4.9_fbdev_20180706.tar.gz - > tar xfz buildroot_openlinux_kernel_4.9_fbdev_20180706.tar.gz buildroot_openlinux_kernel_4.9_fbdev_20180706/bootloader - > export BRDIR=$PWD/buildroot_openlinux_kernel_4.9_fbdev_20180706 - > export FIPDIR=$BRDIR/bootloader/uboot-repo/fip - -Go back to mainline U-Boot source tree then : - > mkdir fip - - > wget https://github.com/BayLibre/u-boot/releases/download/v2017.11-libretech-cc/blx_fix_g12a.sh -O fip/blx_fix.sh - > cp $UBOOTDIR/build/scp_task/bl301.bin fip/ - > cp $UBOOTDIR/build/board/amlogic/g12a_u200_v1/firmware/acs.bin fip/ - > cp $BRDIR/bootloader/uboot-repo/bl2/bin/g12a/bl2.bin fip/ - > cp $BRDIR/bootloader/uboot-repo/bl30/bin/g12a/bl30.bin fip/ - > cp $BRDIR/bootloader/uboot-repo/bl31_1.3/bin/g12a/bl31.img fip/ - > cp $FIPDIR/g12a/ddr3_1d.fw fip/ - > cp $FIPDIR/g12a/ddr4_1d.fw fip/ - > cp $FIPDIR/g12a/ddr4_2d.fw fip/ - > cp $FIPDIR/g12a/diag_lpddr4.fw fip/ - > cp $FIPDIR/g12a/lpddr4_1d.fw fip/ - > cp $FIPDIR/g12a/lpddr4_2d.fw fip/ - > cp $FIPDIR/g12a/piei.fw fip/ - > cp u-boot.bin fip/bl33.bin - - > sh fip/blx_fix.sh \ - fip/bl30.bin \ - fip/zero_tmp \ - fip/bl30_zero.bin \ - fip/bl301.bin \ - fip/bl301_zero.bin \ - fip/bl30_new.bin \ - bl30 - - > sh fip/blx_fix.sh \ - fip/bl2.bin \ - fip/zero_tmp \ - fip/bl2_zero.bin \ - fip/acs.bin \ - fip/bl21_zero.bin \ - fip/bl2_new.bin \ - bl2 - - > $FIPDIR/g12a/aml_encrypt_g12a --bl30sig --input fip/bl30_new.bin \ - --output fip/bl30_new.bin.g12a.enc \ - --level v3 - > $FIPDIR/g12a/aml_encrypt_g12a --bl3sig --input fip/bl30_new.bin.g12a.enc \ - --output fip/bl30_new.bin.enc \ - --level v3 --type bl30 - > $FIPDIR/g12a/aml_encrypt_g12a --bl3sig --input fip/bl31.img \ - --output fip/bl31.img.enc \ - --level v3 --type bl31 - > $FIPDIR/g12a/aml_encrypt_g12a --bl3sig --input fip/bl33.bin --compress lz4 \ - --output fip/bl33.bin.enc \ - --level v3 --type bl33 - > $FIPDIR/g12a/aml_encrypt_g12a --bl2sig --input fip/bl2_new.bin \ - --output fip/bl2.n.bin.sig - > $FIPDIR/g12a/aml_encrypt_g12a --bootmk \ - --output fip/u-boot.bin \ - --bl2 fip/bl2.n.bin.sig \ - --bl30 fip/bl30_new.bin.enc \ - --bl31 fip/bl31.img.enc \ - --bl33 fip/bl33.bin.enc \ - --ddrfw1 fip/ddr4_1d.fw \ - --ddrfw2 fip/ddr4_2d.fw \ - --ddrfw3 fip/ddr3_1d.fw \ - --ddrfw4 fip/piei.fw \ - --ddrfw5 fip/lpddr4_1d.fw \ - --ddrfw6 fip/lpddr4_2d.fw \ - --ddrfw7 fip/diag_lpddr4.fw \ - --level v3 - -and then write the image to SD with: - - > DEV=/dev/your_sd_device - > dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1 - > dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444 diff --git a/board/amlogic/sei610/README b/board/amlogic/sei610/README deleted file mode 100644 index d96a94b5e9..0000000000 --- a/board/amlogic/sei610/README +++ /dev/null @@ -1,118 +0,0 @@ -U-Boot for Amlogic SEI610 -========================= - -SEI610 is a customer board manufactured by SEI Robotics with the following -specifications: - - - Amlogic S905X3 ARM Cortex-A55 quad-core SoC - - 2GB DDR4 SDRAM - - 10/100 Ethernet (Internal PHY) - - 1 x USB 3.0 Host - - 1 x USB Type-C DRD - - 1 x FTDI USB Serial Debug Interface - - eMMC - - SDcard - - Infrared receiver - - SDIO WiFi Module - -u-boot compilation -================== - - > export CROSS_COMPILE=aarch64-none-elf- - > make sei610_defconfig - > make - -Image creation -============== - -Amlogic doesn't provide sources for the firmware and for tools needed -to create the bootloader image, so it is necessary to obtain them from -the git tree published by the board vendor: - - > wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz - > wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz - > tar xvfJ gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz - > tar xvfJ gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz - > export PATH=$PWD/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux/bin:$PWD/gcc-linaro-arm-none-eabi-4.8-2013.11_linux/bin:$PATH - > git clone https://github.com/BayLibre/u-boot.git -b buildroot-openlinux-4.9-g12a-201904 amlogic-u-boot - > cd amlogic-u-boot - > make sm1_ac200_v1_defconfig - > make - > export UBOOTDIR=$PWD - -Download the latest Amlogic Buildroot package, and extract it : - > wget http://openlinux2.amlogic.com:8000/ARM/filesystem/buildroot-openlinux-A113-201901.tgz - > tar xfz buildroot-openlinux-A113-201901.tgz buildroot-openlinux-A113-201901/bootloader - > export BRDIR=$PWD/buildroot-openlinux-A113-201901 - > export FIPDIR=$BRDIR/bootloader/uboot-repo/fip - -Go back to mainline U-Boot source tree then : - > mkdir fip - - > wget https://github.com/BayLibre/u-boot/releases/download/v2017.11-libretech-cc/blx_fix_g12a.sh -O fip/blx_fix.sh - > cp $UBOOTDIR/build/scp_task/bl301.bin fip/ - > cp $UBOOTDIR/build/board/amlogic/g12a_u200_v1/firmware/acs.bin fip/ - > cp $BRDIR/bootloader/uboot-repo/bl2/bin/g12a/bl2.bin fip/ - > cp $BRDIR/bootloader/uboot-repo/bl30/bin/g12a/bl30.bin fip/ - > cp $BRDIR/bootloader/uboot-repo/bl31_1.3/bin/g12a/bl31.img fip/ - > cp $FIPDIR/g12a/ddr3_1d.fw fip/ - > cp $FIPDIR/g12a/ddr4_1d.fw fip/ - > cp $FIPDIR/g12a/ddr4_2d.fw fip/ - > cp $FIPDIR/g12a/diag_lpddr4.fw fip/ - > cp $FIPDIR/g12a/lpddr4_1d.fw fip/ - > cp $FIPDIR/g12a/lpddr4_2d.fw fip/ - > cp $FIPDIR/g12a/piei.fw fip/ - > cp u-boot.bin fip/bl33.bin - - > sh fip/blx_fix.sh \ - fip/bl30.bin \ - fip/zero_tmp \ - fip/bl30_zero.bin \ - fip/bl301.bin \ - fip/bl301_zero.bin \ - fip/bl30_new.bin \ - bl30 - - > sh fip/blx_fix.sh \ - fip/bl2.bin \ - fip/zero_tmp \ - fip/bl2_zero.bin \ - fip/acs.bin \ - fip/bl21_zero.bin \ - fip/bl2_new.bin \ - bl2 - - > $FIPDIR/g12a/aml_encrypt_g12a --bl30sig --input fip/bl30_new.bin \ - --output fip/bl30_new.bin.g12a.enc \ - --level v3 - > $FIPDIR/g12a/aml_encrypt_g12a --bl3sig --input fip/bl30_new.bin.g12a.enc \ - --output fip/bl30_new.bin.enc \ - --level v3 --type bl30 - > $FIPDIR/g12a/aml_encrypt_g12a --bl3sig --input fip/bl31.img \ - --output fip/bl31.img.enc \ - --level v3 --type bl31 - > $FIPDIR/g12a/aml_encrypt_g12a --bl3sig --input fip/bl33.bin --compress lz4 \ - --output fip/bl33.bin.enc \ - --level v3 --type bl33 - > $FIPDIR/g12a/aml_encrypt_g12a --bl2sig --input fip/bl2_new.bin \ - --output fip/bl2.n.bin.sig - > $FIPDIR/g12a/aml_encrypt_g12a --bootmk \ - --output fip/u-boot.bin \ - --bl2 fip/bl2.n.bin.sig \ - --bl30 fip/bl30_new.bin.enc \ - --bl31 fip/bl31.img.enc \ - --bl33 fip/bl33.bin.enc \ - --ddrfw1 fip/ddr4_1d.fw \ - --ddrfw2 fip/ddr4_2d.fw \ - --ddrfw3 fip/ddr3_1d.fw \ - --ddrfw4 fip/piei.fw \ - --ddrfw5 fip/lpddr4_1d.fw \ - --ddrfw6 fip/lpddr4_2d.fw \ - --ddrfw7 fip/diag_lpddr4.fw \ - --level v3 - -and then write the image to SD with: - - > DEV=/dev/your_sd_device - > dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1 - > dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444 diff --git a/board/amlogic/u200/README b/board/amlogic/u200/README deleted file mode 100644 index a4080eb299..0000000000 --- a/board/amlogic/u200/README +++ /dev/null @@ -1,127 +0,0 @@ -U-Boot for Amlogic U200 -======================= - -U200 is a reference board manufactured by Amlogic with the following -specifications: - - - Amlogic S905D2 ARM Cortex-A53 quad-core SoC - - 2GB DDR4 SDRAM - - 10/100 Ethernet (Internal PHY) - - 1 x USB 3.0 Host - - eMMC - - SDcard - - Infrared receiver - - SDIO WiFi Module - - MIPI DSI Connector - - Audio HAT Connector - - PCI-E M.2 Connector - -Schematics are available from Amlogic on demand. - -Currently the u-boot port supports the following devices: - - serial - - Ethernet - - Regulators - - Clock controller - -u-boot compilation -================== - - > export CROSS_COMPILE=aarch64-none-elf- - > make u200_defconfig - > make - -Image creation -============== - -Amlogic doesn't provide sources for the firmware and for tools needed -to create the bootloader image, so it is necessary to obtain them from -the git tree published by the board vendor: - - > wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz - > wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz - > tar xvfJ gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz - > tar xvfJ gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz - > export PATH=$PWD/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux/bin:$PWD/gcc-linaro-arm-none-eabi-4.8-2013.11_linux/bin:$PATH - > git clone https://github.com/BayLibre/u-boot.git -b buildroot-openlinux-20180418 amlogic-u-boot - > cd amlogic-u-boot - > make g12a_u200_v1_defconfig - > make - > export UBOOTDIR=$PWD - -Download the latest Amlogic Buildroot package, and extract it : - > wget http://openlinux2.amlogic.com:8000/ARM/filesystem/Linux_BSP/buildroot_openlinux_kernel_4.9_fbdev_20180706.tar.gz - > tar xfz buildroot_openlinux_kernel_4.9_fbdev_20180706.tar.gz buildroot_openlinux_kernel_4.9_fbdev_20180706/bootloader - > export BRDIR=$PWD/buildroot_openlinux_kernel_4.9_fbdev_20180706 - > export FIPDIR=$BRDIR/bootloader/uboot-repo/fip - -Go back to mainline U-Boot source tree then : - > mkdir fip - - > wget https://github.com/BayLibre/u-boot/releases/download/v2017.11-libretech-cc/blx_fix_g12a.sh -O fip/blx_fix.sh - > cp $UBOOTDIR/build/scp_task/bl301.bin fip/ - > cp $UBOOTDIR/build/board/amlogic/g12a_u200_v1/firmware/acs.bin fip/ - > cp $BRDIR/bootloader/uboot-repo/bl2/bin/g12a/bl2.bin fip/ - > cp $BRDIR/bootloader/uboot-repo/bl30/bin/g12a/bl30.bin fip/ - > cp $BRDIR/bootloader/uboot-repo/bl31_1.3/bin/g12a/bl31.img fip/ - > cp $FIPDIR/g12a/ddr3_1d.fw fip/ - > cp $FIPDIR/g12a/ddr4_1d.fw fip/ - > cp $FIPDIR/g12a/ddr4_2d.fw fip/ - > cp $FIPDIR/g12a/diag_lpddr4.fw fip/ - > cp $FIPDIR/g12a/lpddr4_1d.fw fip/ - > cp $FIPDIR/g12a/lpddr4_2d.fw fip/ - > cp $FIPDIR/g12a/piei.fw fip/ - > cp u-boot.bin fip/bl33.bin - - > sh fip/blx_fix.sh \ - fip/bl30.bin \ - fip/zero_tmp \ - fip/bl30_zero.bin \ - fip/bl301.bin \ - fip/bl301_zero.bin \ - fip/bl30_new.bin \ - bl30 - - > sh fip/blx_fix.sh \ - fip/bl2.bin \ - fip/zero_tmp \ - fip/bl2_zero.bin \ - fip/acs.bin \ - fip/bl21_zero.bin \ - fip/bl2_new.bin \ - bl2 - - > $FIPDIR/g12a/aml_encrypt_g12a --bl30sig --input fip/bl30_new.bin \ - --output fip/bl30_new.bin.g12a.enc \ - --level v3 - > $FIPDIR/g12a/aml_encrypt_g12a --bl3sig --input fip/bl30_new.bin.g12a.enc \ - --output fip/bl30_new.bin.enc \ - --level v3 --type bl30 - > $FIPDIR/g12a/aml_encrypt_g12a --bl3sig --input fip/bl31.img \ - --output fip/bl31.img.enc \ - --level v3 --type bl31 - > $FIPDIR/g12a/aml_encrypt_g12a --bl3sig --input fip/bl33.bin --compress lz4 \ - --output fip/bl33.bin.enc \ - --level v3 --type bl33 - > $FIPDIR/g12a/aml_encrypt_g12a --bl2sig --input fip/bl2_new.bin \ - --output fip/bl2.n.bin.sig - > $FIPDIR/g12a/aml_encrypt_g12a --bootmk \ - --output fip/u-boot.bin \ - --bl2 fip/bl2.n.bin.sig \ - --bl30 fip/bl30_new.bin.enc \ - --bl31 fip/bl31.img.enc \ - --bl33 fip/bl33.bin.enc \ - --ddrfw1 fip/ddr4_1d.fw \ - --ddrfw2 fip/ddr4_2d.fw \ - --ddrfw3 fip/ddr3_1d.fw \ - --ddrfw4 fip/piei.fw \ - --ddrfw5 fip/lpddr4_1d.fw \ - --ddrfw6 fip/lpddr4_2d.fw \ - --ddrfw7 fip/diag_lpddr4.fw \ - --level v3 - -and then write the image to SD with: - - > DEV=/dev/your_sd_device - > dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1 - > dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444 diff --git a/board/amlogic/w400/README.khadas-vim3 b/board/amlogic/w400/README.khadas-vim3 deleted file mode 100644 index 399bf49295..0000000000 --- a/board/amlogic/w400/README.khadas-vim3 +++ /dev/null @@ -1,131 +0,0 @@ -U-Boot for Khadas VIM3 -====================== - -Khadas VIM3 is a single board computer manufactured by Shenzhen Wesion -Technology Co., Ltd. with the following specifications: - - - Amlogic A311D Arm Cortex-A53 dual-core + Cortex-A73 quad-core SoC - - 4GB LPDDR4 SDRAM - - Gigabit Ethernet - - HDMI 2.1 display - - 40-pin GPIO header - - 1 x USB 3.0 Host, 1 x USB 2.0 Host - - eMMC, microSD - - M.2 - - Infrared receiver - -Schematics are available on the manufacturer website. - -Currently the U-Boot port supports the following devices: - - serial - - eMMC, microSD - - Ethernet - - I2C - - Regulators - - Reset controller - - Clock controller - - ADC - -u-boot compilation -================== - - > export CROSS_COMPILE=aarch64-none-elf- - > make khadas-vim3_defconfig - > make - -Image creation -============== - -Amlogic doesn't provide sources for the firmware and for tools needed -to create the bootloader image, so it is necessary to obtain them from -the git tree published by the board vendor: - - > wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz - > wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz - > tar xvfJ gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz - > tar xvfJ gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz - > export PATH=$PWD/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux/bin:$PWD/gcc-linaro-arm-none-eabi-4.8-2013.11_linux/bin:$PATH - - > DIR=vim3-u-boot - > git clone --depth 1 \ - https://github.com/khadas/u-boot.git -b khadas-vims-v2015.01 \ - $DIR - - > cd vim3-u-boot - > make kvim3_defconfig - > make - > export UBOOTDIR=$PWD - - Go back to mainline U-Boot source tree then : - > mkdir fip - - > cp $UBOOTDIR/build/scp_task/bl301.bin fip/ - > cp $UBOOTDIR/build/board/khadas/kvim3/firmware/acs.bin fip/ - > cp $UBOOTDIR/fip/g12b/bl2.bin fip/ - > cp $UBOOTDIR/fip/g12b/bl30.bin fip/ - > cp $UBOOTDIR/fip/g12b/bl31.img fip/ - > cp $UBOOTDIR/fip/g12b/ddr3_1d.fw fip/ - > cp $UBOOTDIR/fip/g12b/ddr4_1d.fw fip/ - > cp $UBOOTDIR/fip/g12b/ddr4_2d.fw fip/ - > cp $UBOOTDIR/fip/g12b/diag_lpddr4.fw fip/ - > cp $UBOOTDIR/fip/g12b/lpddr3_1d.fw fip/ - > cp $UBOOTDIR/fip/g12b/lpddr4_1d.fw fip/ - > cp $UBOOTDIR/fip/g12b/lpddr4_2d.fw fip/ - > cp $UBOOTDIR/fip/g12b/piei.fw fip/ - > cp $UBOOTDIR/fip/g12b/aml_ddr.fw fip/ - > cp u-boot.bin fip/bl33.bin - - > sh fip/blx_fix.sh \ - fip/bl30.bin \ - fip/zero_tmp \ - fip/bl30_zero.bin \ - fip/bl301.bin \ - fip/bl301_zero.bin \ - fip/bl30_new.bin \ - bl30 - - > sh fip/blx_fix.sh \ - fip/bl2.bin \ - fip/zero_tmp \ - fip/bl2_zero.bin \ - fip/acs.bin \ - fip/bl21_zero.bin \ - fip/bl2_new.bin \ - bl2 - - > $UBOOTDIR/fip/g12b/aml_encrypt_g12b --bl30sig --input fip/bl30_new.bin \ - --output fip/bl30_new.bin.g12a.enc \ - --level v3 - > $UBOOTDIR/fip/g12b/aml_encrypt_g12b --bl3sig --input fip/bl30_new.bin.g12a.enc \ - --output fip/bl30_new.bin.enc \ - --level v3 --type bl30 - > $UBOOTDIR/fip/g12b/aml_encrypt_g12b --bl3sig --input fip/bl31.img \ - --output fip/bl31.img.enc \ - --level v3 --type bl31 - > $UBOOTDIR/fip/g12b/aml_encrypt_g12b --bl3sig --input fip/bl33.bin --compress lz4 \ - --output fip/bl33.bin.enc \ - --level v3 --type bl33 --compress lz4 - > $UBOOTDIR/fip/g12b/aml_encrypt_g12b --bl2sig --input fip/bl2_new.bin \ - --output fip/bl2.n.bin.sig - > $UBOOTDIR/fip/g12b/aml_encrypt_g12b --bootmk \ - --output fip/u-boot.bin \ - --bl2 fip/bl2.n.bin.sig \ - --bl30 fip/bl30_new.bin.enc \ - --bl31 fip/bl31.img.enc \ - --bl33 fip/bl33.bin.enc \ - --ddrfw1 fip/ddr4_1d.fw \ - --ddrfw2 fip/ddr4_2d.fw \ - --ddrfw3 fip/ddr3_1d.fw \ - --ddrfw4 fip/piei.fw \ - --ddrfw5 fip/lpddr4_1d.fw \ - --ddrfw6 fip/lpddr4_2d.fw \ - --ddrfw7 fip/diag_lpddr4.fw \ - --ddrfw8 fip/aml_ddr.fw \ - --ddrfw9 fip/lpddr3_1d.fw \ - --level v3 - -and then write the image to SD with: - - > DEV=/dev/your_sd_device - > dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1 - > dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444 diff --git a/board/amlogic/w400/README.khadas-vim3l b/board/amlogic/w400/README.khadas-vim3l deleted file mode 100644 index b2d9abbfd9..0000000000 --- a/board/amlogic/w400/README.khadas-vim3l +++ /dev/null @@ -1,131 +0,0 @@ -U-Boot for Khadas VIM3L -======================= - -Khadas VIM3L is a single board computer manufactured by Shenzhen Wesion -Technology Co., Ltd. with the following specifications: - - - Amlogic S905D3 Arm Cortex-A55 quad-core SoC - - 2GB LPDDR4 SDRAM - - Gigabit Ethernet - - HDMI 2.1 display - - 40-pin GPIO header - - 1 x USB 3.0 Host, 1 x USB 2.0 Host - - eMMC, microSD - - M.2 - - Infrared receiver - -Schematics are available on the manufacturer website. - -Currently the U-Boot port supports the following devices: - - serial - - eMMC, microSD - - Ethernet - - I2C - - Regulators - - Reset controller - - Clock controller - - ADC - -u-boot compilation -================== - - > export CROSS_COMPILE=aarch64-none-elf- - > make khadas-vim3l_defconfig - > make - -Image creation -============== - -Amlogic doesn't provide sources for the firmware and for tools needed -to create the bootloader image, so it is necessary to obtain them from -the git tree published by the board vendor: - - > wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz - > wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz - > tar xvfJ gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz - > tar xvfJ gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz - > export PATH=$PWD/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux/bin:$PWD/gcc-linaro-arm-none-eabi-4.8-2013.11_linux/bin:$PATH - - > DIR=vim3l-u-boot - > git clone --depth 1 \ - https://github.com/khadas/u-boot.git -b khadas-vims-v2015.01 \ - $DIR - - > cd vim3l-u-boot - > make kvim3l_defconfig - > make - > export UBOOTDIR=$PWD - - Go back to mainline U-Boot source tree then : - > mkdir fip - - > cp $UBOOTDIR/build/scp_task/bl301.bin fip/ - > cp $UBOOTDIR/build/board/khadas/kvim3l/firmware/acs.bin fip/ - > cp $UBOOTDIR/fip/g12a/bl2.bin fip/ - > cp $UBOOTDIR/fip/g12a/bl30.bin fip/ - > cp $UBOOTDIR/fip/g12a/bl31.img fip/ - > cp $UBOOTDIR/fip/g12a/ddr3_1d.fw fip/ - > cp $UBOOTDIR/fip/g12a/ddr4_1d.fw fip/ - > cp $UBOOTDIR/fip/g12a/ddr4_2d.fw fip/ - > cp $UBOOTDIR/fip/g12a/diag_lpddr4.fw fip/ - > cp $UBOOTDIR/fip/g12a/lpddr3_1d.fw fip/ - > cp $UBOOTDIR/fip/g12a/lpddr4_1d.fw fip/ - > cp $UBOOTDIR/fip/g12a/lpddr4_2d.fw fip/ - > cp $UBOOTDIR/fip/g12a/piei.fw fip/ - > cp $UBOOTDIR/fip/g12a/aml_ddr.fw fip/ - > cp u-boot.bin fip/bl33.bin - - > sh fip/blx_fix.sh \ - fip/bl30.bin \ - fip/zero_tmp \ - fip/bl30_zero.bin \ - fip/bl301.bin \ - fip/bl301_zero.bin \ - fip/bl30_new.bin \ - bl30 - - > sh fip/blx_fix.sh \ - fip/bl2.bin \ - fip/zero_tmp \ - fip/bl2_zero.bin \ - fip/acs.bin \ - fip/bl21_zero.bin \ - fip/bl2_new.bin \ - bl2 - - > $UBOOTDIR/fip/g12a/aml_encrypt_g12a --bl30sig --input fip/bl30_new.bin \ - --output fip/bl30_new.bin.g12a.enc \ - --level v3 - > $UBOOTDIR/fip/g12a/aml_encrypt_g12a --bl3sig --input fip/bl30_new.bin.g12a.enc \ - --output fip/bl30_new.bin.enc \ - --level v3 --type bl30 - > $UBOOTDIR/fip/g12a/aml_encrypt_g12a --bl3sig --input fip/bl31.img \ - --output fip/bl31.img.enc \ - --level v3 --type bl31 - > $UBOOTDIR/fip/g12a/aml_encrypt_g12a --bl3sig --input fip/bl33.bin --compress lz4 \ - --output fip/bl33.bin.enc \ - --level v3 --type bl33 --compress lz4 - > $UBOOTDIR/fip/g12a/aml_encrypt_g12a --bl2sig --input fip/bl2_new.bin \ - --output fip/bl2.n.bin.sig - > $UBOOTDIR/fip/g12a/aml_encrypt_g12a --bootmk \ - --output fip/u-boot.bin \ - --bl2 fip/bl2.n.bin.sig \ - --bl30 fip/bl30_new.bin.enc \ - --bl31 fip/bl31.img.enc \ - --bl33 fip/bl33.bin.enc \ - --ddrfw1 fip/ddr4_1d.fw \ - --ddrfw2 fip/ddr4_2d.fw \ - --ddrfw3 fip/ddr3_1d.fw \ - --ddrfw4 fip/piei.fw \ - --ddrfw5 fip/lpddr4_1d.fw \ - --ddrfw6 fip/lpddr4_2d.fw \ - --ddrfw7 fip/diag_lpddr4.fw \ - --ddrfw8 fip/aml_ddr.fw \ - --ddrfw9 fip/lpddr3_1d.fw \ - --level v3 - -and then write the image to SD with: - - > DEV=/dev/your_sd_device - > dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1 - > dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444 diff --git a/board/amlogic/w400/README.odroid-n2 b/board/amlogic/w400/README.odroid-n2 deleted file mode 100644 index 8142eebea0..0000000000 --- a/board/amlogic/w400/README.odroid-n2 +++ /dev/null @@ -1,129 +0,0 @@ -U-Boot for ODROID-N2 -==================== - -ODROID-N2 is a single board computer manufactured by Hardkernel -Co. Ltd with the following specifications: - - - Amlogic S922X ARM Cortex-A53 dual-core + Cortex-A73 quad-core SoC - - 4GB DDR4 SDRAM - - Gigabit Ethernet - - HDMI 2.1 4K/60Hz display - - 40-pin GPIO header - - 4 x USB 3.0 Host, 1 x USB OTG - - eMMC, microSD - - Infrared receiver - -Schematics are available on the manufacturer website. - -Currently the u-boot port supports the following devices: - - serial - - eMMC, microSD - - Ethernet - - I2C - - Regulators - - Reset controller - - Clock controller - - ADC - -u-boot compilation -================== - - > export CROSS_COMPILE=aarch64-none-elf- - > make odroid-n2_defconfig - > make - -Image creation -============== - -Amlogic doesn't provide sources for the firmware and for tools needed -to create the bootloader image, so it is necessary to obtain them from -the git tree published by the board vendor: - - > wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz - > wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz - > tar xvfJ gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz - > tar xvfJ gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz - > export PATH=$PWD/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux/bin:$PWD/gcc-linaro-arm-none-eabi-4.8-2013.11_linux/bin:$PATH - - > DIR=odroid-n2 - > git clone --depth 1 \ - https://github.com/hardkernel/u-boot.git -b odroidn2-v2015.01 \ - $DIR - - > cd odroid-n2 - > make odroidn2_defconfig - > make - > export UBOOTDIR=$PWD - - Go back to mainline U-Boot source tree then : - > mkdir fip - - > wget https://github.com/BayLibre/u-boot/releases/download/v2017.11-libretech-cc/blx_fix_g12a.sh -O fip/blx_fix.sh - > cp $UBOOTDIR/build/scp_task/bl301.bin fip/ - > cp $UBOOTDIR/build/board/hardkernel/odroidn2/firmware/acs.bin fip/ - > cp $UBOOTDIR/fip/g12b/bl2.bin fip/ - > cp $UBOOTDIR/fip/g12b/bl30.bin fip/ - > cp $UBOOTDIR/fip/g12b/bl31.img fip/ - > cp $UBOOTDIR/fip/g12b/ddr3_1d.fw fip/ - > cp $UBOOTDIR/fip/g12b/ddr4_1d.fw fip/ - > cp $UBOOTDIR/fip/g12b/ddr4_2d.fw fip/ - > cp $UBOOTDIR/fip/g12b/diag_lpddr4.fw fip/ - > cp $UBOOTDIR/fip/g12b/lpddr4_1d.fw fip/ - > cp $UBOOTDIR/fip/g12b/lpddr4_2d.fw fip/ - > cp $UBOOTDIR/fip/g12b/piei.fw fip/ - > cp $UBOOTDIR/fip/g12b/aml_ddr.fw fip/ - > cp u-boot.bin fip/bl33.bin - - > sh fip/blx_fix.sh \ - fip/bl30.bin \ - fip/zero_tmp \ - fip/bl30_zero.bin \ - fip/bl301.bin \ - fip/bl301_zero.bin \ - fip/bl30_new.bin \ - bl30 - - > sh fip/blx_fix.sh \ - fip/bl2.bin \ - fip/zero_tmp \ - fip/bl2_zero.bin \ - fip/acs.bin \ - fip/bl21_zero.bin \ - fip/bl2_new.bin \ - bl2 - - > $UBOOTDIR/fip/g12b/aml_encrypt_g12b --bl30sig --input fip/bl30_new.bin \ - --output fip/bl30_new.bin.g12a.enc \ - --level v3 - > $UBOOTDIR/fip/g12b/aml_encrypt_g12b --bl3sig --input fip/bl30_new.bin.g12a.enc \ - --output fip/bl30_new.bin.enc \ - --level v3 --type bl30 - > $UBOOTDIR/fip/g12b/aml_encrypt_g12b --bl3sig --input fip/bl31.img \ - --output fip/bl31.img.enc \ - --level v3 --type bl31 - > $UBOOTDIR/fip/g12b/aml_encrypt_g12b --bl3sig --input fip/bl33.bin --compress lz4 \ - --output fip/bl33.bin.enc \ - --level v3 --type bl33 --compress lz4 - > $UBOOTDIR/fip/g12b/aml_encrypt_g12b --bl2sig --input fip/bl2_new.bin \ - --output fip/bl2.n.bin.sig - > $UBOOTDIR/fip/g12b/aml_encrypt_g12b --bootmk \ - --output fip/u-boot.bin \ - --bl2 fip/bl2.n.bin.sig \ - --bl30 fip/bl30_new.bin.enc \ - --bl31 fip/bl31.img.enc \ - --bl33 fip/bl33.bin.enc \ - --ddrfw1 fip/ddr4_1d.fw \ - --ddrfw2 fip/ddr4_2d.fw \ - --ddrfw3 fip/ddr3_1d.fw \ - --ddrfw4 fip/piei.fw \ - --ddrfw5 fip/lpddr4_1d.fw \ - --ddrfw6 fip/lpddr4_2d.fw \ - --ddrfw7 fip/diag_lpddr4.fw \ - --ddrfw8 fip/aml_ddr.fw \ - --level v3 - -and then write the image to SD with: - - > DEV=/dev/your_sd_device - > dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1 - > dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444 diff --git a/board/amlogic/w400/README.w400 b/board/amlogic/w400/README.w400 deleted file mode 100644 index c129717a11..0000000000 --- a/board/amlogic/w400/README.w400 +++ /dev/null @@ -1,129 +0,0 @@ -U-Boot for Amlogic W400 -======================= - -U200 is a reference board manufactured by Amlogic with the following -specifications: - - - Amlogic S922X ARM Cortex-A53 dual-core + Cortex-A73 quad-core SoC - - 2GB DDR4 SDRAM - - 10/100 Ethernet (Internal PHY) - - 1 x USB 3.0 Host - - eMMC - - SDcard - - Infrared receiver - - SDIO WiFi Module - - MIPI DSI Connector - - Audio HAT Connector - - PCI-E M.2 Connector - -Schematics are available from Amlogic on demand. - -Currently the u-boot port supports the following devices: - - serial - - Ethernet - - Regulators - - Clock controller - -u-boot compilation -================== - - > export CROSS_COMPILE=aarch64-none-elf- - > make w400_defconfig - > make - -Image creation -============== - -Amlogic doesn't provide sources for the firmware and for tools needed -to create the bootloader image, so it is necessary to obtain them from -the git tree published by the board vendor: - - > wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz - > wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz - > tar xvfJ gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz - > tar xvfJ gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz - > export PATH=$PWD/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux/bin:$PWD/gcc-linaro-arm-none-eabi-4.8-2013.11_linux/bin:$PATH - > git clone https://github.com/BayLibre/u-boot.git -b buildroot-openlinux-20180418 amlogic-u-boot - > cd amlogic-u-boot - > make g12b_w400_v1_defconfig - > make - > export UBOOTDIR=$PWD - -Download the latest Amlogic Buildroot package, and extract it : - > wget http://openlinux2.amlogic.com:8000/ARM/filesystem/Linux_BSP/buildroot_openlinux_kernel_4.9_fbdev_20180706.tar.gz - > tar xfz buildroot_openlinux_kernel_4.9_fbdev_20180706.tar.gz buildroot_openlinux_kernel_4.9_fbdev_20180706/bootloader - > export BRDIR=$PWD/buildroot_openlinux_kernel_4.9_fbdev_20180706 - > export FIPDIR=$BRDIR/bootloader/uboot-repo/fip - -Go back to mainline U-Boot source tree then : - > mkdir fip - - > wget https://github.com/BayLibre/u-boot/releases/download/v2017.11-libretech-cc/blx_fix_g12a.sh -O fip/blx_fix.sh - > cp $UBOOTDIR/build/scp_task/bl301.bin fip/ - > cp $UBOOTDIR/build/board/amlogic/g12b_w400_v1/firmware/acs.bin fip/ - > cp $BRDIR/bootloader/uboot-repo/bl2/bin/g12b/bl2.bin fip/ - > cp $BRDIR/bootloader/uboot-repo/bl30/bin/g12b/bl30.bin fip/ - > cp $BRDIR/bootloader/uboot-repo/bl31_1.3/bin/g12b/bl31.img fip/ - > cp $FIPDIR/g12b/ddr3_1d.fw fip/ - > cp $FIPDIR/g12b/ddr4_1d.fw fip/ - > cp $FIPDIR/g12b/ddr4_2d.fw fip/ - > cp $FIPDIR/g12b/diag_lpddr4.fw fip/ - > cp $FIPDIR/g12b/lpddr4_1d.fw fip/ - > cp $FIPDIR/g12b/lpddr4_2d.fw fip/ - > cp $FIPDIR/g12b/piei.fw fip/ - > cp $FIPDIR/g12b/aml_ddr.fw fip/ - > cp u-boot.bin fip/bl33.bin - - > sh fip/blx_fix.sh \ - fip/bl30.bin \ - fip/zero_tmp \ - fip/bl30_zero.bin \ - fip/bl301.bin \ - fip/bl301_zero.bin \ - fip/bl30_new.bin \ - bl30 - - > sh fip/blx_fix.sh \ - fip/bl2.bin \ - fip/zero_tmp \ - fip/bl2_zero.bin \ - fip/acs.bin \ - fip/bl21_zero.bin \ - fip/bl2_new.bin \ - bl2 - - > $FIPDIR/g12b/aml_encrypt_g12b --bl30sig --input fip/bl30_new.bin \ - --output fip/bl30_new.bin.g12a.enc \ - --level v3 - > $FIPDIR/g12b/aml_encrypt_g12b --bl3sig --input fip/bl30_new.bin.g12a.enc \ - --output fip/bl30_new.bin.enc \ - --level v3 --type bl30 - > $FIPDIR/g12b/aml_encrypt_g12b --bl3sig --input fip/bl31.img \ - --output fip/bl31.img.enc \ - --level v3 --type bl31 - > $FIPDIR/g12b/aml_encrypt_g12b --bl3sig --input fip/bl33.bin --compress lz4 \ - --output fip/bl33.bin.enc \ - --level v3 --type bl33 - > $FIPDIR/g12b/aml_encrypt_g12b --bl2sig --input fip/bl2_new.bin \ - --output fip/bl2.n.bin.sig - > $FIPDIR/g12b/aml_encrypt_g12b --bootmk \ - --output fip/u-boot.bin \ - --bl2 fip/bl2.n.bin.sig \ - --bl30 fip/bl30_new.bin.enc \ - --bl31 fip/bl31.img.enc \ - --bl33 fip/bl33.bin.enc \ - --ddrfw1 fip/ddr4_1d.fw \ - --ddrfw2 fip/ddr4_2d.fw \ - --ddrfw3 fip/ddr3_1d.fw \ - --ddrfw4 fip/piei.fw \ - --ddrfw5 fip/lpddr4_1d.fw \ - --ddrfw6 fip/lpddr4_2d.fw \ - --ddrfw7 fip/diag_lpddr4.fw \ - --ddrfw8 fip/aml_ddr.fw \ - --level v3 - -and then write the image to SD with: - - > DEV=/dev/your_sd_device - > dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1 - > dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444 diff --git a/doc/board/amlogic/index.rst b/doc/board/amlogic/index.rst new file mode 100644 index 0000000000..3730419167 --- /dev/null +++ b/doc/board/amlogic/index.rst @@ -0,0 +1,95 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +Amlogic +======= + +Hardware Support Matrix +----------------------- + +An up-do-date matrix is also available on: http://linux-meson.com + +This matrix concerns the actual source code version. + ++-------------------------------+-----------+--------------+--------------+------------+------------+-------------+--------------+ +| | S905 | S905X | S912 | A113X | S905X2 | S922X | S905X3 | +| | | S805X | S905D | | S905D2 | A311D | S905D3 | +| | | | | | S905Y2 | | | ++===============================+===========+==============+==============+============+============+=============+==============+ +| Boards | Odroid-C2 | P212 | Khadas VIM2 | S400 | U200 | Odroid-N2 | SEI610 | +| | Nanopi-K2 | Khadas-VIM | Libretech-PC | | SEI510 | Khadas-VIM3 | Khadas-VIM3L | +| | P200 | LibreTech-CC | | | | | | +| | P201 | LibreTech-AC | | | | | | ++-------------------------------+-----------+--------------+--------------+------------+------------+-------------+--------------+ +| UART | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | ++-------------------------------+-----------+--------------+--------------+------------+------------+-------------+--------------+ +| Pinctrl/GPIO | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | ++-------------------------------+-----------+--------------+--------------+------------+------------+-------------+--------------+ +| Clock Control | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | ++-------------------------------+-----------+--------------+--------------+------------+------------+-------------+--------------+ +| PWM | No | No | No | No | No | No | No | ++-------------------------------+-----------+--------------+--------------+------------+------------+-------------+--------------+ +| Reset Control | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | ++-------------------------------+-----------+--------------+--------------+------------+------------+-------------+--------------+ +| Infrared Decoder | No | No | No | No | No | No | No | ++-------------------------------+-----------+--------------+--------------+------------+------------+-------------+--------------+ +| Ethernet | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | ++-------------------------------+-----------+--------------+--------------+------------+------------+-------------+--------------+ +| Multi-core | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | ++-------------------------------+-----------+--------------+--------------+------------+------------+-------------+--------------+ +| Fuse access | **Yes** | **Yes** |**Yes** |**Yes** |**Yes** |**Yes** | **Yes** | ++-------------------------------+-----------+--------------+--------------+------------+------------+-------------+--------------+ +| SPI (FC) | **Yes** | **Yes** | **Yes** | **Yes** |**Yes** | **Yes** | No | ++-------------------------------+-----------+--------------+--------------+------------+------------+-------------+--------------+ +| SPI (CC) | No | No | No | No | No | No | No | ++-------------------------------+-----------+--------------+--------------+------------+------------+-------------+--------------+ +| I2C | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | ++-------------------------------+-----------+--------------+--------------+------------+------------+-------------+--------------+ +| USB | **Yes** | **Yes** | **Yes** | No | **Yes** | **Yes** | **Yes** | ++-------------------------------+-----------+--------------+--------------+------------+------------+-------------+--------------+ +| USB OTG | No | **Yes** | **Yes** | No | **Yes** | **Yes** | **Yes** | ++-------------------------------+-----------+--------------+--------------+------------+------------+-------------+--------------+ +| eMMC | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | ++-------------------------------+-----------+--------------+--------------+------------+------------+-------------+--------------+ +| SDCard | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | ++-------------------------------+-----------+--------------+--------------+------------+------------+-------------+--------------+ +| NAND | No | No | No | No | No | No | No | ++-------------------------------+-----------+--------------+--------------+------------+------------+-------------+--------------+ +| ADC | **Yes** | **Yes** | **Yes** | No | No | No | No | ++-------------------------------+-----------+--------------+--------------+------------+------------+-------------+--------------+ +| CVBS Output | **Yes** | **Yes** | **Yes** | *N/A* | **Yes** | **Yes** | **Yes** | ++-------------------------------+-----------+--------------+--------------+------------+------------+-------------+--------------+ +| HDMI Output | **Yes** | **Yes** | **Yes** | *N/A* | **Yes** | **Yes** | **Yes** | ++-------------------------------+-----------+--------------+--------------+------------+------------+-------------+--------------+ +| CEC | No | No | No | *N/A* | No | No | No | ++-------------------------------+-----------+--------------+--------------+------------+------------+-------------+--------------+ +| Thermal Sensor | No | No | No | No | No | No | No | ++-------------------------------+-----------+--------------+--------------+------------+------------+-------------+--------------+ +| LCD/LVDS Output | No | *N/A* | No | No | No | No | No | ++-------------------------------+-----------+--------------+--------------+------------+------------+-------------+--------------+ +| SoC (version) information | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | ++-------------------------------+-----------+--------------+--------------+------------+------------+-------------+--------------+ + +Board Documentation +------------------- + +.. toctree:: + :maxdepth: 1 + + khadas-vim2 + khadas-vim3l + khadas-vim3 + khadas-vim + libretech-ac + libretech-cc + nanopi-k2 + odroid-c2 + odroid-n2 + p200 + p201 + p212 + q200 + s400 + sei510 + sei610 + u200 + w400 diff --git a/doc/board/amlogic/khadas-vim.rst b/doc/board/amlogic/khadas-vim.rst new file mode 100644 index 0000000000..bbb61c29ef --- /dev/null +++ b/doc/board/amlogic/khadas-vim.rst @@ -0,0 +1,101 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +U-Boot for Khadas VIM +====================== + +Khadas VIM is an Open Source DIY Box manufactured by Shenzhen Wesion +Technology Co., Ltd with the following specifications: + + - Amlogic S905X ARM Cortex-A53 quad-core SoC @ 1.5GHz + - ARM Mali 450 GPU + - 2GB DDR3 SDRAM + - 10/100 Ethernet + - HDMI 2.0 4K/60Hz display + - 40-pin GPIO header + - 2 x USB 2.0 Host, 1 x USB 2.0 Type-C OTG + - 8GB/16GBeMMC + - microSD + - SDIO Wifi Module, Bluetooth + - Two channels IR receiver + +U-Boot compilation +------------------ + +.. code-block:: bash + + $ export CROSS_COMPILE=aarch64-none-elf- + $ make khadas-vim_defconfig + $ make + +Image creation +-------------- + +Amlogic doesn't provide sources for the firmware and for tools needed +to create the bootloader image, so it is necessary to obtain them from +the git tree published by the board vendor: + +.. code-block:: bash + + $ wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz + $ wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz + $ tar xvfJ gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz + $ tar xvfJ gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz + $ export PATH=$PWD/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux/bin:$PWD/gcc-linaro-arm-none-eabi-4.8-2013.11_linux/bin:$PATH + $ git clone https://github.com/khadas/u-boot -b Vim vim-u-boot + $ cd vim-u-boot + $ make kvim_defconfig + $ make CROSS_COMPILE=aarch64-none-elf- + $ export FIPDIR=$PWD/fip + +Go back to mainline U-Boot source tree then : + +.. code-block:: bash + + $ mkdir fip + + $ cp $FIPDIR/gxl/bl2.bin fip/ + $ cp $FIPDIR/gxl/acs.bin fip/ + $ cp $FIPDIR/gxl/bl21.bin fip/ + $ cp $FIPDIR/gxl/bl30.bin fip/ + $ cp $FIPDIR/gxl/bl301.bin fip/ + $ cp $FIPDIR/gxl/bl31.img fip/ + $ cp u-boot.bin fip/bl33.bin + + $ $FIPDIR/blx_fix.sh \ + fip/bl30.bin \ + fip/zero_tmp \ + fip/bl30_zero.bin \ + fip/bl301.bin \ + fip/bl301_zero.bin \ + fip/bl30_new.bin \ + bl30 + + $ python $FIPDIR/acs_tool.pyc fip/bl2.bin fip/bl2_acs.bin fip/acs.bin 0 + + $ $FIPDIR/blx_fix.sh \ + fip/bl2_acs.bin \ + fip/zero_tmp \ + fip/bl2_zero.bin \ + fip/bl21.bin \ + fip/bl21_zero.bin \ + fip/bl2_new.bin \ + bl2 + + $ $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl30_new.bin + $ $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl31.img + $ $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl33.bin + $ $FIPDIR/gxl/aml_encrypt_gxl --bl2sig --input fip/bl2_new.bin --output fip/bl2.n.bin.sig + $ $FIPDIR/gxl/aml_encrypt_gxl --bootmk \ + --output fip/u-boot.bin \ + --bl2 fip/bl2.n.bin.sig \ + --bl30 fip/bl30_new.bin.enc \ + --bl31 fip/bl31.img.enc \ + --bl33 fip/bl33.bin.enc + +and then write the image to SD with: + +.. code-block:: bash + + $ DEV=/dev/your_sd_device + $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1 + $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444 diff --git a/doc/board/amlogic/khadas-vim2.rst b/doc/board/amlogic/khadas-vim2.rst new file mode 100644 index 0000000000..c57d96d8b0 --- /dev/null +++ b/doc/board/amlogic/khadas-vim2.rst @@ -0,0 +1,102 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +U-Boot for Khadas VIM2 +======================= + +Khadas VIM2 is an Open Source DIY Box manufactured by Shenzhen Wesion +Technology Co., Ltd with the following specifications: + + - Amlogic S912 ARM Cortex-A53 octo-core SoC @ 1.5GHz + - ARM Mali T860 GPU + - 2/3GB DDR4 SDRAM + - 10/100/1000 Ethernet + - HDMI 2.0 4K/60Hz display + - 40-pin GPIO header + - 2 x USB 2.0 Host, 1 x USB 2.0 Type-C OTG + - 16GB/32GB/64GB eMMC + - 2MB SPI Flash + - microSD + - SDIO Wifi Module, Bluetooth + - Two channels IR receiver + +U-Boot compilation +------------------ + +.. code-block:: bash + + $ export CROSS_COMPILE=aarch64-none-elf- + $ make khadas-vim2_defconfig + $ make + +Image creation +-------------- + +Amlogic doesn't provide sources for the firmware and for tools needed +to create the bootloader image, so it is necessary to obtain them from +the git tree published by the board vendor: + +.. code-block:: bash + + $ wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz + $ wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz + $ tar xvfJ gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz + $ tar xvfJ gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz + $ export PATH=$PWD/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux/bin:$PWD/gcc-linaro-arm-none-eabi-4.8-2013.11_linux/bin:$PATH + $ git clone https://github.com/khadas/u-boot -b khadas-vim-v2015.01 vim-u-boot + $ cd vim-u-boot + $ make kvim2_defconfig + $ make + $ export FIPDIR=$PWD/fip + +Go back to mainline U-Boot source tree then : + +.. code-block:: bash + + $ mkdir fip + + $ cp $FIPDIR/gxl/bl2.bin fip/ + $ cp $FIPDIR/gxl/acs.bin fip/ + $ cp $FIPDIR/gxl/bl21.bin fip/ + $ cp $FIPDIR/gxl/bl30.bin fip/ + $ cp $FIPDIR/gxl/bl301.bin fip/ + $ cp $FIPDIR/gxl/bl31.img fip/ + $ cp u-boot.bin fip/bl33.bin + + $ $FIPDIR/blx_fix.sh \ + fip/bl30.bin \ + fip/zero_tmp \ + fip/bl30_zero.bin \ + fip/bl301.bin \ + fip/bl301_zero.bin \ + fip/bl30_new.bin \ + bl30 + + $ python $FIPDIR/acs_tool.pyc fip/bl2.bin fip/bl2_acs.bin fip/acs.bin 0 + + $ $FIPDIR/blx_fix.sh \ + fip/bl2_acs.bin \ + fip/zero_tmp \ + fip/bl2_zero.bin \ + fip/bl21.bin \ + fip/bl21_zero.bin \ + fip/bl2_new.bin \ + bl2 + + $ $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl30_new.bin + $ $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl31.img + $ $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl33.bin + $ $FIPDIR/gxl/aml_encrypt_gxl --bl2sig --input fip/bl2_new.bin --output fip/bl2.n.bin.sig + $ $FIPDIR/gxl/aml_encrypt_gxl --bootmk \ + --output fip/u-boot.bin \ + --bl2 fip/bl2.n.bin.sig \ + --bl30 fip/bl30_new.bin.enc \ + --bl31 fip/bl31.img.enc \ + --bl33 fip/bl33.bin.enc + +and then write the image to SD with: + +.. code-block:: bash + + $ DEV=/dev/your_sd_device + $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1 + $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444 diff --git a/doc/board/amlogic/khadas-vim3.rst b/doc/board/amlogic/khadas-vim3.rst new file mode 100644 index 0000000000..c1c03212d2 --- /dev/null +++ b/doc/board/amlogic/khadas-vim3.rst @@ -0,0 +1,132 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +U-Boot for Khadas VIM3 +====================== + +Khadas VIM3 is a single board computer manufactured by Shenzhen Wesion +Technology Co., Ltd. with the following specifications: + + - Amlogic A311D Arm Cortex-A53 dual-core + Cortex-A73 quad-core SoC + - 4GB LPDDR4 SDRAM + - Gigabit Ethernet + - HDMI 2.1 display + - 40-pin GPIO header + - 1 x USB 3.0 Host, 1 x USB 2.0 Host + - eMMC, microSD + - M.2 + - Infrared receiver + +Schematics are available on the manufacturer website. + +U-Boot compilation +------------------ + +.. code-block:: bash + + $ export CROSS_COMPILE=aarch64-none-elf- + $ make khadas-vim3_defconfig + $ make + +Image creation +-------------- + +Amlogic doesn't provide sources for the firmware and for tools needed +to create the bootloader image, so it is necessary to obtain them from +the git tree published by the board vendor: + +.. code-block:: bash + + $ wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz + $ wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz + $ tar xvfJ gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz + $ tar xvfJ gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz + $ export PATH=$PWD/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux/bin:$PWD/gcc-linaro-arm-none-eabi-4.8-2013.11_linux/bin:$PATH + + $ DIR=vim3-u-boot + $ git clone --depth 1 \ + https://github.com/khadas/u-boot.git -b khadas-vims-v2015.01 \ + $DIR + + $ cd vim3-u-boot + $ make kvim3_defconfig + $ make + $ export UBOOTDIR=$PWD + + Go back to mainline U-Boot source tree then : + +.. code-block:: bash + + $ mkdir fip + + $ cp $UBOOTDIR/build/scp_task/bl301.bin fip/ + $ cp $UBOOTDIR/build/board/khadas/kvim3/firmware/acs.bin fip/ + $ cp $UBOOTDIR/fip/g12b/bl2.bin fip/ + $ cp $UBOOTDIR/fip/g12b/bl30.bin fip/ + $ cp $UBOOTDIR/fip/g12b/bl31.img fip/ + $ cp $UBOOTDIR/fip/g12b/ddr3_1d.fw fip/ + $ cp $UBOOTDIR/fip/g12b/ddr4_1d.fw fip/ + $ cp $UBOOTDIR/fip/g12b/ddr4_2d.fw fip/ + $ cp $UBOOTDIR/fip/g12b/diag_lpddr4.fw fip/ + $ cp $UBOOTDIR/fip/g12b/lpddr3_1d.fw fip/ + $ cp $UBOOTDIR/fip/g12b/lpddr4_1d.fw fip/ + $ cp $UBOOTDIR/fip/g12b/lpddr4_2d.fw fip/ + $ cp $UBOOTDIR/fip/g12b/piei.fw fip/ + $ cp $UBOOTDIR/fip/g12b/aml_ddr.fw fip/ + $ cp u-boot.bin fip/bl33.bin + + $ sh fip/blx_fix.sh \ + fip/bl30.bin \ + fip/zero_tmp \ + fip/bl30_zero.bin \ + fip/bl301.bin \ + fip/bl301_zero.bin \ + fip/bl30_new.bin \ + bl30 + + $ sh fip/blx_fix.sh \ + fip/bl2.bin \ + fip/zero_tmp \ + fip/bl2_zero.bin \ + fip/acs.bin \ + fip/bl21_zero.bin \ + fip/bl2_new.bin \ + bl2 + + $ $UBOOTDIR/fip/g12b/aml_encrypt_g12b --bl30sig --input fip/bl30_new.bin \ + --output fip/bl30_new.bin.g12a.enc \ + --level v3 + $ $UBOOTDIR/fip/g12b/aml_encrypt_g12b --bl3sig --input fip/bl30_new.bin.g12a.enc \ + --output fip/bl30_new.bin.enc \ + --level v3 --type bl30 + $ $UBOOTDIR/fip/g12b/aml_encrypt_g12b --bl3sig --input fip/bl31.img \ + --output fip/bl31.img.enc \ + --level v3 --type bl31 + $ $UBOOTDIR/fip/g12b/aml_encrypt_g12b --bl3sig --input fip/bl33.bin --compress lz4 \ + --output fip/bl33.bin.enc \ + --level v3 --type bl33 --compress lz4 + $ $UBOOTDIR/fip/g12b/aml_encrypt_g12b --bl2sig --input fip/bl2_new.bin \ + --output fip/bl2.n.bin.sig + $ $UBOOTDIR/fip/g12b/aml_encrypt_g12b --bootmk \ + --output fip/u-boot.bin \ + --bl2 fip/bl2.n.bin.sig \ + --bl30 fip/bl30_new.bin.enc \ + --bl31 fip/bl31.img.enc \ + --bl33 fip/bl33.bin.enc \ + --ddrfw1 fip/ddr4_1d.fw \ + --ddrfw2 fip/ddr4_2d.fw \ + --ddrfw3 fip/ddr3_1d.fw \ + --ddrfw4 fip/piei.fw \ + --ddrfw5 fip/lpddr4_1d.fw \ + --ddrfw6 fip/lpddr4_2d.fw \ + --ddrfw7 fip/diag_lpddr4.fw \ + --ddrfw8 fip/aml_ddr.fw \ + --ddrfw9 fip/lpddr3_1d.fw \ + --level v3 + +and then write the image to SD with: + +.. code-block:: bash + + $ DEV=/dev/your_sd_device + $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1 + $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444 diff --git a/doc/board/amlogic/khadas-vim3l.rst b/doc/board/amlogic/khadas-vim3l.rst new file mode 100644 index 0000000000..b380c17456 --- /dev/null +++ b/doc/board/amlogic/khadas-vim3l.rst @@ -0,0 +1,130 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +U-Boot for Khadas VIM3L +======================= + +Khadas VIM3L is a single board computer manufactured by Shenzhen Wesion +Technology Co., Ltd. with the following specifications: + + - Amlogic S905D3 Arm Cortex-A55 quad-core SoC + - 2GB LPDDR4 SDRAM + - Gigabit Ethernet + - HDMI 2.1 display + - 40-pin GPIO header + - 1 x USB 3.0 Host, 1 x USB 2.0 Host + - eMMC, microSD + - M.2 + - Infrared receiver + +Schematics are available on the manufacturer website. + +U-Boot compilation +------------------ + + $ export CROSS_COMPILE=aarch64-none-elf- + $ make khadas-vim3l_defconfig + $ make + +Image creation +-------------- + +Amlogic doesn't provide sources for the firmware and for tools needed +to create the bootloader image, so it is necessary to obtain them from +the git tree published by the board vendor: + +.. code-block:: bash + + $ wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz + $ wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz + $ tar xvfJ gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz + $ tar xvfJ gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz + $ export PATH=$PWD/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux/bin:$PWD/gcc-linaro-arm-none-eabi-4.8-2013.11_linux/bin:$PATH + + $ DIR=vim3l-u-boot + $ git clone --depth 1 \ + https://github.com/khadas/u-boot.git -b khadas-vims-v2015.01 \ + $DIR + + $ cd vim3l-u-boot + $ make kvim3l_defconfig + $ make + $ export UBOOTDIR=$PWD + + Go back to mainline U-Boot source tree then : + +.. code-block:: bash + + $ mkdir fip + + $ cp $UBOOTDIR/build/scp_task/bl301.bin fip/ + $ cp $UBOOTDIR/build/board/khadas/kvim3l/firmware/acs.bin fip/ + $ cp $UBOOTDIR/fip/g12a/bl2.bin fip/ + $ cp $UBOOTDIR/fip/g12a/bl30.bin fip/ + $ cp $UBOOTDIR/fip/g12a/bl31.img fip/ + $ cp $UBOOTDIR/fip/g12a/ddr3_1d.fw fip/ + $ cp $UBOOTDIR/fip/g12a/ddr4_1d.fw fip/ + $ cp $UBOOTDIR/fip/g12a/ddr4_2d.fw fip/ + $ cp $UBOOTDIR/fip/g12a/diag_lpddr4.fw fip/ + $ cp $UBOOTDIR/fip/g12a/lpddr3_1d.fw fip/ + $ cp $UBOOTDIR/fip/g12a/lpddr4_1d.fw fip/ + $ cp $UBOOTDIR/fip/g12a/lpddr4_2d.fw fip/ + $ cp $UBOOTDIR/fip/g12a/piei.fw fip/ + $ cp $UBOOTDIR/fip/g12a/aml_ddr.fw fip/ + $ cp u-boot.bin fip/bl33.bin + + $ sh fip/blx_fix.sh \ + fip/bl30.bin \ + fip/zero_tmp \ + fip/bl30_zero.bin \ + fip/bl301.bin \ + fip/bl301_zero.bin \ + fip/bl30_new.bin \ + bl30 + + $ sh fip/blx_fix.sh \ + fip/bl2.bin \ + fip/zero_tmp \ + fip/bl2_zero.bin \ + fip/acs.bin \ + fip/bl21_zero.bin \ + fip/bl2_new.bin \ + bl2 + + $ $UBOOTDIR/fip/g12a/aml_encrypt_g12a --bl30sig --input fip/bl30_new.bin \ + --output fip/bl30_new.bin.g12a.enc \ + --level v3 + $ $UBOOTDIR/fip/g12a/aml_encrypt_g12a --bl3sig --input fip/bl30_new.bin.g12a.enc \ + --output fip/bl30_new.bin.enc \ + --level v3 --type bl30 + $ $UBOOTDIR/fip/g12a/aml_encrypt_g12a --bl3sig --input fip/bl31.img \ + --output fip/bl31.img.enc \ + --level v3 --type bl31 + $ $UBOOTDIR/fip/g12a/aml_encrypt_g12a --bl3sig --input fip/bl33.bin --compress lz4 \ + --output fip/bl33.bin.enc \ + --level v3 --type bl33 --compress lz4 + $ $UBOOTDIR/fip/g12a/aml_encrypt_g12a --bl2sig --input fip/bl2_new.bin \ + --output fip/bl2.n.bin.sig + $ $UBOOTDIR/fip/g12a/aml_encrypt_g12a --bootmk \ + --output fip/u-boot.bin \ + --bl2 fip/bl2.n.bin.sig \ + --bl30 fip/bl30_new.bin.enc \ + --bl31 fip/bl31.img.enc \ + --bl33 fip/bl33.bin.enc \ + --ddrfw1 fip/ddr4_1d.fw \ + --ddrfw2 fip/ddr4_2d.fw \ + --ddrfw3 fip/ddr3_1d.fw \ + --ddrfw4 fip/piei.fw \ + --ddrfw5 fip/lpddr4_1d.fw \ + --ddrfw6 fip/lpddr4_2d.fw \ + --ddrfw7 fip/diag_lpddr4.fw \ + --ddrfw8 fip/aml_ddr.fw \ + --ddrfw9 fip/lpddr3_1d.fw \ + --level v3 + +and then write the image to SD with: + +.. code-block:: bash + + $ DEV=/dev/your_sd_device + $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1 + $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444 diff --git a/doc/board/amlogic/libretech-ac.rst b/doc/board/amlogic/libretech-ac.rst new file mode 100644 index 0000000000..39bae86d32 --- /dev/null +++ b/doc/board/amlogic/libretech-ac.rst @@ -0,0 +1,110 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +U-Boot for LibreTech AC +======================= + +LibreTech AC is a single board computer manufactured by Libre Technology +with the following specifications: + + - Amlogic S805X ARM Cortex-A53 quad-core SoC @ 1.2GHz + - ARM Mali 450 GPU + - 512MiB DDR4 SDRAM + - 10/100 Ethernet + - HDMI 2.0 4K/60Hz display + - 40-pin GPIO header + - 4 x USB 2.0 Host + - eMMC, SPI NOR Flash + - Infrared receiver + +Schematics are available on the manufacturer website. + +U-Boot compilation +------------------ + +.. code-block:: bash + + $ export CROSS_COMPILE=aarch64-none-elf- + $ make libretech-ac_defconfig + $ make + +Image creation +-------------- + +Amlogic doesn't provide sources for the firmware and for tools needed +to create the bootloader image, so it is necessary to obtain them from +the git tree published by the board vendor: + +.. code-block:: bash + + $ wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz + $ wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz + $ tar xvfJ gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz + $ tar xvfJ gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz + $ export PATH=$PWD/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux/bin:$PWD/gcc-linaro-arm-none-eabi-4.8-2013.11_linux/bin:$PATH + $ git clone https://github.com/BayLibre/u-boot.git -b libretech-ac amlogic-u-boot + $ cd amlogic-u-boot + $ wget https://raw.githubusercontent.com/BayLibre/u-boot/libretech-cc/fip/blx_fix.sh + $ make libretech_ac_defconfig + $ make + $ export UBOOTDIR=$PWD + +Download the latest Amlogic Buildroot package, and extract it : + +.. code-block:: bash + + $ wget http://openlinux2.amlogic.com:8000/ARM/filesystem/Linux_BSP/buildroot_openlinux_kernel_4.9_fbdev_20180418.tar.gz + $ tar xfz buildroot_openlinux_kernel_4.9_fbdev_20180418.tar.gz buildroot_openlinux_kernel_4.9_fbdev_20180418/bootloader + $ export BRDIR=$PWD/buildroot_openlinux_kernel_4.9_fbdev_20180418 + +Go back to mainline U-Boot source tree then : + +.. code-block:: bash + + $ mkdir fip + + $ cp $UBOOTDIR/build/scp_task/bl301.bin fip/ + $ cp $UBOOTDIR/build/board/amlogic/libretech_ac/firmware/bl21.bin fip/ + $ cp $UBOOTDIR/build/board/amlogic/libretech_ac/firmware/acs.bin fip/ + $ cp $BRDIR/bootloader/uboot-repo/bl2/bin/gxl/bl2.bin fip/ + $ cp $BRDIR/bootloader/uboot-repo/bl30/bin/gxl/bl30.bin fip/ + $ cp $BRDIR/bootloader/uboot-repo/bl31/bin/gxl/bl31.img fip/ + $ cp u-boot.bin fip/bl33.bin + + $ sh $UBOOTDIR/blx_fix.sh \ + fip/bl30.bin \ + fip/zero_tmp \ + fip/bl30_zero.bin \ + fip/bl301.bin \ + fip/bl301_zero.bin \ + fip/bl30_new.bin \ + bl30 + + $ $BRDIR/bootloader/uboot-repo/fip/acs_tool.pyc fip/bl2.bin fip/bl2_acs.bin fip/acs.bin 0 + + $ sh $UBOOTDIR/blx_fix.sh \ + fip/bl2_acs.bin \ + fip/zero_tmp \ + fip/bl2_zero.bin \ + fip/bl21.bin \ + fip/bl21_zero.bin \ + fip/bl2_new.bin \ + bl2 + + $ $BRDIR/bootloader/uboot-repo/fip/gxl/aml_encrypt_gxl --bl3enc --input fip/bl30_new.bin + $ $BRDIR/bootloader/uboot-repo/fip/gxl/aml_encrypt_gxl --bl3enc --input fip/bl31.img + $ $BRDIR/bootloader/uboot-repo/fip/gxl/aml_encrypt_gxl --bl3enc --input fip/bl33.bin + $ $BRDIR/bootloader/uboot-repo/fip/gxl/aml_encrypt_gxl --bl2sig --input fip/bl2_new.bin --output fip/bl2.n.bin.sig + $ $BRDIR/bootloader/uboot-repo/fip/gxl/aml_encrypt_gxl --bootmk \ + --output fip/u-boot.bin \ + --bl2 fip/bl2.n.bin.sig \ + --bl30 fip/bl30_new.bin.enc \ + --bl31 fip/bl31.img.enc \ + --bl33 fip/bl33.bin.enc + +and then write the image to SD with: + +.. code-block:: bash + + $ DEV=/dev/your_sd_device + $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1 + $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444 diff --git a/doc/board/amlogic/libretech-cc.rst b/doc/board/amlogic/libretech-cc.rst new file mode 100644 index 0000000000..f2e26cabf9 --- /dev/null +++ b/doc/board/amlogic/libretech-cc.rst @@ -0,0 +1,135 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +U-Boot for LibreTech CC +======================= + +LibreTech CC is a single board computer manufactured by Libre Technology +with the following specifications: + + - Amlogic S905X ARM Cortex-A53 quad-core SoC @ 1.5GHz + - ARM Mali 450 GPU + - 2GB DDR3 SDRAM + - 10/100 Ethernet + - HDMI 2.0 4K/60Hz display + - 40-pin GPIO header + - 4 x USB 2.0 Host + - eMMC, microSD + - Infrared receiver + +Schematics are available on the manufacturer website. + +U-Boot compilation +------------------ + +.. code-block:: bash + + $ export CROSS_COMPILE=aarch64-none-elf- + $ make libretech-cc_defconfig + $ make + +Image creation +-------------- + +To boot the system, u-boot must be combined with several earlier stage +bootloaders: + +* bl2.bin: vendor-provided binary blob +* bl21.bin: built from vendor u-boot source +* bl30.bin: vendor-provided binary blob +* bl301.bin: built from vendor u-boot source +* bl31.bin: vendor-provided binary blob +* acs.bin: built from vendor u-boot source + +These binaries and the tools required below have been collected and prebuilt +for convenience at + +Download and extract the libretech-cc release from there, and set FIPDIR to +point to the `fip` subdirectory. + +.. code-block:: bash + + $ export FIPDIR=/path/to/extracted/fip + +Alternatively, you can obtain the original vendor u-boot tree which +contains the required blobs and sources, and build yourself. +Note that old compilers are required for this to build. The compilers here +are suggested by Amlogic, and they are 32-bit x86 binaries. + +.. code-block:: bash + + $ wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz + $ wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz + $ tar xvfJ gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz + $ tar xvfJ gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz + $ export PATH=$PWD/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux/bin:$PWD/gcc-linaro-arm-none-eabi-4.8-2013.11_linux/bin:$PATH + $ git clone https://github.com/BayLibre/u-boot.git -b libretech-cc amlogic-u-boot + $ cd amlogic-u-boot + $ make libretech_cc_defconfig + $ make + $ export FIPDIR=$PWD/fip + +Once you have the binaries available (either through the prebuilt download, +or having built the vendor u-boot yourself), you can then proceed to glue +everything together. Go back to mainline U-Boot source tree then : + +.. code-block:: bash + + $ mkdir fip + + $ cp $FIPDIR/gxl/bl2.bin fip/ + $ cp $FIPDIR/gxl/acs.bin fip/ + $ cp $FIPDIR/gxl/bl21.bin fip/ + $ cp $FIPDIR/gxl/bl30.bin fip/ + $ cp $FIPDIR/gxl/bl301.bin fip/ + $ cp $FIPDIR/gxl/bl31.img fip/ + $ cp u-boot.bin fip/bl33.bin + + $ $FIPDIR/blx_fix.sh \ + fip/bl30.bin \ + fip/zero_tmp \ + fip/bl30_zero.bin \ + fip/bl301.bin \ + fip/bl301_zero.bin \ + fip/bl30_new.bin \ + bl30 + + $ $FIPDIR/acs_tool.pyc fip/bl2.bin fip/bl2_acs.bin fip/acs.bin 0 + + $ $FIPDIR/blx_fix.sh \ + fip/bl2_acs.bin \ + fip/zero_tmp \ + fip/bl2_zero.bin \ + fip/bl21.bin \ + fip/bl21_zero.bin \ + fip/bl2_new.bin \ + bl2 + + $ $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl30_new.bin + $ $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl31.img + $ $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl33.bin + $ $FIPDIR/gxl/aml_encrypt_gxl --bl2sig --input fip/bl2_new.bin --output fip/bl2.n.bin.sig + $ $FIPDIR/gxl/aml_encrypt_gxl --bootmk \ + --output fip/u-boot.bin \ + --bl2 fip/bl2.n.bin.sig \ + --bl30 fip/bl30_new.bin.enc \ + --bl31 fip/bl31.img.enc \ + --bl33 fip/bl33.bin.enc + +and then write the image to SD with: + +.. code-block:: bash + + $ DEV=/dev/your_sd_device + $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1 + $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444 + +Note that Amlogic provides aml_encrypt_gxl as a 32-bit x86 binary with no +source code. Should you prefer to avoid that, there are open source reverse +engineered versions available: + +1. gxlimg , which comes with a handy + Makefile that automates the whole process. +2. meson-tools + +However, these community-developed alternatives are not endorsed by or +supported by Amlogic. diff --git a/doc/board/amlogic/nanopi-k2.rst b/doc/board/amlogic/nanopi-k2.rst new file mode 100644 index 0000000000..1222ee4e85 --- /dev/null +++ b/doc/board/amlogic/nanopi-k2.rst @@ -0,0 +1,104 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +U-Boot for NanoPi-K2 +==================== + +NanoPi-K2 is a single board computer manufactured by FriendlyElec +with the following specifications: + + - Amlogic S905 ARM Cortex-A53 quad-core SoC @ 1.5GHz + - ARM Mali 450 GPU + - 2GB DDR3 SDRAM + - Gigabit Ethernet + - HDMI 2.0 4K/60Hz display + - 40-pin GPIO header + - 4 x USB 2.0 Host, 1 x USB OTG + - eMMC, microSD + - Infrared receiver + +Schematics are available on the manufacturer website. + +U-Boot compilation +------------------ + +.. code-block:: bash + + $ export CROSS_COMPILE=aarch64-none-elf- + $ make nanopi-k2_defconfig + $ make + +Image creation +-------------- + +Amlogic doesn't provide sources for the firmware and for tools needed +to create the bootloader image, so it is necessary to obtain them from +the git tree published by the board vendor: + +.. code-block:: bash + + $ wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz + $ wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz + $ tar xvfJ gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz + $ tar xvfJ gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz + $ export PATH=$PWD/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux/bin:$PWD/gcc-linaro-arm-none-eabi-4.8-2013.11_linux/bin:$PATH + $ git clone https://github.com/BayLibre/u-boot.git -b libretech-cc amlogic-u-boot + $ git clone https://github.com/friendlyarm/u-boot.git -b nanopi-k2-v2015.01 amlogic-u-boot + $ cd amlogic-u-boot + $ sed -i 's/aarch64-linux-gnu-/aarch64-none-elf-/' Makefile + $ sed -i 's/arm-linux-/arm-none-eabi-/' arch/arm/cpu/armv8/gxb/firmware/scp_task/Makefile + $ make nanopi-k2_defconfig + $ make + $ export FIPDIR=$PWD/fip + +Go back to mainline U-Boot source tree then : + +.. code-block:: bash + + $ mkdir fip + + $ cp $FIPDIR/gxb/bl2.bin fip/ + $ cp $FIPDIR/gxb/acs.bin fip/ + $ cp $FIPDIR/gxb/bl21.bin fip/ + $ cp $FIPDIR/gxb/bl30.bin fip/ + $ cp $FIPDIR/gxb/bl301.bin fip/ + $ cp $FIPDIR/gxb/bl31.img fip/ + $ cp u-boot.bin fip/bl33.bin + + $ $FIPDIR/blx_fix.sh \ + fip/bl30.bin \ + fip/zero_tmp \ + fip/bl30_zero.bin \ + fip/bl301.bin \ + fip/bl301_zero.bin \ + fip/bl30_new.bin \ + bl30 + + $ $FIPDIR/fip_create \ + --bl30 fip/bl30_new.bin \ + --bl31 fip/bl31.img \ + --bl33 fip/bl33.bin \ + fip/fip.bin + + $ python $FIPDIR/acs_tool.pyc fip/bl2.bin fip/bl2_acs.bin fip/acs.bin 0 + + $ $FIPDIR/blx_fix.sh \ + fip/bl2_acs.bin \ + fip/zero_tmp \ + fip/bl2_zero.bin \ + fip/bl21.bin \ + fip/bl21_zero.bin \ + fip/bl2_new.bin \ + bl2 + + $ cat fip/bl2_new.bin fip/fip.bin > fip/boot_new.bin + + $ $FIPDIR/gxb/aml_encrypt_gxb --bootsig \ + --input fip/boot_new.bin + --output fip/u-boot.bin + +and then write the image to SD with: + +.. code-block:: bash + + $ DEV=/dev/your_sd_device + $ dd if=fip/u-boot.bin of=$DEV conv=fsync,notrunc bs=512 seek=1 diff --git a/board/amlogic/p200/README.odroid-c2 b/doc/board/amlogic/odroid-c2.rst similarity index 56% rename from board/amlogic/p200/README.odroid-c2 rename to doc/board/amlogic/odroid-c2.rst index 3b9f80df29..966c18b36e 100644 --- a/board/amlogic/p200/README.odroid-c2 +++ b/doc/board/amlogic/odroid-c2.rst @@ -1,3 +1,5 @@ +.. SPDX-License-Identifier: GPL-2.0+ + U-Boot for ODROID-C2 ==================== @@ -16,50 +18,46 @@ Co. Ltd with the following specifications: Schematics are available on the manufacturer website. -Currently the u-boot port supports the following devices: - - serial - - eMMC, microSD - - Ethernet - - I2C - - Regulators - - Reset controller - - Clock controller - - ADC +U-Boot compilation +------------------ -u-boot compilation -================== +.. code-block:: bash - > export CROSS_COMPILE=aarch64-none-elf- - > make odroid-c2_defconfig - > make + $ export CROSS_COMPILE=aarch64-none-elf- + $ make odroid-c2_defconfig + $ make Image creation -============== +-------------- Amlogic doesn't provide sources for the firmware and for tools needed to create the bootloader image, so it is necessary to obtain them from the git tree published by the board vendor: - > DIR=odroid-c2 - > git clone --depth 1 \ +.. code-block:: bash + + $ DIR=odroid-c2 + $ git clone --depth 1 \ https://github.com/hardkernel/u-boot.git -b odroidc2-v2015.01 \ $DIR - > $DIR/fip/fip_create --bl30 $DIR/fip/gxb/bl30.bin \ + $ $DIR/fip/fip_create --bl30 $DIR/fip/gxb/bl30.bin \ --bl301 $DIR/fip/gxb/bl301.bin \ --bl31 $DIR/fip/gxb/bl31.bin \ --bl33 u-boot.bin \ $DIR/fip.bin - > $DIR/fip/fip_create --dump $DIR/fip.bin - > cat $DIR/fip/gxb/bl2.package $DIR/fip.bin > $DIR/boot_new.bin - > $DIR/fip/gxb/aml_encrypt_gxb --bootsig \ + $ $DIR/fip/fip_create --dump $DIR/fip.bin + $ cat $DIR/fip/gxb/bl2.package $DIR/fip.bin > $DIR/boot_new.bin + $ $DIR/fip/gxb/aml_encrypt_gxb --bootsig \ --input $DIR/boot_new.bin \ --output $DIR/u-boot.img - > dd if=$DIR/u-boot.img of=$DIR/u-boot.gxbb bs=512 skip=96 + $ dd if=$DIR/u-boot.img of=$DIR/u-boot.gxbb bs=512 skip=96 and then write the image to SD with: - > DEV=/dev/your_sd_device - > BL1=$DIR/sd_fuse/bl1.bin.hardkernel - > dd if=$BL1 of=$DEV conv=fsync bs=1 count=442 - > dd if=$BL1 of=$DEV conv=fsync bs=512 skip=1 seek=1 - > dd if=$DIR/u-boot.gxbb of=$DEV conv=fsync bs=512 seek=97 +.. code-block:: bash + + $ DEV=/dev/your_sd_device + $ BL1=$DIR/sd_fuse/bl1.bin.hardkernel + $ dd if=$BL1 of=$DEV conv=fsync bs=1 count=442 + $ dd if=$BL1 of=$DEV conv=fsync bs=512 skip=1 seek=1 + $ dd if=$DIR/u-boot.gxbb of=$DEV conv=fsync bs=512 seek=97 diff --git a/doc/board/amlogic/odroid-n2.rst b/doc/board/amlogic/odroid-n2.rst new file mode 100644 index 0000000000..fe63113230 --- /dev/null +++ b/doc/board/amlogic/odroid-n2.rst @@ -0,0 +1,130 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +U-Boot for ODROID-N2 +==================== + +ODROID-N2 is a single board computer manufactured by Hardkernel +Co. Ltd with the following specifications: + + - Amlogic S922X ARM Cortex-A53 dual-core + Cortex-A73 quad-core SoC + - 4GB DDR4 SDRAM + - Gigabit Ethernet + - HDMI 2.1 4K/60Hz display + - 40-pin GPIO header + - 4 x USB 3.0 Host, 1 x USB OTG + - eMMC, microSD + - Infrared receiver + +Schematics are available on the manufacturer website. + +U-Boot compilation +------------------ + +.. code-block:: bash + + $ export CROSS_COMPILE=aarch64-none-elf- + $ make odroid-n2_defconfig + $ make + +Image creation +-------------- + +Amlogic doesn't provide sources for the firmware and for tools needed +to create the bootloader image, so it is necessary to obtain them from +the git tree published by the board vendor: + +.. code-block:: bash + + $ wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz + $ wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz + $ tar xvfJ gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz + $ tar xvfJ gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz + $ export PATH=$PWD/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux/bin:$PWD/gcc-linaro-arm-none-eabi-4.8-2013.11_linux/bin:$PATH + + $ DIR=odroid-n2 + $ git clone --depth 1 \ + https://github.com/hardkernel/u-boot.git -b odroidn2-v2015.01 \ + $DIR + + $ cd odroid-n2 + $ make odroidn2_defconfig + $ make + $ export UBOOTDIR=$PWD + + Go back to mainline U-Boot source tree then : + +.. code-block:: bash + + $ mkdir fip + + $ wget https://github.com/BayLibre/u-boot/releases/download/v2017.11-libretech-cc/blx_fix_g12a.sh -O fip/blx_fix.sh + $ cp $UBOOTDIR/build/scp_task/bl301.bin fip/ + $ cp $UBOOTDIR/build/board/hardkernel/odroidn2/firmware/acs.bin fip/ + $ cp $UBOOTDIR/fip/g12b/bl2.bin fip/ + $ cp $UBOOTDIR/fip/g12b/bl30.bin fip/ + $ cp $UBOOTDIR/fip/g12b/bl31.img fip/ + $ cp $UBOOTDIR/fip/g12b/ddr3_1d.fw fip/ + $ cp $UBOOTDIR/fip/g12b/ddr4_1d.fw fip/ + $ cp $UBOOTDIR/fip/g12b/ddr4_2d.fw fip/ + $ cp $UBOOTDIR/fip/g12b/diag_lpddr4.fw fip/ + $ cp $UBOOTDIR/fip/g12b/lpddr4_1d.fw fip/ + $ cp $UBOOTDIR/fip/g12b/lpddr4_2d.fw fip/ + $ cp $UBOOTDIR/fip/g12b/piei.fw fip/ + $ cp $UBOOTDIR/fip/g12b/aml_ddr.fw fip/ + $ cp u-boot.bin fip/bl33.bin + + $ sh fip/blx_fix.sh \ + fip/bl30.bin \ + fip/zero_tmp \ + fip/bl30_zero.bin \ + fip/bl301.bin \ + fip/bl301_zero.bin \ + fip/bl30_new.bin \ + bl30 + + $ sh fip/blx_fix.sh \ + fip/bl2.bin \ + fip/zero_tmp \ + fip/bl2_zero.bin \ + fip/acs.bin \ + fip/bl21_zero.bin \ + fip/bl2_new.bin \ + bl2 + + $ $UBOOTDIR/fip/g12b/aml_encrypt_g12b --bl30sig --input fip/bl30_new.bin \ + --output fip/bl30_new.bin.g12a.enc \ + --level v3 + $ $UBOOTDIR/fip/g12b/aml_encrypt_g12b --bl3sig --input fip/bl30_new.bin.g12a.enc \ + --output fip/bl30_new.bin.enc \ + --level v3 --type bl30 + $ $UBOOTDIR/fip/g12b/aml_encrypt_g12b --bl3sig --input fip/bl31.img \ + --output fip/bl31.img.enc \ + --level v3 --type bl31 + $ $UBOOTDIR/fip/g12b/aml_encrypt_g12b --bl3sig --input fip/bl33.bin --compress lz4 \ + --output fip/bl33.bin.enc \ + --level v3 --type bl33 --compress lz4 + $ $UBOOTDIR/fip/g12b/aml_encrypt_g12b --bl2sig --input fip/bl2_new.bin \ + --output fip/bl2.n.bin.sig + $ $UBOOTDIR/fip/g12b/aml_encrypt_g12b --bootmk \ + --output fip/u-boot.bin \ + --bl2 fip/bl2.n.bin.sig \ + --bl30 fip/bl30_new.bin.enc \ + --bl31 fip/bl31.img.enc \ + --bl33 fip/bl33.bin.enc \ + --ddrfw1 fip/ddr4_1d.fw \ + --ddrfw2 fip/ddr4_2d.fw \ + --ddrfw3 fip/ddr3_1d.fw \ + --ddrfw4 fip/piei.fw \ + --ddrfw5 fip/lpddr4_1d.fw \ + --ddrfw6 fip/lpddr4_2d.fw \ + --ddrfw7 fip/diag_lpddr4.fw \ + --ddrfw8 fip/aml_ddr.fw \ + --level v3 + +and then write the image to SD with: + +.. code-block:: bash + + $ DEV=/dev/your_sd_device + $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1 + $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444 diff --git a/doc/board/amlogic/p200.rst b/doc/board/amlogic/p200.rst new file mode 100644 index 0000000000..c3d6441fd3 --- /dev/null +++ b/doc/board/amlogic/p200.rst @@ -0,0 +1,102 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +U-Boot for Amlogic P200 +======================= + +P200 is a reference board manufactured by Amlogic with the following +specifications: + + - Amlogic S905 ARM Cortex-A53 quad-core SoC @ 1.5GHz + - ARM Mali 450 GPU + - 2GB DDR3 SDRAM + - Gigabit Ethernet + - HDMI 2.0 4K/60Hz display + - 2 x USB 2.0 Host + - eMMC, microSD + - Infrared receiver + - SDIO WiFi Module + - CVBS+Stereo Audio Jack + +Schematics are available from Amlogic on demand. + +U-Boot compilation +------------------ + +.. code-block:: bash + + $ export CROSS_COMPILE=aarch64-none-elf- + $ make p200_defconfig + $ make + +Image creation +-------------- + +Amlogic doesn't provide sources for the firmware and for tools needed +to create the bootloader image, so it is necessary to obtain them from +the git tree published by the board vendor: + +.. code-block:: bash + + $ wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz + $ wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz + $ tar xvfJ gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz + $ tar xvfJ gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz + $ export PATH=$PWD/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux/bin:$PWD/gcc-linaro-arm-none-eabi-4.8-2013.11_linux/bin:$PATH + $ git clone https://github.com/BayLibre/u-boot.git -b n-amlogic-openlinux-20170606 amlogic-u-boot + $ cd amlogic-u-boot + $ make gxb_p200_v1_defconfig + $ make + $ export FIPDIR=$PWD/fip + +Go back to mainline U-boot source tree then : + +.. code-block:: bash + + $ mkdir fip + + $ cp $FIPDIR/gxl/bl2.bin fip/ + $ cp $FIPDIR/gxl/acs.bin fip/ + $ cp $FIPDIR/gxl/bl21.bin fip/ + $ cp $FIPDIR/gxl/bl30.bin fip/ + $ cp $FIPDIR/gxl/bl301.bin fip/ + $ cp $FIPDIR/gxl/bl31.img fip/ + $ cp u-boot.bin fip/bl33.bin + + $ $FIPDIR/blx_fix.sh \ + fip/bl30.bin \ + fip/zero_tmp \ + fip/bl30_zero.bin \ + fip/bl301.bin \ + fip/bl301_zero.bin \ + fip/bl30_new.bin \ + bl30 + + $ $FIPDIR/acs_tool.pyc fip/bl2.bin fip/bl2_acs.bin fip/acs.bin 0 + + $ $FIPDIR/blx_fix.sh \ + fip/bl2_acs.bin \ + fip/zero_tmp \ + fip/bl2_zero.bin \ + fip/bl21.bin \ + fip/bl21_zero.bin \ + fip/bl2_new.bin \ + bl2 + + $ $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl30_new.bin + $ $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl31.img + $ $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl33.bin + $ $FIPDIR/gxl/aml_encrypt_gxl --bl2sig --input fip/bl2_new.bin --output fip/bl2.n.bin.sig + $ $FIPDIR/gxl/aml_encrypt_gxl --bootmk \ + --output fip/u-boot.bin \ + --bl2 fip/bl2.n.bin.sig \ + --bl30 fip/bl30_new.bin.enc \ + --bl31 fip/bl31.img.enc \ + --bl33 fip/bl33.bin.enc + +and then write the image to SD with: + +.. code-block:: bash + + $ DEV=/dev/your_sd_device + $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1 + $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444 diff --git a/doc/board/amlogic/p201.rst b/doc/board/amlogic/p201.rst new file mode 100644 index 0000000000..06da933a2a --- /dev/null +++ b/doc/board/amlogic/p201.rst @@ -0,0 +1,102 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +U-Boot for Amlogic P201 +======================= + +P201 is a reference board manufactured by Amlogic with the following +specifications: + + - Amlogic S905 ARM Cortex-A53 quad-core SoC @ 1.5GHz + - ARM Mali 450 GPU + - 2GB DDR3 SDRAM + - 10/100 Ethernet + - HDMI 2.0 4K/60Hz display + - 2 x USB 2.0 Host + - eMMC, microSD + - Infrared receiver + - SDIO WiFi Module + - CVBS+Stereo Audio Jack + +Schematics are available from Amlogic on demand. + +U-Boot compilation +------------------ + +.. code-block:: bash + + $ export CROSS_COMPILE=aarch64-none-elf- + $ make p201_defconfig + $ make + +Image creation +-------------- + +Amlogic doesn't provide sources for the firmware and for tools needed +to create the bootloader image, so it is necessary to obtain them from +the git tree published by the board vendor: + +.. code-block:: bash + + $ wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz + $ wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz + $ tar xvfJ gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz + $ tar xvfJ gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz + $ export PATH=$PWD/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux/bin:$PWD/gcc-linaro-arm-none-eabi-4.8-2013.11_linux/bin:$PATH + $ git clone https://github.com/BayLibre/u-boot.git -b n-amlogic-openlinux-20170606 amlogic-u-boot + $ cd amlogic-u-boot + $ make gxb_p201_v1_defconfig + $ make + $ export FIPDIR=$PWD/fip + +Go back to mainline U-boot source tree then : + +.. code-block:: bash + + $ mkdir fip + + $ cp $FIPDIR/gxl/bl2.bin fip/ + $ cp $FIPDIR/gxl/acs.bin fip/ + $ cp $FIPDIR/gxl/bl21.bin fip/ + $ cp $FIPDIR/gxl/bl30.bin fip/ + $ cp $FIPDIR/gxl/bl301.bin fip/ + $ cp $FIPDIR/gxl/bl31.img fip/ + $ cp u-boot.bin fip/bl33.bin + + $ $FIPDIR/blx_fix.sh \ + fip/bl30.bin \ + fip/zero_tmp \ + fip/bl30_zero.bin \ + fip/bl301.bin \ + fip/bl301_zero.bin \ + fip/bl30_new.bin \ + bl30 + + $ $FIPDIR/acs_tool.pyc fip/bl2.bin fip/bl2_acs.bin fip/acs.bin 0 + + $ $FIPDIR/blx_fix.sh \ + fip/bl2_acs.bin \ + fip/zero_tmp \ + fip/bl2_zero.bin \ + fip/bl21.bin \ + fip/bl21_zero.bin \ + fip/bl2_new.bin \ + bl2 + + $ $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl30_new.bin + $ $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl31.img + $ $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl33.bin + $ $FIPDIR/gxl/aml_encrypt_gxl --bl2sig --input fip/bl2_new.bin --output fip/bl2.n.bin.sig + $ $FIPDIR/gxl/aml_encrypt_gxl --bootmk \ + --output fip/u-boot.bin \ + --bl2 fip/bl2.n.bin.sig \ + --bl30 fip/bl30_new.bin.enc \ + --bl31 fip/bl31.img.enc \ + --bl33 fip/bl33.bin.enc + +and then write the image to SD with: + +.. code-block:: bash + + $ DEV=/dev/your_sd_device + $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1 + $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444 diff --git a/doc/board/amlogic/p212.rst b/doc/board/amlogic/p212.rst new file mode 100644 index 0000000000..e2f3fe313b --- /dev/null +++ b/doc/board/amlogic/p212.rst @@ -0,0 +1,102 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +U-Boot for Amlogic P212 +======================= + +P212 is a reference board manufactured by Amlogic with the following +specifications: + + - Amlogic S905X ARM Cortex-A53 quad-core SoC @ 1.5GHz + - ARM Mali 450 GPU + - 2GB DDR3 SDRAM + - 10/100 Ethernet + - HDMI 2.0 4K/60Hz display + - 2 x USB 2.0 Host + - eMMC, microSD + - Infrared receiver + - SDIO WiFi Module + - CVBS+Stereo Audio Jack + +Schematics are available from Amlogic on demand. + +U-Boot compilation +------------------ + +.. code-block:: bash + + $ export CROSS_COMPILE=aarch64-none-elf- + $ make p212_defconfig + $ make + +Image creation +-------------- + +Amlogic doesn't provide sources for the firmware and for tools needed +to create the bootloader image, so it is necessary to obtain them from +the git tree published by the board vendor: + +.. code-block:: bash + + $ wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz + $ wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz + $ tar xvfJ gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz + $ tar xvfJ gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz + $ export PATH=$PWD/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux/bin:$PWD/gcc-linaro-arm-none-eabi-4.8-2013.11_linux/bin:$PATH + $ git clone https://github.com/BayLibre/u-boot.git -b n-amlogic-openlinux-20170606 amlogic-u-boot + $ cd amlogic-u-boot + $ make gxl_p212_v1_defconfig + $ make + $ export FIPDIR=$PWD/fip + +Go back to mainline U-boot source tree then : + +.. code-block:: bash + + $ mkdir fip + + $ cp $FIPDIR/gxl/bl2.bin fip/ + $ cp $FIPDIR/gxl/acs.bin fip/ + $ cp $FIPDIR/gxl/bl21.bin fip/ + $ cp $FIPDIR/gxl/bl30.bin fip/ + $ cp $FIPDIR/gxl/bl301.bin fip/ + $ cp $FIPDIR/gxl/bl31.img fip/ + $ cp u-boot.bin fip/bl33.bin + + $ $FIPDIR/blx_fix.sh \ + fip/bl30.bin \ + fip/zero_tmp \ + fip/bl30_zero.bin \ + fip/bl301.bin \ + fip/bl301_zero.bin \ + fip/bl30_new.bin \ + bl30 + + $ $FIPDIR/acs_tool.pyc fip/bl2.bin fip/bl2_acs.bin fip/acs.bin 0 + + $ $FIPDIR/blx_fix.sh \ + fip/bl2_acs.bin \ + fip/zero_tmp \ + fip/bl2_zero.bin \ + fip/bl21.bin \ + fip/bl21_zero.bin \ + fip/bl2_new.bin \ + bl2 + + $ $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl30_new.bin + $ $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl31.img + $ $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl33.bin + $ $FIPDIR/gxl/aml_encrypt_gxl --bl2sig --input fip/bl2_new.bin --output fip/bl2.n.bin.sig + $ $FIPDIR/gxl/aml_encrypt_gxl --bootmk \ + --output fip/u-boot.bin \ + --bl2 fip/bl2.n.bin.sig \ + --bl30 fip/bl30_new.bin.enc \ + --bl31 fip/bl31.img.enc \ + --bl33 fip/bl33.bin.enc + +and then write the image to SD with: + +.. code-block:: bash + + $ DEV=/dev/your_sd_device + $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1 + $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444 diff --git a/doc/board/amlogic/q200.rst b/doc/board/amlogic/q200.rst new file mode 100644 index 0000000000..3ac4116be4 --- /dev/null +++ b/doc/board/amlogic/q200.rst @@ -0,0 +1,101 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +U-Boot for Amlogic Q200 +======================= + +Q200 is a reference board manufactured by Amlogic with the following +specifications: + + - Amlogic S912 ARM Cortex-A53 octo-core SoC @ 1.5GHz + - ARM Mali T860 GPU + - 2/3GB DDR4 SDRAM + - 10/100/1000 Ethernet + - HDMI 2.0 4K/60Hz display + - 2 x USB 2.0 Host, 1 x USB 2.0 Device + - 16GB/32GB/64GB eMMC + - 2MB SPI Flash + - microSD + - SDIO Wifi Module, Bluetooth + - IR receiver + +U-Boot compilation +------------------ + +.. code-block:: bash + + $ export CROSS_COMPILE=aarch64-none-elf- + $ make khadas-vim2_defconfig + $ make + +Image creation +-------------- + +Amlogic doesn't provide sources for the firmware and for tools needed +to create the bootloader image, so it is necessary to obtain them from +the git tree published by the board vendor: + +.. code-block:: bash + + $ wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz + $ wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz + $ tar xvfJ gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz + $ tar xvfJ gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz + $ export PATH=$PWD/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux/bin:$PWD/gcc-linaro-arm-none-eabi-4.8-2013.11_linux/bin:$PATH + $ git clone https://github.com/BayLibre/u-boot.git -b n-amlogic-openlinux-20170606 amlogic-u-boot + $ cd amlogic-u-boot + $ make gxm_q200_v1_defconfig + $ make + $ export FIPDIR=$PWD/fip + +Go back to mainline U-Boot source tree then : + +.. code-block:: bash + + $ mkdir fip + + $ cp $FIPDIR/gxl/bl2.bin fip/ + $ cp $FIPDIR/gxl/acs.bin fip/ + $ cp $FIPDIR/gxl/bl21.bin fip/ + $ cp $FIPDIR/gxl/bl30.bin fip/ + $ cp $FIPDIR/gxl/bl301.bin fip/ + $ cp $FIPDIR/gxl/bl31.img fip/ + $ cp u-boot.bin fip/bl33.bin + + $ $FIPDIR/blx_fix.sh \ + fip/bl30.bin \ + fip/zero_tmp \ + fip/bl30_zero.bin \ + fip/bl301.bin \ + fip/bl301_zero.bin \ + fip/bl30_new.bin \ + bl30 + + $ python $FIPDIR/acs_tool.pyc fip/bl2.bin fip/bl2_acs.bin fip/acs.bin 0 + + $ $FIPDIR/blx_fix.sh \ + fip/bl2_acs.bin \ + fip/zero_tmp \ + fip/bl2_zero.bin \ + fip/bl21.bin \ + fip/bl21_zero.bin \ + fip/bl2_new.bin \ + bl2 + + $ $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl30_new.bin + $ $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl31.img + $ $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl33.bin + $ $FIPDIR/gxl/aml_encrypt_gxl --bl2sig --input fip/bl2_new.bin --output fip/bl2.n.bin.sig + $ $FIPDIR/gxl/aml_encrypt_gxl --bootmk \ + --output fip/u-boot.bin \ + --bl2 fip/bl2.n.bin.sig \ + --bl30 fip/bl30_new.bin.enc \ + --bl31 fip/bl31.img.enc \ + --bl33 fip/bl33.bin.enc + +and then write the image to SD with: + +.. code-block:: bash + + $ DEV=/dev/your_sd_device + $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1 + $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444 diff --git a/doc/board/amlogic/s400.rst b/doc/board/amlogic/s400.rst new file mode 100644 index 0000000000..52c7b27332 --- /dev/null +++ b/doc/board/amlogic/s400.rst @@ -0,0 +1,109 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +U-Boot for Amlogic S400 +======================= + +S400 is a reference board manufactured by Amlogic with the following +specifications: + + - Amlogic A113DX ARM Cortex-A53 quad-core SoC @ 1.2GHz + - 1GB DDR4 SDRAM + - 10/100 Ethernet + - 2 x USB 2.0 Host + - eMMC + - Infrared receiver + - SDIO WiFi Module + - MIPI DSI Connector + - Audio HAT Connector + - PCI-E M.2 Connectors + +Schematics are available from Amlogic on demand. + +U-Boot compilation +------------------ + +.. code-block:: bash + + $ export CROSS_COMPILE=aarch64-none-elf- + $ make s400_defconfig + $ make + +Image creation +-------------- + +Amlogic doesn't provide sources for the firmware and for tools needed +to create the bootloader image, so it is necessary to obtain them from +the git tree published by the board vendor: + +.. code-block:: bash + + $ wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz + $ wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz + $ tar xvfJ gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz + $ tar xvfJ gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz + $ export PATH=$PWD/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux/bin:$PWD/gcc-linaro-arm-none-eabi-4.8-2013.11_linux/bin:$PATH + $ git clone https://github.com/BayLibre/u-boot.git -b n-amlogic-openlinux-20170606 amlogic-u-boot + $ cd amlogic-u-boot + $ make axg_s400_v1_defconfig + $ make + $ export FIPDIR=$PWD/fip + +Go back to mainline U-boot source tree then : + +.. code-block:: bash + + $ mkdir fip + + $ cp $FIPDIR/axg/bl2.bin fip/ + $ cp $FIPDIR/axg/acs.bin fip/ + $ cp $FIPDIR/axg/bl21.bin fip/ + $ cp $FIPDIR/axg/bl30.bin fip/ + $ cp $FIPDIR/axg/bl301.bin fip/ + $ cp $FIPDIR/axg/bl31.img fip/ + $ cp u-boot.bin fip/bl33.bin + + $ $FIPDIR/blx_fix.sh \ + fip/bl30.bin \ + fip/zero_tmp \ + fip/bl30_zero.bin \ + fip/bl301.bin \ + fip/bl301_zero.bin \ + fip/bl30_new.bin \ + bl30 + + $ $FIPDIR/acs_tool.pyc fip/bl2.bin fip/bl2_acs.bin fip/acs.bin 0 + + $ $FIPDIR/blx_fix.sh \ + fip/bl2_acs.bin \ + fip/zero_tmp \ + fip/bl2_zero.bin \ + fip/bl21.bin \ + fip/bl21_zero.bin \ + fip/bl2_new.bin \ + bl2 + + $ $FIPDIR/axg/aml_encrypt_axg --bl3sig --input fip/bl30_new.bin \ + --output fip/bl30_new.bin.enc \ + --level v3 --type bl30 + $ $FIPDIR/axg/aml_encrypt_axg --bl3sig --input fip/bl31.img \ + --output fip/bl31.img.enc \ + --level v3 --type bl31 + $ $FIPDIR/axg/aml_encrypt_axg --bl3sig --input fip/bl33.bin --compress lz4 \ + --output fip/bl33.bin.enc \ + --level v3 --type bl33 + $ $FIPDIR/axg/aml_encrypt_axg --bl2sig --input fip/bl2_new.bin \ + --output fip/bl2.n.bin.sig + $ $FIPDIR/axg/aml_encrypt_axg --bootmk \ + --output fip/u-boot.bin \ + --bl2 fip/bl2.n.bin.sig \ + --bl30 fip/bl30_new.bin.enc \ + --bl31 fip/bl31.img.enc \ + --bl33 fip/bl33.bin.enc --level v3 + +and then write the image to SD with: + +.. code-block:: bash + + $ DEV=/dev/your_sd_device + $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1 + $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444 diff --git a/doc/board/amlogic/sei510.rst b/doc/board/amlogic/sei510.rst new file mode 100644 index 0000000000..2d296b1c3c --- /dev/null +++ b/doc/board/amlogic/sei510.rst @@ -0,0 +1,130 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +U-Boot for Amlogic SEI510 +========================= + +SEI510 is a customer board manufactured by SEI Robotics with the following +specifications: + + - Amlogic S905X2 ARM Cortex-A53 quad-core SoC + - 2GB DDR4 SDRAM + - 10/100 Ethernet (Internal PHY) + - 1 x USB 3.0 Host + - eMMC + - SDcard + - Infrared receiver + - SDIO WiFi Module + +U-Boot compilation +------------------ + +.. code-block:: bash + + $ export CROSS_COMPILE=aarch64-none-elf- + $ make sei510_defconfig + $ make + +Image creation +-------------- + +Amlogic doesn't provide sources for the firmware and for tools needed +to create the bootloader image, so it is necessary to obtain them from +the git tree published by the board vendor: + +.. code-block:: bash + + $ wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz + $ wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz + $ tar xvfJ gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz + $ tar xvfJ gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz + $ export PATH=$PWD/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux/bin:$PWD/gcc-linaro-arm-none-eabi-4.8-2013.11_linux/bin:$PATH + $ git clone https://github.com/BayLibre/u-boot.git -b buildroot-openlinux-20180418 amlogic-u-boot + $ cd amlogic-u-boot + $ make g12a_u200_v1_defconfig + $ make + $ export UBOOTDIR=$PWD + +Download the latest Amlogic Buildroot package, and extract it : + +.. code-block:: bash + + $ wget http://openlinux2.amlogic.com:8000/ARM/filesystem/Linux_BSP/buildroot_openlinux_kernel_4.9_fbdev_20180706.tar.gz + $ tar xfz buildroot_openlinux_kernel_4.9_fbdev_20180706.tar.gz buildroot_openlinux_kernel_4.9_fbdev_20180706/bootloader + $ export BRDIR=$PWD/buildroot_openlinux_kernel_4.9_fbdev_20180706 + $ export FIPDIR=$BRDIR/bootloader/uboot-repo/fip + +Go back to mainline U-Boot source tree then : + +.. code-block:: bash + + $ mkdir fip + + $ wget https://github.com/BayLibre/u-boot/releases/download/v2017.11-libretech-cc/blx_fix_g12a.sh -O fip/blx_fix.sh + $ cp $UBOOTDIR/build/scp_task/bl301.bin fip/ + $ cp $UBOOTDIR/build/board/amlogic/g12a_u200_v1/firmware/acs.bin fip/ + $ cp $BRDIR/bootloader/uboot-repo/bl2/bin/g12a/bl2.bin fip/ + $ cp $BRDIR/bootloader/uboot-repo/bl30/bin/g12a/bl30.bin fip/ + $ cp $BRDIR/bootloader/uboot-repo/bl31_1.3/bin/g12a/bl31.img fip/ + $ cp $FIPDIR/g12a/ddr3_1d.fw fip/ + $ cp $FIPDIR/g12a/ddr4_1d.fw fip/ + $ cp $FIPDIR/g12a/ddr4_2d.fw fip/ + $ cp $FIPDIR/g12a/diag_lpddr4.fw fip/ + $ cp $FIPDIR/g12a/lpddr4_1d.fw fip/ + $ cp $FIPDIR/g12a/lpddr4_2d.fw fip/ + $ cp $FIPDIR/g12a/piei.fw fip/ + $ cp u-boot.bin fip/bl33.bin + + $ sh fip/blx_fix.sh \ + fip/bl30.bin \ + fip/zero_tmp \ + fip/bl30_zero.bin \ + fip/bl301.bin \ + fip/bl301_zero.bin \ + fip/bl30_new.bin \ + bl30 + + $ sh fip/blx_fix.sh \ + fip/bl2.bin \ + fip/zero_tmp \ + fip/bl2_zero.bin \ + fip/acs.bin \ + fip/bl21_zero.bin \ + fip/bl2_new.bin \ + bl2 + + $ $FIPDIR/g12a/aml_encrypt_g12a --bl30sig --input fip/bl30_new.bin \ + --output fip/bl30_new.bin.g12a.enc \ + --level v3 + $ $FIPDIR/g12a/aml_encrypt_g12a --bl3sig --input fip/bl30_new.bin.g12a.enc \ + --output fip/bl30_new.bin.enc \ + --level v3 --type bl30 + $ $FIPDIR/g12a/aml_encrypt_g12a --bl3sig --input fip/bl31.img \ + --output fip/bl31.img.enc \ + --level v3 --type bl31 + $ $FIPDIR/g12a/aml_encrypt_g12a --bl3sig --input fip/bl33.bin --compress lz4 \ + --output fip/bl33.bin.enc \ + --level v3 --type bl33 + $ $FIPDIR/g12a/aml_encrypt_g12a --bl2sig --input fip/bl2_new.bin \ + --output fip/bl2.n.bin.sig + $ $FIPDIR/g12a/aml_encrypt_g12a --bootmk \ + --output fip/u-boot.bin \ + --bl2 fip/bl2.n.bin.sig \ + --bl30 fip/bl30_new.bin.enc \ + --bl31 fip/bl31.img.enc \ + --bl33 fip/bl33.bin.enc \ + --ddrfw1 fip/ddr4_1d.fw \ + --ddrfw2 fip/ddr4_2d.fw \ + --ddrfw3 fip/ddr3_1d.fw \ + --ddrfw4 fip/piei.fw \ + --ddrfw5 fip/lpddr4_1d.fw \ + --ddrfw6 fip/lpddr4_2d.fw \ + --ddrfw7 fip/diag_lpddr4.fw \ + --level v3 + +and then write the image to SD with: + +.. code-block:: bash + + $ DEV=/dev/your_sd_device + $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1 + $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444 diff --git a/doc/board/amlogic/sei610.rst b/doc/board/amlogic/sei610.rst new file mode 100644 index 0000000000..9434e6f023 --- /dev/null +++ b/doc/board/amlogic/sei610.rst @@ -0,0 +1,133 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +U-Boot for Amlogic SEI610 +========================= + +SEI610 is a customer board manufactured by SEI Robotics with the following +specifications: + + - Amlogic S905X3 ARM Cortex-A55 quad-core SoC + - 2GB DDR4 SDRAM + - 10/100 Ethernet (Internal PHY) + - 1 x USB 3.0 Host + - 1 x USB Type-C DRD + - 1 x FTDI USB Serial Debug Interface + - eMMC + - SDcard + - Infrared receiver + - SDIO WiFi Module + +U-Boot compilation +------------------ + +.. code-block:: bash + + $ export CROSS_COMPILE=aarch64-none-elf- + $ make sei610_defconfig + $ make + +Image creation +-------------- + +Amlogic doesn't provide sources for the firmware and for tools needed +to create the bootloader image, so it is necessary to obtain them from +the git tree published by the board vendor: + +.. code-block:: bash + + $ wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz + $ wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz + $ tar xvfJ gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz + $ tar xvfJ gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz + $ export PATH=$PWD/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux/bin:$PWD/gcc-linaro-arm-none-eabi-4.8-2013.11_linux/bin:$PATH + $ git clone https://github.com/BayLibre/u-boot.git -b buildroot-openlinux-4.9-g12a-201904 amlogic-u-boot + $ cd amlogic-u-boot + $ make sm1_ac200_v1_defconfig + $ make + $ export UBOOTDIR=$PWD + +Download the latest Amlogic Buildroot package, and extract it : + +.. code-block:: bash + + $ wget http://openlinux2.amlogic.com:8000/ARM/filesystem/buildroot-openlinux-A113-201901.tgz + $ tar xfz buildroot-openlinux-A113-201901.tgz buildroot-openlinux-A113-201901/bootloader + $ export BRDIR=$PWD/buildroot-openlinux-A113-201901 + $ export FIPDIR=$BRDIR/bootloader/uboot-repo/fip + +Go back to mainline U-Boot source tree then : + + +.. code-block:: bash + + $ mkdir fip + + $ wget https://github.com/BayLibre/u-boot/releases/download/v2017.11-libretech-cc/blx_fix_g12a.sh -O fip/blx_fix.sh + $ cp $UBOOTDIR/build/scp_task/bl301.bin fip/ + $ cp $UBOOTDIR/build/board/amlogic/g12a_u200_v1/firmware/acs.bin fip/ + $ cp $BRDIR/bootloader/uboot-repo/bl2/bin/g12a/bl2.bin fip/ + $ cp $BRDIR/bootloader/uboot-repo/bl30/bin/g12a/bl30.bin fip/ + $ cp $BRDIR/bootloader/uboot-repo/bl31_1.3/bin/g12a/bl31.img fip/ + $ cp $FIPDIR/g12a/ddr3_1d.fw fip/ + $ cp $FIPDIR/g12a/ddr4_1d.fw fip/ + $ cp $FIPDIR/g12a/ddr4_2d.fw fip/ + $ cp $FIPDIR/g12a/diag_lpddr4.fw fip/ + $ cp $FIPDIR/g12a/lpddr4_1d.fw fip/ + $ cp $FIPDIR/g12a/lpddr4_2d.fw fip/ + $ cp $FIPDIR/g12a/piei.fw fip/ + $ cp u-boot.bin fip/bl33.bin + + $ sh fip/blx_fix.sh \ + fip/bl30.bin \ + fip/zero_tmp \ + fip/bl30_zero.bin \ + fip/bl301.bin \ + fip/bl301_zero.bin \ + fip/bl30_new.bin \ + bl30 + + $ sh fip/blx_fix.sh \ + fip/bl2.bin \ + fip/zero_tmp \ + fip/bl2_zero.bin \ + fip/acs.bin \ + fip/bl21_zero.bin \ + fip/bl2_new.bin \ + bl2 + + $ $FIPDIR/g12a/aml_encrypt_g12a --bl30sig --input fip/bl30_new.bin \ + --output fip/bl30_new.bin.g12a.enc \ + --level v3 + $ $FIPDIR/g12a/aml_encrypt_g12a --bl3sig --input fip/bl30_new.bin.g12a.enc \ + --output fip/bl30_new.bin.enc \ + --level v3 --type bl30 + $ $FIPDIR/g12a/aml_encrypt_g12a --bl3sig --input fip/bl31.img \ + --output fip/bl31.img.enc \ + --level v3 --type bl31 + $ $FIPDIR/g12a/aml_encrypt_g12a --bl3sig --input fip/bl33.bin --compress lz4 \ + --output fip/bl33.bin.enc \ + --level v3 --type bl33 + $ $FIPDIR/g12a/aml_encrypt_g12a --bl2sig --input fip/bl2_new.bin \ + --output fip/bl2.n.bin.sig + $ $FIPDIR/g12a/aml_encrypt_g12a --bootmk \ + --output fip/u-boot.bin \ + --bl2 fip/bl2.n.bin.sig \ + --bl30 fip/bl30_new.bin.enc \ + --bl31 fip/bl31.img.enc \ + --bl33 fip/bl33.bin.enc \ + --ddrfw1 fip/ddr4_1d.fw \ + --ddrfw2 fip/ddr4_2d.fw \ + --ddrfw3 fip/ddr3_1d.fw \ + --ddrfw4 fip/piei.fw \ + --ddrfw5 fip/lpddr4_1d.fw \ + --ddrfw6 fip/lpddr4_2d.fw \ + --ddrfw7 fip/diag_lpddr4.fw \ + --level v3 + +and then write the image to SD with: + +.. code-block:: bash + + $ DEV=/dev/your_sd_device + $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1 + $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444 diff --git a/doc/board/amlogic/u200.rst b/doc/board/amlogic/u200.rst new file mode 100644 index 0000000000..5aa3936c28 --- /dev/null +++ b/doc/board/amlogic/u200.rst @@ -0,0 +1,135 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +U-Boot for Amlogic U200 +======================= + +U200 is a reference board manufactured by Amlogic with the following +specifications: + + - Amlogic S905D2 ARM Cortex-A53 quad-core SoC + - 2GB DDR4 SDRAM + - 10/100 Ethernet (Internal PHY) + - 1 x USB 3.0 Host + - eMMC + - SDcard + - Infrared receiver + - SDIO WiFi Module + - MIPI DSI Connector + - Audio HAT Connector + - PCI-E M.2 Connector + +Schematics are available from Amlogic on demand. + +U-Boot compilation +------------------ + +.. code-block:: bash + + $ export CROSS_COMPILE=aarch64-none-elf- + $ make u200_defconfig + $ make + +Image creation +-------------- + +Amlogic doesn't provide sources for the firmware and for tools needed +to create the bootloader image, so it is necessary to obtain them from +the git tree published by the board vendor: + +.. code-block:: bash + + $ wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz + $ wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz + $ tar xvfJ gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz + $ tar xvfJ gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz + $ export PATH=$PWD/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux/bin:$PWD/gcc-linaro-arm-none-eabi-4.8-2013.11_linux/bin:$PATH + $ git clone https://github.com/BayLibre/u-boot.git -b buildroot-openlinux-20180418 amlogic-u-boot + $ cd amlogic-u-boot + $ make g12a_u200_v1_defconfig + $ make + $ export UBOOTDIR=$PWD + +Download the latest Amlogic Buildroot package, and extract it : + +.. code-block:: bash + + $ wget http://openlinux2.amlogic.com:8000/ARM/filesystem/Linux_BSP/buildroot_openlinux_kernel_4.9_fbdev_20180706.tar.gz + $ tar xfz buildroot_openlinux_kernel_4.9_fbdev_20180706.tar.gz buildroot_openlinux_kernel_4.9_fbdev_20180706/bootloader + $ export BRDIR=$PWD/buildroot_openlinux_kernel_4.9_fbdev_20180706 + $ export FIPDIR=$BRDIR/bootloader/uboot-repo/fip + +Go back to mainline U-Boot source tree then : + +.. code-block:: bash + + $ mkdir fip + + $ wget https://github.com/BayLibre/u-boot/releases/download/v2017.11-libretech-cc/blx_fix_g12a.sh -O fip/blx_fix.sh + $ cp $UBOOTDIR/build/scp_task/bl301.bin fip/ + $ cp $UBOOTDIR/build/board/amlogic/g12a_u200_v1/firmware/acs.bin fip/ + $ cp $BRDIR/bootloader/uboot-repo/bl2/bin/g12a/bl2.bin fip/ + $ cp $BRDIR/bootloader/uboot-repo/bl30/bin/g12a/bl30.bin fip/ + $ cp $BRDIR/bootloader/uboot-repo/bl31_1.3/bin/g12a/bl31.img fip/ + $ cp $FIPDIR/g12a/ddr3_1d.fw fip/ + $ cp $FIPDIR/g12a/ddr4_1d.fw fip/ + $ cp $FIPDIR/g12a/ddr4_2d.fw fip/ + $ cp $FIPDIR/g12a/diag_lpddr4.fw fip/ + $ cp $FIPDIR/g12a/lpddr4_1d.fw fip/ + $ cp $FIPDIR/g12a/lpddr4_2d.fw fip/ + $ cp $FIPDIR/g12a/piei.fw fip/ + $ cp u-boot.bin fip/bl33.bin + + $ sh fip/blx_fix.sh \ + fip/bl30.bin \ + fip/zero_tmp \ + fip/bl30_zero.bin \ + fip/bl301.bin \ + fip/bl301_zero.bin \ + fip/bl30_new.bin \ + bl30 + + $ sh fip/blx_fix.sh \ + fip/bl2.bin \ + fip/zero_tmp \ + fip/bl2_zero.bin \ + fip/acs.bin \ + fip/bl21_zero.bin \ + fip/bl2_new.bin \ + bl2 + + $ $FIPDIR/g12a/aml_encrypt_g12a --bl30sig --input fip/bl30_new.bin \ + --output fip/bl30_new.bin.g12a.enc \ + --level v3 + $ $FIPDIR/g12a/aml_encrypt_g12a --bl3sig --input fip/bl30_new.bin.g12a.enc \ + --output fip/bl30_new.bin.enc \ + --level v3 --type bl30 + $ $FIPDIR/g12a/aml_encrypt_g12a --bl3sig --input fip/bl31.img \ + --output fip/bl31.img.enc \ + --level v3 --type bl31 + $ $FIPDIR/g12a/aml_encrypt_g12a --bl3sig --input fip/bl33.bin --compress lz4 \ + --output fip/bl33.bin.enc \ + --level v3 --type bl33 + $ $FIPDIR/g12a/aml_encrypt_g12a --bl2sig --input fip/bl2_new.bin \ + --output fip/bl2.n.bin.sig + $ $FIPDIR/g12a/aml_encrypt_g12a --bootmk \ + --output fip/u-boot.bin \ + --bl2 fip/bl2.n.bin.sig \ + --bl30 fip/bl30_new.bin.enc \ + --bl31 fip/bl31.img.enc \ + --bl33 fip/bl33.bin.enc \ + --ddrfw1 fip/ddr4_1d.fw \ + --ddrfw2 fip/ddr4_2d.fw \ + --ddrfw3 fip/ddr3_1d.fw \ + --ddrfw4 fip/piei.fw \ + --ddrfw5 fip/lpddr4_1d.fw \ + --ddrfw6 fip/lpddr4_2d.fw \ + --ddrfw7 fip/diag_lpddr4.fw \ + --level v3 + +and then write the image to SD with: + +.. code-block:: bash + + $ DEV=/dev/your_sd_device + $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1 + $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444 diff --git a/doc/board/amlogic/w400.rst b/doc/board/amlogic/w400.rst new file mode 100644 index 0000000000..38dbf52fb9 --- /dev/null +++ b/doc/board/amlogic/w400.rst @@ -0,0 +1,137 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +U-Boot for Amlogic W400 +======================= + +U200 is a reference board manufactured by Amlogic with the following +specifications: + + - Amlogic S922X ARM Cortex-A53 dual-core + Cortex-A73 quad-core SoC + - 2GB DDR4 SDRAM + - 10/100 Ethernet (Internal PHY) + - 1 x USB 3.0 Host + - eMMC + - SDcard + - Infrared receiver + - SDIO WiFi Module + - MIPI DSI Connector + - Audio HAT Connector + - PCI-E M.2 Connector + +Schematics are available from Amlogic on demand. + +U-Boot compilation +------------------ + +.. code-block:: bash + + $ export CROSS_COMPILE=aarch64-none-elf- + $ make w400_defconfig + $ make + +Image creation +-------------- + +Amlogic doesn't provide sources for the firmware and for tools needed +to create the bootloader image, so it is necessary to obtain them from +the git tree published by the board vendor: + +.. code-block:: bash + + $ wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz + $ wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz + $ tar xvfJ gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz + $ tar xvfJ gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz + $ export PATH=$PWD/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux/bin:$PWD/gcc-linaro-arm-none-eabi-4.8-2013.11_linux/bin:$PATH + $ git clone https://github.com/BayLibre/u-boot.git -b buildroot-openlinux-20180418 amlogic-u-boot + $ cd amlogic-u-boot + $ make g12b_w400_v1_defconfig + $ make + $ export UBOOTDIR=$PWD + +Download the latest Amlogic Buildroot package, and extract it : + +.. code-block:: bash + + $ wget http://openlinux2.amlogic.com:8000/ARM/filesystem/Linux_BSP/buildroot_openlinux_kernel_4.9_fbdev_20180706.tar.gz + $ tar xfz buildroot_openlinux_kernel_4.9_fbdev_20180706.tar.gz buildroot_openlinux_kernel_4.9_fbdev_20180706/bootloader + $ export BRDIR=$PWD/buildroot_openlinux_kernel_4.9_fbdev_20180706 + $ export FIPDIR=$BRDIR/bootloader/uboot-repo/fip + +Go back to mainline U-Boot source tree then : + +.. code-block:: bash + + $ mkdir fip + + $ wget https://github.com/BayLibre/u-boot/releases/download/v2017.11-libretech-cc/blx_fix_g12a.sh -O fip/blx_fix.sh + $ cp $UBOOTDIR/build/scp_task/bl301.bin fip/ + $ cp $UBOOTDIR/build/board/amlogic/g12b_w400_v1/firmware/acs.bin fip/ + $ cp $BRDIR/bootloader/uboot-repo/bl2/bin/g12b/bl2.bin fip/ + $ cp $BRDIR/bootloader/uboot-repo/bl30/bin/g12b/bl30.bin fip/ + $ cp $BRDIR/bootloader/uboot-repo/bl31_1.3/bin/g12b/bl31.img fip/ + $ cp $FIPDIR/g12b/ddr3_1d.fw fip/ + $ cp $FIPDIR/g12b/ddr4_1d.fw fip/ + $ cp $FIPDIR/g12b/ddr4_2d.fw fip/ + $ cp $FIPDIR/g12b/diag_lpddr4.fw fip/ + $ cp $FIPDIR/g12b/lpddr4_1d.fw fip/ + $ cp $FIPDIR/g12b/lpddr4_2d.fw fip/ + $ cp $FIPDIR/g12b/piei.fw fip/ + $ cp $FIPDIR/g12b/aml_ddr.fw fip/ + $ cp u-boot.bin fip/bl33.bin + + $ sh fip/blx_fix.sh \ + fip/bl30.bin \ + fip/zero_tmp \ + fip/bl30_zero.bin \ + fip/bl301.bin \ + fip/bl301_zero.bin \ + fip/bl30_new.bin \ + bl30 + + $ sh fip/blx_fix.sh \ + fip/bl2.bin \ + fip/zero_tmp \ + fip/bl2_zero.bin \ + fip/acs.bin \ + fip/bl21_zero.bin \ + fip/bl2_new.bin \ + bl2 + + $ $FIPDIR/g12b/aml_encrypt_g12b --bl30sig --input fip/bl30_new.bin \ + --output fip/bl30_new.bin.g12a.enc \ + --level v3 + $ $FIPDIR/g12b/aml_encrypt_g12b --bl3sig --input fip/bl30_new.bin.g12a.enc \ + --output fip/bl30_new.bin.enc \ + --level v3 --type bl30 + $ $FIPDIR/g12b/aml_encrypt_g12b --bl3sig --input fip/bl31.img \ + --output fip/bl31.img.enc \ + --level v3 --type bl31 + $ $FIPDIR/g12b/aml_encrypt_g12b --bl3sig --input fip/bl33.bin --compress lz4 \ + --output fip/bl33.bin.enc \ + --level v3 --type bl33 + $ $FIPDIR/g12b/aml_encrypt_g12b --bl2sig --input fip/bl2_new.bin \ + --output fip/bl2.n.bin.sig + $ $FIPDIR/g12b/aml_encrypt_g12b --bootmk \ + --output fip/u-boot.bin \ + --bl2 fip/bl2.n.bin.sig \ + --bl30 fip/bl30_new.bin.enc \ + --bl31 fip/bl31.img.enc \ + --bl33 fip/bl33.bin.enc \ + --ddrfw1 fip/ddr4_1d.fw \ + --ddrfw2 fip/ddr4_2d.fw \ + --ddrfw3 fip/ddr3_1d.fw \ + --ddrfw4 fip/piei.fw \ + --ddrfw5 fip/lpddr4_1d.fw \ + --ddrfw6 fip/lpddr4_2d.fw \ + --ddrfw7 fip/diag_lpddr4.fw \ + --ddrfw8 fip/aml_ddr.fw \ + --level v3 + +and then write the image to SD with: + +.. code-block:: bash + + $ DEV=/dev/your_sd_device + $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1 + $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444 diff --git a/doc/board/index.rst b/doc/board/index.rst index 01b233f737..dc683f0acb 100644 --- a/doc/board/index.rst +++ b/doc/board/index.rst @@ -8,6 +8,7 @@ Board-specific doc actions/index AndesTech/index + amlogic/index atmel/index coreboot/index emulation/index From 9c55f5d11260c5aa0f91d8cb32aa0ad00910659d Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Thu, 11 Jun 2020 10:57:39 +0200 Subject: [PATCH 02/79] board: amlogic: add board doc files to MAINTAINERS Add the recently added reStructuredText board documentation in the appropriate MAINTAINERS files. Signed-off-by: Neil Armstrong --- MAINTAINERS | 1 + board/amlogic/p200/MAINTAINERS | 3 +++ board/amlogic/p201/MAINTAINERS | 1 + board/amlogic/p212/MAINTAINERS | 4 ++++ board/amlogic/q200/MAINTAINERS | 1 + board/amlogic/s400/MAINTAINERS | 1 + board/amlogic/sei510/MAINTAINERS | 1 + board/amlogic/sei610/MAINTAINERS | 1 + board/amlogic/u200/MAINTAINERS | 1 + board/amlogic/w400/MAINTAINERS | 4 ++++ 10 files changed, 18 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 00985c0e8e..db8cecd5e0 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -145,6 +145,7 @@ F: drivers/power/domain/meson-gx-pwrc-vpu.c F: drivers/video/meson/ F: include/configs/meson64.h F: include/configs/meson64_android.h +F: doc/board/amlogic/ N: meson ARM BROADCOM BCM283X diff --git a/board/amlogic/p200/MAINTAINERS b/board/amlogic/p200/MAINTAINERS index c20f056af2..1df9b8b24b 100644 --- a/board/amlogic/p200/MAINTAINERS +++ b/board/amlogic/p200/MAINTAINERS @@ -7,3 +7,6 @@ F: board/amlogic/p200/ F: configs/nanopi-k2_defconfig F: configs/odroid-c2_defconfig F: configs/p200_defconfig +F: doc/board/amlogic/p200.rst +F: doc/board/amlogic/nanopi-k2.rst +F: doc/board/amlogic/odroid-c2.rst diff --git a/board/amlogic/p201/MAINTAINERS b/board/amlogic/p201/MAINTAINERS index f84984d7ab..1501b6280d 100644 --- a/board/amlogic/p201/MAINTAINERS +++ b/board/amlogic/p201/MAINTAINERS @@ -4,3 +4,4 @@ S: Maintained L: u-boot-amlogic@groups.io F: board/amlogic/p201/ F: configs/p201_defconfig +F: doc/board/amlogic/p201.rst diff --git a/board/amlogic/p212/MAINTAINERS b/board/amlogic/p212/MAINTAINERS index 8848df05b7..cae6994393 100644 --- a/board/amlogic/p212/MAINTAINERS +++ b/board/amlogic/p212/MAINTAINERS @@ -8,3 +8,7 @@ F: configs/khadas-vim_defconfig F: configs/libretech-ac_defconfig F: configs/libretech-cc_defconfig F: configs/p212_defconfig +F: doc/board/amlogic/p212.rst +F: doc/board/amlogic/libretech-ac.rst +F: doc/board/amlogic/libretech-cc.rst +F: doc/board/amlogic/khadas-vim.rst diff --git a/board/amlogic/q200/MAINTAINERS b/board/amlogic/q200/MAINTAINERS index 6f00f87386..ec05aa6f4c 100644 --- a/board/amlogic/q200/MAINTAINERS +++ b/board/amlogic/q200/MAINTAINERS @@ -7,3 +7,4 @@ F: include/configs/q200.h F: configs/khadas-vim2_defconfig F: configs/libretech-s905d-pc_defconfig F: configs/libretech-s912-pc_defconfig +F: doc/board/amlogic/khadas-vim2.rst diff --git a/board/amlogic/s400/MAINTAINERS b/board/amlogic/s400/MAINTAINERS index da90cf9b6f..fb46b1bbbf 100644 --- a/board/amlogic/s400/MAINTAINERS +++ b/board/amlogic/s400/MAINTAINERS @@ -5,3 +5,4 @@ L: u-boot-amlogic@groups.io F: board/amlogic/s400/ F: include/configs/s400.h F: configs/s400_defconfig +F: doc/board/amlogic/s400.rst diff --git a/board/amlogic/sei510/MAINTAINERS b/board/amlogic/sei510/MAINTAINERS index 8dc655e8cc..c01c1d60df 100644 --- a/board/amlogic/sei510/MAINTAINERS +++ b/board/amlogic/sei510/MAINTAINERS @@ -5,3 +5,4 @@ L: u-boot-amlogic@groups.io F: board/amlogic/sei510/ F: configs/sei510_defconfig F: include/configs/sei510.h +F: doc/board/amlogic/sei510.rst diff --git a/board/amlogic/sei610/MAINTAINERS b/board/amlogic/sei610/MAINTAINERS index da77aafa41..092178b2c8 100644 --- a/board/amlogic/sei610/MAINTAINERS +++ b/board/amlogic/sei610/MAINTAINERS @@ -5,3 +5,4 @@ L: u-boot-amlogic@groups.io F: board/amlogic/sei610/ F: configs/sei610_defconfig F: include/configs/sei610.h +F: doc/board/amlogic/sei610.rst diff --git a/board/amlogic/u200/MAINTAINERS b/board/amlogic/u200/MAINTAINERS index 5ae7f5e66a..8c23f9a7d3 100644 --- a/board/amlogic/u200/MAINTAINERS +++ b/board/amlogic/u200/MAINTAINERS @@ -4,3 +4,4 @@ S: Maintained L: u-boot-amlogic@groups.io F: board/amlogic/u200/ F: configs/u200_defconfig +F: doc/board/amlogic/u200.rst diff --git a/board/amlogic/w400/MAINTAINERS b/board/amlogic/w400/MAINTAINERS index 2ff90039ca..5e837cfaef 100644 --- a/board/amlogic/w400/MAINTAINERS +++ b/board/amlogic/w400/MAINTAINERS @@ -6,3 +6,7 @@ F: board/amlogic/w400/ F: configs/khadas-vim3_defconfig F: configs/khadas-vim3l_defconfig F: configs/odroid-n2_defconfig +F: doc/board/amlogic/w400.rst +F: doc/board/amlogic/khadas-vim3.rst +F: doc/board/amlogic/khadas-vim3l.rst +F: doc/board/amlogic/odroid-n2.rst From f94e54811a74a2e0589bef6a11ebf488f86d1dd3 Mon Sep 17 00:00:00 2001 From: Anatolij Gustschin Date: Tue, 26 May 2020 10:52:00 +0200 Subject: [PATCH 03/79] cm_fx6: fix video stdout in default environment After migration to DM 'vga' name is not longer supported, change it to 'vidconsole' in the default environment. Signed-off-by: Anatolij Gustschin Cc: Nikita Kiryanov --- include/configs/cm_fx6.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/include/configs/cm_fx6.h b/include/configs/cm_fx6.h index 302907dcfb..35f251c15e 100644 --- a/include/configs/cm_fx6.h +++ b/include/configs/cm_fx6.h @@ -49,8 +49,8 @@ "scriptaddr=" __stringify(CONFIG_LOADADDR) "\0" \ "fdtfile=undefined\0" \ "stdin=serial,usbkbd\0" \ - "stdout=serial,vga\0" \ - "stderr=serial,vga\0" \ + "stdout=serial,vidconsole\0" \ + "stderr=serial,vidconsole\0" \ "panel=HDMI\0" \ "autoload=no\0" \ "uImage=uImage-cm-fx6\0" \ From d8c37c63098ee6133739c94230dd4f283c481543 Mon Sep 17 00:00:00 2001 From: Anatolij Gustschin Date: Tue, 26 May 2020 10:43:44 +0200 Subject: [PATCH 04/79] apalis_imx6: fix video stdout in default environment After migration to DM 'vga' name is not longer supported, change it to 'vidconsole' in the default environment. Signed-off-by: Anatolij Gustschin Acked-by: Igor Opaniuk --- include/configs/apalis_imx6.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/include/configs/apalis_imx6.h b/include/configs/apalis_imx6.h index d5a0625e02..6fc7c3982c 100644 --- a/include/configs/apalis_imx6.h +++ b/include/configs/apalis_imx6.h @@ -169,7 +169,8 @@ BOOTENV \ "bootcmd=setenv fdtfile ${fdt_file}; run distro_bootcmd ; " \ "usb start ; " \ - "setenv stdout serial,vga ; setenv stdin serial,usbkbd\0" \ + "setenv stdout serial,vidconsole; " \ + "setenv stdin serial,usbkbd\0" \ "boot_file=zImage\0" \ "console=ttymxc0\0" \ "defargs=enable_wait_mode=off vmalloc=400M\0" \ From 1099b2abef35c3c887f6afac1a8ef18c7924d5d2 Mon Sep 17 00:00:00 2001 From: Anatolij Gustschin Date: Tue, 26 May 2020 10:50:17 +0200 Subject: [PATCH 05/79] colibri_imx6: fix video stdout in default environment After migration to DM 'vga' name is not longer supported, change it to 'vidconsole' in the default environment. Signed-off-by: Anatolij Gustschin Acked-by: Igor Opaniuk --- include/configs/colibri_imx6.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/include/configs/colibri_imx6.h b/include/configs/colibri_imx6.h index 6beef25094..0a52a701c6 100644 --- a/include/configs/colibri_imx6.h +++ b/include/configs/colibri_imx6.h @@ -152,7 +152,8 @@ BOOTENV \ "bootcmd=setenv fdtfile ${fdt_file}; run distro_bootcmd; " \ "usb start ; " \ - "setenv stdout serial,vga ; setenv stdin serial,usbkbd\0" \ + "setenv stdout serial,vidconsole; " \ + "setenv stdin serial,usbkbd\0" \ "boot_file=zImage\0" \ "console=ttymxc0\0" \ "defargs=enable_wait_mode=off galcore.contiguousSize=50331648\0" \ From 10fa7ec9f64dec9bc90e85e37248eabfb9b44bf2 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 14 Jun 2020 14:41:07 +0200 Subject: [PATCH 06/79] ARM: rmobile: Increase PHY auto-negotiation timeout to 20s The ethernet PHY on all known Gen3 boards takes a while to come out of reset, increase the auto-negotiation timeout to prevent it from timing out in case the ethernet is used right after the board was reset. Signed-off-by: Marek Vasut Cc: Nobuhiro Iwamatsu --- include/configs/rcar-gen3-common.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/include/configs/rcar-gen3-common.h b/include/configs/rcar-gen3-common.h index 8f400ba05a..cf4d3bad2e 100644 --- a/include/configs/rcar-gen3-common.h +++ b/include/configs/rcar-gen3-common.h @@ -34,6 +34,9 @@ #define CONFIG_SYS_MAXARGS 64 #define CONFIG_SYS_BAUDRATE_TABLE { 115200, 38400 } +/* PHY needs a longer autoneg timeout */ +#define PHY_ANEG_TIMEOUT 20000 + /* MEMORY */ #define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE From 717e779f6e2e14a876e5965a455604ab966f1f26 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Thu, 18 Jun 2020 13:51:39 -0400 Subject: [PATCH 07/79] Azure/GitLab: Move to latest Docker image - Add guestfstools, efitools - Latest Ubuntu/bionic snapshot Signed-off-by: Tom Rini --- .azure-pipelines.yml | 2 +- .gitlab-ci.yml | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/.azure-pipelines.yml b/.azure-pipelines.yml index 636500d6ce..28387ce17c 100644 --- a/.azure-pipelines.yml +++ b/.azure-pipelines.yml @@ -2,7 +2,7 @@ variables: windows_vm: vs2017-win2016 ubuntu_vm: ubuntu-18.04 macos_vm: macOS-10.15 - ci_runner_image: trini/u-boot-gitlab-ci-runner:bionic-20200403-27Apr2020 + ci_runner_image: trini/u-boot-gitlab-ci-runner:bionic-20200526-18Jun2020 # Add '-u 0' options for Azure pipelines, otherwise we get "permission # denied" error when it tries to "useradd -m -u 1001 vsts_azpcontainer", # since our $(ci_runner_image) user is not root. diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index badfcb4254..f2e491c117 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -2,7 +2,7 @@ # Grab our configured image. The source for this is found at: # https://gitlab.denx.de/u-boot/gitlab-ci-runner -image: trini/u-boot-gitlab-ci-runner:bionic-20200403-27Apr2020 +image: trini/u-boot-gitlab-ci-runner:bionic-20200526-18Jun2020 # We run some tests in different order, to catch some failures quicker. stages: From fb264efbd2fef45ca96630c355cbe30957132f3f Mon Sep 17 00:00:00 2001 From: Jon Hunter Date: Thu, 18 Jun 2020 12:54:38 +0100 Subject: [PATCH 08/79] firmware: PSCI: Fix PSCI support for OF live trees When CONFIG_OF_LIVE is enabled, dev_of_offset() cannot be used and if used returns an invalid offset. This causes the call to fdt_stringlist_get() in the psci_probe() to fail to read the 'method' property from the PSCI node for the device and hence prevents PSCI from working. Fix this by using the ofnode_read_string() API instead of the fdt_stringlist_get() because this will handle reading the property both when CONFIG_OF_LIVE is enabled or disabled. Due to the above problem and since commit 81ea00838c68 ("efi_loader: PSCI reset and shutdown") was added, the EFI system reset has been broken for Tegra210 and Tegra196 platforms. This also fixes the EFI system reset for these Tegra platforms. Signed-off-by: Jon Hunter Tested-by: Peter Robinson --- drivers/firmware/psci.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/drivers/firmware/psci.c b/drivers/firmware/psci.c index e0d66d74f5..23cf807591 100644 --- a/drivers/firmware/psci.c +++ b/drivers/firmware/psci.c @@ -67,11 +67,9 @@ static int psci_bind(struct udevice *dev) static int psci_probe(struct udevice *dev) { - DECLARE_GLOBAL_DATA_PTR; const char *method; - method = fdt_stringlist_get(gd->fdt_blob, dev_of_offset(dev), "method", - 0, NULL); + method = ofnode_read_string(dev_ofnode(dev), "method"); if (!method) { pr_warn("missing \"method\" property\n"); return -ENXIO; From 1ec74533840650b914ccdf9f62a298ecb29994ab Mon Sep 17 00:00:00 2001 From: Jon Hunter Date: Thu, 18 Jun 2020 12:54:39 +0100 Subject: [PATCH 09/79] ARM: tegra: Enable PSCI support for Tegra210 and Tegra186 The PSCI nodes are currently not populated for the Tegra210 and Tegra186 devices. This prevents the PSCI driver from being able to identify the PSCI method used by these devices and causes the probe of the PSCI driver to fail. Since commit 81ea00838c68 ("efi_loader: PSCI reset and shutdown") was added, which moves the PSCI EFI system reset handler into the PSCI driver, this has prevented the EFI system reset from working for Tegra210 and Tegra186. Therefore, populating these nodes is necessary to fix the EFI system reset for Tegra210 and Tegra186. Signed-off-by: Jon Hunter Tested-by: Peter Robinson --- arch/arm/dts/tegra186.dtsi | 5 +++++ arch/arm/dts/tegra210.dtsi | 5 +++++ 2 files changed, 10 insertions(+) diff --git a/arch/arm/dts/tegra186.dtsi b/arch/arm/dts/tegra186.dtsi index 0a9db9825b..edcb7aacb8 100644 --- a/arch/arm/dts/tegra186.dtsi +++ b/arch/arm/dts/tegra186.dtsi @@ -335,4 +335,9 @@ status = "disabled"; }; }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; }; diff --git a/arch/arm/dts/tegra210.dtsi b/arch/arm/dts/tegra210.dtsi index 3ec54b11c4..a521a43d6c 100644 --- a/arch/arm/dts/tegra210.dtsi +++ b/arch/arm/dts/tegra210.dtsi @@ -867,6 +867,11 @@ }; }; + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + timer { compatible = "arm,armv8-timer"; interrupts = Date: Mon, 13 Apr 2020 18:11:42 +0300 Subject: [PATCH 10/79] colibri_t20: change maintainer Take over maintainership for Colibri T20 module. Signed-off-by: Igor Opaniuk Acked-by: Lucas Stach --- board/toradex/colibri_t20/MAINTAINERS | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/toradex/colibri_t20/MAINTAINERS b/board/toradex/colibri_t20/MAINTAINERS index b251c000fe..2a8e6fb74b 100644 --- a/board/toradex/colibri_t20/MAINTAINERS +++ b/board/toradex/colibri_t20/MAINTAINERS @@ -1,5 +1,5 @@ COLIBRI_T20 -M: Lucas Stach +M: Igor Opaniuk S: Maintained F: board/toradex/colibri_t20/ F: include/configs/colibri_t20.h From 7b4f42b6cd5d8fa32f763b5ec03b7b8fdf7c4303 Mon Sep 17 00:00:00 2001 From: Tom Warren Date: Mon, 11 May 2020 16:38:58 -0700 Subject: [PATCH 11/79] t210: Nano: Add NVME support This allows Nano to use the key M.2 on the CVB to connect and use a M.2 NVMe SSD stick. Works on my Nano B00, WD SN750 NVMe SSD shows up w/'nvme' commands. Will add booting from NVMe via distro cmds in a future patch. Signed-off-by: Tom Warren --- configs/p3450-0000_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/p3450-0000_defconfig b/configs/p3450-0000_defconfig index 2bf8f97ca2..c27a6ea237 100644 --- a/configs/p3450-0000_defconfig +++ b/configs/p3450-0000_defconfig @@ -56,3 +56,4 @@ CONFIG_CI_UDC=y CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y +CONFIG_NVME=y From 0d7c2913fdf71d74e0d6c710dcceaa29f3862d8c Mon Sep 17 00:00:00 2001 From: Atish Patra Date: Thu, 18 Jun 2020 18:51:50 -0700 Subject: [PATCH 12/79] cmd: bootefi: Honor the address & size cells properties correctly fdtdec_get_addr_size reads the uses a fixed value for address & size cell properties which may not be correct always. Use the auto variant of the function which automatically reads #address-cells & #size-cells from parent and uses to read the "reg" property. Signed-off-by: Atish Patra On 32 bit systems fdt_addr_t may be 4 bytes long but size is defined as u64. Avoid filling the upper 4 bytes of the sizep parameter of fdtdec_get_addr_size_auto_parent() with random bytes from the stack by defining a separate variable fdt_size. Reviewed-by: Heinrich Schuchardt --- cmd/bootefi.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/cmd/bootefi.c b/cmd/bootefi.c index 0f6d0f7750..ac713cad1b 100644 --- a/cmd/bootefi.c +++ b/cmd/bootefi.c @@ -189,16 +189,19 @@ static void efi_carve_out_dt_rsv(void *fdt) if (nodeoffset >= 0) { subnode = fdt_first_subnode(fdt, nodeoffset); while (subnode >= 0) { + fdt_addr_t fdt_addr, fdt_size; + /* check if this subnode has a reg property */ - addr = fdtdec_get_addr_size(fdt, subnode, "reg", - (fdt_size_t *)&size); + fdt_addr = fdtdec_get_addr_size_auto_parent( + fdt, nodeoffset, subnode, + "reg", 0, &fdt_size, false); /* * The /reserved-memory node may have children with * a size instead of a reg property. */ if (addr != FDT_ADDR_T_NONE && fdtdec_get_is_enabled(fdt, subnode)) - efi_reserve_memory(addr, size); + efi_reserve_memory(fdt_addr, fdt_size); subnode = fdt_next_subnode(fdt, subnode); } } From 3c2e2a1a79608c5e046313a8c47586d9a734e2a3 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Thu, 18 Jun 2020 20:35:17 +0200 Subject: [PATCH 13/79] ARM: dts: stm32: Reinstate card detect behavior on DHSOM The cd-gpios with (GPIO_ACTIVE_LOW | GPIO_PULL_UP) gpio is thus far unsupported, reinstate the old cd-gpios behavior until this handling is fully implemented. This permits the DHSOM to boot from SD again, without this patch the card detect fails. Signed-off-by: Marek Vasut Cc: Patrick Delaunay Cc: Patrice Chotard Reviewed-by: Patrick Delaunay --- arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi b/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi index 75d75266e8..df63ad4a24 100644 --- a/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi +++ b/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi @@ -273,6 +273,9 @@ &sdmmc1 { u-boot,dm-spl; + broken-cd; + /delete-property/ cd-gpios; + /delete-property/ disable-wp; }; &sdmmc1_b4_pins_a { From 792919241b3d750cd5295dfe6dd1d0958b9be468 Mon Sep 17 00:00:00 2001 From: Patrick Delaunay Date: Fri, 19 Jun 2020 11:19:45 +0200 Subject: [PATCH 14/79] ARM: dts: stm32: Reinstate card detect behavior on ST boards The cd-gpios with (GPIO_ACTIVE_LOW | GPIO_PULL_UP) gpio is thus far unsupported, reinstate the old cd-gpios behavior until this handling is fully implemented. This avoid potential issue for SDCard boot: the card detect fails with floating gpio. Signed-off-by: Patrick Delaunay Reviewed-by: Patrice Chotard --- arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi | 2 ++ arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi | 2 ++ 2 files changed, 4 insertions(+) diff --git a/arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi b/arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi index 3fedb6f1e1..e13dade463 100644 --- a/arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi +++ b/arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi @@ -171,6 +171,8 @@ &sdmmc1 { u-boot,dm-spl; + broken-cd; + /delete-property/ cd-gpios; }; &sdmmc1_b4_pins_a { diff --git a/arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi b/arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi index a07c585415..b16dc28d47 100644 --- a/arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi +++ b/arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi @@ -167,6 +167,8 @@ &sdmmc1 { u-boot,dm-spl; + broken-cd; + /delete-property/ cd-gpios; }; &sdmmc1_b4_pins_a { From 338d9b032a2ab0dbbcfcf1bfe373b4852399a636 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Thu, 18 Jun 2020 20:21:17 -0300 Subject: [PATCH 15/79] phy: atheros: ar8035: Fix clock output calculation The clock ouput frequency is calculated incorrectly for AR8035 due to wrong masking of priv->clk_25m_reg and priv->clk_25m_mask. This same issue has been already fixed in the kernel by: commit b1f4c209d84057b6d40b939b6e4404854271d797 Author: Oleksij Rempel Date: Wed Apr 1 11:57:32 2020 +0200 net: phy: at803x: fix clock sink configuration on ATH8030 and ATH8035 The masks in priv->clk_25m_reg and priv->clk_25m_mask are one-bits-set for the values that comprise the fields, not zero-bits-set. This patch fixes the clock frequency configuration for ATH8030 and ATH8035 Atheros PHYs by removing the erroneous "~". To reproduce this bug, configure the PHY with the device tree binding "qca,clk-out-frequency" and remove the machine specific PHY fixups. Fixes: 2f664823a47021 ("net: phy: at803x: add device tree binding") Signed-off-by: Oleksij Rempel Reported-by: Russell King Reviewed-by: Russell King Tested-by: Russell King Signed-off-by: David S. Miller Apply the same fix in the U-Boot driver. Tested on a i.MX6 Hummingboard. Signed-off-by: Fabio Estevam Reviewed-by: Michael Walle Tested-by: Tom Rini --- drivers/net/phy/atheros.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/drivers/net/phy/atheros.c b/drivers/net/phy/atheros.c index 13f7275d17..f922fecd6b 100644 --- a/drivers/net/phy/atheros.c +++ b/drivers/net/phy/atheros.c @@ -275,11 +275,10 @@ static int ar803x_of_init(struct phy_device *phydev) * Fixup for the AR8035 which only has two bits. The two * remaining bits map to the same frequencies. */ - if (phydev->drv->uid == AR8035_PHY_ID) { - u16 clear = AR803x_CLK_25M_MASK & AR8035_CLK_25M_MASK; - priv->clk_25m_mask &= ~clear; - priv->clk_25m_reg &= ~clear; + if (phydev->drv->uid == AR8035_PHY_ID) { + priv->clk_25m_reg &= AR8035_CLK_25M_MASK; + priv->clk_25m_mask &= AR8035_CLK_25M_MASK; } } From 89b5bd54c1a425e416d67ce21b0fd5fd7da6a1d4 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Thu, 18 Jun 2020 20:21:18 -0300 Subject: [PATCH 16/79] net: fec: Allow the PHY node to be retrieved As we move towards driver model, it is required to let the FEC driver know how to properly deal with an Ethernet PHY subnode in the device tree. For example: &fec { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_microsom_enet_ar8035>; phy-handle = <&phy>; phy-mode = "rgmii-id"; phy-reset-duration = <2>; phy-reset-gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; status = "okay"; mdio { #address-cells = <1>; #size-cells = <0>; phy: ethernet-phy@0 { reg = <0>; qca,clk-out-frequency = <125000000>; }; }; }; Currently the PHY node pointer is incorrectly associated with the Ethernel controller instead of the PHY node itself. This causes the PHY properties, such as "qca,clk-out-frequency" in the example above to not get parsed. Fix this problem by populating the phy_of_node node. Suggested-by: Vladimir Oltean Signed-off-by: Fabio Estevam Tested-by: Tom Rini --- drivers/net/fec_mxc.c | 7 +++++-- drivers/net/fec_mxc.h | 1 + 2 files changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c index 9ae2db033e..992180df86 100644 --- a/drivers/net/fec_mxc.c +++ b/drivers/net/fec_mxc.c @@ -1294,7 +1294,7 @@ static const struct eth_ops fecmxc_ops = { .read_rom_hwaddr = fecmxc_read_rom_hwaddr, }; -static int device_get_phy_addr(struct udevice *dev) +static int device_get_phy_addr(struct fec_priv *priv, struct udevice *dev) { struct ofnode_phandle_args phandle_args; int reg; @@ -1305,6 +1305,8 @@ static int device_get_phy_addr(struct udevice *dev) return -ENODEV; } + priv->phy_of_node = phandle_args.node; + reg = ofnode_read_u32_default(phandle_args.node, "reg", 0); return reg; @@ -1315,7 +1317,7 @@ static int fec_phy_init(struct fec_priv *priv, struct udevice *dev) struct phy_device *phydev; int addr; - addr = device_get_phy_addr(dev); + addr = device_get_phy_addr(priv, dev); #ifdef CONFIG_FEC_MXC_PHYADDR addr = CONFIG_FEC_MXC_PHYADDR; #endif @@ -1325,6 +1327,7 @@ static int fec_phy_init(struct fec_priv *priv, struct udevice *dev) return -ENODEV; priv->phydev = phydev; + priv->phydev->node = priv->phy_of_node; phy_config(phydev); return 0; diff --git a/drivers/net/fec_mxc.h b/drivers/net/fec_mxc.h index 0e8f08a51a..659d62646f 100644 --- a/drivers/net/fec_mxc.h +++ b/drivers/net/fec_mxc.h @@ -250,6 +250,7 @@ struct fec_priv { struct mii_dev *bus; #ifdef CONFIG_PHYLIB struct phy_device *phydev; + ofnode phy_of_node; #else int phy_id; int (*mii_postcall)(int); From db86e6c66a8c17911c1442e974c8380ada009975 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Thu, 18 Jun 2020 20:21:19 -0300 Subject: [PATCH 17/79] ARM: dts: imx6qdl-sr-som: Sync with kernel 5.8-rc1 Sync the device tree with 5.8-rc1. It basically contains the following extra kernel commit: commit 86b08bd5b99480b79a25343f24c1b8c4ddcb5c09 Author: Russell King Date: Wed Apr 15 16:44:17 2020 +0100 ARM: dts: imx6-sr-som: add ethernet PHY configuration Add ethernet PHY configuration ahead of removing the quirk that configures the clocking mode for the PHY. The RGMII delay is already set correctly. Signed-off-by: Russell King Reviewed-by: Fabio Estevam Signed-off-by: Shawn Guo , which passes the 'qca,clk-out-frequency' property and it is important to specify the correct frequency generated by the AR8035. Signed-off-by: Fabio Estevam Tested-by: Tom Rini --- arch/arm/dts/imx6qdl-sr-som.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm/dts/imx6qdl-sr-som.dtsi b/arch/arm/dts/imx6qdl-sr-som.dtsi index 6d7f6b9035..b06577808f 100644 --- a/arch/arm/dts/imx6qdl-sr-som.dtsi +++ b/arch/arm/dts/imx6qdl-sr-som.dtsi @@ -53,10 +53,21 @@ &fec { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_microsom_enet_ar8035>; + phy-handle = <&phy>; phy-mode = "rgmii-id"; phy-reset-duration = <2>; phy-reset-gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + phy: ethernet-phy@0 { + reg = <0>; + qca,clk-out-frequency = <125000000>; + }; + }; }; &iomuxc { From d8da22c5dbdc7bc61b575278ea0e02919ffbe734 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Thu, 18 Jun 2020 20:21:20 -0300 Subject: [PATCH 18/79] mx6cuboxi: Convert to DM_ETH Migration to DM_ETH is mandatory, so convert mx6cuboxi to Ethernet Driver Model. This also brings the benefit of restoring Ethernet functionality. Reported-by: Tom Rini Signed-off-by: Fabio Estevam Tested-by: Tom Rini --- board/solidrun/mx6cuboxi/mx6cuboxi.c | 134 ++++----------------------- configs/mx6cuboxi_defconfig | 3 + include/configs/mx6cuboxi.h | 6 -- 3 files changed, 20 insertions(+), 123 deletions(-) diff --git a/board/solidrun/mx6cuboxi/mx6cuboxi.c b/board/solidrun/mx6cuboxi/mx6cuboxi.c index 94707bccb2..59e8b1dca1 100644 --- a/board/solidrun/mx6cuboxi/mx6cuboxi.c +++ b/board/solidrun/mx6cuboxi/mx6cuboxi.c @@ -17,7 +17,6 @@ #include #include #include -#include #include #include #include @@ -33,8 +32,6 @@ #include #include #include -#include -#include #include #include #include @@ -52,16 +49,6 @@ DECLARE_GLOBAL_DATA_PTR; PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \ PAD_CTL_SRE_FAST | PAD_CTL_HYS) -#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ - PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS) - -#define ENET_PAD_CTRL_PD (PAD_CTL_PUS_100K_DOWN | \ - PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS) - -#define ENET_PAD_CTRL_CLK ((PAD_CTL_PUS_100K_UP & ~PAD_CTL_PKE) | \ - PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) - -#define ETH_PHY_RESET IMX_GPIO_NR(4, 15) #define USB_H1_VBUS IMX_GPIO_NR(1, 0) enum board_type { @@ -237,110 +224,6 @@ int board_mmc_init(bd_t *bis) return 0; } -static iomux_v3_cfg_t const enet_pads[] = { - IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)), - IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)), - /* AR8035 reset */ - IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD)), - /* AR8035 interrupt */ - IOMUX_PADS(PAD_DI0_PIN2__GPIO4_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL)), - /* GPIO16 -> AR8035 25MHz */ - IOMUX_PADS(PAD_GPIO_16__ENET_REF_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)), - IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(NO_PAD_CTRL)), - IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)), - IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)), - IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)), - IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)), - IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL)), - /* AR8035 CLK_25M --> ENET_REF_CLK (V22) */ - IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL_CLK)), - IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)), - IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD)), - IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD)), - IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)), - IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)), - IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL_PD)), - IOMUX_PADS(PAD_ENET_RXD0__GPIO1_IO27 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD)), - IOMUX_PADS(PAD_ENET_RXD1__GPIO1_IO26 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD)), -}; - -static void setup_iomux_enet(void) -{ - struct gpio_desc desc; - int ret; - - SETUP_IOMUX_PADS(enet_pads); - - ret = dm_gpio_lookup_name("GPIO4_15", &desc); - if (ret) { - printf("%s: phy reset lookup failed\n", __func__); - return; - } - - ret = dm_gpio_request(&desc, "phy-reset"); - if (ret) { - printf("%s: phy reset request failed\n", __func__); - return; - } - - gpio_direction_output(ETH_PHY_RESET, 0); - mdelay(10); - gpio_set_value(ETH_PHY_RESET, 1); - udelay(100); - - gpio_free_list_nodev(&desc, 1); -} - -int board_phy_config(struct phy_device *phydev) -{ - if (phydev->drv->config) - phydev->drv->config(phydev); - - return 0; -} - -/* On Cuboxi Ethernet PHY can be located at addresses 0x0 or 0x4 */ -#define ETH_PHY_MASK ((1 << 0x0) | (1 << 0x4)) - -int board_eth_init(bd_t *bis) -{ - struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; - struct mii_dev *bus; - struct phy_device *phydev; - - int ret = enable_fec_anatop_clock(0, ENET_25MHZ); - if (ret) - return ret; - - /* set gpr1[ENET_CLK_SEL] */ - setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_ENET_CLK_SEL_MASK); - - setup_iomux_enet(); - - bus = fec_get_miibus(IMX_FEC_BASE, -1); - if (!bus) - return -EINVAL; - - phydev = phy_find_by_mask(bus, ETH_PHY_MASK, PHY_INTERFACE_MODE_RGMII); - if (!phydev) { - ret = -EINVAL; - goto free_bus; - } - - debug("using phy at address %d\n", phydev->addr); - ret = fec_probe(bis, -1, IMX_FEC_BASE, bus, phydev); - if (ret) - goto free_phydev; - - return 0; - -free_phydev: - free(phydev); -free_bus: - free(bus); - return ret; -} - #ifdef CONFIG_VIDEO_IPUV3 static void do_enable_hdmi(struct display_info_t const *dev) { @@ -433,6 +316,21 @@ static int setup_display(void) } #endif /* CONFIG_VIDEO_IPUV3 */ +static int setup_fec(void) +{ + struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; + int ret; + + ret = enable_fec_anatop_clock(0, ENET_25MHZ); + if (ret) + return ret; + + /* set gpr1[ENET_CLK_SEL] */ + setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_ENET_CLK_SEL_MASK); + + return 0; +} + int board_early_init_f(void) { setup_iomux_uart(); @@ -440,6 +338,8 @@ int board_early_init_f(void) #ifdef CONFIG_CMD_SATA setup_sata(); #endif + setup_fec(); + return 0; } diff --git a/configs/mx6cuboxi_defconfig b/configs/mx6cuboxi_defconfig index df7e4611a0..568cfce4c0 100644 --- a/configs/mx6cuboxi_defconfig +++ b/configs/mx6cuboxi_defconfig @@ -50,6 +50,9 @@ CONFIG_DM_MMC=y CONFIG_FSL_USDHC=y CONFIG_PHYLIB=y CONFIG_PHY_ATHEROS=y +CONFIG_DM_ETH=y +CONFIG_FEC_MXC=y +CONFIG_RGMII=y CONFIG_MII=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX6=y diff --git a/include/configs/mx6cuboxi.h b/include/configs/mx6cuboxi.h index 2ccf44e573..96f79e6b58 100644 --- a/include/configs/mx6cuboxi.h +++ b/include/configs/mx6cuboxi.h @@ -29,12 +29,6 @@ #define CONFIG_LBA48 #endif -/* Ethernet Configuration */ -#define CONFIG_FEC_MXC -#define IMX_FEC_BASE ENET_BASE_ADDR -#define CONFIG_FEC_XCV_TYPE RGMII -#define CONFIG_FEC_MXC_PHYADDR 0 - /* Framebuffer */ #define CONFIG_VIDEO_BMP_RLE8 #define CONFIG_SPLASH_SCREEN From 64e2793f70c4688977b5e3fa7b503c7f3c7205ac Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Thu, 18 Jun 2020 22:14:42 -0300 Subject: [PATCH 19/79] ARM: dts: imx6qdl-sabreauto: Fix AR8031 phy-mode As per kernel commit 0672d22a1924 ("ARM: dts: imx: Fix the AR803X phy-mode) the correct phy-mode should be "rgmii-id", so fix it accordingly to fix the Ethernet regression. This problem has been exposed by commit: commit 13114f38e2ccea9386726d8b9831dfc310589548 Author: Vladimir Oltean Date: Thu May 7 00:11:51 2020 +0200 phy: atheros: Explicitly disable RGMII delays To eliminate any doubts about the out-of-reset value of the PHY, that the driver previously relied on. If bisecting shows that this commit breaks your board you probably have a wrong PHY interface mode. You probably want the PHY_INTERFACE_MODE_RGMII_RXID or PHY_INTERFACE_MODE_RGMII_ID mode. Signed-off-by: Vladimir Oltean Acked-by: Joe Hershberger Fix the phy-mode accordingly to fix the regression. Signed-off-by: Fabio Estevam --- arch/arm/dts/imx6qdl-sabreauto.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/dts/imx6qdl-sabreauto.dtsi b/arch/arm/dts/imx6qdl-sabreauto.dtsi index a6dc5c42c6..28a7fdb0f1 100644 --- a/arch/arm/dts/imx6qdl-sabreauto.dtsi +++ b/arch/arm/dts/imx6qdl-sabreauto.dtsi @@ -281,7 +281,7 @@ &fec { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_enet>; - phy-mode = "rgmii"; + phy-mode = "rgmii-id"; interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>, <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>; fsl,err006687-workaround-present; From 041dd8e9c4be5bcb49845955e4c472d0c2c46e1e Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Wed, 17 Jun 2020 14:33:16 -0300 Subject: [PATCH 20/79] ARM: dts: imx6qdl-sabresd: Fix AR8031 phy-mode As per kernel commit 0672d22a1924 ("ARM: dts: imx: Fix the AR803X phy-mode) the correct phy-mode should be "rgmii-id", so fix it accordingly to fix the Ethernet regression. This problem has been exposed by commit: commit 13114f38e2ccea9386726d8b9831dfc310589548 Author: Vladimir Oltean Date: Thu May 7 00:11:51 2020 +0200 phy: atheros: Explicitly disable RGMII delays To eliminate any doubts about the out-of-reset value of the PHY, that the driver previously relied on. If bisecting shows that this commit breaks your board you probably have a wrong PHY interface mode. You probably want the PHY_INTERFACE_MODE_RGMII_RXID or PHY_INTERFACE_MODE_RGMII_ID mode. Signed-off-by: Vladimir Oltean Acked-by: Joe Hershberger Signed-off-by: Fabio Estevam --- arch/arm/dts/imx6qdl-sabresd.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/dts/imx6qdl-sabresd.dtsi b/arch/arm/dts/imx6qdl-sabresd.dtsi index 2cd5a9fbac..eddb390174 100644 --- a/arch/arm/dts/imx6qdl-sabresd.dtsi +++ b/arch/arm/dts/imx6qdl-sabresd.dtsi @@ -204,7 +204,7 @@ &fec { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_enet>; - phy-mode = "rgmii"; + phy-mode = "rgmii-id"; phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>; status = "okay"; }; From 4e8aba4dd5823ac5e5a4759aa8ceb4f6ab92fd62 Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Tue, 16 Jun 2020 22:19:59 +0300 Subject: [PATCH 21/79] apalis-imx8: enable of_system_setup Enable CONFIG_OF_SYSTEM_DEFAULT for Apalis iMX8. Signed-off-by: Marcel Ziswiler --- configs/apalis-imx8qm_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/apalis-imx8qm_defconfig b/configs/apalis-imx8qm_defconfig index 4c27c33459..fdc1e4e192 100644 --- a/configs/apalis-imx8qm_defconfig +++ b/configs/apalis-imx8qm_defconfig @@ -9,6 +9,7 @@ CONFIG_TARGET_APALIS_IMX8=y CONFIG_NR_DRAM_BANKS=3 CONFIG_DISTRO_DEFAULTS=y CONFIG_FIT=y +CONFIG_OF_SYSTEM_SETUP=y CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/toradex/apalis-imx8/apalis-imx8qm-imximage.cfg" CONFIG_LOG=y CONFIG_VERSION_VARIABLE=y From 1b25ee978c20844b2334064aba97ee7b6795d997 Mon Sep 17 00:00:00 2001 From: Max Krummenacher Date: Tue, 16 Jun 2020 22:20:00 +0300 Subject: [PATCH 22/79] apalis/colibri-imx8: re-enable CONFIG_IMX_SCU_THERMAL This got dropped by a global 'make savedefconfig' resync as required patches are still in flight. Signed-off-by: Max Krummenacher --- configs/apalis-imx8qm_defconfig | 1 + configs/colibri-imx8qxp_defconfig | 1 + 2 files changed, 2 insertions(+) diff --git a/configs/apalis-imx8qm_defconfig b/configs/apalis-imx8qm_defconfig index fdc1e4e192..289d644edb 100644 --- a/configs/apalis-imx8qm_defconfig +++ b/configs/apalis-imx8qm_defconfig @@ -62,4 +62,5 @@ CONFIG_DM_REGULATOR_GPIO=y CONFIG_DM_SERIAL=y CONFIG_FSL_LPUART=y CONFIG_DM_THERMAL=y +CONFIG_IMX_SCU_THERMAL=y # CONFIG_EFI_LOADER is not set diff --git a/configs/colibri-imx8qxp_defconfig b/configs/colibri-imx8qxp_defconfig index d86cefafc6..57b48e35b4 100644 --- a/configs/colibri-imx8qxp_defconfig +++ b/configs/colibri-imx8qxp_defconfig @@ -59,4 +59,5 @@ CONFIG_DM_REGULATOR_GPIO=y CONFIG_DM_SERIAL=y CONFIG_FSL_LPUART=y CONFIG_DM_THERMAL=y +CONFIG_IMX_SCU_THERMAL=y # CONFIG_EFI_LOADER is not set From 506619da80a61d2b24e5deecce41889af2fe4106 Mon Sep 17 00:00:00 2001 From: Oleksandr Suvorov Date: Tue, 16 Jun 2020 22:20:01 +0300 Subject: [PATCH 23/79] colibri-imx8x: declare consoleargs Store all console-related kernel parameters in dedicated variable. Signed-off-by: Oleksandr Suvorov --- include/configs/colibri-imx8x.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/include/configs/colibri-imx8x.h b/include/configs/colibri-imx8x.h index da9226e2fb..7d007071e5 100644 --- a/include/configs/colibri-imx8x.h +++ b/include/configs/colibri-imx8x.h @@ -62,7 +62,7 @@ #define BOOTENV_RUN_NET_USB_START "" #define CONFIG_MFG_ENV_SETTINGS \ - "mfgtool_args=setenv bootargs console=${console},${baudrate} " \ + "mfgtool_args=setenv bootargs ${consoleargs} " \ "rdinit=/linuxrc g_mass_storage.stall=0 " \ "g_mass_storage.removable=1 g_mass_storage.idVendor=0x066F " \ "g_mass_storage.idProduct=0x37FF " \ @@ -81,7 +81,7 @@ M4_BOOT_ENV \ MEM_LAYOUT_ENV_SETTINGS \ "boot_file=Image\0" \ - "console=ttyLP3 earlycon\0" \ + "consoleargs=console=ttyLP3,${baudrate} earlycon\0" \ "fdt_addr=0x83000000\0" \ "fdt_file=fsl-imx8qxp-colibri-dsihdmi-eval-v3.dtb\0" \ "fdtfile=fsl-imx8qxp-colibri-dsihdmi-eval-v3.dtb\0" \ @@ -89,11 +89,11 @@ "image=Image\0" \ "initrd_addr=0x83800000\0" \ "initrd_high=0xffffffffffffffff\0" \ - "mmcargs=setenv bootargs console=${console},${baudrate} " \ + "mmcargs=setenv bootargs ${consoleargs} " \ "root=PARTUUID=${uuid} rootwait " \ "mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \ "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \ - "netargs=setenv bootargs console=${console},${baudrate} " \ + "netargs=setenv bootargs ${consoleargs} " \ "root=/dev/nfs ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp " \ "${vidargs}\0" \ "nfsboot=run netargs; dhcp ${loadaddr} ${image}; tftp ${fdt_addr} " \ From d3976cc2feddedf4283b9a567c8157e0ccb4226e Mon Sep 17 00:00:00 2001 From: Stefan Agner Date: Tue, 16 Jun 2020 22:20:02 +0300 Subject: [PATCH 24/79] colibri_imx7: add addresses required for distro boot Define addresses required for full distro boot support. Signed-off-by: Stefan Agner --- include/configs/colibri_imx7.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/include/configs/colibri_imx7.h b/include/configs/colibri_imx7.h index 09722f47e7..b550bc6156 100644 --- a/include/configs/colibri_imx7.h +++ b/include/configs/colibri_imx7.h @@ -109,8 +109,9 @@ "bootm_size=0x10000000\0" \ "fdt_addr_r=0x82000000\0" \ "kernel_addr_r=0x81000000\0" \ + "pxefile_addr_r=0x87100000\0" \ "ramdisk_addr_r=0x82100000\0" \ - "scriptaddr=0x82500000\0" + "scriptaddr=0x87000000\0" #define NFS_BOOTCMD \ "nfsargs=ip=:::::eth0: root=/dev/nfs\0" \ From b0a8cefd5b2b5128f8dc406002acd558679fbe5d Mon Sep 17 00:00:00 2001 From: Stefan Agner Date: Tue, 16 Jun 2020 22:20:03 +0300 Subject: [PATCH 25/79] colibri-imx6ull/imx7: define bootubipart for distro boot When using distro boot to boot from UBI volumes the boot partition has been hardcoded to "UBI" (capital letters). However, our default MTD layout uses "ubi" (lower case letter). Define "ubi" as the default UBI partition for distro boot for Toradex. This allows to use distro boot without having to redefine the MTD partition layout which is useful for TorizonCore. Signed-off-by: Stefan Agner --- include/configs/colibri-imx6ull.h | 1 + include/configs/colibri_imx7.h | 1 + 2 files changed, 2 insertions(+) diff --git a/include/configs/colibri-imx6ull.h b/include/configs/colibri-imx6ull.h index 2d3b4c1817..c80fb96fe2 100644 --- a/include/configs/colibri-imx6ull.h +++ b/include/configs/colibri-imx6ull.h @@ -88,6 +88,7 @@ NFS_BOOTCMD \ UBI_BOOTCMD \ UBOOT_UPDATE \ + "bootubipart=ubi\0" \ "console=ttymxc0\0" \ "defargs=user_debug=30\0" \ "dfu_alt_info=" DFU_ALT_NAND_INFO "\0" \ diff --git a/include/configs/colibri_imx7.h b/include/configs/colibri_imx7.h index b550bc6156..b3f660b6fa 100644 --- a/include/configs/colibri_imx7.h +++ b/include/configs/colibri_imx7.h @@ -169,6 +169,7 @@ MODULE_EXTRA_ENV_SETTINGS \ UBOOT_UPDATE \ "boot_file=zImage\0" \ + "bootubipart=ubi\0" \ "console=ttymxc0\0" \ "defargs=\0" \ "fdt_board=eval-v3\0" \ From a0092cf236907e8ced652c9ef1fc5bfa7e6fdee7 Mon Sep 17 00:00:00 2001 From: Max Krummenacher Date: Tue, 16 Jun 2020 22:20:04 +0300 Subject: [PATCH 26/79] colibri_vf_defconfig: enable part cmd This allows to boot from SD/USB with passing the rootfs partition via UUID. Signed-off-by: Max Krummenacher --- configs/colibri_vf_defconfig | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/configs/colibri_vf_defconfig b/configs/colibri_vf_defconfig index c494fb40e9..ed0acbe58e 100644 --- a/configs/colibri_vf_defconfig +++ b/configs/colibri_vf_defconfig @@ -18,8 +18,6 @@ CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_ARCH_MISC_INIT=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_HUSH_PARSER=y -# CONFIG_CMDLINE_EDITING is not set -# CONFIG_AUTO_COMPLETE is not set # CONFIG_SYS_LONGHELP is not set CONFIG_SYS_PROMPT="Colibri VFxx # " # CONFIG_CMD_BOOTD is not set @@ -39,6 +37,7 @@ CONFIG_CMD_GPIO=y # CONFIG_CMD_LOADB is not set # CONFIG_CMD_LOADS is not set CONFIG_CMD_MMC=y +CONFIG_CMD_PART=y CONFIG_CMD_USB=y CONFIG_CMD_USB_MASS_STORAGE=y # CONFIG_CMD_SETEXPR is not set From 1fd988a9fade5ecff8a6841f9f7932cf83ee18cd Mon Sep 17 00:00:00 2001 From: Max Krummenacher Date: Tue, 16 Jun 2020 22:20:05 +0300 Subject: [PATCH 27/79] configs/colibri_vf.h: drop sdboot in favour of distro_bootcmd The distro bootscript uses kernel_image to get the file name of the kernel, so change that variable name. UBI boot has precedence in the default boot command. If one wants to boot from SD with a working NAND installation stop in U-Boot and enter: setenv fdtfile ${soc}-colibri-${fdt_board}.dtb && run distro_bootcmd Signed-off-by: Max Krummenacher --- include/configs/colibri_vf.h | 18 +----------------- 1 file changed, 1 insertion(+), 17 deletions(-) diff --git a/include/configs/colibri_vf.h b/include/configs/colibri_vf.h index 7d17bd8e6a..012350d9bf 100644 --- a/include/configs/colibri_vf.h +++ b/include/configs/colibri_vf.h @@ -69,21 +69,6 @@ "tftp ${fdt_addr_r} ${soc}-colibri-${fdt_board}.dtb && " \ "run fdt_fixup && bootz ${kernel_addr_r} - ${fdt_addr_r}\0" \ -#define SD_BOOTCMD \ - "set_sdargs=setenv sdargs root=PARTUUID=${uuid} ro rootwait\0" \ - "sdboot=run setup; run sdfinduuid; run set_sdargs; " \ - "setenv bootargs ${defargs} ${sdargs} ${mtdparts} " \ - "${setupargs} ${vidargs}; echo Booting from MMC/SD card...; " \ - "load mmc ${sddev}:${sdbootpart} ${kernel_addr_r} ${kernel_file} && " \ - "load mmc ${sddev}:${sdbootpart} ${fdt_addr_r} " \ - "${soc}-colibri-${fdt_board}.dtb && " \ - "run fdt_fixup && bootz ${kernel_addr_r} - ${fdt_addr_r}\0" \ - "sdbootpart=1\0" \ - "sddev=0\0" \ - "sdfinduuid=part uuid mmc ${sddev}:${sdrootpart} uuid\0" \ - "sdrootpart=2\0" - - #define UBI_BOOTCMD \ "ubiargs=ubi.mtd=ubi root=ubi0:rootfs rootfstype=ubifs " \ "ubi.fm_autoconvert=1\0" \ @@ -112,7 +97,6 @@ BOOTENV \ MEM_LAYOUT_ENV_SETTINGS \ NFS_BOOTCMD \ - SD_BOOTCMD \ UBI_BOOTCMD \ UBOOT_UPDATE \ "console=ttyLP0\0" \ @@ -120,7 +104,7 @@ "dfu_alt_info=" DFU_ALT_NAND_INFO "\0" \ "fdt_board=eval-v3\0" \ "fdt_fixup=;\0" \ - "kernel_file=zImage\0" \ + "kernel_image=zImage\0" \ "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ "setsdupdate=mmc rescan && set interface mmc && " \ "fatload ${interface} 0:1 ${loadaddr} flash_blk.img && " \ From adff136c28704ca0d13194e139a39f0ac45721ad Mon Sep 17 00:00:00 2001 From: Igor Opaniuk Date: Tue, 16 Jun 2020 22:20:06 +0300 Subject: [PATCH 28/79] apalis-tk1: enable distroboot 1. Use distro_bootcmd as default boot command instead of legacy emmcboot wrapper. 2. Drop emmcboot and sdboot wrappers. 3. Provide proper boot order for Distro Boot. Signed-off-by: Igor Opaniuk --- configs/apalis-tk1_defconfig | 2 +- include/configs/apalis-tk1.h | 51 ++++++++++-------------------------- 2 files changed, 15 insertions(+), 38 deletions(-) diff --git a/configs/apalis-tk1_defconfig b/configs/apalis-tk1_defconfig index 868303a29c..db66d68f63 100644 --- a/configs/apalis-tk1_defconfig +++ b/configs/apalis-tk1_defconfig @@ -11,7 +11,7 @@ CONFIG_SPL_TEXT_BASE=0x80108000 CONFIG_FIT=y CONFIG_OF_SYSTEM_SETUP=y CONFIG_BOOTDELAY=1 -CONFIG_BOOTCOMMAND="run emmcboot; setenv fdtfile ${soc}-${fdt-module}-${fdt_board}.dtb && run distro_bootcmd" +CONFIG_BOOTCOMMAND="setenv fdtfile ${soc}-${fdt-module}-${fdt_board}.dtb && run distro_bootcmd" CONFIG_CONSOLE_MUX=y CONFIG_SYS_STDIO_DEREGISTER=y CONFIG_VERSION_VARIABLE=y diff --git a/include/configs/apalis-tk1.h b/include/configs/apalis-tk1.h index 965259c5e1..6f73606427 100644 --- a/include/configs/apalis-tk1.h +++ b/include/configs/apalis-tk1.h @@ -34,6 +34,20 @@ /* General networking support */ #define CONFIG_TFTP_TSIZE +/* + * Custom Distro Boot configuration: + * 1. 8bit SD port (MMC1) + * 2. 4bit SD port (MMC2) + * 3. eMMC (MMC0) + */ +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 1) \ + func(MMC, mmc, 2) \ + func(MMC, mmc, 0) \ + func(USB, usb, 0) \ + func(PXE, pxe, na) \ + func(DHCP, dhcp, na) + #undef CONFIG_IPADDR #define CONFIG_IPADDR 192.168.10.2 #define CONFIG_NETMASK 255.255.255.0 @@ -54,24 +68,6 @@ "update_uboot=run set_blkcnt && mmc dev 0 ${uboot_hwpart} && " \ "mmc write ${loadaddr} ${uboot_blk} ${blkcnt}\0" \ -#define EMMC_BOOTCMD \ - "set_emmcargs=setenv emmcargs ip=off root=PARTUUID=${uuid} " \ - "ro rootfstype=ext4 rootwait\0" \ - "emmcboot=run setup; run emmcfinduuid; run set_emmcargs; " \ - "setenv bootargs ${defargs} ${emmcargs} " \ - "${setupargs} ${vidargs}; echo Booting from internal eMMC; " \ - "run emmcdtbload; " \ - "load mmc ${emmcdev}:${emmcbootpart} ${kernel_addr_r} " \ - "${boot_file} && run fdt_fixup && " \ - "bootz ${kernel_addr_r} - ${dtbparam}\0" \ - "emmcbootpart=1\0" \ - "emmcdev=0\0" \ - "emmcdtbload=setenv dtbparam; load mmc ${emmcdev}:${emmcbootpart} " \ - "${fdt_addr_r} ${soc}-${fdt_module}-${fdt_board}.dtb && " \ - "setenv dtbparam ${fdt_addr_r}\0" \ - "emmcfinduuid=part uuid mmc ${mmcdev}:${emmcrootpart} uuid\0" \ - "emmcrootpart=2\0" - #define NFS_BOOTCMD \ "nfsargs=ip=:::::eth0:on root=/dev/nfs rw\0" \ "nfsboot=pci enum; run setup; setenv bootargs ${defargs} ${nfsargs} " \ @@ -82,23 +78,6 @@ "${soc}-${fdt_module}-${fdt_board}.dtb " \ "&& setenv dtbparam ${fdt_addr_r}\0" -#define SD_BOOTCMD \ - "set_sdargs=setenv sdargs ip=off root=PARTUUID=${uuid} ro " \ - "rootfstype=ext4 rootwait\0" \ - "sdboot=run setup; run sdfinduuid; run set_sdargs; " \ - "setenv bootargs ${defargs} ${sdargs} ${setupargs} " \ - "${vidargs}; echo Booting from SD card in 8bit slot...; " \ - "run sddtbload; load mmc ${sddev}:${sdbootpart} " \ - "${kernel_addr_r} ${boot_file} && run fdt_fixup && " \ - "bootz ${kernel_addr_r} - ${dtbparam}\0" \ - "sdbootpart=1\0" \ - "sddev=1\0" \ - "sddtbload=setenv dtbparam; load mmc ${sddev}:${sdbootpart} " \ - "${fdt_addr_r} ${soc}-${fdt_module}-${fdt_board}.dtb " \ - "&& setenv dtbparam ${fdt_addr_r}\0" \ - "sdfinduuid=part uuid mmc ${sddev}:${sdrootpart} uuid\0" \ - "sdrootpart=2\0" - #define BOARD_EXTRA_ENV_SETTINGS \ "boot_file=zImage\0" \ "console=ttyS0\0" \ @@ -106,12 +85,10 @@ "usb_port_owner_info=2 lane_owner_info=6 emc_max_dvfs=0 " \ "user_debug=30 pcie_aspm=off\0" \ "dfu_alt_info=" DFU_ALT_EMMC_INFO "\0" \ - EMMC_BOOTCMD \ "fdt_board=eval\0" \ "fdt_fixup=;\0" \ "fdt_module=" FDT_MODULE "\0" \ NFS_BOOTCMD \ - SD_BOOTCMD \ UBOOT_UPDATE \ "setethupdate=if env exists ethaddr; then; else setenv ethaddr " \ "00:14:2d:00:00:00; fi; pci enum && tftpboot ${loadaddr} " \ From 670795a38dd71c9eb3c293edd39cc2bdc1304b98 Mon Sep 17 00:00:00 2001 From: Igor Opaniuk Date: Tue, 16 Jun 2020 22:20:07 +0300 Subject: [PATCH 29/79] apalis-tk1: fix setting fdtfile value s/fdt-module/fdt_module/g, as we don't use dash in fdt_file anymore. Fixes: 4c63a601("apalis-tk1: support v1.2 hardware revision") Signed-off-by: Igor Opaniuk --- configs/apalis-tk1_defconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/configs/apalis-tk1_defconfig b/configs/apalis-tk1_defconfig index db66d68f63..42e320e2e3 100644 --- a/configs/apalis-tk1_defconfig +++ b/configs/apalis-tk1_defconfig @@ -11,7 +11,7 @@ CONFIG_SPL_TEXT_BASE=0x80108000 CONFIG_FIT=y CONFIG_OF_SYSTEM_SETUP=y CONFIG_BOOTDELAY=1 -CONFIG_BOOTCOMMAND="setenv fdtfile ${soc}-${fdt-module}-${fdt_board}.dtb && run distro_bootcmd" +CONFIG_BOOTCOMMAND="setenv fdtfile ${soc}-${fdt_module}-${fdt_board}.dtb && run distro_bootcmd" CONFIG_CONSOLE_MUX=y CONFIG_SYS_STDIO_DEREGISTER=y CONFIG_VERSION_VARIABLE=y From 1cfe8d6b309d2458f2daa25eee67293f6ac58c36 Mon Sep 17 00:00:00 2001 From: Igor Opaniuk Date: Tue, 16 Jun 2020 22:20:08 +0300 Subject: [PATCH 30/79] toradex: imx: enable BOOTCOUNT feature This introduces automatic boot counter that increases after every reset.After a power-on reset, it will be initialized with 1, and each reboot will increment the value by 1. By default it's disabled if bootlimit isn't set. To enable this feature you have set bootcount limit ("bootlimit"), alternate boot action ("altbootcmd") that will be performed if the new value of bootcount exceeds the value of bootlimit, and "upgrade_available" to let U-Boot automatically increase and save the counter value after every reset: > setenv bootlimit 5 > setenv upgrade_available 1 > setenv altbootcmd "bootm ..." In case the bootlimit exceeds, the message will be shown and albootcmd executed: Warning: Bootlimit (5) exceeded. Using altbootcmd. To reset bootcount run: > bootcount reset Print current value: > bootcount print Signed-off-by: Igor Opaniuk --- configs/apalis_imx6_defconfig | 3 +++ configs/colibri-imx6ull_defconfig | 3 +++ configs/colibri_imx6_defconfig | 3 +++ configs/colibri_imx7_defconfig | 3 +++ configs/colibri_imx7_emmc_defconfig | 3 +++ 5 files changed, 15 insertions(+) diff --git a/configs/apalis_imx6_defconfig b/configs/apalis_imx6_defconfig index 6b0f0e4638..65162a26f6 100644 --- a/configs/apalis_imx6_defconfig +++ b/configs/apalis_imx6_defconfig @@ -53,6 +53,7 @@ CONFIG_CMD_USB_SDP=y CONFIG_CMD_USB_MASS_STORAGE=y # CONFIG_CMD_NFS is not set CONFIG_CMD_BMP=y +CONFIG_CMD_BOOTCOUNT=y CONFIG_CMD_CACHE=y CONFIG_CMD_TIME=y CONFIG_CMD_PMIC=y @@ -65,6 +66,8 @@ CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_IP_DEFRAG=y CONFIG_TFTP_BLOCKSIZE=4096 CONFIG_DWC_AHSATA=y +CONFIG_BOOTCOUNT_LIMIT=y +CONFIG_BOOTCOUNT_ENV=y CONFIG_DM_I2C=y CONFIG_DM_MMC=y CONFIG_SUPPORT_EMMC_BOOT=y diff --git a/configs/colibri-imx6ull_defconfig b/configs/colibri-imx6ull_defconfig index 74a67a0200..ce145cd24f 100644 --- a/configs/colibri-imx6ull_defconfig +++ b/configs/colibri-imx6ull_defconfig @@ -40,6 +40,7 @@ CONFIG_CMD_USB=y CONFIG_CMD_USB_SDP=y CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_CMD_BMP=y +CONFIG_CMD_BOOTCOUNT=y CONFIG_CMD_CACHE=y CONFIG_CMD_REGULATOR=y CONFIG_CMD_MTDPARTS=y @@ -54,6 +55,8 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_IP_DEFRAG=y CONFIG_TFTP_BLOCKSIZE=16352 +CONFIG_BOOTCOUNT_LIMIT=y +CONFIG_BOOTCOUNT_ENV=y CONFIG_DFU_NAND=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_MXC=y diff --git a/configs/colibri_imx6_defconfig b/configs/colibri_imx6_defconfig index 44a3ff859c..ca33327c6b 100644 --- a/configs/colibri_imx6_defconfig +++ b/configs/colibri_imx6_defconfig @@ -52,6 +52,7 @@ CONFIG_CMD_USB_SDP=y CONFIG_CMD_USB_MASS_STORAGE=y # CONFIG_CMD_NFS is not set CONFIG_CMD_BMP=y +CONFIG_CMD_BOOTCOUNT=y CONFIG_CMD_CACHE=y CONFIG_CMD_TIME=y CONFIG_CMD_UUID=y @@ -64,6 +65,8 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_IP_DEFRAG=y CONFIG_TFTP_BLOCKSIZE=16352 +CONFIG_BOOTCOUNT_LIMIT=y +CONFIG_BOOTCOUNT_ENV=y CONFIG_DM_I2C=y CONFIG_DM_MMC=y CONFIG_SUPPORT_EMMC_BOOT=y diff --git a/configs/colibri_imx7_defconfig b/configs/colibri_imx7_defconfig index 7596478ee3..89ee6e5a07 100644 --- a/configs/colibri_imx7_defconfig +++ b/configs/colibri_imx7_defconfig @@ -40,6 +40,7 @@ CONFIG_CMD_USB=y CONFIG_CMD_USB_MASS_STORAGE=y # CONFIG_BOOTP_PXE is not set CONFIG_CMD_BMP=y +CONFIG_CMD_BOOTCOUNT=y CONFIG_CMD_CACHE=y # CONFIG_CMD_HASH is not set CONFIG_CMD_MTDPARTS=y @@ -54,6 +55,8 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_IP_DEFRAG=y CONFIG_TFTP_BLOCKSIZE=16352 +CONFIG_BOOTCOUNT_LIMIT=y +CONFIG_BOOTCOUNT_ENV=y CONFIG_FSL_CAAM=y CONFIG_DFU_NAND=y CONFIG_DM_I2C=y diff --git a/configs/colibri_imx7_emmc_defconfig b/configs/colibri_imx7_emmc_defconfig index c23ff97daa..13a3aae9a7 100644 --- a/configs/colibri_imx7_emmc_defconfig +++ b/configs/colibri_imx7_emmc_defconfig @@ -38,6 +38,7 @@ CONFIG_CMD_MMC=y CONFIG_CMD_USB=y CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_CMD_BMP=y +CONFIG_CMD_BOOTCOUNT=y CONFIG_CMD_CACHE=y # CONFIG_CMD_HASH is not set # CONFIG_ISO_PARTITION is not set @@ -48,6 +49,8 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_IP_DEFRAG=y CONFIG_TFTP_BLOCKSIZE=16352 +CONFIG_BOOTCOUNT_LIMIT=y +CONFIG_BOOTCOUNT_ENV=y CONFIG_FSL_CAAM=y CONFIG_USB_FUNCTION_FASTBOOT=y CONFIG_FASTBOOT_BUF_ADDR=0x82000000 From 8b9c0cb464717581d8d33e5b0c25b95ce846da8e Mon Sep 17 00:00:00 2001 From: Igor Opaniuk Date: Tue, 16 Jun 2020 22:20:09 +0300 Subject: [PATCH 31/79] apalis_imx6: boot env configuration updates 1. Drop legacy emmcboot wrapper from env. 2. Change the "boot try" order. Default one is: SD -> eMMC -> USB -> DHCP 3. Drop DFU defines Signed-off-by: Igor Opaniuk --- include/configs/apalis_imx6.h | 29 +---------------------------- 1 file changed, 1 insertion(+), 28 deletions(-) diff --git a/include/configs/apalis_imx6.h b/include/configs/apalis_imx6.h index 6fc7c3982c..38d0a6e2e9 100644 --- a/include/configs/apalis_imx6.h +++ b/include/configs/apalis_imx6.h @@ -93,9 +93,9 @@ #ifndef CONFIG_SPL_BUILD #define BOOT_TARGET_DEVICES(func) \ - func(MMC, mmc, 0) \ func(MMC, mmc, 1) \ func(MMC, mmc, 2) \ + func(MMC, mmc, 0) \ func(USB, usb, 0) \ func(DHCP, dhcp, na) #include @@ -105,14 +105,6 @@ #define BOOTENV #endif /* CONFIG_SPL_BUILD */ -#define DFU_ALT_EMMC_INFO \ - "u-boot.imx raw 0x2 0x3ff mmcpart 0;" \ - "boot part 0 1;" \ - "rootfs part 0 2;" \ - "zImage fat 0 1;" \ - "imx6q-apalis-eval.dtb fat 0 1;" \ - "imx6q-apalis-cam-eval.dtb fat 0 1" - #define UBOOT_UPDATE \ "uboot_hwpart=1\0" \ "uboot_blk=8a\0" \ @@ -124,23 +116,6 @@ "update_spl=run set_blkcnt && mmc dev 0 ${uboot_hwpart} && " \ "mmc write ${loadaddr} ${uboot_spl_blk} ${blkcnt}\0" -#define EMMC_BOOTCMD \ - "set_emmcargs=setenv emmcargs ip=off root=PARTUUID=${uuid} " \ - "ro,noatime rootfstype=ext4 rootwait\0" \ - "emmcboot=run setup; run emmcfinduuid; run set_emmcargs; " \ - "setenv bootargs ${defargs} ${emmcargs} ${setupargs} " \ - "${vidargs}; echo Booting from internal eMMC chip...; " \ - "run emmcdtbload; load mmc ${emmcdev}:${emmcbootpart} " \ - "${kernel_addr_r} ${boot_file} && run fdt_fixup && " \ - "bootz ${kernel_addr_r} ${dtbparam}\0" \ - "emmcbootpart=1\0" \ - "emmcdev=0\0" \ - "emmcdtbload=setenv dtbparam; load mmc ${emmcdev}:${emmcbootpart} " \ - "${fdt_addr_r} ${fdt_file} && " \ - "setenv dtbparam \" - ${fdt_addr_r}\" && true\0" \ - "emmcfinduuid=part uuid mmc ${mmcdev}:${emmcrootpart} uuid\0" \ - "emmcrootpart=2\0" - #define MEM_LAYOUT_ENV_SETTINGS \ "bootm_size=0x20000000\0" \ "fdt_addr_r=0x12100000\0" \ @@ -174,8 +149,6 @@ "boot_file=zImage\0" \ "console=ttymxc0\0" \ "defargs=enable_wait_mode=off vmalloc=400M\0" \ - "dfu_alt_info=" DFU_ALT_EMMC_INFO "\0" \ - EMMC_BOOTCMD \ "fdt_file=" FDT_FILE "\0" \ "fdt_fixup=;\0" \ MEM_LAYOUT_ENV_SETTINGS \ From a17930a36c92ad2adc06b583ccd9b7af6c626432 Mon Sep 17 00:00:00 2001 From: Igor Opaniuk Date: Tue, 16 Jun 2020 22:20:10 +0300 Subject: [PATCH 32/79] colibri_imx7: boot env configuration updates 1. Drop legacy emmcboot wrapper from env. 2. Change the "boot try" order. Default one is: SD -> eMMC -> USB -> DHCP 3. Drop DFU defines Signed-off-by: Igor Opaniuk --- include/configs/colibri_imx7.h | 24 +----------------------- 1 file changed, 1 insertion(+), 23 deletions(-) diff --git a/include/configs/colibri_imx7.h b/include/configs/colibri_imx7.h index b3f660b6fa..1afa9373a1 100644 --- a/include/configs/colibri_imx7.h +++ b/include/configs/colibri_imx7.h @@ -88,23 +88,6 @@ "mmc read ${android_fdt_addr} ${env_start} ${env_size}; " \ "bootm ${loadaddr} ${loadaddr} ${android_fdt_addr}\0 " -#define EMMC_BOOTCMD \ - "set_emmcargs=setenv emmcargs ip=off root=PARTUUID=${uuid} ro " \ - "rootfstype=ext4 rootwait\0" \ - "emmcboot=run setup; run emmcfinduuid; run set_emmcargs; " \ - "setenv bootargs ${defargs} ${emmcargs} ${setupargs} " \ - "${vidargs}; echo Booting from internal eMMC chip...; " \ - "run m4boot && " \ - "load mmc ${emmcdev}:${emmcbootpart} ${fdt_addr_r} " \ - "${soc}-colibri-emmc-${fdt_board}.dtb && " \ - "load mmc ${emmcdev}:${emmcbootpart} ${kernel_addr_r} " \ - "${boot_file} && run fdt_fixup && " \ - "bootz ${kernel_addr_r} - ${fdt_addr_r}\0" \ - "emmcbootpart=1\0" \ - "emmcdev=0\0" \ - "emmcfinduuid=part uuid mmc ${emmcdev}:${emmcrootpart} uuid\0" \ - "emmcrootpart=2\0" - #define MEM_LAYOUT_ENV_SETTINGS \ "bootm_size=0x10000000\0" \ "fdt_addr_r=0x82000000\0" \ @@ -144,7 +127,6 @@ "setenv fdtfile ${soc}-colibri-emmc-${fdt_board}.dtb && run distro_bootcmd;" #define MODULE_EXTRA_ENV_SETTINGS \ "variant=-emmc\0" \ - EMMC_BOOTCMD \ EMMC_ANDROID_BOOTCMD #endif @@ -155,8 +137,8 @@ func(DHCP, dhcp, na) #elif defined(CONFIG_TARGET_COLIBRI_IMX7_EMMC) #define BOOT_TARGET_DEVICES(func) \ - func(MMC, mmc, 0) \ func(MMC, mmc, 1) \ + func(MMC, mmc, 0) \ func(USB, usb, 0) \ func(DHCP, dhcp, na) #endif @@ -239,10 +221,6 @@ #define CONFIG_USBD_HS -/* USB Device Firmware Update support */ -#define CONFIG_SYS_DFU_DATA_BUF_SIZE SZ_16M -#define DFU_DEFAULT_POLL_TIMEOUT 300 - #if defined(CONFIG_VIDEO) || defined(CONFIG_DM_VIDEO) #define CONFIG_VIDEO_MXS #define CONFIG_VIDEO_LOGO From 0e15165bc4e03e48937baf63303b8812f5cdf6ca Mon Sep 17 00:00:00 2001 From: Igor Opaniuk Date: Tue, 16 Jun 2020 22:20:11 +0300 Subject: [PATCH 33/79] colibri_imx6: boot env configuration updates 1. Drop legacy emmcboot wrapper from env. 2. Change the "boot try" order. Default one is: SD -> eMMC -> USB -> DHCP 3. Drop DFU defines Signed-off-by: Igor Opaniuk --- include/configs/colibri_imx6.h | 29 +---------------------------- 1 file changed, 1 insertion(+), 28 deletions(-) diff --git a/include/configs/colibri_imx6.h b/include/configs/colibri_imx6.h index 0a52a701c6..f5f86f083c 100644 --- a/include/configs/colibri_imx6.h +++ b/include/configs/colibri_imx6.h @@ -83,6 +83,7 @@ #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 0) \ func(MMC, mmc, 1) \ + func(MMC, mmc, 0) \ func(USB, usb, 0) \ func(DHCP, dhcp, na) #include @@ -92,14 +93,6 @@ #define BOOTENV #endif /* CONFIG_SPL_BUILD */ -#define DFU_ALT_EMMC_INFO \ - "u-boot.imx raw 0x2 0x3ff mmcpart 0;" \ - "boot part 0 1;" \ - "rootfs part 0 2;" \ - "zImage fat 0 1;" \ - "imx6dl-colibri-eval-v3.dtb fat 0 1;" \ - "imx6dl-colibri-cam-eval-v3.dtb fat 0 1" - #define UBOOT_UPDATE \ "uboot_hwpart=1\0" \ "uboot_blk=8a\0" \ @@ -111,24 +104,6 @@ "update_spl=run set_blkcnt && mmc dev 0 ${uboot_hwpart} && " \ "mmc write ${loadaddr} ${uboot_spl_blk} ${blkcnt}\0" -#define EMMC_BOOTCMD \ - "set_emmcargs=setenv emmcargs ip=off root=PARTUUID=${uuid} "\ - "rw,noatime rootfstype=ext4 " \ - "rootwait\0" \ - "emmcboot=run setup; run emmcfinduuid; run set_emmcargs; " \ - "setenv bootargs ${defargs} ${emmcargs} ${setupargs} " \ - "${vidargs}; echo Booting from internal eMMC chip...; " \ - "run emmcdtbload; load mmc ${emmcdev}:${emmcbootpart} " \ - "${kernel_addr_r} ${boot_file} && run fdt_fixup && " \ - "bootz ${kernel_addr_r} ${dtbparam}\0" \ - "emmcbootpart=1\0" \ - "emmcdev=0\0" \ - "emmcdtbload=setenv dtbparam; load mmc ${emmcdev}:${emmcbootpart} " \ - "${fdt_addr_r} ${fdt_file} && " \ - "setenv dtbparam \" - ${fdt_addr_r}\" && true\0" \ - "emmcfinduuid=part uuid mmc ${mmcdev}:${emmcrootpart} uuid\0" \ - "emmcrootpart=2\0" - #define MEM_LAYOUT_ENV_SETTINGS \ "bootm_size=0x10000000\0" \ "fdt_addr_r=0x12100000\0" \ @@ -157,8 +132,6 @@ "boot_file=zImage\0" \ "console=ttymxc0\0" \ "defargs=enable_wait_mode=off galcore.contiguousSize=50331648\0" \ - "dfu_alt_info=" DFU_ALT_EMMC_INFO "\0" \ - EMMC_BOOTCMD \ "fdt_file=" FDT_FILE "\0" \ "fdt_fixup=;\0" \ MEM_LAYOUT_ENV_SETTINGS \ From f7ac30b042dc9c9383e102fb54431c664c281d0d Mon Sep 17 00:00:00 2001 From: Martyn Welch Date: Thu, 11 Jun 2020 18:53:50 +0100 Subject: [PATCH 34/79] Fix MMC access on Sabrelite It appears that MMC access on the Sabrelite has been broken since cdcaee9518: Loading Environment from MMC... Card did not respond to voltage select! *** Warning - No block device, using default environment Remove the board_mmc_init() and related entries now that we should be using DM_MMC, add PINCTRL so that things work as expected. Signed-off-by: Martyn Welch Reviewed-by: Jaehoon Chung Reviewed-by: Fabio Estevam Tested-by: Troy Kisky Acked-by: Troy Kisky --- board/boundary/nitrogen6x/nitrogen6x.c | 72 -------------------------- configs/mx6qsabrelite_defconfig | 3 ++ 2 files changed, 3 insertions(+), 72 deletions(-) diff --git a/board/boundary/nitrogen6x/nitrogen6x.c b/board/boundary/nitrogen6x/nitrogen6x.c index d49725daa8..b3b121bad8 100644 --- a/board/boundary/nitrogen6x/nitrogen6x.c +++ b/board/boundary/nitrogen6x/nitrogen6x.c @@ -25,7 +25,6 @@ #include #include #include -#include #include #include #include @@ -161,26 +160,6 @@ static iomux_v3_cfg_t const usdhc2_pads[] = { IOMUX_PAD_CTRL(SD2_DAT3__SD2_DATA3, USDHC_PAD_CTRL), }; -static iomux_v3_cfg_t const usdhc3_pads[] = { - IOMUX_PAD_CTRL(SD3_CLK__SD3_CLK, USDHC_PAD_CTRL), - IOMUX_PAD_CTRL(SD3_CMD__SD3_CMD, USDHC_PAD_CTRL), - IOMUX_PAD_CTRL(SD3_DAT0__SD3_DATA0, USDHC_PAD_CTRL), - IOMUX_PAD_CTRL(SD3_DAT1__SD3_DATA1, USDHC_PAD_CTRL), - IOMUX_PAD_CTRL(SD3_DAT2__SD3_DATA2, USDHC_PAD_CTRL), - IOMUX_PAD_CTRL(SD3_DAT3__SD3_DATA3, USDHC_PAD_CTRL), - IOMUX_PAD_CTRL(SD3_DAT5__GPIO7_IO00, NO_PAD_CTRL), /* CD */ -}; - -static iomux_v3_cfg_t const usdhc4_pads[] = { - IOMUX_PAD_CTRL(SD4_CLK__SD4_CLK, USDHC_PAD_CTRL), - IOMUX_PAD_CTRL(SD4_CMD__SD4_CMD, USDHC_PAD_CTRL), - IOMUX_PAD_CTRL(SD4_DAT0__SD4_DATA0, USDHC_PAD_CTRL), - IOMUX_PAD_CTRL(SD4_DAT1__SD4_DATA1, USDHC_PAD_CTRL), - IOMUX_PAD_CTRL(SD4_DAT2__SD4_DATA2, USDHC_PAD_CTRL), - IOMUX_PAD_CTRL(SD4_DAT3__SD4_DATA3, USDHC_PAD_CTRL), - IOMUX_PAD_CTRL(NANDF_D6__GPIO2_IO06, NO_PAD_CTRL), /* CD */ -}; - static iomux_v3_cfg_t const enet_pads1[] = { IOMUX_PAD_CTRL(ENET_MDIO__ENET_MDIO, ENET_PAD_CTRL), IOMUX_PAD_CTRL(ENET_MDC__ENET_MDC, ENET_PAD_CTRL), @@ -305,57 +284,6 @@ int board_ehci_power(int port, int on) #endif -#ifdef CONFIG_FSL_ESDHC_IMX -static struct fsl_esdhc_cfg usdhc_cfg[2] = { - {USDHC3_BASE_ADDR}, - {USDHC4_BASE_ADDR}, -}; - -int board_mmc_getcd(struct mmc *mmc) -{ - struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; - int gp_cd = (cfg->esdhc_base == USDHC3_BASE_ADDR) ? IMX_GPIO_NR(7, 0) : - IMX_GPIO_NR(2, 6); - - gpio_direction_input(gp_cd); - return !gpio_get_value(gp_cd); -} - -int board_mmc_init(bd_t *bis) -{ - int ret; - u32 index = 0; - - usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); - usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); - - usdhc_cfg[0].max_bus_width = 4; - usdhc_cfg[1].max_bus_width = 4; - - for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) { - switch (index) { - case 0: - SETUP_IOMUX_PADS(usdhc3_pads); - break; - case 1: - SETUP_IOMUX_PADS(usdhc4_pads); - break; - default: - printf("Warning: you configured more USDHC controllers" - "(%d) then supported by the board (%d)\n", - index + 1, CONFIG_SYS_FSL_USDHC_NUM); - return -EINVAL; - } - - ret = fsl_esdhc_initialize(bis, &usdhc_cfg[index]); - if (ret) - return ret; - } - - return 0; -} -#endif - #ifdef CONFIG_MXC_SPI int board_spi_cs_gpio(unsigned bus, unsigned cs) { diff --git a/configs/mx6qsabrelite_defconfig b/configs/mx6qsabrelite_defconfig index ea338c1b53..39b0ef7a42 100644 --- a/configs/mx6qsabrelite_defconfig +++ b/configs/mx6qsabrelite_defconfig @@ -28,6 +28,7 @@ CONFIG_CMD_GPT=y # CONFIG_RANDOM_UUID is not set CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y +# CONFIG_CMD_PINMUX is not set CONFIG_CMD_SATA=y CONFIG_CMD_USB=y CONFIG_CMD_USB_MASS_STORAGE=y @@ -55,6 +56,8 @@ CONFIG_PHYLIB=y CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_MXC_SPI=y From a1f79c2170ba425972d626cc6351bcdef2ca9d08 Mon Sep 17 00:00:00 2001 From: Heinrich Schuchardt Date: Mon, 8 Jun 2020 01:43:47 +0200 Subject: [PATCH 35/79] arm: wandboard: move CONFIG_MXC_UART to defconfig For using a debug UART on the Wandboard CONFIG_MXC_UART=y must be set in the .config file. To avoid duplicate definitions move the setting from include/configs/wandboard.h to configs/wandboard_defconfig. Document the debug UART settings in the README. Signed-off-by: Heinrich Schuchardt Reviewed-by: Fabio Estevam --- board/wandboard/README | 10 ++++++++++ configs/wandboard_defconfig | 1 + include/configs/wandboard.h | 1 - 3 files changed, 11 insertions(+), 1 deletion(-) diff --git a/board/wandboard/README b/board/wandboard/README index f84f205337..2d514a7214 100644 --- a/board/wandboard/README +++ b/board/wandboard/README @@ -37,3 +37,13 @@ as the mx6 processor) - Connect the serial cable to the host PC - Power up the board and U-Boot messages will appear in the serial console. + +Debug UART +---------- + +The following settings provide a debug UART for the Wandboard: + +CONFIG_DEBUG_UART=y +CONFIG_DEBUG_UART_MXC=y +CONFIG_DEBUG_UART_BASE=0x02020000 +CONFIG_DEBUG_UART_CLOCK=80000000 diff --git a/configs/wandboard_defconfig b/configs/wandboard_defconfig index 733b4e82ed..8febe56f2e 100644 --- a/configs/wandboard_defconfig +++ b/configs/wandboard_defconfig @@ -67,6 +67,7 @@ CONFIG_PINCTRL_IMX6=y CONFIG_DM_PMIC=y CONFIG_DM_PMIC_PFUZE100=y CONFIG_DM_SCSI=y +CONFIG_MXC_UART=y CONFIG_DM_THERMAL=y CONFIG_USB=y CONFIG_DM_USB=y diff --git a/include/configs/wandboard.h b/include/configs/wandboard.h index 2b0576e1e6..c798ca64bf 100644 --- a/include/configs/wandboard.h +++ b/include/configs/wandboard.h @@ -17,7 +17,6 @@ /* Size of malloc() pool */ #define CONFIG_SYS_MALLOC_LEN (10 * SZ_1M) -#define CONFIG_MXC_UART #define CONFIG_MXC_UART_BASE UART1_BASE /* SATA Configs */ From ba78c25afe96e4038849e9716e41261b9e114ab6 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Thu, 14 May 2020 18:49:10 +0200 Subject: [PATCH 36/79] ARM: imx6: Fetch MAC address in board_init_late() on DH iMX6 PDK2 This is needed to obtain the MAC from EEPROM/OTP only after the final env is populated, otherwise the ethaddr might be overriden. Signed-off-by: Marek Vasut Cc: Claudius Heine Cc: Harald Seiler Cc: Ludwig Zenz Cc: Stefano Babic --- board/dhelectronics/dh_imx6/dh_imx6.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/board/dhelectronics/dh_imx6/dh_imx6.c b/board/dhelectronics/dh_imx6/dh_imx6.c index 8f50433f17..9937d6b010 100644 --- a/board/dhelectronics/dh_imx6/dh_imx6.c +++ b/board/dhelectronics/dh_imx6/dh_imx6.c @@ -142,8 +142,6 @@ int board_init(void) /* Enable eim_slow clocks */ setbits_le32(&mxc_ccm->CCGR6, 0x1 << MXC_CCM_CCGR6_EMI_SLOW_OFFSET); - setup_dhcom_mac_from_fuse(); - setup_fec_clock(); return 0; @@ -189,6 +187,8 @@ int board_late_init(void) u32 hw_code; char buf[16]; + setup_dhcom_mac_from_fuse(); + hw_code = board_get_hwcode(); switch (get_cpu_type()) { From fb0b862e81afd60ee788ac4c8edfddf034d6dd47 Mon Sep 17 00:00:00 2001 From: Oliver Graute Date: Wed, 20 May 2020 13:47:06 +0200 Subject: [PATCH 37/79] imx: imx8qm_rom7720_a1: update README Update README to extract firmware from scripts Signed-off-by: Oliver Graute --- board/advantech/imx8qm_rom7720_a1/README | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/board/advantech/imx8qm_rom7720_a1/README b/board/advantech/imx8qm_rom7720_a1/README index bff5712589..585fde440d 100644 --- a/board/advantech/imx8qm_rom7720_a1/README +++ b/board/advantech/imx8qm_rom7720_a1/README @@ -29,6 +29,17 @@ $ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.0.bin $ chmod +x firmware-imx-8.0.bin $ ./firmware-imx-8.0.bin +Or use this to avoid running random scripts from the internet, +but note that you must agree to the license the script displays: + +$ dd if=imx-sc-firmware-1.1.bin of=imx-sc-firmware-1.1.tar.bz2 bs=37185 skip=1 +$ tar -xf imx-sc-firmware-1.1.tar.bz2 +$ cp imx-sc-firmware-1.1/mx8qm-val-scfw-tcm.bin $(builddir) + +$ dd if=firmware-imx-8.0.bin of=firmware-imx-8.0.tar.bz2 bs=37180 skip=1 +$ tar -xf firmware-imx-8.0.tar.bz2 +$ cp firmware-imx-8.0/firmware/seco/mx8qm-ahab-container.img $(builddir) + Build U-Boot ============ From cb82ee25f76757ff07d3d42a10e3432af40e0a64 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Fri, 22 May 2020 01:12:39 +0200 Subject: [PATCH 38/79] ARM: imx: ddr: Fill in missing DDRC ZQCTLx on i.MX7 The iMX7 defines further DDRC ZQCTLx registers, however those were thus far missing from the list of registers and not programmed. On systems with LPDDR2 or DDR3, those registers must be programmed with correct values, otherwise the DRAM may not work. However, existing systems which worked without programming these registers before are now setting those registers to 0, which is the default value, so no functional change there. Signed-off-by: Marek Vasut Cc: Fabio Estevam Cc: NXP i.MX U-Boot Team Cc: Peng Fan Cc: Stefano Babic --- arch/arm/include/asm/arch-mx7/mx7-ddr.h | 4 +++- arch/arm/mach-imx/mx7/ddr.c | 1 + 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/arch/arm/include/asm/arch-mx7/mx7-ddr.h b/arch/arm/include/asm/arch-mx7/mx7-ddr.h index 37aaee0ad7..bea5dd8ec5 100644 --- a/arch/arm/include/asm/arch-mx7/mx7-ddr.h +++ b/arch/arm/include/asm/arch-mx7/mx7-ddr.h @@ -39,7 +39,9 @@ struct ddrc { u32 dramtmg8; /* 0x0120 */ u32 reserved7[0x17]; u32 zqctl0; /* 0x0180 */ - u32 reserved8[0x03]; + u32 zqctl1; /* 0x0184 */ + u32 zqctl2; /* 0x0188 */ + u32 zqstat; /* 0x018c */ u32 dfitmg0; /* 0x0190 */ u32 dfitmg1; /* 0x0194 */ u32 reserved9[0x02]; diff --git a/arch/arm/mach-imx/mx7/ddr.c b/arch/arm/mach-imx/mx7/ddr.c index d1e10a6788..45954ed1ed 100644 --- a/arch/arm/mach-imx/mx7/ddr.c +++ b/arch/arm/mach-imx/mx7/ddr.c @@ -74,6 +74,7 @@ void mx7_dram_cfg(struct ddrc *ddrc_regs_val, struct ddrc_mp *ddrc_mp_val, writel(ddrc_regs_val->dramtmg5, &ddrc_regs->dramtmg5); writel(ddrc_regs_val->dramtmg8, &ddrc_regs->dramtmg8); writel(ddrc_regs_val->zqctl0, &ddrc_regs->zqctl0); + writel(ddrc_regs_val->zqctl1, &ddrc_regs->zqctl1); writel(ddrc_regs_val->dfitmg0, &ddrc_regs->dfitmg0); writel(ddrc_regs_val->dfitmg1, &ddrc_regs->dfitmg1); writel(ddrc_regs_val->dfiupd0, &ddrc_regs->dfiupd0); From 720416031560b21e173306b5495d4757987115f8 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Fri, 22 May 2020 01:13:00 +0200 Subject: [PATCH 39/79] ARM: imx: soc: Switch BOARD_EARLY_INIT_F to imply on MX7 There are systems where board_early_init_f() is plain empty. Switch the config option from "select" to "imply", to permit user to unset the BOARD_EARLY_INIT_F if it were to be empty. Signed-off-by: Marek Vasut Cc: Fabio Estevam Cc: NXP i.MX U-Boot Team Cc: Peng Fan Cc: Stefano Babic --- arch/arm/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index edc9e38c6c..54d65f8488 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -873,11 +873,11 @@ config ARCH_MX7ULP config ARCH_MX7 bool "Freescale MX7" select ARCH_MISC_INIT - select BOARD_EARLY_INIT_F select CPU_V7A select SYS_FSL_HAS_SEC if IMX_HAB select SYS_FSL_SEC_COMPAT_4 select SYS_FSL_SEC_LE + imply BOARD_EARLY_INIT_F imply MXC_GPIO imply SYS_THUMB_BUILD From a1f6d04aa1f41f5ebcec95a37b4dc54b9c7f98c5 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Fri, 22 May 2020 01:13:54 +0200 Subject: [PATCH 40/79] ARM: imx: soc: Select default TEXT_BASE for MX7 Select default U-Boot and SPL text base for the MX7 SoC. The U-Boot text base is picked as the one used by various MX7 boards. The SPL text base however is different. The SPL text base is set to 0x912000 instead of the usual 0x911000, that is because the 0x911000 value cannot work. Using 0x911000 as a SPL text base will result in the DCD header being placed below the 0x911000 address, which is a reserved SRAM area which must not be used. This will actually trigger eMMC boot failure on MX7D at least. Hence the increment. Update all boards affected by this SPL problem to the new SPL_TEXT_BASE. Signed-off-by: Marek Vasut Cc: Fabio Estevam Cc: NXP i.MX U-Boot Team Cc: Peng Fan Cc: Stefano Babic --- arch/arm/mach-imx/mx7/Kconfig | 7 +++++++ configs/cl-som-imx7_defconfig | 2 -- configs/pico-dwarf-imx7d_defconfig | 2 -- configs/pico-hobbit-imx7d_defconfig | 2 -- configs/pico-imx7d_defconfig | 2 -- configs/pico-nymph-imx7d_defconfig | 2 -- configs/pico-pi-imx7d_defconfig | 2 -- 7 files changed, 7 insertions(+), 12 deletions(-) diff --git a/arch/arm/mach-imx/mx7/Kconfig b/arch/arm/mach-imx/mx7/Kconfig index 286d36589d..c8146c3509 100644 --- a/arch/arm/mach-imx/mx7/Kconfig +++ b/arch/arm/mach-imx/mx7/Kconfig @@ -16,6 +16,13 @@ config MX7D select ROM_UNIFIED_SECTIONS imply CMD_FUSE +config SYS_TEXT_BASE + default 0x87800000 + +config SPL_TEXT_BASE + depends on SPL + default 0x00912000 + choice prompt "MX7 board select" optional diff --git a/configs/cl-som-imx7_defconfig b/configs/cl-som-imx7_defconfig index a38c6c2429..4d590578e2 100644 --- a/configs/cl-som-imx7_defconfig +++ b/configs/cl-som-imx7_defconfig @@ -1,6 +1,5 @@ CONFIG_ARM=y CONFIG_ARCH_MX7=y -CONFIG_SYS_TEXT_BASE=0x87800000 CONFIG_SPL_GPIO_SUPPORT=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y @@ -17,7 +16,6 @@ CONFIG_SPL_SPI_SUPPORT=y CONFIG_ARMV7_BOOT_SEC_DEFAULT=y CONFIG_IMX_RDC=y CONFIG_IMX_BOOTAUX=y -CONFIG_SPL_TEXT_BASE=0x00911000 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" CONFIG_SPI_BOOT=y CONFIG_BOOTDELAY=3 diff --git a/configs/pico-dwarf-imx7d_defconfig b/configs/pico-dwarf-imx7d_defconfig index 8a1e15de65..07b17f52ec 100644 --- a/configs/pico-dwarf-imx7d_defconfig +++ b/configs/pico-dwarf-imx7d_defconfig @@ -1,6 +1,5 @@ CONFIG_ARM=y CONFIG_ARCH_MX7=y -CONFIG_SYS_TEXT_BASE=0x87800000 CONFIG_SPL_GPIO_SUPPORT=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y @@ -15,7 +14,6 @@ CONFIG_SPL=y CONFIG_ARMV7_BOOT_SEC_DEFAULT=y CONFIG_IMX_RDC=y CONFIG_IMX_BOOTAUX=y -CONFIG_SPL_TEXT_BASE=0x00911000 CONFIG_DISTRO_DEFAULTS=y CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" CONFIG_BOOTCOMMAND="run findfdt; run finduuid; run distro_bootcmd" diff --git a/configs/pico-hobbit-imx7d_defconfig b/configs/pico-hobbit-imx7d_defconfig index 830fddeee9..d04b0d7dd6 100644 --- a/configs/pico-hobbit-imx7d_defconfig +++ b/configs/pico-hobbit-imx7d_defconfig @@ -1,6 +1,5 @@ CONFIG_ARM=y CONFIG_ARCH_MX7=y -CONFIG_SYS_TEXT_BASE=0x87800000 CONFIG_SPL_GPIO_SUPPORT=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y @@ -15,7 +14,6 @@ CONFIG_SPL=y CONFIG_ARMV7_BOOT_SEC_DEFAULT=y CONFIG_IMX_RDC=y CONFIG_IMX_BOOTAUX=y -CONFIG_SPL_TEXT_BASE=0x00911000 CONFIG_DISTRO_DEFAULTS=y CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" CONFIG_BOOTCOMMAND="run findfdt; run finduuid; run distro_bootcmd" diff --git a/configs/pico-imx7d_defconfig b/configs/pico-imx7d_defconfig index 545acd2c89..f3719187ef 100644 --- a/configs/pico-imx7d_defconfig +++ b/configs/pico-imx7d_defconfig @@ -1,6 +1,5 @@ CONFIG_ARM=y CONFIG_ARCH_MX7=y -CONFIG_SYS_TEXT_BASE=0x87800000 CONFIG_SPL_GPIO_SUPPORT=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y @@ -15,7 +14,6 @@ CONFIG_SPL=y CONFIG_ARMV7_BOOT_SEC_DEFAULT=y CONFIG_IMX_RDC=y CONFIG_IMX_BOOTAUX=y -CONFIG_SPL_TEXT_BASE=0x00911000 CONFIG_DISTRO_DEFAULTS=y CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" CONFIG_BOOTCOMMAND="run findfdt; run finduuid; run distro_bootcmd" diff --git a/configs/pico-nymph-imx7d_defconfig b/configs/pico-nymph-imx7d_defconfig index 8a1e15de65..07b17f52ec 100644 --- a/configs/pico-nymph-imx7d_defconfig +++ b/configs/pico-nymph-imx7d_defconfig @@ -1,6 +1,5 @@ CONFIG_ARM=y CONFIG_ARCH_MX7=y -CONFIG_SYS_TEXT_BASE=0x87800000 CONFIG_SPL_GPIO_SUPPORT=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y @@ -15,7 +14,6 @@ CONFIG_SPL=y CONFIG_ARMV7_BOOT_SEC_DEFAULT=y CONFIG_IMX_RDC=y CONFIG_IMX_BOOTAUX=y -CONFIG_SPL_TEXT_BASE=0x00911000 CONFIG_DISTRO_DEFAULTS=y CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" CONFIG_BOOTCOMMAND="run findfdt; run finduuid; run distro_bootcmd" diff --git a/configs/pico-pi-imx7d_defconfig b/configs/pico-pi-imx7d_defconfig index c9e6abc7d2..13b6a2f35c 100644 --- a/configs/pico-pi-imx7d_defconfig +++ b/configs/pico-pi-imx7d_defconfig @@ -1,6 +1,5 @@ CONFIG_ARM=y CONFIG_ARCH_MX7=y -CONFIG_SYS_TEXT_BASE=0x87800000 CONFIG_SPL_GPIO_SUPPORT=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y @@ -15,7 +14,6 @@ CONFIG_SPL=y CONFIG_ARMV7_BOOT_SEC_DEFAULT=y CONFIG_IMX_RDC=y CONFIG_IMX_BOOTAUX=y -CONFIG_SPL_TEXT_BASE=0x00911000 CONFIG_DISTRO_DEFAULTS=y CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" CONFIG_BOOTCOMMAND="run findfdt; run finduuid; run distro_bootcmd" From 87ea9f784c0e2eb9de52f272daf1f65493b0c6ca Mon Sep 17 00:00:00 2001 From: Otavio Salvador Date: Tue, 9 Jun 2020 13:22:49 -0300 Subject: [PATCH 41/79] mx6ul_14x14_evk: Enable SPL USB and SDP support This fixes the boot from USB loader, which is critical to easy the manufacture process. Signed-off-by: Otavio Salvador Reviewed-by: Fabio Estevam --- configs/mx6ul_14x14_evk_defconfig | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/configs/mx6ul_14x14_evk_defconfig b/configs/mx6ul_14x14_evk_defconfig index 2906782b12..cad766443c 100644 --- a/configs/mx6ul_14x14_evk_defconfig +++ b/configs/mx6ul_14x14_evk_defconfig @@ -22,6 +22,9 @@ CONFIG_BOUNCE_BUFFER=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SPL_FS_EXT4=y CONFIG_SPL_I2C_SUPPORT=y +CONFIG_SPL_USB_HOST_SUPPORT=y +CONFIG_SPL_USB_GADGET=y +CONFIG_SPL_USB_SDP_SUPPORT=y CONFIG_SPL_WATCHDOG_SUPPORT=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y @@ -32,6 +35,8 @@ CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y +CONFIG_CMD_USB_SDP=y +CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_CMD_DHCP=y CONFIG_CMD_PING=y CONFIG_CMD_BMP=y @@ -46,6 +51,7 @@ CONFIG_DEFAULT_DEVICE_TREE="imx6ul-14x14-evk" CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_USB_FUNCTION_FASTBOOT=y CONFIG_DM_74X164=y CONFIG_DM_I2C=y CONFIG_DM_MMC=y @@ -73,5 +79,10 @@ CONFIG_SOFT_SPI=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_CI_UDC=y CONFIG_DM_VIDEO=y CONFIG_SYS_WHITE_ON_BLACK=y From 9959d0f679671c6edf91ef2213a08c90531a5980 Mon Sep 17 00:00:00 2001 From: Otavio Salvador Date: Tue, 9 Jun 2020 13:22:50 -0300 Subject: [PATCH 42/79] mx6ul_14x14_evk: Avoid overlap of environment over U-Boot proper We need to change the environment offset to avoid corrupting the U-Boot binary when saving it. Signed-off-by: Otavio Salvador Reviewed-by: Fabio Estevam --- configs/mx6ul_14x14_evk_defconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/configs/mx6ul_14x14_evk_defconfig b/configs/mx6ul_14x14_evk_defconfig index cad766443c..4ec5f80ee6 100644 --- a/configs/mx6ul_14x14_evk_defconfig +++ b/configs/mx6ul_14x14_evk_defconfig @@ -5,7 +5,7 @@ CONFIG_SPL_GPIO_SUPPORT=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_OFFSET=0x80000 +CONFIG_ENV_OFFSET=0xC0000 CONFIG_TARGET_MX6UL_14X14_EVK=y CONFIG_DM_GPIO=y CONFIG_SPL_MMC_SUPPORT=y From e168eacde1cfbdcf75e92bfda6d51fa59d488dfd Mon Sep 17 00:00:00 2001 From: Ye Li Date: Tue, 9 Jun 2020 20:28:02 -0700 Subject: [PATCH 43/79] gpio: mxc_gpio: change gpio index for i.MX8 Since the i.MX8 GPIO banks are indexed from 0 not 1 on other i.MX platforms, so we have to adjust the index accordingly. Signed-off-by: Adrian Alonso Signed-off-by: Ye Li --- drivers/gpio/mxc_gpio.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/gpio/mxc_gpio.c b/drivers/gpio/mxc_gpio.c index c924e52f07..316dcc757b 100644 --- a/drivers/gpio/mxc_gpio.c +++ b/drivers/gpio/mxc_gpio.c @@ -281,7 +281,10 @@ static int mxc_gpio_probe(struct udevice *dev) char name[18], *str; banknum = plat->bank_index; - sprintf(name, "GPIO%d_", banknum + 1); + if (IS_ENABLED(CONFIG_ARCH_IMX8)) + sprintf(name, "GPIO%d_", banknum); + else + sprintf(name, "GPIO%d_", banknum + 1); str = strdup(name); if (!str) return -ENOMEM; From 59a88e0af03e253ecb180db0821bde9616b64d8f Mon Sep 17 00:00:00 2001 From: Ye Li Date: Tue, 9 Jun 2020 20:28:03 -0700 Subject: [PATCH 44/79] arm: dts: imx: fsl-imx8qm.dtsi: fix gpio aliases Current aliases missed gpio0 node, and this node shoud be aliased to gpio index 0 to align with i.MX8QXP. Otherwise, we will get below message when running "gpio status" command, and see the reason by "dm uclass". => gpio status Device 'gpio@5d090000': seq 0 is in use by 'gpio@5d080000' Device 'gpio@5d0a0000': seq 1 is in use by 'gpio@5d090000' Device 'gpio@5d0b0000': seq 2 is in use by 'gpio@5d0a0000' => dm uclass uclass 36: gpio 0 * gpio@5d080000 @ fbaefb90, seq 0, (req -1) 1 * gpio@5d090000 @ fbaefc70, seq 1, (req 0) 2 * gpio@5d0a0000 @ fbaefd50, seq 2, (req 1) 3 * gpio@5d0b0000 @ fbaefe30, seq 5, (req 2) 4 * gpio@5d0c0000 @ fbaeff10, seq 3, (req 3) 5 * gpio@5d0d0000 @ fbaefff0, seq 4, (req 4) 6 * gpio@5d0e0000 @ fbaf00d0, seq 6, (req 5) 7 * gpio@5d0f0000 @ fbaf01b0, seq 7, (req 6) Signed-off-by: Ye Li --- arch/arm/dts/fsl-imx8qm.dtsi | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) diff --git a/arch/arm/dts/fsl-imx8qm.dtsi b/arch/arm/dts/fsl-imx8qm.dtsi index 2e887add79..88aeaf65b3 100644 --- a/arch/arm/dts/fsl-imx8qm.dtsi +++ b/arch/arm/dts/fsl-imx8qm.dtsi @@ -21,13 +21,14 @@ aliases { ethernet0 = &fec1; ethernet1 = &fec2; - gpio0 = &gpio1; - gpio1 = &gpio2; - gpio2 = &gpio3; - gpio3 = &gpio4; - gpio4 = &gpio5; - gpio5 = &gpio6; - gpio6 = &gpio7; + gpio0 = &gpio0; + gpio1 = &gpio1; + gpio2 = &gpio2; + gpio3 = &gpio3; + gpio4 = &gpio4; + gpio5 = &gpio5; + gpio6 = &gpio6; + gpio7 = &gpio7; serial0 = &lpuart0; serial1 = &lpuart1; serial2 = &lpuart2; From eea10754cd7c92a39d9de40fe551f75008ea33e7 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Tue, 9 Jun 2020 10:43:58 -0300 Subject: [PATCH 45/79] mx6slevk_spinor: Convert to DM_ETH Convert to DM_ETH to avoid board removal from the project. Signed-off-by: Fabio Estevam --- configs/mx6slevk_spinor_defconfig | 3 +++ 1 file changed, 3 insertions(+) diff --git a/configs/mx6slevk_spinor_defconfig b/configs/mx6slevk_spinor_defconfig index 4d348df691..67de522dd8 100644 --- a/configs/mx6slevk_spinor_defconfig +++ b/configs/mx6slevk_spinor_defconfig @@ -44,6 +44,9 @@ CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=20000000 CONFIG_SPI_FLASH_STMICRO=y CONFIG_PHYLIB=y +CONFIG_PHY_SMSC=y +CONFIG_DM_ETH=y +CONFIG_FEC_MXC=y CONFIG_MII=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX6=y From a5df831620a42876941c2a1e836fb92f1f6ffc56 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Tue, 9 Jun 2020 10:43:59 -0300 Subject: [PATCH 46/79] mx6slevk_spl: Convert to DM_ETH Convert to DM_ETH to avoid board removal from the project. Signed-off-by: Fabio Estevam --- configs/mx6slevk_spl_defconfig | 3 +++ 1 file changed, 3 insertions(+) diff --git a/configs/mx6slevk_spl_defconfig b/configs/mx6slevk_spl_defconfig index 3a0ae92bf2..143718a6a7 100644 --- a/configs/mx6slevk_spl_defconfig +++ b/configs/mx6slevk_spl_defconfig @@ -52,6 +52,9 @@ CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=20000000 CONFIG_SPI_FLASH_STMICRO=y CONFIG_PHYLIB=y +CONFIG_PHY_SMSC=y +CONFIG_DM_ETH=y +CONFIG_FEC_MXC=y CONFIG_MII=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX6=y From dbb0c4bf4970d5902bec5d572f153cf7808d22fa Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Tue, 9 Jun 2020 10:44:00 -0300 Subject: [PATCH 47/79] mx6ull_14x14_evk_plugin: Convert to DM_ETH Convert to DM_ETH to avoid board removal from the project. Signed-off-by: Fabio Estevam --- configs/mx6ull_14x14_evk_plugin_defconfig | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/configs/mx6ull_14x14_evk_plugin_defconfig b/configs/mx6ull_14x14_evk_plugin_defconfig index 2811d868ac..e6c31e64ba 100644 --- a/configs/mx6ull_14x14_evk_plugin_defconfig +++ b/configs/mx6ull_14x14_evk_plugin_defconfig @@ -41,6 +41,12 @@ CONFIG_DM_SPI_FLASH=y CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=40000000 CONFIG_SPI_FLASH_STMICRO=y +CONFIG_PHYLIB=y +CONFIG_PHY_MICREL=y +CONFIG_PHY_MICREL_KSZ8XXX=y +CONFIG_DM_ETH=y +CONFIG_FEC_MXC=y +CONFIG_MII=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX6=y CONFIG_DM_REGULATOR=y From 24899e03a56f56e4c78a03247818196ce0cafbb0 Mon Sep 17 00:00:00 2001 From: Walter Lozano Date: Tue, 19 May 2020 15:24:21 -0300 Subject: [PATCH 48/79] mx6cuboxi: enable MMC and eMMC in DT for SPL Signed-off-by: Walter Lozano --- .../dts/imx6qdl-hummingboard2-emmc-som-v15-u-boot.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/dts/imx6qdl-hummingboard2-emmc-som-v15-u-boot.dtsi b/arch/arm/dts/imx6qdl-hummingboard2-emmc-som-v15-u-boot.dtsi index d302b2e275..400b885e43 100644 --- a/arch/arm/dts/imx6qdl-hummingboard2-emmc-som-v15-u-boot.dtsi +++ b/arch/arm/dts/imx6qdl-hummingboard2-emmc-som-v15-u-boot.dtsi @@ -34,3 +34,11 @@ &usdhc1 { status = "disabled"; }; + +&usdhc2 { + u-boot,dm-pre-reloc; +}; + +&usdhc3 { + u-boot,dm-pre-reloc; +}; From 6c3fbf3e456c49c2f43c0c286106a0d4b099b67b Mon Sep 17 00:00:00 2001 From: Walter Lozano Date: Tue, 19 May 2020 15:24:22 -0300 Subject: [PATCH 49/79] mx6cuboxi: customize board_boot_order to access eMMC In SPL legacy code only one MMC device is created, based on BOOT_CFG register, which can be either SD or eMMC. In this context board_boot_order return always MMC1 when configure to boot from SD/eMMC. After switching to DM both SD and eMMC devices are created based on the information available on DT, but as board_boot_order only returns MMC1 is not possible to boot from eMMC. This patch customizes board_boot_order taking into account BOOT_CFG register to point to correct MMC1 / MMC2 device. Additionally, handle IO mux for the desired boot device. Signed-off-by: Walter Lozano --- board/solidrun/mx6cuboxi/mx6cuboxi.c | 48 ++++++++++++++++++++++++++++ 1 file changed, 48 insertions(+) diff --git a/board/solidrun/mx6cuboxi/mx6cuboxi.c b/board/solidrun/mx6cuboxi/mx6cuboxi.c index 59e8b1dca1..c531fbec71 100644 --- a/board/solidrun/mx6cuboxi/mx6cuboxi.c +++ b/board/solidrun/mx6cuboxi/mx6cuboxi.c @@ -529,6 +529,54 @@ int board_fit_config_name_match(const char *name) return strcmp(name, tmp_name); } +void board_boot_order(u32 *spl_boot_list) +{ + struct src *psrc = (struct src *)SRC_BASE_ADDR; + unsigned int reg = readl(&psrc->sbmr1) >> 11; + u32 boot_mode = imx6_src_get_boot_mode() & IMX6_BMODE_MASK; + unsigned int bmode = readl(&src_base->sbmr2); + + /* If bmode is serial or USB phy is active, return serial */ + if (((bmode >> 24) & 0x03) == 0x01 || is_usbotg_phy_active()) { + spl_boot_list[0] = BOOT_DEVICE_BOARD; + return; + } + + switch (boot_mode >> IMX6_BMODE_SHIFT) { + case IMX6_BMODE_SD: + case IMX6_BMODE_ESD: + case IMX6_BMODE_MMC: + case IMX6_BMODE_EMMC: + /* + * Upon reading BOOT_CFG register the following map is done: + * Bit 11 and 12 of BOOT_CFG register can determine the current + * mmc port + * 0x1 SD2 + * 0x2 SD3 + */ + + reg &= 0x3; /* Only care about bottom 2 bits */ + switch (reg) { + case 1: + SETUP_IOMUX_PADS(usdhc2_pads); + spl_boot_list[0] = BOOT_DEVICE_MMC1; + break; + case 2: + SETUP_IOMUX_PADS(usdhc3_pads); + spl_boot_list[0] = BOOT_DEVICE_MMC2; + break; + } + break; + default: + /* By default use USB downloader */ + spl_boot_list[0] = BOOT_DEVICE_BOARD; + break; + } + + /* As a last resort, use serial downloader */ + spl_boot_list[1] = BOOT_DEVICE_BOARD; +} + #ifdef CONFIG_SPL_BUILD #include static const struct mx6dq_iomux_ddr_regs mx6q_ddr_ioregs = { From 6a4bae6c37206aaeab845f8b05a5b260b2c0b228 Mon Sep 17 00:00:00 2001 From: Walter Lozano Date: Tue, 19 May 2020 15:24:23 -0300 Subject: [PATCH 50/79] mx6cuboxi: enable OF_CONTROL and DM in SPL In order to take the beneficts of DT and DM in SPL, like reusing the code and avoid redundancy, enable SPL_OF_CONTROL, SPL_DM and SPL_DM_MMC. With this new configuration SPL image is 50 KB, higher than the 38 KB from the previous version, but it still under the 68 KB limit. Signed-off-by: Walter Lozano --- configs/mx6cuboxi_defconfig | 3 +++ 1 file changed, 3 insertions(+) diff --git a/configs/mx6cuboxi_defconfig b/configs/mx6cuboxi_defconfig index 568cfce4c0..bfb4b86521 100644 --- a/configs/mx6cuboxi_defconfig +++ b/configs/mx6cuboxi_defconfig @@ -25,6 +25,7 @@ CONFIG_USE_PREBOOT=y CONFIG_PREBOOT="if hdmidet; then usb start; setenv stdin serial,usbkbd; setenv stdout serial,vga; setenv stderr serial,vga; else setenv stdin serial; setenv stdout serial; setenv stderr serial; fi;" CONFIG_BOUNCE_BUFFER=y CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SPL_SEPARATE_BSS=y CONFIG_SPL_FS_EXT4=y CONFIG_SPL_I2C_SUPPORT=y CONFIG_SPL_WATCHDOG_SUPPORT=y @@ -37,6 +38,7 @@ CONFIG_CMD_CACHE=y CONFIG_CMD_EXT4_WRITE=y # CONFIG_SPL_PARTITION_UUIDS is not set CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="imx6dl-hummingboard2-emmc-som-v15" CONFIG_OF_LIST="imx6dl-hummingboard2-emmc-som-v15 imx6q-hummingboard2-emmc-som-v15" CONFIG_MULTI_DTB_FIT=y @@ -45,6 +47,7 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y +CONFIG_SPL_DM=y CONFIG_DWC_AHSATA=y CONFIG_DM_MMC=y CONFIG_FSL_USDHC=y From 824e6fe0ae0280cabd9df763fbc3bbaca2682b32 Mon Sep 17 00:00:00 2001 From: Walter Lozano Date: Tue, 19 May 2020 15:24:24 -0300 Subject: [PATCH 51/79] mx6cuboxi: remove unused code After enabling SPL_OF_CONTROL, SPL_DM and SPL_DM_MMC the MMC initialization code is not longer needed. This patch removes the unused code. Signed-off-by: Walter Lozano --- board/solidrun/mx6cuboxi/mx6cuboxi.c | 65 ---------------------------- 1 file changed, 65 deletions(-) diff --git a/board/solidrun/mx6cuboxi/mx6cuboxi.c b/board/solidrun/mx6cuboxi/mx6cuboxi.c index c531fbec71..ae1c04df87 100644 --- a/board/solidrun/mx6cuboxi/mx6cuboxi.c +++ b/board/solidrun/mx6cuboxi/mx6cuboxi.c @@ -154,76 +154,11 @@ static void setup_iomux_uart(void) SETUP_IOMUX_PADS(uart1_pads); } -static struct fsl_esdhc_cfg usdhc_cfg = { - .esdhc_base = USDHC2_BASE_ADDR, - .max_bus_width = 4, -}; - -static struct fsl_esdhc_cfg emmc_cfg = { - .esdhc_base = USDHC3_BASE_ADDR, - .max_bus_width = 8, -}; - int board_mmc_get_env_dev(int devno) { return devno; } -#define USDHC2_CD_GPIO IMX_GPIO_NR(1, 4) - -int board_mmc_getcd(struct mmc *mmc) -{ - struct fsl_esdhc_cfg *cfg = mmc->priv; - int ret = 0; - - switch (cfg->esdhc_base) { - case USDHC2_BASE_ADDR: - ret = !gpio_get_value(USDHC2_CD_GPIO); - break; - case USDHC3_BASE_ADDR: - ret = (mmc_get_op_cond(mmc) < 0) ? 0 : 1; /* eMMC/uSDHC3 has no CD GPIO */ - break; - } - - return ret; -} - -static int mmc_init_spl(bd_t *bis) -{ - struct src *psrc = (struct src *)SRC_BASE_ADDR; - unsigned reg = readl(&psrc->sbmr1) >> 11; - - /* - * Upon reading BOOT_CFG register the following map is done: - * Bit 11 and 12 of BOOT_CFG register can determine the current - * mmc port - * 0x1 SD2 - * 0x2 SD3 - */ - switch (reg & 0x3) { - case 0x1: - SETUP_IOMUX_PADS(usdhc2_pads); - usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); - gd->arch.sdhc_clk = usdhc_cfg.sdhc_clk; - return fsl_esdhc_initialize(bis, &usdhc_cfg); - case 0x2: - SETUP_IOMUX_PADS(usdhc3_pads); - emmc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); - gd->arch.sdhc_clk = emmc_cfg.sdhc_clk; - return fsl_esdhc_initialize(bis, &emmc_cfg); - } - - return -ENODEV; -} - -int board_mmc_init(bd_t *bis) -{ - if (IS_ENABLED(CONFIG_SPL_BUILD)) - return mmc_init_spl(bis); - - return 0; -} - #ifdef CONFIG_VIDEO_IPUV3 static void do_enable_hdmi(struct display_info_t const *dev) { From 868fb9969c85ce5a1b33c6bb713c8158c04acee9 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Mon, 22 Jun 2020 20:49:04 -0400 Subject: [PATCH 52/79] Prepare v2020.07-rc5 Signed-off-by: Tom Rini --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index 149f839948..e3c18d8c39 100644 --- a/Makefile +++ b/Makefile @@ -3,7 +3,7 @@ VERSION = 2020 PATCHLEVEL = 07 SUBLEVEL = -EXTRAVERSION = -rc4 +EXTRAVERSION = -rc5 NAME = # *DOCUMENTATION* From 7635defaf2c65755a19e6faa08d604421ad2a06f Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Tue, 23 Jun 2020 08:20:07 -0400 Subject: [PATCH 53/79] configs: Resync with savedefconfig Rsync all defconfig files using moveconfig.py Signed-off-by: Tom Rini --- configs/P2041RDB_SECURE_BOOT_defconfig | 2 -- configs/T1024RDB_NAND_defconfig | 2 +- configs/T1024RDB_SDCARD_defconfig | 2 +- configs/T1024RDB_SECURE_BOOT_defconfig | 4 +--- configs/T1024RDB_SPIFLASH_defconfig | 2 +- configs/T1024RDB_defconfig | 2 +- configs/firefly-rk3399_defconfig | 2 +- configs/imx8mp_evk_defconfig | 2 +- configs/p3450-0000_defconfig | 2 +- configs/rock-pi-e-rk3328_defconfig | 4 ++-- configs/rockpro64-rk3399_defconfig | 4 ++-- scripts/config_whitelist.txt | 14 -------------- 12 files changed, 12 insertions(+), 30 deletions(-) diff --git a/configs/P2041RDB_SECURE_BOOT_defconfig b/configs/P2041RDB_SECURE_BOOT_defconfig index b3e428025b..35a9d00e4b 100644 --- a/configs/P2041RDB_SECURE_BOOT_defconfig +++ b/configs/P2041RDB_SECURE_BOOT_defconfig @@ -46,7 +46,6 @@ CONFIG_PHY_VITESSE=y CONFIG_DM_ETH=y CONFIG_DM_MDIO=y CONFIG_PHY_GIGE=y -CONFIG_E1000=y CONFIG_FMAN_ENET=y CONFIG_MII=y CONFIG_SYS_QE_FMAN_FW_IN_NOR=y @@ -58,4 +57,3 @@ CONFIG_USB_STORAGE=y CONFIG_RSA=y CONFIG_SPL_RSA=y CONFIG_RSA_SOFTWARE_EXP=y -CONFIG_OF_LIBFDT=y diff --git a/configs/T1024RDB_NAND_defconfig b/configs/T1024RDB_NAND_defconfig index f6deee94e4..e3a955abf9 100644 --- a/configs/T1024RDB_NAND_defconfig +++ b/configs/T1024RDB_NAND_defconfig @@ -34,9 +34,9 @@ CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMTEST=y CONFIG_SYS_ALT_MEMTEST=y -CONFIG_CMD_DM=y CONFIG_SYS_MEMTEST_START=0x00200000 CONFIG_SYS_MEMTEST_END=0x00400000 +CONFIG_CMD_DM=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_SF=y diff --git a/configs/T1024RDB_SDCARD_defconfig b/configs/T1024RDB_SDCARD_defconfig index a0042d826b..b3abeeb817 100644 --- a/configs/T1024RDB_SDCARD_defconfig +++ b/configs/T1024RDB_SDCARD_defconfig @@ -32,9 +32,9 @@ CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMTEST=y CONFIG_SYS_ALT_MEMTEST=y -CONFIG_CMD_DM=y CONFIG_SYS_MEMTEST_START=0x00200000 CONFIG_SYS_MEMTEST_END=0x00400000 +CONFIG_CMD_DM=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_SF=y diff --git a/configs/T1024RDB_SECURE_BOOT_defconfig b/configs/T1024RDB_SECURE_BOOT_defconfig index 6ef2dfda57..fe3d28b373 100644 --- a/configs/T1024RDB_SECURE_BOOT_defconfig +++ b/configs/T1024RDB_SECURE_BOOT_defconfig @@ -19,9 +19,9 @@ CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMTEST=y CONFIG_SYS_ALT_MEMTEST=y -CONFIG_CMD_DM=y CONFIG_SYS_MEMTEST_START=0x00200000 CONFIG_SYS_MEMTEST_END=0x00400000 +CONFIG_CMD_DM=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_SF=y @@ -53,7 +53,6 @@ CONFIG_SPI_FLASH_STMICRO=y CONFIG_PHYLIB=y CONFIG_PHY_AQUANTIA=y CONFIG_PHY_REALTEK=y -CONFIG_E1000=y CONFIG_DM_ETH=y CONFIG_DM_MDIO=y CONFIG_FMAN_ENET=y @@ -67,4 +66,3 @@ CONFIG_USB_STORAGE=y CONFIG_RSA=y CONFIG_SPL_RSA=y CONFIG_RSA_SOFTWARE_EXP=y -CONFIG_OF_LIBFDT=y diff --git a/configs/T1024RDB_SPIFLASH_defconfig b/configs/T1024RDB_SPIFLASH_defconfig index a07c391d86..04e8cc6a44 100644 --- a/configs/T1024RDB_SPIFLASH_defconfig +++ b/configs/T1024RDB_SPIFLASH_defconfig @@ -34,9 +34,9 @@ CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMTEST=y CONFIG_SYS_ALT_MEMTEST=y -CONFIG_CMD_DM=y CONFIG_SYS_MEMTEST_START=0x00200000 CONFIG_SYS_MEMTEST_END=0x00400000 +CONFIG_CMD_DM=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_SF=y diff --git a/configs/T1024RDB_defconfig b/configs/T1024RDB_defconfig index 79fb3959e3..46c857d6c5 100644 --- a/configs/T1024RDB_defconfig +++ b/configs/T1024RDB_defconfig @@ -19,9 +19,9 @@ CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMTEST=y CONFIG_SYS_ALT_MEMTEST=y -CONFIG_CMD_DM=y CONFIG_SYS_MEMTEST_START=0x00200000 CONFIG_SYS_MEMTEST_END=0x00400000 +CONFIG_CMD_DM=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_SF=y diff --git a/configs/firefly-rk3399_defconfig b/configs/firefly-rk3399_defconfig index 5bb54f5835..5181510aac 100644 --- a/configs/firefly-rk3399_defconfig +++ b/configs/firefly-rk3399_defconfig @@ -18,8 +18,8 @@ CONFIG_TPL=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y -CONFIG_CMD_USB=y CONFIG_CMD_PCI=y +CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_TIME=y CONFIG_SPL_OF_CONTROL=y diff --git a/configs/imx8mp_evk_defconfig b/configs/imx8mp_evk_defconfig index 17452b6214..8877bdd349 100644 --- a/configs/imx8mp_evk_defconfig +++ b/configs/imx8mp_evk_defconfig @@ -5,7 +5,6 @@ CONFIG_SPL_GPIO_SUPPORT=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_SYS_MALLOC_F_LEN=0x8000 -CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_ENV_SIZE=0x1000 CONFIG_ENV_OFFSET=0x400000 CONFIG_SYS_I2C_MXC_I2C1=y @@ -31,6 +30,7 @@ CONFIG_BOARD_LATE_INIT=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_BOOTROM_SUPPORT=y +CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_SEPARATE_BSS=y CONFIG_SPL_I2C_SUPPORT=y CONFIG_SPL_POWER_SUPPORT=y diff --git a/configs/p3450-0000_defconfig b/configs/p3450-0000_defconfig index c27a6ea237..d39c8777bd 100644 --- a/configs/p3450-0000_defconfig +++ b/configs/p3450-0000_defconfig @@ -37,6 +37,7 @@ CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=24000000 CONFIG_SPI_FLASH_MACRONIX=y CONFIG_RTL8169=y +CONFIG_NVME=y CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y @@ -56,4 +57,3 @@ CONFIG_CI_UDC=y CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y -CONFIG_NVME=y diff --git a/configs/rock-pi-e-rk3328_defconfig b/configs/rock-pi-e-rk3328_defconfig index 759838775f..e0941225a3 100644 --- a/configs/rock-pi-e-rk3328_defconfig +++ b/configs/rock-pi-e-rk3328_defconfig @@ -27,9 +27,9 @@ CONFIG_DISPLAY_BOARDINFO_LATE=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_TPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_STACK_R=y +CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 CONFIG_SPL_I2C_SUPPORT=y CONFIG_SPL_POWER_SUPPORT=y -CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 CONFIG_SPL_ATF=y CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y CONFIG_TPL_DRIVERS_MISC_SUPPORT=y @@ -72,8 +72,8 @@ CONFIG_DM_PMIC=y CONFIG_PMIC_RK8XX=y CONFIG_SPL_DM_REGULATOR=y CONFIG_REGULATOR_PWM=y -CONFIG_SPL_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_FIXED=y +CONFIG_SPL_DM_REGULATOR_FIXED=y CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y CONFIG_RAM=y diff --git a/configs/rockpro64-rk3399_defconfig b/configs/rockpro64-rk3399_defconfig index 807747485a..ad0c6ab2b4 100644 --- a/configs/rockpro64-rk3399_defconfig +++ b/configs/rockpro64-rk3399_defconfig @@ -22,8 +22,8 @@ CONFIG_TPL=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y -CONFIG_CMD_USB=y CONFIG_CMD_PCI=y +CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_TIME=y CONFIG_SPL_OF_CONTROL=y @@ -50,8 +50,8 @@ CONFIG_PMIC_RK8XX=y CONFIG_REGULATOR_PWM=y CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y -CONFIG_DM_RESET=y CONFIG_RAM_RK3399_LPDDR4=y +CONFIG_DM_RESET=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 CONFIG_ROCKCHIP_SPI=y diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index f6bf6f2474..916768f361 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -1416,8 +1416,6 @@ CONFIG_RESET_TO_RETRY CONFIG_RESET_VECTOR_ADDRESS CONFIG_RESTORE_FLASH CONFIG_RES_BLOCK_SIZE -CONFIG_REV1 -CONFIG_REV3 CONFIG_REVISION_TAG CONFIG_RFSPART CONFIG_RIO @@ -2226,10 +2224,6 @@ CONFIG_SYS_DSPI_CTAR0 CONFIG_SYS_DSPI_CTAR1 CONFIG_SYS_DSPI_CTAR2 CONFIG_SYS_DSPI_CTAR3 -CONFIG_SYS_DSPI_CTAR4 -CONFIG_SYS_DSPI_CTAR5 -CONFIG_SYS_DSPI_CTAR6 -CONFIG_SYS_DSPI_CTAR7 CONFIG_SYS_DV_NOR_BOOT_CFG CONFIG_SYS_EBI_CFGR_VAL CONFIG_SYS_EBI_CSA_VAL @@ -3789,14 +3783,6 @@ CONFIG_SYS_SPCR_OPT CONFIG_SYS_SPCR_TSEC1EP CONFIG_SYS_SPCR_TSEC2EP CONFIG_SYS_SPD_BUS_NUM -CONFIG_SYS_SPI0 -CONFIG_SYS_SPI0_NUM_CS -CONFIG_SYS_SPI1 -CONFIG_SYS_SPI1_BASE -CONFIG_SYS_SPI1_NUM_CS -CONFIG_SYS_SPI2 -CONFIG_SYS_SPI2_BASE -CONFIG_SYS_SPI2_NUM_CS CONFIG_SYS_SPI_ARGS_OFFS CONFIG_SYS_SPI_ARGS_SIZE CONFIG_SYS_SPI_BASE From 0ef8cd38d066a51143a9f5dfaf52f9212ca94a32 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 16 Apr 2020 18:04:43 +0200 Subject: [PATCH 54/79] arm: versal: Fix xspi0 boot mode Use proper number to be aligned with xspi0 boot mode. Signed-off-by: Michal Simek --- include/configs/xilinx_versal.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/configs/xilinx_versal.h b/include/configs/xilinx_versal.h index 1276612503..804525dcad 100644 --- a/include/configs/xilinx_versal.h +++ b/include/configs/xilinx_versal.h @@ -108,7 +108,7 @@ "source ${scriptaddr}; echo XSPI: SCRIPT FAILED: continuing...;\0" #define BOOTENV_DEV_NAME_XSPI(devtypeu, devtypel, instance) \ - "xspi " + "xspi0 " #define BOOT_TARGET_DEVICES_JTAG(func) func(JTAG, jtag, na) From aeb3c386c81017657f4faef34d5c203fe32d3aeb Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 16 Apr 2020 14:48:44 +0200 Subject: [PATCH 55/79] mmc: zynq_sdhci: Remove global pointer Driver is not calling gd anywhere that's why there is not need to define it. Signed-off-by: Michal Simek --- drivers/mmc/zynq_sdhci.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/mmc/zynq_sdhci.c b/drivers/mmc/zynq_sdhci.c index de404aa956..43b9f21522 100644 --- a/drivers/mmc/zynq_sdhci.c +++ b/drivers/mmc/zynq_sdhci.c @@ -19,8 +19,6 @@ #include #include -DECLARE_GLOBAL_DATA_PTR; - struct arasan_sdhci_plat { struct mmc_config cfg; struct mmc mmc; From 70014a78023e7fe400824217d082b96986fcbde8 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 5 May 2020 16:17:57 +0200 Subject: [PATCH 56/79] arm64: versal: Let U-Boot to update memory node by default There is no reason not to let U-Boot to update memory node by default. In past this was disabled by purpose to be able to test different memory configurations from one U-Boot instance. Signed-off-by: Michal Simek --- configs/xilinx_versal_virt_defconfig | 1 - 1 file changed, 1 deletion(-) diff --git a/configs/xilinx_versal_virt_defconfig b/configs/xilinx_versal_virt_defconfig index 4ed14f7030..a307702e7b 100644 --- a/configs/xilinx_versal_virt_defconfig +++ b/configs/xilinx_versal_virt_defconfig @@ -7,7 +7,6 @@ CONFIG_COUNTER_FREQUENCY=62500000 CONFIG_DISTRO_DEFAULTS=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y -# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set CONFIG_BOOTDELAY=5 # CONFIG_DISPLAY_CPUINFO is not set CONFIG_BOARD_EARLY_INIT_R=y From 2b2012d1c1d8515417ba139339d0aa9b47789dca Mon Sep 17 00:00:00 2001 From: Rajan Vaja Date: Mon, 4 May 2020 22:53:56 -0700 Subject: [PATCH 57/79] clk: versal: Remove alt_ref_clk from clock sources alt_ref_clk is applicable only for PS extended version. For PS base version there is no separate alt_ref_clk. It is tied with ref_clk, so remove it from driver. Signed-off-by: Rajan Vaja Signed-off-by: Michal Simek --- drivers/clk/clk_versal.c | 8 +------- 1 file changed, 1 insertion(+), 7 deletions(-) diff --git a/drivers/clk/clk_versal.c b/drivers/clk/clk_versal.c index 2fb3171d71..6f82b60f04 100644 --- a/drivers/clk/clk_versal.c +++ b/drivers/clk/clk_versal.c @@ -117,7 +117,6 @@ struct versal_clk_priv { struct versal_clock *clk; }; -static ulong alt_ref_clk; static ulong pl_alt_ref_clk; static ulong ref_clk; @@ -548,8 +547,7 @@ int soc_clk_dump(void) printf("\n ****** VERSAL CLOCKS *****\n"); - printf("alt_ref_clk:%ld pl_alt_ref_clk:%ld ref_clk:%ld\n", - alt_ref_clk, pl_alt_ref_clk, ref_clk); + printf("pl_alt_ref_clk:%ld ref_clk:%ld\n", pl_alt_ref_clk, ref_clk); for (i = 0; i < clock_max_idx; i++) { debug("%s\n", clock[i].clk_name); ret = versal_get_clock_type(i, &type); @@ -667,10 +665,6 @@ static int versal_clk_probe(struct udevice *dev) debug("%s\n", __func__); - ret = versal_clock_get_freq_by_name("alt_ref_clk", dev, &alt_ref_clk); - if (ret < 0) - return -EINVAL; - ret = versal_clock_get_freq_by_name("pl_alt_ref_clk", dev, &pl_alt_ref_clk); if (ret < 0) From 4c86e0834aeb3ae06389534ccbc90b8bcf5d95bf Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Mon, 27 Apr 2020 11:51:40 +0200 Subject: [PATCH 58/79] firmware: zynqmp: Change panic logic in zynqmp_pmufw_load_config_object() There is no need to panic all the time when pmufw config object loading failed. The patch improves function logic to report permission deny case and also panic only for SPL case. Signed-off-by: Michal Simek Reviewed-by: Luca Ceresoli --- drivers/firmware/firmware-zynqmp.c | 19 +++++++++++++++---- 1 file changed, 15 insertions(+), 4 deletions(-) diff --git a/drivers/firmware/firmware-zynqmp.c b/drivers/firmware/firmware-zynqmp.c index 2bdf7771f6..66edc16930 100644 --- a/drivers/firmware/firmware-zynqmp.c +++ b/drivers/firmware/firmware-zynqmp.c @@ -18,6 +18,8 @@ #define PMUFW_PAYLOAD_ARG_CNT 8 +#define XST_PM_NO_ACCESS 2002L + struct zynqmp_power { struct mbox_chan tx_chan; struct mbox_chan rx_chan; @@ -99,16 +101,25 @@ void zynqmp_pmufw_load_config_object(const void *cfg_obj, size_t size) PM_SET_CONFIGURATION, (u32)((u64)cfg_obj) }; - u32 response; + u32 response = 0; int err; printf("Loading new PMUFW cfg obj (%ld bytes)\n", size); err = send_req(request, ARRAY_SIZE(request), &response, 1); + if (err == XST_PM_NO_ACCESS) { + printf("PMUFW no permission to change config object\n"); + return; + } + if (err) - panic("Cannot load PMUFW configuration object (%d)\n", err); - if (response != 0) - panic("PMUFW returned 0x%08x status!\n", response); + printf("Cannot load PMUFW configuration object (%d)\n", err); + + if (response) + printf("PMUFW returned 0x%08x status!\n", response); + + if ((err || response) && IS_ENABLED(CONFIG_SPL_BUILD)) + panic("PMUFW config object loading failed in EL3\n"); } static int zynqmp_power_probe(struct udevice *dev) From 3427f4d2045729c8995b19407daf91ea9a50e4f8 Mon Sep 17 00:00:00 2001 From: Siva Durga Prasad Paladugu Date: Wed, 9 Dec 2015 18:46:43 +0530 Subject: [PATCH 59/79] fpga: zynqpl: Correct PL bitstream loading sequence for zynqaes Correct the PL bitstream loading sequence for zynqaes command by clearing the loaded PL bitstream before loading the new encrypted bitstream using the zynq aes command. This was done by setting the PROG_B same as in case of fpgaload commands. This patch fixes the issue of loading the encrypted PL bitstream onto the PL in which a bitstream has already been loaded successfully. Signed-off-by: Siva Durga Prasad Paladugu Signed-off-by: Michal Simek --- board/xilinx/zynq/cmds.c | 7 +++++-- drivers/fpga/zynqpl.c | 7 ++++--- include/zynqpl.h | 3 ++- 3 files changed, 11 insertions(+), 6 deletions(-) diff --git a/board/xilinx/zynq/cmds.c b/board/xilinx/zynq/cmds.c index 0c46de7599..d5e7d70bdf 100644 --- a/board/xilinx/zynq/cmds.c +++ b/board/xilinx/zynq/cmds.c @@ -399,7 +399,8 @@ static int zynq_verify_image(u32 src_ptr) status = zynq_decrypt_load(part_load_addr, part_img_len, part_dst_addr, - part_data_len); + part_data_len, + BIT_NONE); if (status != 0) { printf("DECRYPTION_FAIL\n"); return -1; @@ -438,6 +439,7 @@ static int zynq_decrypt_image(struct cmd_tbl *cmdtp, int flag, int argc, char *endp; u32 srcaddr, srclen, dstaddr, dstlen; int status; + u8 imgtype = BIT_NONE; if (argc < 5 && argc > cmdtp->maxargs) return CMD_RET_USAGE; @@ -464,7 +466,8 @@ static int zynq_decrypt_image(struct cmd_tbl *cmdtp, int flag, int argc, if (dstlen % 4) dstlen = roundup(dstlen, 4); - status = zynq_decrypt_load(srcaddr, srclen >> 2, dstaddr, dstlen >> 2); + status = zynq_decrypt_load(srcaddr, srclen >> 2, dstaddr, + dstlen >> 2, imgtype); if (status != 0) return CMD_RET_FAILURE; diff --git a/drivers/fpga/zynqpl.c b/drivers/fpga/zynqpl.c index dcfe513eeb..4ab354bbba 100644 --- a/drivers/fpga/zynqpl.c +++ b/drivers/fpga/zynqpl.c @@ -204,7 +204,7 @@ static int zynq_dma_xfer_init(bitstream_type bstype) /* Clear loopback bit */ clrbits_le32(&devcfg_base->mctrl, DEVCFG_MCTRL_PCAP_LPBK); - if (bstype != BIT_PARTIAL) { + if (bstype != BIT_PARTIAL && bstype != BIT_NONE) { zynq_slcr_devcfg_disable(); /* Setting PCFG_PROG_B signal to high */ @@ -511,7 +511,8 @@ struct xilinx_fpga_op zynq_op = { * Load the encrypted image from src addr and decrypt the image and * place it back the decrypted image into dstaddr. */ -int zynq_decrypt_load(u32 srcaddr, u32 srclen, u32 dstaddr, u32 dstlen) +int zynq_decrypt_load(u32 srcaddr, u32 srclen, u32 dstaddr, u32 dstlen, + u8 bstype) { if (srcaddr < SZ_1M || dstaddr < SZ_1M) { printf("%s: src and dst addr should be > 1M\n", @@ -519,7 +520,7 @@ int zynq_decrypt_load(u32 srcaddr, u32 srclen, u32 dstaddr, u32 dstlen) return FPGA_FAIL; } - if (zynq_dma_xfer_init(BIT_NONE)) { + if (zynq_dma_xfer_init(bstype)) { printf("%s: zynq_dma_xfer_init FAIL\n", __func__); return FPGA_FAIL; } diff --git a/include/zynqpl.h b/include/zynqpl.h index 766e6918cd..d7dc064585 100644 --- a/include/zynqpl.h +++ b/include/zynqpl.h @@ -12,7 +12,8 @@ #include #ifdef CONFIG_CMD_ZYNQ_AES -int zynq_decrypt_load(u32 srcaddr, u32 dstaddr, u32 srclen, u32 dstlen); +int zynq_decrypt_load(u32 srcaddr, u32 dstaddr, u32 srclen, u32 dstlen, + u8 bstype); #endif extern struct xilinx_fpga_op zynq_op; From 1d9632a3ccca00638ace1ff6bbce7eba1e15aac7 Mon Sep 17 00:00:00 2001 From: T Karthik Reddy Date: Tue, 12 Mar 2019 20:20:20 +0530 Subject: [PATCH 60/79] fpga: zynqpl: Check fpga config completion This patch checks fpga config completion when a bitstream is loaded into PL. Signed-off-by: T Karthik Reddy Signed-off-by: Siva Durga Prasad Paladugu Signed-off-by: Michal Simek --- drivers/fpga/zynqpl.c | 19 +++++++++++++++++-- 1 file changed, 17 insertions(+), 2 deletions(-) diff --git a/drivers/fpga/zynqpl.c b/drivers/fpga/zynqpl.c index 4ab354bbba..de71969399 100644 --- a/drivers/fpga/zynqpl.c +++ b/drivers/fpga/zynqpl.c @@ -514,6 +514,8 @@ struct xilinx_fpga_op zynq_op = { int zynq_decrypt_load(u32 srcaddr, u32 srclen, u32 dstaddr, u32 dstlen, u8 bstype) { + u32 isr_status, ts; + if (srcaddr < SZ_1M || dstaddr < SZ_1M) { printf("%s: src and dst addr should be > 1M\n", __func__); @@ -544,8 +546,21 @@ int zynq_decrypt_load(u32 srcaddr, u32 srclen, u32 dstaddr, u32 dstlen, if (zynq_dma_transfer(srcaddr | 1, srclen, dstaddr | 1, dstlen)) return FPGA_FAIL; - writel((readl(&devcfg_base->ctrl) & ~DEVCFG_CTRL_PCAP_RATE_EN_MASK), - &devcfg_base->ctrl); + if (bstype == BIT_FULL) { + isr_status = readl(&devcfg_base->int_sts); + /* Check FPGA configuration completion */ + ts = get_timer(0); + while (!(isr_status & DEVCFG_ISR_PCFG_DONE)) { + if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT) { + printf("%s: Timeout wait for FPGA to config\n", + __func__); + return FPGA_FAIL; + } + isr_status = readl(&devcfg_base->int_sts); + } + printf("%s: FPGA config done\n", __func__); + zynq_slcr_devcfg_enable(); + } return FPGA_SUCCESS; } From c64afba2fb483d416ad5da9dfe3f1f156ccf2366 Mon Sep 17 00:00:00 2001 From: Ibai Erkiaga Date: Thu, 5 Apr 2018 05:19:27 -0700 Subject: [PATCH 61/79] fpga: zynqpl: Check if aes engine is enabled AES engine cannot be used if has not been enabled at boot time with an encrypted boot image. Signed-off-by: Ibai Erkiaga Acked-by: Siva Durga Prasad Paladugu Signed-off-by: Michal Simek --- drivers/fpga/zynqpl.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/fpga/zynqpl.c b/drivers/fpga/zynqpl.c index de71969399..90bb850833 100644 --- a/drivers/fpga/zynqpl.c +++ b/drivers/fpga/zynqpl.c @@ -22,6 +22,7 @@ #define DEVCFG_CTRL_PCFG_PROG_B 0x40000000 #define DEVCFG_CTRL_PCFG_AES_EFUSE_MASK 0x00001000 #define DEVCFG_CTRL_PCAP_RATE_EN_MASK 0x02000000 +#define DEVCFG_CTRL_PCFG_AES_EN_MASK 0x00000E00 #define DEVCFG_ISR_FATAL_ERROR_MASK 0x00740040 #define DEVCFG_ISR_ERROR_FLAGS_MASK 0x00340840 #define DEVCFG_ISR_RX_FIFO_OV 0x00040000 @@ -522,6 +523,13 @@ int zynq_decrypt_load(u32 srcaddr, u32 srclen, u32 dstaddr, u32 dstlen, return FPGA_FAIL; } + /* Check AES engine is enabled */ + if (!(readl(&devcfg_base->ctrl) & + DEVCFG_CTRL_PCFG_AES_EN_MASK)) { + printf("%s: AES engine is not enabled\n", __func__); + return FPGA_FAIL; + } + if (zynq_dma_xfer_init(bstype)) { printf("%s: zynq_dma_xfer_init FAIL\n", __func__); return FPGA_FAIL; From ca0c0e07adf3c3baf3851fc17490a0160398c834 Mon Sep 17 00:00:00 2001 From: T Karthik Reddy Date: Tue, 12 Mar 2019 20:20:23 +0530 Subject: [PATCH 62/79] fpga: zynqpl: Flush dcache only for non-bitstream data In case of aes decryption destination address range must be flushed before transferring decrypted data to destination. Signed-off-by: T Karthik Reddy Signed-off-by: Siva Durga Prasad Paladugu Signed-off-by: Michal Simek --- drivers/fpga/zynqpl.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/fpga/zynqpl.c b/drivers/fpga/zynqpl.c index 90bb850833..a11e485525 100644 --- a/drivers/fpga/zynqpl.c +++ b/drivers/fpga/zynqpl.c @@ -548,8 +548,9 @@ int zynq_decrypt_load(u32 srcaddr, u32 srclen, u32 dstaddr, u32 dstlen, * Flush destination address range only if image is not * bitstream. */ - flush_dcache_range((u32)dstaddr, (u32)dstaddr + - roundup(dstlen << 2, ARCH_DMA_MINALIGN)); + if (bstype == BIT_NONE && dstaddr != 0xFFFFFFFF) + flush_dcache_range((u32)dstaddr, (u32)dstaddr + + roundup(dstlen << 2, ARCH_DMA_MINALIGN)); if (zynq_dma_transfer(srcaddr | 1, srclen, dstaddr | 1, dstlen)) return FPGA_FAIL; From b80a476faa3a36ea66a706cf985533792e1e185e Mon Sep 17 00:00:00 2001 From: T Karthik Reddy Date: Tue, 12 Mar 2019 20:20:22 +0530 Subject: [PATCH 63/79] fpga: zynqpl: Add zynq aes load & loadp commands Added support for zynq aes load & loadp commands. Signed-off-by: T Karthik Reddy Signed-off-by: Siva Durga Prasad Paladugu Signed-off-by: Michal Simek --- board/xilinx/zynq/cmds.c | 47 ++++++++++++++++++++++++++++++---------- 1 file changed, 35 insertions(+), 12 deletions(-) diff --git a/board/xilinx/zynq/cmds.c b/board/xilinx/zynq/cmds.c index d5e7d70bdf..73e2b0eac7 100644 --- a/board/xilinx/zynq/cmds.c +++ b/board/xilinx/zynq/cmds.c @@ -444,18 +444,37 @@ static int zynq_decrypt_image(struct cmd_tbl *cmdtp, int flag, int argc, if (argc < 5 && argc > cmdtp->maxargs) return CMD_RET_USAGE; - srcaddr = simple_strtoul(argv[2], &endp, 16); - if (*argv[2] == 0 || *endp != 0) - return CMD_RET_USAGE; - srclen = simple_strtoul(argv[3], &endp, 16); - if (*argv[3] == 0 || *endp != 0) - return CMD_RET_USAGE; - dstaddr = simple_strtoul(argv[4], &endp, 16); - if (*argv[4] == 0 || *endp != 0) - return CMD_RET_USAGE; - dstlen = simple_strtoul(argv[5], &endp, 16); - if (*argv[5] == 0 || *endp != 0) - return CMD_RET_USAGE; + if (argc == 5) { + if (!strcmp("load", argv[2])) + imgtype = BIT_FULL; + else if (!strcmp("loadp", argv[2])) + imgtype = BIT_PARTIAL; + else + return CMD_RET_USAGE; + + srcaddr = simple_strtoul(argv[3], &endp, 16); + if (*argv[3] == 0 || *endp != 0) + return CMD_RET_USAGE; + srclen = simple_strtoul(argv[4], &endp, 16); + if (*argv[4] == 0 || *endp != 0) + return CMD_RET_USAGE; + + dstaddr = 0xFFFFFFFF; + dstlen = srclen; + } else { + srcaddr = simple_strtoul(argv[2], &endp, 16); + if (*argv[2] == 0 || *endp != 0) + return CMD_RET_USAGE; + srclen = simple_strtoul(argv[3], &endp, 16); + if (*argv[3] == 0 || *endp != 0) + return CMD_RET_USAGE; + dstaddr = simple_strtoul(argv[4], &endp, 16); + if (*argv[4] == 0 || *endp != 0) + return CMD_RET_USAGE; + dstlen = simple_strtoul(argv[5], &endp, 16); + if (*argv[5] == 0 || *endp != 0) + return CMD_RET_USAGE; + } /* * Roundup source and destination lengths to @@ -520,6 +539,10 @@ static char zynq_help_text[] = " - Decrypts the encrypted image present in source\n" " address and places the decrypted image at\n" " destination address\n" + "aes load \n" + "aes loadp \n" + " if operation type is load or loadp, it loads the encrypted\n" + " full or partial bitstream on to PL respectively.\n" #endif ; #endif From 032d9aa1896dc8298155a6b5f71351169032405f Mon Sep 17 00:00:00 2001 From: Ashok Reddy Soma Date: Thu, 30 Apr 2020 23:44:23 -0600 Subject: [PATCH 64/79] arm: zynq: Enable alternative memory test Enable alternative memory test for zynq platforms. Signed-off-by: Ashok Reddy Soma Signed-off-by: Michal Simek --- configs/xilinx_zynq_virt_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/xilinx_zynq_virt_defconfig b/configs/xilinx_zynq_virt_defconfig index 5da7440af2..54c3076c24 100644 --- a/configs/xilinx_zynq_virt_defconfig +++ b/configs/xilinx_zynq_virt_defconfig @@ -24,6 +24,7 @@ CONFIG_SPL_SPI_LOAD=y CONFIG_CMD_IMLS=y CONFIG_CMD_THOR_DOWNLOAD=y CONFIG_CMD_MEMTEST=y +CONFIG_SYS_ALT_MEMTEST=y CONFIG_SYS_MEMTEST_START=0x00000000 CONFIG_SYS_MEMTEST_END=0x00001000 CONFIG_CMD_DFU=y From a0f309ee9e4fc36b8395c9808985ed70d6045b11 Mon Sep 17 00:00:00 2001 From: Ashok Reddy Soma Date: Thu, 30 Apr 2020 23:44:22 -0600 Subject: [PATCH 65/79] arm64: versal: Enable config to map TCM and OCM Enable CONFIG_DEFINE_TCM_OCM_MMAP to map TCM and OCM memory. Signed-off-by: Ashok Reddy Soma Signed-off-by: Michal Simek --- configs/xilinx_versal_virt_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/xilinx_versal_virt_defconfig b/configs/xilinx_versal_virt_defconfig index a307702e7b..4510a093fb 100644 --- a/configs/xilinx_versal_virt_defconfig +++ b/configs/xilinx_versal_virt_defconfig @@ -3,6 +3,7 @@ CONFIG_ARCH_VERSAL=y CONFIG_SYS_TEXT_BASE=0x8000000 CONFIG_SYS_MALLOC_F_LEN=0x100000 CONFIG_DM_GPIO=y +CONFIG_DEFINE_TCM_OCM_MMAP=y CONFIG_COUNTER_FREQUENCY=62500000 CONFIG_DISTRO_DEFAULTS=y CONFIG_FIT=y From 052451c10b281f17e2ab0334f071810439faf1a4 Mon Sep 17 00:00:00 2001 From: T Karthik Reddy Date: Tue, 5 May 2020 08:14:28 -0600 Subject: [PATCH 66/79] arm64: zynqmp: Reduce console buffer size Reduce console buffer size to 1kbyte to accommodate memory allocations in mini u-boot for zynqmp. Signed-off-by: T Karthik Reddy Signed-off-by: Michal Simek --- include/configs/xilinx_zynqmp_mini.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/configs/xilinx_zynqmp_mini.h b/include/configs/xilinx_zynqmp_mini.h index ae751aa395..3f57423b78 100644 --- a/include/configs/xilinx_zynqmp_mini.h +++ b/include/configs/xilinx_zynqmp_mini.h @@ -24,5 +24,7 @@ /* BOOTP options */ #undef CONFIG_BOOTP_BOOTFILESIZE #undef CONFIG_BOOTP_MAY_FAIL +#undef CONFIG_SYS_CBSIZE +#define CONFIG_SYS_CBSIZE 1024 #endif /* __CONFIG_ZYNQMP_MINI_H */ From 3ab205c117b5f85bea1565b37db10736f858854c Mon Sep 17 00:00:00 2001 From: Saeed Nowshadi Date: Wed, 4 Mar 2020 10:21:34 -0800 Subject: [PATCH 67/79] arm64: zynqmp: Fix si570 clock output names and references Align clock output names with node references. Signed-off-by: Saeed Nowshadi Signed-off-by: Michal Simek --- arch/arm/dts/zynqmp-e-a2197-00-revA.dts | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm/dts/zynqmp-e-a2197-00-revA.dts b/arch/arm/dts/zynqmp-e-a2197-00-revA.dts index bf982e2218..c260411d75 100644 --- a/arch/arm/dts/zynqmp-e-a2197-00-revA.dts +++ b/arch/arm/dts/zynqmp-e-a2197-00-revA.dts @@ -2,7 +2,7 @@ /* * dts file for Xilinx Versal a2197 RevA System Controller * - * (C) Copyright 2019, Xilinx, Inc. + * (C) Copyright 2019 - 2020, Xilinx, Inc. * * Michal Simek */ @@ -421,14 +421,14 @@ temperature-stability = <50>; factory-fout = <156250000>; clock-frequency = <156250000>; - clock-output-names = "si570_hsdp_clk"; + clock-output-names = "si570_zsfp_clk"; }; }; i2c@6 { /* USER_SI570_1 */ #address-cells = <1>; #size-cells = <0>; reg = <6>; - si570_user1_clk: clock-generator@5d { /* u205 */ + si570_user1: clock-generator@5d { /* u205 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5f>; @@ -510,7 +510,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <4>; - si570_ddr_dimm2: clock-generator@60 { /* u3 */ + si570_lpddr4clk2: clock-generator@60 { /* u3 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; @@ -524,7 +524,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <5>; - si570_lpddr4: clock-generator@60 { /* u4 */ + si570_lpddr4clk1: clock-generator@60 { /* u4 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; From 7831292fc94d9624b33b3418a73c35ece232b35e Mon Sep 17 00:00:00 2001 From: T Karthik Reddy Date: Tue, 5 May 2020 08:14:30 -0600 Subject: [PATCH 68/79] arm64: zynqmp: Change spi-max-frequency for qspi mini Change mini u-boot qspi spi-max-frequency to 108Mhz, make the frequency similar to full u-boot qspi flash spi-max-frequency. Signed-off-by: T Karthik Reddy Signed-off-by: Michal Simek --- arch/arm/dts/zynqmp-mini-qspi.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/dts/zynqmp-mini-qspi.dts b/arch/arm/dts/zynqmp-mini-qspi.dts index c523e81236..a76e640466 100644 --- a/arch/arm/dts/zynqmp-mini-qspi.dts +++ b/arch/arm/dts/zynqmp-mini-qspi.dts @@ -70,7 +70,7 @@ reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; - spi-max-frequency = <10000000>; + spi-max-frequency = <108000000>; }; }; From 26e62cc9713ebe728d01826e8c22c3c56f8e3bf4 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 13 May 2020 08:05:01 -0600 Subject: [PATCH 69/79] net: gem: Disable PCS autonegotiation in case of fixed-link Disable PCS autonegotiation if fixed-link node is present in device tree. This way systems with multiple GEM instances with a combination of SGMII-fixed and SGMII-PHY will work. Reported-by: Goran Marinkovic Signed-off-by: Michal Simek Signed-off-by: Ashok Reddy Soma Signed-off-by: Michal Simek --- drivers/net/zynq_gem.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c index 412daf7d58..da4b6fba9f 100644 --- a/drivers/net/zynq_gem.c +++ b/drivers/net/zynq_gem.c @@ -451,8 +451,12 @@ static int zynq_gem_init(struct udevice *dev) nwconfig |= ZYNQ_GEM_NWCFG_SGMII_ENBL | ZYNQ_GEM_NWCFG_PCS_SEL; #ifdef CONFIG_ARM64 + if (priv->phydev->phy_id != PHY_FIXED_ID) writel(readl(®s->pcscntrl) | ZYNQ_GEM_PCS_CTL_ANEG_ENBL, ®s->pcscntrl); + else + writel(readl(®s->pcscntrl) & ~ZYNQ_GEM_PCS_CTL_ANEG_ENBL, + ®s->pcscntrl); #endif } From f44bd3bcfd91cd7b1be709c9cfb0824e6a71b9b0 Mon Sep 17 00:00:00 2001 From: Ashok Reddy Soma Date: Mon, 18 May 2020 01:11:00 -0600 Subject: [PATCH 70/79] spi: zynq_[q]spi: Convert config's to macro's Remove below config options and convert them to macros. They have never been configured to different values than default one. And also it makes sense to reduce the config_whitelist. CONFIG_SYS_ZYNQ_SPI_WAIT CONFIG_SYS_ZYNQ_QSPI_WAIT CONFIG_XILINX_SPI_IDLE_VAL Signed-off-by: Ashok Reddy Soma Signed-off-by: Michal Simek --- drivers/spi/xilinx_spi.c | 6 ++---- drivers/spi/zynq_qspi.c | 6 ++---- drivers/spi/zynq_spi.c | 6 ++---- scripts/config_whitelist.txt | 3 --- 4 files changed, 6 insertions(+), 15 deletions(-) diff --git a/drivers/spi/xilinx_spi.c b/drivers/spi/xilinx_spi.c index 05768eef72..348630faf3 100644 --- a/drivers/spi/xilinx_spi.c +++ b/drivers/spi/xilinx_spi.c @@ -76,9 +76,7 @@ SPICR_SPE) #define XILSPI_SPICR_DFLT_OFF (SPICR_MASTER_INHIBIT | SPICR_MANUAL_SS) -#ifndef CONFIG_XILINX_SPI_IDLE_VAL -#define CONFIG_XILINX_SPI_IDLE_VAL GENMASK(7, 0) -#endif +#define XILINX_SPI_IDLE_VAL GENMASK(7, 0) #define XILINX_SPISR_TIMEOUT 10000 /* in milliseconds */ @@ -176,7 +174,7 @@ static u32 xilinx_spi_fill_txfifo(struct udevice *bus, const u8 *txp, while (txbytes && !(readl(®s->spisr) & SPISR_TX_FULL) && i < priv->fifo_depth) { - d = txp ? *txp++ : CONFIG_XILINX_SPI_IDLE_VAL; + d = txp ? *txp++ : XILINX_SPI_IDLE_VAL; debug("spi_xfer: tx:%x ", d); /* write out and wait for processing (receive data) */ writel(d & SPIDTR_8BIT_MASK, ®s->spidtr); diff --git a/drivers/spi/zynq_qspi.c b/drivers/spi/zynq_qspi.c index db473da6ea..3f39ef05f2 100644 --- a/drivers/spi/zynq_qspi.c +++ b/drivers/spi/zynq_qspi.c @@ -47,9 +47,7 @@ DECLARE_GLOBAL_DATA_PTR; #define ZYNQ_QSPI_CR_SS_SHIFT 10 /* Slave select shift */ #define ZYNQ_QSPI_FIFO_DEPTH 63 -#ifndef CONFIG_SYS_ZYNQ_QSPI_WAIT -#define CONFIG_SYS_ZYNQ_QSPI_WAIT CONFIG_SYS_HZ/100 /* 10 ms */ -#endif +#define ZYNQ_QSPI_WAIT (CONFIG_SYS_HZ / 100) /* 10 ms */ /* zynq qspi register set */ struct zynq_qspi_regs { @@ -350,7 +348,7 @@ static int zynq_qspi_irq_poll(struct zynq_qspi_priv *priv) do { status = readl(®s->isr); } while ((status == 0) && - (get_timer(timeout) < CONFIG_SYS_ZYNQ_QSPI_WAIT)); + (get_timer(timeout) < ZYNQ_QSPI_WAIT)); if (status == 0) { printf("zynq_qspi_irq_poll: Timeout!\n"); diff --git a/drivers/spi/zynq_spi.c b/drivers/spi/zynq_spi.c index 3e66b34ebb..78ffd3e2fe 100644 --- a/drivers/spi/zynq_spi.c +++ b/drivers/spi/zynq_spi.c @@ -36,9 +36,7 @@ DECLARE_GLOBAL_DATA_PTR; #define ZYNQ_SPI_CR_SS_SHIFT 10 /* Slave select shift */ #define ZYNQ_SPI_FIFO_DEPTH 128 -#ifndef CONFIG_SYS_ZYNQ_SPI_WAIT -#define CONFIG_SYS_ZYNQ_SPI_WAIT (CONFIG_SYS_HZ/100) /* 10 ms */ -#endif +#define ZYNQ_SPI_WAIT (CONFIG_SYS_HZ / 100) /* 10 ms */ /* zynq spi register set */ struct zynq_spi_regs { @@ -251,7 +249,7 @@ static int zynq_spi_xfer(struct udevice *dev, unsigned int bitlen, ts = get_timer(0); status = readl(®s->isr); while (!(status & ZYNQ_SPI_IXR_TXOW_MASK)) { - if (get_timer(ts) > CONFIG_SYS_ZYNQ_SPI_WAIT) { + if (get_timer(ts) > ZYNQ_SPI_WAIT) { printf("spi_xfer: Timeout! TX FIFO not full\n"); return -1; } diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index 916768f361..b023806efc 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -3984,8 +3984,6 @@ CONFIG_SYS_XHCI_USB1_ADDR CONFIG_SYS_XHCI_USB2_ADDR CONFIG_SYS_XHCI_USB3_ADDR CONFIG_SYS_XIMG_LEN -CONFIG_SYS_ZYNQ_QSPI_WAIT -CONFIG_SYS_ZYNQ_SPI_WAIT CONFIG_SYS_i2C_FSL CONFIG_TAM3517_SETTINGS CONFIG_TCA642X @@ -4211,7 +4209,6 @@ CONFIG_X86_MRC_ADDR CONFIG_X86_REFCODE_ADDR CONFIG_X86_REFCODE_RUN_ADDR CONFIG_XGI_XG22_BASE -CONFIG_XILINX_SPI_IDLE_VAL CONFIG_XSENGINE CONFIG_XTFPGA CONFIG_YAFFSFS_PROVIDE_VALUES From 33d3f8e57754f9b498fa7c14408f2bc20be43900 Mon Sep 17 00:00:00 2001 From: T Karthik Reddy Date: Thu, 14 May 2020 07:49:36 -0600 Subject: [PATCH 71/79] arm64: xilinx: Print fpga error value in hex Fpga returns error value when fails, error status should be printed in hex format. Signed-off-by: T Karthik Reddy Signed-off-by: Michal Simek --- drivers/fpga/versalpl.c | 2 +- drivers/fpga/zynqmppl.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/fpga/versalpl.c b/drivers/fpga/versalpl.c index b96519e1a4..8e2ef4f0da 100644 --- a/drivers/fpga/versalpl.c +++ b/drivers/fpga/versalpl.c @@ -45,7 +45,7 @@ static int versal_load(xilinx_desc *desc, const void *buf, size_t bsize, ret = xilinx_pm_request(VERSAL_PM_LOAD_PDI, VERSAL_PM_PDI_TYPE, buf_lo, buf_hi, 0, ret_payload); if (ret) - puts("PL FPGA LOAD fail\n"); + printf("PL FPGA LOAD failed with err: 0x%08x\n", ret); return ret; } diff --git a/drivers/fpga/zynqmppl.c b/drivers/fpga/zynqmppl.c index 2ac4e38952..5b103cfeaf 100644 --- a/drivers/fpga/zynqmppl.c +++ b/drivers/fpga/zynqmppl.c @@ -239,7 +239,7 @@ static int zynqmp_load(xilinx_desc *desc, const void *buf, size_t bsize, buf_hi, (u32)bsize, 0, ret_payload); if (ret) - puts("PL FPGA LOAD fail\n"); + printf("PL FPGA LOAD failed with err: 0x%08x\n", ret); return ret; } From 6b3984c6318447e954942c9780b714a676f977e6 Mon Sep 17 00:00:00 2001 From: Johannes Krottmayer Date: Wed, 3 Jun 2020 11:50:06 +0200 Subject: [PATCH 72/79] doc: board: xilinx: zynq.rst: add description how to flash a SD card Add a short description in the ZYNQ documentation how to prepare a SD card and copy the related images to SD card. Signed-off-by: Johannes Krottmayer Cc: Michal Simek Signed-off-by: Michal Simek --- doc/board/xilinx/zynq.rst | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/doc/board/xilinx/zynq.rst b/doc/board/xilinx/zynq.rst index 6a09df1d15..f564434b69 100644 --- a/doc/board/xilinx/zynq.rst +++ b/doc/board/xilinx/zynq.rst @@ -60,6 +60,25 @@ SLCR bootmode register Bit[3:0] values "modeboot" variable can assign any of "norboot", "sdboot" or "jtagboot" bootmode strings at runtime. +Flashing +-------- + +SD Card +^^^^^^^ + +To write an image that boots from a SD card first create a FAT32 partition +and a FAT32 filesystem on the SD card:: + + sudo fdisk /dev/sdx + sudo mkfs.vfat -F 32 /dev/sdx1 + +Mount the SD card and copy the SPL and U-Boot to the root directory of the +SD card:: + + sudo mount -t vfat /dev/sdx1 /mnt + sudo cp spl/boot.bin /mnt + sudo cp u-boot.img /mnt + Mainline status --------------- From 945a55050dbd2e916724c2db0ac7eb6c3e29518e Mon Sep 17 00:00:00 2001 From: Patrick van Gelder Date: Wed, 3 Jun 2020 14:18:04 +0200 Subject: [PATCH 73/79] net: xilinx: axi_emac: Fix endless loop when no PHYs are connected The index used to iterate over the possible PHYs in axiemac_phy_init was an unsigned int and decremented. Therefor it was always >= 0 and never exited the loop. Signed-off-by: Patrick van Gelder Signed-off-by: Michal Simek --- drivers/net/xilinx_axi_emac.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/net/xilinx_axi_emac.c b/drivers/net/xilinx_axi_emac.c index d0683db80d..2cd5596768 100644 --- a/drivers/net/xilinx_axi_emac.c +++ b/drivers/net/xilinx_axi_emac.c @@ -244,7 +244,8 @@ static u32 phywrite(struct axidma_priv *priv, u32 phyaddress, u32 registernum, static int axiemac_phy_init(struct udevice *dev) { u16 phyreg; - u32 i, ret; + int i; + u32 ret; struct axidma_priv *priv = dev_get_priv(dev); struct axi_regs *regs = priv->iobase; struct phy_device *phydev; From fe1eb9945b9d28a91f5a0e20710e3ed5e54d877e Mon Sep 17 00:00:00 2001 From: Mike Looijmans Date: Wed, 22 Apr 2020 16:27:19 +0200 Subject: [PATCH 74/79] board: topic-miami: Set FCLK1 to 150MHz In all reference designs the FCLK1 runs at 150MHz, but the bootloader doesn't set it up like that. Set the divider to 8 to generate the correct clock. Fixes (a.o.) the DMA speed being too slow. Signed-off-by: Mike Looijmans Signed-off-by: Michal Simek --- board/topic/zynq/zynq-topic-miami/ps7_init_gpl.c | 2 +- board/topic/zynq/zynq-topic-miamilite/ps7_init_gpl.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/board/topic/zynq/zynq-topic-miami/ps7_init_gpl.c b/board/topic/zynq/zynq-topic-miami/ps7_init_gpl.c index 360beaef8e..e7cc2c2dec 100644 --- a/board/topic/zynq/zynq-topic-miami/ps7_init_gpl.c +++ b/board/topic/zynq/zynq-topic-miami/ps7_init_gpl.c @@ -49,7 +49,7 @@ static unsigned long ps7_clock_init_data_3_0[] = { EMIT_MASKWRITE(0XF8000158, 0x00003F33U, 0x00000601U), EMIT_MASKWRITE(0XF8000168, 0x00003F31U, 0x00000601U), EMIT_MASKWRITE(0XF8000170, 0x03F03F30U, 0x00100C00U), - EMIT_MASKWRITE(0XF8000180, 0x03F03F30U, 0x00100C00U), + EMIT_MASKWRITE(0XF8000180, 0x03F03F30U, 0x00100800U), EMIT_MASKWRITE(0XF8000190, 0x03F03F30U, 0x00100600U), EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U, 0x00101800U), EMIT_MASKWRITE(0XF80001C4, 0x00000001U, 0x00000001U), diff --git a/board/topic/zynq/zynq-topic-miamilite/ps7_init_gpl.c b/board/topic/zynq/zynq-topic-miamilite/ps7_init_gpl.c index ae4666f7d5..0f141260ff 100644 --- a/board/topic/zynq/zynq-topic-miamilite/ps7_init_gpl.c +++ b/board/topic/zynq/zynq-topic-miamilite/ps7_init_gpl.c @@ -49,7 +49,7 @@ static unsigned long ps7_clock_init_data_3_0[] = { EMIT_MASKWRITE(0xF8000158, 0x00003F33U, 0x00000601U), EMIT_MASKWRITE(0xF8000168, 0x00003F31U, 0x00000601U), EMIT_MASKWRITE(0xF8000170, 0x03F03F30U, 0x00100C00U), - EMIT_MASKWRITE(0xF8000180, 0x03F03F30U, 0x00100C00U), + EMIT_MASKWRITE(0xF8000180, 0x03F03F30U, 0x00100800U), EMIT_MASKWRITE(0xF8000190, 0x03F03F30U, 0x00100600U), EMIT_MASKWRITE(0xF80001A0, 0x03F03F30U, 0x00101800U), EMIT_MASKWRITE(0xF80001C4, 0x00000001U, 0x00000001U), From dfbe492edef421de09617dc26805fc428440924e Mon Sep 17 00:00:00 2001 From: Mike Looijmans Date: Fri, 18 Oct 2019 07:34:13 +0200 Subject: [PATCH 75/79] board: zynqmp: Fix for wrong AMS setting by ROM A bug in the ZynqMP bootrom sets the PS_SYSMON_ANALOG_BUS register at 0xFFA50914 to the wrong value 0x3201. This causes the AMS to exchange the PS supply voltages 0 and 1. On Xilinx boards this is not noticeable since these are tied together, it's only really noticeable if banks 500 and 501 have different supplies. Xilinx' tech support reported this undocumented register to be the cause, and this patch applies a fix for all boards by programming the correct value. Signed-off-by: Mike Looijmans Signed-off-by: Michal Simek --- board/xilinx/zynqmp/zynqmp.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c index cb72914adb..a6cd41af1a 100644 --- a/board/xilinx/zynqmp/zynqmp.c +++ b/board/xilinx/zynqmp/zynqmp.c @@ -359,6 +359,9 @@ static int multi_boot(void) return 0; } +#define PS_SYSMON_ANALOG_BUS_VAL 0x3210 +#define PS_SYSMON_ANALOG_BUS_REG 0xFFA50914 + int board_init(void) { #if defined(CONFIG_ZYNQMP_FIRMWARE) @@ -378,6 +381,9 @@ int board_init(void) printf("EL Level:\tEL%d\n", current_el()); + /* Bug in ROM sets wrong value in this register */ + writel(PS_SYSMON_ANALOG_BUS_VAL, PS_SYSMON_ANALOG_BUS_REG); + #if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \ !defined(CONFIG_SPL_BUILD) || (defined(CONFIG_SPL_FPGA_SUPPORT) && \ defined(CONFIG_SPL_BUILD)) From 39c5cf0e7082fd822b6bf80e896caf8be5a6a10e Mon Sep 17 00:00:00 2001 From: Mike Looijmans Date: Thu, 6 Jun 2019 09:47:41 +0200 Subject: [PATCH 76/79] topic: zynqmp: Add support for zynqmp-xilinx-xdp platform XDP - Xilinx Drone Platform is a board for drones or other UAV. Pinmux the SD card by default, and if the SD card detect line is high (inactive) then pinmux the SD1 interface to EMIO instead. SD is placed on extension card and shares connection with on board wife. That means that when SD card is present in the board wifi can't be used. There seems to be an issue with DDR access from PL at 2400MT/s, after updating the PMU and ATF firmware this is causing extremely slow DDR access. Reducing the DDR speed from 2400 to 2133 appears to solve that issue, even though the hardware has proven to be 2400 capable. Signed-off-by: Mike Looijmans Signed-off-by: Michal Simek --- arch/arm/dts/Makefile | 1 + .../zynqmp-topic-miamimp-xilinx-xdp-v1r1.dts | 117 ++ .../psu_init_gpl.c | 1038 +++++++++++++++++ configs/xilinx_zynqmp_virt_defconfig | 2 +- 4 files changed, 1157 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/zynqmp-topic-miamimp-xilinx-xdp-v1r1.dts create mode 100644 board/xilinx/zynqmp/zynqmp-topic-miamimp-xilinx-xdp-v1r1/psu_init_gpl.c diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 9900b44274..aa10bb6b35 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -280,6 +280,7 @@ dtb-$(CONFIG_ARCH_ZYNQMP) += \ zynqmp-mini-emmc1.dtb \ zynqmp-mini-nand.dtb \ zynqmp-mini-qspi.dtb \ + zynqmp-topic-miamimp-xilinx-xdp-v1r1.dtb \ zynqmp-zcu100-revC.dtb \ zynqmp-zcu102-revA.dtb \ zynqmp-zcu102-revB.dtb \ diff --git a/arch/arm/dts/zynqmp-topic-miamimp-xilinx-xdp-v1r1.dts b/arch/arm/dts/zynqmp-topic-miamimp-xilinx-xdp-v1r1.dts new file mode 100644 index 0000000000..0ee8c62f6b --- /dev/null +++ b/arch/arm/dts/zynqmp-topic-miamimp-xilinx-xdp-v1r1.dts @@ -0,0 +1,117 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * dts file for Topic XDP (Xilinx Drone Platform) + * + * (C) Copyright 2016, Topic Embedded Products BV + * Mike Looijmans + */ + +/dts-v1/; + +#include "zynqmp.dtsi" +#include "zynqmp-clk-ccf.dtsi" +#include +#include + +/ { + model = "Topic Miamimp ZynqMP XDP v1r1"; + compatible = "topic,miamimp-xdp-v1r1", "topic,miamimp-xdp", + "topic,miamimp", "xlnx,zynqmp"; + + aliases { + gpio0 = &gpio; + i2c0 = &i2c0; + i2c1 = &i2c1; + mmc0 = &sdhci0; + mmc1 = &sdhci1; + rtc0 = &rtc; + serial0 = &uart1; + serial1 = &uart0; + serial2 = &dcc; + spi0 = &qspi; + usb0 = &usb0; + }; + + chosen { + bootargs = "earlycon"; + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>; + }; +}; + +&dcc { + status = "okay"; +}; + +&gpio { + status = "okay"; +}; + +&gpu { + status = "okay"; +}; + +&qspi { + status = "okay"; + is-dual = <1>; + flash@0 { + compatible = "st,m25p80", "n25q256a"; + m25p,fast-read; + reg = <0x0>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <4>; + spi-max-frequency = <166000000>; + #address-cells = <1>; + #size-cells = <1>; + is-dual = <1>; + partition@0 { + label = "qspi-boot-bin"; + reg = <0x00000 0x60000>; + }; + partition@60000 { + label = "qspi-u-boot-itb"; + reg = <0x60000 0x100000>; + }; + partition@160000 { + label = "qspi-u-boot-env"; + reg = <0x160000 0x20000>; + }; + partition@200000 { + label = "qspi-rootfs"; + reg = <0x200000 0x1e00000>; + }; + }; +}; + +&rtc { + status = "okay"; +}; + +/* eMMC device */ +&sdhci0 { + status = "okay"; + non-removable; + disable-wp; /* We don't have a write-protect detection */ + bus-width = <8>; + xlnx,mio_bank = <0>; +}; + +/* SD1 with level shifter */ +&sdhci1 { + status = "okay"; + xlnx,mio_bank = <1>; + disable-wp; /* We don't have a write-protect detection */ + bus-width = <4>; +}; + +&uart0 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; diff --git a/board/xilinx/zynqmp/zynqmp-topic-miamimp-xilinx-xdp-v1r1/psu_init_gpl.c b/board/xilinx/zynqmp/zynqmp-topic-miamimp-xilinx-xdp-v1r1/psu_init_gpl.c new file mode 100644 index 0000000000..dbed7b789e --- /dev/null +++ b/board/xilinx/zynqmp/zynqmp-topic-miamimp-xilinx-xdp-v1r1/psu_init_gpl.c @@ -0,0 +1,1038 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (c) Copyright 2015 Xilinx, Inc. All rights reserved. + */ + +#include +#include + +static unsigned long psu_pll_init_data(void) +{ + psu_mask_write(0xFF5E0034, 0xFE7FEDEFU, 0x7E4B0C82U); + psu_mask_write(0xFF5E0030, 0x00717F00U, 0x00015A00U); + psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000008U); + psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000001U); + psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000000U); + mask_poll(0xFF5E0040, 0x00000002U); + psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000000U); + psu_mask_write(0xFF5E0048, 0x00003F00U, 0x00000300U); + psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01012300U); + psu_mask_write(0xFF5E0024, 0xFE7FEDEFU, 0x7E4B0C62U); + psu_mask_write(0xFF5E0020, 0x00717F00U, 0x00014800U); + psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000008U); + psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000001U); + psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000000U); + mask_poll(0xFF5E0040, 0x00000001U); + psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000000U); + psu_mask_write(0xFF5E0044, 0x00003F00U, 0x00000300U); + psu_mask_write(0xFD1A0024, 0xFE7FEDEFU, 0x7E4B0C62U); + psu_mask_write(0xFD1A0020, 0x00717F00U, 0x00014800U); + psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000008U); + psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000000U); + mask_poll(0xFD1A0044, 0x00000001U); + psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000000U); + psu_mask_write(0xFD1A0048, 0x00003F00U, 0x00000300U); + psu_mask_write(0xFD1A0030, 0xFE7FEDEFU, 0x7E4B0C62U); + psu_mask_write(0xFD1A002C, 0x00717F00U, 0x00014000U); + psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000008U); + psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000000U); + mask_poll(0xFD1A0044, 0x00000002U); + psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000000U); + psu_mask_write(0xFD1A004C, 0x00003F00U, 0x00000200U); + psu_mask_write(0xFD1A003C, 0xFE7FEDEFU, 0x7E4B0C82U); + psu_mask_write(0xFD1A0038, 0x00717F00U, 0x00015A00U); + psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000008U); + psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000000U); + mask_poll(0xFD1A0044, 0x00000004U); + psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000000U); + psu_mask_write(0xFD1A0050, 0x00003F00U, 0x00000300U); + + return 1; +} + +static unsigned long psu_clock_init_data(void) +{ + psu_mask_write(0xFF5E0060, 0x023F3F07U, 0x02010602U); + psu_mask_write(0xFF5E004C, 0x023F3F07U, 0x02013C00U); + psu_mask_write(0xFF5E0068, 0x013F3F07U, 0x01010400U); + psu_mask_write(0xFF5E006C, 0x013F3F07U, 0x01010600U); + psu_mask_write(0xFF5E0070, 0x013F3F07U, 0x01010600U); + psu_mask_write(0xFF18030C, 0x00070007U, 0x00000000U); + psu_mask_write(0xFF5E0074, 0x013F3F07U, 0x01010C00U); + psu_mask_write(0xFF5E0078, 0x013F3F07U, 0x01010C00U); + psu_mask_write(0xFF5E0120, 0x013F3F07U, 0x01010C00U); + psu_mask_write(0xFF5E0124, 0x013F3F07U, 0x01010C00U); + psu_mask_write(0xFF5E007C, 0x013F3F07U, 0x01010600U); + psu_mask_write(0xFF5E0080, 0x013F3F07U, 0x01010600U); + psu_mask_write(0xFF5E0090, 0x01003F07U, 0x01000300U); + psu_mask_write(0xFF5E009C, 0x01003F07U, 0x01000502U); + psu_mask_write(0xFF5E00A4, 0x01003F07U, 0x01000600U); + psu_mask_write(0xFF5E00A8, 0x01003F07U, 0x01000302U); + psu_mask_write(0xFF5E00AC, 0x01003F07U, 0x01000C02U); + psu_mask_write(0xFF5E00B0, 0x01003F07U, 0x01000600U); + psu_mask_write(0xFF5E00B8, 0x01003F07U, 0x01000103U); + psu_mask_write(0xFF5E00C0, 0x013F3F07U, 0x01010C00U); + psu_mask_write(0xFF5E00C4, 0x013F3F07U, 0x01010800U); + psu_mask_write(0xFF5E00C8, 0x013F3F07U, 0x01010600U); + psu_mask_write(0xFF5E00CC, 0x013F3F07U, 0x01010400U); + psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01011802U); + psu_mask_write(0xFF5E0104, 0x00000007U, 0x00000001U); + psu_mask_write(0xFF5E0128, 0x01003F07U, 0x01000C00U); + psu_mask_write(0xFD1A00B4, 0x01003F07U, 0x01000202U); + psu_mask_write(0xFD1A0060, 0x03003F07U, 0x03000100U); + psu_mask_write(0xFD1A0068, 0x01003F07U, 0x01000200U); + psu_mask_write(0xFD1A0080, 0x00003F07U, 0x00000200U); + psu_mask_write(0xFD1A0084, 0x07003F07U, 0x07000100U); + psu_mask_write(0xFD1A00B8, 0x01003F07U, 0x01000200U); + psu_mask_write(0xFD1A00BC, 0x01003F07U, 0x01000200U); + psu_mask_write(0xFD1A00C0, 0x01003F07U, 0x01000203U); + psu_mask_write(0xFD1A00C4, 0x01003F07U, 0x01000402U); + psu_mask_write(0xFD1A00F8, 0x00003F07U, 0x00000200U); + psu_mask_write(0xFF180380, 0x000000FFU, 0x00000000U); + psu_mask_write(0xFD610100, 0x00000001U, 0x00000000U); + psu_mask_write(0xFF180300, 0x00000001U, 0x00000000U); + psu_mask_write(0xFF410050, 0x00000001U, 0x00000000U); + + return 1; +} + +static unsigned long psu_ddr_init_data(void) +{ + psu_mask_write(0xFD1A0108, 0x00000008U, 0x00000008U); + psu_mask_write(0xFD070000, 0xE30FBE3DU, 0x81040010U); + psu_mask_write(0xFD070010, 0x8000F03FU, 0x00000030U); + psu_mask_write(0xFD070020, 0x000003F3U, 0x00000200U); + psu_mask_write(0xFD070024, 0xFFFFFFFFU, 0x00800000U); + psu_mask_write(0xFD070030, 0x0000007FU, 0x00000000U); + psu_mask_write(0xFD070034, 0x00FFFF1FU, 0x00408410U); + psu_mask_write(0xFD070050, 0x00F1F1F4U, 0x00210000U); + psu_mask_write(0xFD070054, 0x0FFF0FFFU, 0x00000000U); + psu_mask_write(0xFD070060, 0x00000073U, 0x00000001U); + psu_mask_write(0xFD070064, 0x0FFF83FFU, 0x008180BBU); + psu_mask_write(0xFD070070, 0x00000017U, 0x00000010U); + psu_mask_write(0xFD070074, 0x00000003U, 0x00000000U); + psu_mask_write(0xFD0700C4, 0x3F000391U, 0x10000200U); + psu_mask_write(0xFD0700C8, 0x01FF1F3FU, 0x0040051FU); + psu_mask_write(0xFD0700D0, 0xC3FF0FFFU, 0x00020106U); + psu_mask_write(0xFD0700D4, 0x01FF7F0FU, 0x00020000U); + psu_mask_write(0xFD0700D8, 0x0000FF0FU, 0x00002305U); + psu_mask_write(0xFD0700DC, 0xFFFFFFFFU, 0x07340301U); + psu_mask_write(0xFD0700E0, 0xFFFFFFFFU, 0x00200200U); + psu_mask_write(0xFD0700E4, 0x00FF03FFU, 0x00210004U); + psu_mask_write(0xFD0700E8, 0xFFFFFFFFU, 0x000006C0U); + psu_mask_write(0xFD0700EC, 0xFFFF0000U, 0x08190000U); + psu_mask_write(0xFD0700F0, 0x0000003FU, 0x00000010U); + psu_mask_write(0xFD0700F4, 0x00000FFFU, 0x0000066FU); + psu_mask_write(0xFD070100, 0x7F3F7F3FU, 0x11102412U); + psu_mask_write(0xFD070104, 0x001F1F7FU, 0x0004041AU); + psu_mask_write(0xFD070108, 0x3F3F3F3FU, 0x0708060DU); + psu_mask_write(0xFD07010C, 0x3FF3F3FFU, 0x0050400CU); + psu_mask_write(0xFD070110, 0x1F0F0F1FU, 0x08030409U); + psu_mask_write(0xFD070114, 0x0F0F3F1FU, 0x06060403U); + psu_mask_write(0xFD070118, 0x0F0F000FU, 0x01010004U); + psu_mask_write(0xFD07011C, 0x00000F0FU, 0x00000606U); + psu_mask_write(0xFD070120, 0x7F7F7F7FU, 0x04040D07U); + psu_mask_write(0xFD070124, 0x40070F3FU, 0x0002030BU); + psu_mask_write(0xFD07012C, 0x7F1F031FU, 0x1207010EU); + psu_mask_write(0xFD070130, 0x00030F1FU, 0x00020608U); + psu_mask_write(0xFD070180, 0xF7FF03FFU, 0x81000040U); + psu_mask_write(0xFD070184, 0x3FFFFFFFU, 0x020196E5U); + psu_mask_write(0xFD070190, 0x1FBFBF3FU, 0x048C820BU); + psu_mask_write(0xFD070194, 0xF31F0F0FU, 0x00030304U); + psu_mask_write(0xFD070198, 0x0FF1F1F1U, 0x07000101U); + psu_mask_write(0xFD07019C, 0x000000F1U, 0x00000021U); + psu_mask_write(0xFD0701A0, 0xC3FF03FFU, 0x00400003U); + psu_mask_write(0xFD0701A4, 0x00FF00FFU, 0x00C800FFU); + psu_mask_write(0xFD0701B0, 0x00000007U, 0x00000000U); + psu_mask_write(0xFD0701B4, 0x00003F3FU, 0x00000A09U); + psu_mask_write(0xFD0701C0, 0x00000007U, 0x00000001U); + psu_mask_write(0xFD070200, 0x0000001FU, 0x0000001FU); + psu_mask_write(0xFD070204, 0x001F1F1FU, 0x001F0909U); + psu_mask_write(0xFD070208, 0x0F0F0F0FU, 0x01010100U); + psu_mask_write(0xFD07020C, 0x0F0F0F0FU, 0x01010101U); + psu_mask_write(0xFD070210, 0x00000F0FU, 0x00000F0FU); + psu_mask_write(0xFD070214, 0x0F0F0F0FU, 0x070F0707U); + psu_mask_write(0xFD070218, 0x8F0F0F0FU, 0x07070707U); + psu_mask_write(0xFD07021C, 0x00000F0FU, 0x00000F0FU); + psu_mask_write(0xFD070220, 0x00001F1FU, 0x00001F01U); + psu_mask_write(0xFD070224, 0x0F0F0F0FU, 0x07070707U); + psu_mask_write(0xFD070228, 0x0F0F0F0FU, 0x07070707U); + psu_mask_write(0xFD07022C, 0x0000000FU, 0x00000007U); + psu_mask_write(0xFD070240, 0x0F1F0F7CU, 0x06000604U); + psu_mask_write(0xFD070244, 0x00003333U, 0x00000001U); + psu_mask_write(0xFD070250, 0x7FFF3F07U, 0x01002001U); + psu_mask_write(0xFD070264, 0xFF00FFFFU, 0x08000040U); + psu_mask_write(0xFD07026C, 0xFF00FFFFU, 0x08000040U); + psu_mask_write(0xFD070280, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD070284, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD070288, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD07028C, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD070290, 0x0000FFFFU, 0x00000000U); + psu_mask_write(0xFD070294, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD070300, 0x00000011U, 0x00000000U); + psu_mask_write(0xFD07030C, 0x80000033U, 0x00000000U); + psu_mask_write(0xFD070320, 0x00000001U, 0x00000000U); + psu_mask_write(0xFD070400, 0x00000111U, 0x00000001U); + psu_mask_write(0xFD070404, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD070408, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD070490, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD070494, 0x0033000FU, 0x0020000BU); + psu_mask_write(0xFD070498, 0x07FF07FFU, 0x00000000U); + psu_mask_write(0xFD0704B4, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD0704B8, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD070540, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD070544, 0x03330F0FU, 0x02000B03U); + psu_mask_write(0xFD070548, 0x07FF07FFU, 0x00000000U); + psu_mask_write(0xFD070564, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD070568, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD0705F0, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD0705F4, 0x03330F0FU, 0x02000B03U); + psu_mask_write(0xFD0705F8, 0x07FF07FFU, 0x00000000U); + psu_mask_write(0xFD070614, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD070618, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD0706A0, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD0706A4, 0x0033000FU, 0x00100003U); + psu_mask_write(0xFD0706A8, 0x07FF07FFU, 0x0000004FU); + psu_mask_write(0xFD0706AC, 0x0033000FU, 0x00100003U); + psu_mask_write(0xFD0706B0, 0x000007FFU, 0x0000004FU); + psu_mask_write(0xFD0706C4, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD0706C8, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD070750, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD070754, 0x0033000FU, 0x00100003U); + psu_mask_write(0xFD070758, 0x07FF07FFU, 0x0000004FU); + psu_mask_write(0xFD07075C, 0x0033000FU, 0x00100003U); + psu_mask_write(0xFD070760, 0x000007FFU, 0x0000004FU); + psu_mask_write(0xFD070774, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD070778, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD070800, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD070804, 0x0033000FU, 0x00100003U); + psu_mask_write(0xFD070808, 0x07FF07FFU, 0x0000004FU); + psu_mask_write(0xFD07080C, 0x0033000FU, 0x00100003U); + psu_mask_write(0xFD070810, 0x000007FFU, 0x0000004FU); + psu_mask_write(0xFD070F04, 0x000001FFU, 0x00000000U); + psu_mask_write(0xFD070F08, 0x000000FFU, 0x00000000U); + psu_mask_write(0xFD070F0C, 0x000001FFU, 0x00000010U); + psu_mask_write(0xFD070F10, 0x000000FFU, 0x0000000FU); + psu_mask_write(0xFD072190, 0x1FBFBF3FU, 0x07828002U); + psu_mask_write(0xFD1A0108, 0x0000000CU, 0x00000000U); + psu_mask_write(0xFD080010, 0xFFFFFFFFU, 0x07001E00U); + psu_mask_write(0xFD080018, 0xFFFFFFFFU, 0x00F10010U); + psu_mask_write(0xFD08001C, 0xFFFFFFFFU, 0x55AA5480U); + psu_mask_write(0xFD080024, 0xFFFFFFFFU, 0x010100F4U); + psu_mask_write(0xFD080040, 0xFFFFFFFFU, 0x42C21590U); + psu_mask_write(0xFD080044, 0xFFFFFFFFU, 0xD05512C0U); + psu_mask_write(0xFD080068, 0xFFFFFFFFU, 0x01100000U); + psu_mask_write(0xFD080090, 0xFFFFFFFFU, 0x02A04161U); + psu_mask_write(0xFD0800C0, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD0800C4, 0xFFFFFFFFU, 0x000000E0U); + psu_mask_write(0xFD080100, 0xFFFFFFFFU, 0x0800040CU); + psu_mask_write(0xFD080110, 0xFFFFFFFFU, 0x07241008U); + psu_mask_write(0xFD080114, 0xFFFFFFFFU, 0x28200008U); + psu_mask_write(0xFD080118, 0xFFFFFFFFU, 0x000F0300U); + psu_mask_write(0xFD08011C, 0xFFFFFFFFU, 0x83000800U); + psu_mask_write(0xFD080120, 0xFFFFFFFFU, 0x01762B07U); + psu_mask_write(0xFD080124, 0xFFFFFFFFU, 0x00331008U); + psu_mask_write(0xFD080128, 0xFFFFFFFFU, 0x00000E10U); + psu_mask_write(0xFD080140, 0xFFFFFFFFU, 0x08400020U); + psu_mask_write(0xFD080144, 0xFFFFFFFFU, 0x00000C80U); + psu_mask_write(0xFD080150, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080154, 0xFFFFFFFFU, 0x00000200U); + psu_mask_write(0xFD080180, 0xFFFFFFFFU, 0x00000634U); + psu_mask_write(0xFD080184, 0xFFFFFFFFU, 0x00000301U); + psu_mask_write(0xFD080188, 0xFFFFFFFFU, 0x00000020U); + psu_mask_write(0xFD08018C, 0xFFFFFFFFU, 0x00000200U); + psu_mask_write(0xFD080190, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080194, 0xFFFFFFFFU, 0x000006C0U); + psu_mask_write(0xFD080198, 0xFFFFFFFFU, 0x00000819U); + psu_mask_write(0xFD0801AC, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD0801B0, 0xFFFFFFFFU, 0x0000004DU); + psu_mask_write(0xFD0801B4, 0xFFFFFFFFU, 0x00000008U); + psu_mask_write(0xFD0801B8, 0xFFFFFFFFU, 0x0000004DU); + psu_mask_write(0xFD0801D8, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080200, 0xFFFFFFFFU, 0x800091C7U); + psu_mask_write(0xFD080204, 0xFFFFFFFFU, 0x00010236U); + psu_mask_write(0xFD080240, 0xFFFFFFFFU, 0x00141054U); + psu_mask_write(0xFD080250, 0xFFFFFFFFU, 0x00088000U); + psu_mask_write(0xFD080414, 0xFFFFFFFFU, 0x12341000U); + psu_mask_write(0xFD0804F4, 0xFFFFFFFFU, 0x00000005U); + psu_mask_write(0xFD080500, 0xFFFFFFFFU, 0x30000028U); + psu_mask_write(0xFD080508, 0xFFFFFFFFU, 0x0A000000U); + psu_mask_write(0xFD08050C, 0xFFFFFFFFU, 0x00000009U); + psu_mask_write(0xFD080510, 0xFFFFFFFFU, 0x0A000000U); + psu_mask_write(0xFD080520, 0xFFFFFFFFU, 0x0300B0CEU); + psu_mask_write(0xFD080528, 0xFFFFFFFFU, 0xF9032019U); + psu_mask_write(0xFD08052C, 0xFFFFFFFFU, 0x07F001E3U); + psu_mask_write(0xFD080544, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080548, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080558, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD08055C, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080560, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080564, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080680, 0xFFFFFFFFU, 0x008AAA58U); + psu_mask_write(0xFD080684, 0xFFFFFFFFU, 0x000079DDU); + psu_mask_write(0xFD080694, 0xFFFFFFFFU, 0x01E10210U); + psu_mask_write(0xFD080698, 0xFFFFFFFFU, 0x01E10000U); + psu_mask_write(0xFD0806A4, 0xFFFFFFFFU, 0x00087BDBU); + psu_mask_write(0xFD080700, 0xFFFFFFFFU, 0x40800604U); + psu_mask_write(0xFD080704, 0xFFFFFFFFU, 0x00007FFFU); + psu_mask_write(0xFD08070C, 0xFFFFFFFFU, 0x3F000008U); + psu_mask_write(0xFD080710, 0xFFFFFFFFU, 0x0E00B03CU); + psu_mask_write(0xFD080714, 0xFFFFFFFFU, 0x09094F4FU); + psu_mask_write(0xFD080718, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080800, 0xFFFFFFFFU, 0x40800604U); + psu_mask_write(0xFD080804, 0xFFFFFFFFU, 0x00007FFFU); + psu_mask_write(0xFD08080C, 0xFFFFFFFFU, 0x3F000008U); + psu_mask_write(0xFD080810, 0xFFFFFFFFU, 0x0E00B03CU); + psu_mask_write(0xFD080814, 0xFFFFFFFFU, 0x09094F4FU); + psu_mask_write(0xFD080818, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080900, 0xFFFFFFFFU, 0x40800604U); + psu_mask_write(0xFD080904, 0xFFFFFFFFU, 0x00007FFFU); + psu_mask_write(0xFD08090C, 0xFFFFFFFFU, 0x3F000008U); + psu_mask_write(0xFD080910, 0xFFFFFFFFU, 0x0E00B004U); + psu_mask_write(0xFD080914, 0xFFFFFFFFU, 0x09094F4FU); + psu_mask_write(0xFD080918, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080A00, 0xFFFFFFFFU, 0x40800604U); + psu_mask_write(0xFD080A04, 0xFFFFFFFFU, 0x00007FFFU); + psu_mask_write(0xFD080A0C, 0xFFFFFFFFU, 0x3F000008U); + psu_mask_write(0xFD080A10, 0xFFFFFFFFU, 0x0E00B004U); + psu_mask_write(0xFD080A14, 0xFFFFFFFFU, 0x09094F4FU); + psu_mask_write(0xFD080A18, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080B00, 0xFFFFFFFFU, 0x40800604U); + psu_mask_write(0xFD080B04, 0xFFFFFFFFU, 0x00007FFFU); + psu_mask_write(0xFD080B08, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080B0C, 0xFFFFFFFFU, 0x3F000008U); + psu_mask_write(0xFD080B10, 0xFFFFFFFFU, 0x0E00B004U); + psu_mask_write(0xFD080B14, 0xFFFFFFFFU, 0x09094F4FU); + psu_mask_write(0xFD080B18, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080C00, 0xFFFFFFFFU, 0x40800604U); + psu_mask_write(0xFD080C04, 0xFFFFFFFFU, 0x00007FFFU); + psu_mask_write(0xFD080C08, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080C0C, 0xFFFFFFFFU, 0x3F000008U); + psu_mask_write(0xFD080C10, 0xFFFFFFFFU, 0x0E00B03CU); + psu_mask_write(0xFD080C14, 0xFFFFFFFFU, 0x09094F4FU); + psu_mask_write(0xFD080C18, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080D00, 0xFFFFFFFFU, 0x40800604U); + psu_mask_write(0xFD080D04, 0xFFFFFFFFU, 0x00007FFFU); + psu_mask_write(0xFD080D08, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080D0C, 0xFFFFFFFFU, 0x3F000008U); + psu_mask_write(0xFD080D10, 0xFFFFFFFFU, 0x0E00B004U); + psu_mask_write(0xFD080D14, 0xFFFFFFFFU, 0x09094F4FU); + psu_mask_write(0xFD080D18, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080E00, 0xFFFFFFFFU, 0x40800604U); + psu_mask_write(0xFD080E04, 0xFFFFFFFFU, 0x00007FFFU); + psu_mask_write(0xFD080E08, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080E0C, 0xFFFFFFFFU, 0x3F000008U); + psu_mask_write(0xFD080E10, 0xFFFFFFFFU, 0x0E00B03CU); + psu_mask_write(0xFD080E14, 0xFFFFFFFFU, 0x09094F4FU); + psu_mask_write(0xFD080E18, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080F00, 0xFFFFFFFFU, 0x80803660U); + psu_mask_write(0xFD080F04, 0xFFFFFFFFU, 0x55556000U); + psu_mask_write(0xFD080F08, 0xFFFFFFFFU, 0xAAAAAAAAU); + psu_mask_write(0xFD080F0C, 0xFFFFFFFFU, 0x0029A4A4U); + psu_mask_write(0xFD080F10, 0xFFFFFFFFU, 0x0C00B000U); + psu_mask_write(0xFD080F14, 0xFFFFFFFFU, 0x09094F4FU); + psu_mask_write(0xFD080F18, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD081400, 0xFFFFFFFFU, 0x2A019FFEU); + psu_mask_write(0xFD081404, 0xFFFFFFFFU, 0x01100000U); + psu_mask_write(0xFD08141C, 0xFFFFFFFFU, 0x01264300U); + psu_mask_write(0xFD08142C, 0xFFFFFFFFU, 0x00041800U); + psu_mask_write(0xFD081430, 0xFFFFFFFFU, 0x70800000U); + psu_mask_write(0xFD081440, 0xFFFFFFFFU, 0x2A019FFEU); + psu_mask_write(0xFD081444, 0xFFFFFFFFU, 0x01100000U); + psu_mask_write(0xFD08145C, 0xFFFFFFFFU, 0x01264300U); + psu_mask_write(0xFD08146C, 0xFFFFFFFFU, 0x00041800U); + psu_mask_write(0xFD081470, 0xFFFFFFFFU, 0x70800000U); + psu_mask_write(0xFD081480, 0xFFFFFFFFU, 0x2A019FFEU); + psu_mask_write(0xFD081484, 0xFFFFFFFFU, 0x01100000U); + psu_mask_write(0xFD08149C, 0xFFFFFFFFU, 0x01264300U); + psu_mask_write(0xFD0814AC, 0xFFFFFFFFU, 0x00041800U); + psu_mask_write(0xFD0814B0, 0xFFFFFFFFU, 0x70800000U); + psu_mask_write(0xFD0814C0, 0xFFFFFFFFU, 0x2A019FFEU); + psu_mask_write(0xFD0814C4, 0xFFFFFFFFU, 0x01100000U); + psu_mask_write(0xFD0814DC, 0xFFFFFFFFU, 0x01264300U); + psu_mask_write(0xFD0814EC, 0xFFFFFFFFU, 0x00041800U); + psu_mask_write(0xFD0814F0, 0xFFFFFFFFU, 0x70800000U); + psu_mask_write(0xFD081500, 0xFFFFFFFFU, 0x15019FFEU); + psu_mask_write(0xFD081504, 0xFFFFFFFFU, 0x21100000U); + psu_mask_write(0xFD08151C, 0xFFFFFFFFU, 0x01266300U); + psu_mask_write(0xFD08152C, 0xFFFFFFFFU, 0x00041800U); + psu_mask_write(0xFD081530, 0xFFFFFFFFU, 0x70400000U); + psu_mask_write(0xFD0817DC, 0xFFFFFFFFU, 0x012643C4U); + + return 1; +} + +static unsigned long psu_ddr_qos_init_data(void) +{ + psu_mask_write(0xFD360008, 0x0000000FU, 0x00000000U); + psu_mask_write(0xFD36001C, 0x0000000FU, 0x00000000U); + psu_mask_write(0xFD370008, 0x0000000FU, 0x00000000U); + psu_mask_write(0xFD37001C, 0x0000000FU, 0x00000000U); + psu_mask_write(0xFD380008, 0x0000000FU, 0x00000000U); + psu_mask_write(0xFD38001C, 0x0000000FU, 0x00000000U); + psu_mask_write(0xFD390008, 0x0000000FU, 0x00000000U); + psu_mask_write(0xFD39001C, 0x0000000FU, 0x00000000U); + psu_mask_write(0xFD3A0008, 0x0000000FU, 0x00000000U); + psu_mask_write(0xFD3A001C, 0x0000000FU, 0x00000000U); + psu_mask_write(0xFD3B0008, 0x0000000FU, 0x00000000U); + psu_mask_write(0xFD3B001C, 0x0000000FU, 0x00000000U); + psu_mask_write(0xFF9B0008, 0x0000000FU, 0x00000000U); + psu_mask_write(0xFF9B001C, 0x0000000FU, 0x00000000U); + + return 1; +} + +static unsigned long psu_mio_init_data(void) +{ + psu_mask_write(0xFF180000, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180004, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180008, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF18000C, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180010, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180014, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180018, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF18001C, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180020, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180024, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180028, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF18002C, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180030, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180034, 0x000000FEU, 0x00000008U); + psu_mask_write(0xFF180038, 0x000000FEU, 0x00000008U); + psu_mask_write(0xFF18003C, 0x000000FEU, 0x00000008U); + psu_mask_write(0xFF180040, 0x000000FEU, 0x00000008U); + psu_mask_write(0xFF180044, 0x000000FEU, 0x00000008U); + psu_mask_write(0xFF180048, 0x000000FEU, 0x00000008U); + psu_mask_write(0xFF18004C, 0x000000FEU, 0x00000008U); + psu_mask_write(0xFF180050, 0x000000FEU, 0x00000008U); + psu_mask_write(0xFF180054, 0x000000FEU, 0x00000008U); + psu_mask_write(0xFF180058, 0x000000FEU, 0x00000008U); + psu_mask_write(0xFF18005C, 0x000000FEU, 0x00000008U); + psu_mask_write(0xFF180060, 0x000000FEU, 0x000000C0U); + psu_mask_write(0xFF180064, 0x000000FEU, 0x000000C0U); + psu_mask_write(0xFF180068, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF18006C, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180070, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180074, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180078, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF18007C, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180080, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180084, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180088, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF18008C, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180090, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180094, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180098, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF18009C, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF1800A0, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF1800A4, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF1800A8, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF1800AC, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF1800B0, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF1800B4, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF1800B8, 0x000000FEU, 0x00000010U); + psu_mask_write(0xFF1800BC, 0x000000FEU, 0x00000010U); + psu_mask_write(0xFF1800C0, 0x000000FEU, 0x00000010U); + psu_mask_write(0xFF1800C4, 0x000000FEU, 0x00000010U); + psu_mask_write(0xFF1800C8, 0x000000FEU, 0x00000010U); + psu_mask_write(0xFF1800CC, 0x000000FEU, 0x00000010U); + psu_mask_write(0xFF1800D0, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF1800D4, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF1800D8, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF1800DC, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF1800E0, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF1800E4, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF1800E8, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF1800EC, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF1800F0, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF1800F4, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF1800F8, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF1800FC, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF180100, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180104, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180108, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF18010C, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180110, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180114, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180118, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF18011C, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180120, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180124, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180128, 0x000000FEU, 0x00000040U); + psu_mask_write(0xFF18012C, 0x000000FEU, 0x00000040U); + psu_mask_write(0xFF180130, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180134, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180204, 0xFFFFFFFFU, 0x1A000000U); + psu_mask_write(0xFF180208, 0xFFFFFFFFU, 0x00B02000U); + psu_mask_write(0xFF18020C, 0x00003FFFU, 0x00000000U); + psu_mask_write(0xFF180138, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF18013C, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180140, 0x03FFFFFFU, 0x023FEF1EU); + psu_mask_write(0xFF180148, 0x03FFFFFFU, 0x02A00F1EU); + psu_mask_write(0xFF18014C, 0x03FFFFFFU, 0x01001FFFU); + psu_mask_write(0xFF180144, 0x02A00F1EU, 0x02A00F1EU); + psu_mask_write(0xFF180154, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180158, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF18015C, 0x03FFFFFFU, 0x01FFFFFFU); + psu_mask_write(0xFF180160, 0x01FFFFFFU, 0x01FFFFFFU); + psu_mask_write(0xFF180164, 0x03FFFFFFU, 0x03FFF7FFU); + psu_mask_write(0xFF180168, 0x03FFFFFFU, 0x0007FFF9U); + psu_mask_write(0xFF180170, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180174, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180178, 0x03FFFFFFU, 0x03FEDFBFU); + psu_mask_write(0xFF18017C, 0x01FFFFFFU, 0x01FFFFFFU); + psu_mask_write(0xFF180180, 0x03FFFFFFU, 0x01FFFFFFU); + psu_mask_write(0xFF180184, 0x03FFFFFFU, 0x03FFFFF4U); + psu_mask_write(0xFF180404, 0x00000003U, 0x00000000U); + psu_mask_write(0xFF180200, 0x0000000FU, 0x00000000U); + + return 1; +} + +static unsigned long psu_peripherals_pre_init_data(void) +{ + psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01012302U); + psu_mask_write(0xFF5E0238, 0x00000001U, 0x00000001U); + + return 1; +} + +static unsigned long psu_peripherals_init_data(void) +{ + psu_mask_write(0xFD1A0100, 0x000E807CU, 0x00000000U); + psu_mask_write(0xFF5E0238, 0x001A0000U, 0x00000000U); + psu_mask_write(0xFF5E023C, 0x0093C018U, 0x00000000U); + psu_mask_write(0xFF5E0238, 0x00000001U, 0x00000000U); + psu_mask_write(0xFF180390, 0x00000004U, 0x00000000U); + psu_mask_write(0xFF5E023C, 0x00000400U, 0x00000000U); + psu_mask_write(0xFF5E0238, 0x00000060U, 0x00000000U); + psu_mask_write(0xFF180310, 0x00008001U, 0x00000001U); + psu_mask_write(0xFF180320, 0x33843384U, 0x00801284U); + psu_mask_write(0xFF18031C, 0x00007FFEU, 0x00006450U); + psu_mask_write(0xFF180358, 0x00080000U, 0x00080000U); + psu_mask_write(0xFF18031C, 0x7FFE0000U, 0x64500000U); + psu_mask_write(0xFF180358, 0x00000008U, 0x00000008U); + psu_mask_write(0xFF180324, 0x000003C0U, 0x00000000U); + psu_mask_write(0xFF180324, 0x03C00000U, 0x00000000U); + psu_mask_write(0xFF5E0238, 0x00000600U, 0x00000000U); + psu_mask_write(0xFF5E0238, 0x00008000U, 0x00000000U); + psu_mask_write(0xFF5E0238, 0x00000018U, 0x00000000U); + psu_mask_write(0xFF5E0238, 0x00007800U, 0x00000000U); + psu_mask_write(0xFF5E0238, 0x00000006U, 0x00000000U); + psu_mask_write(0xFF000034, 0x000000FFU, 0x00000005U); + psu_mask_write(0xFF000018, 0x0000FFFFU, 0x0000008FU); + psu_mask_write(0xFF000000, 0x000001FFU, 0x00000017U); + psu_mask_write(0xFF000004, 0x000003FFU, 0x00000020U); + psu_mask_write(0xFF010034, 0x000000FFU, 0x00000005U); + psu_mask_write(0xFF010018, 0x0000FFFFU, 0x0000008FU); + psu_mask_write(0xFF010000, 0x000001FFU, 0x00000017U); + psu_mask_write(0xFF010004, 0x000003FFU, 0x00000020U); + psu_mask_write(0xFF5E0238, 0x00040000U, 0x00000000U); + psu_mask_write(0xFF4B0024, 0x000000FFU, 0x000000FFU); + psu_mask_write(0xFFCA5000, 0x00001FFFU, 0x00000000U); + psu_mask_write(0xFD5C0060, 0x000F000FU, 0x00000000U); + psu_mask_write(0xFFA60040, 0x80000000U, 0x80000000U); + psu_mask_write(0xFF260020, 0xFFFFFFFFU, 0x05F5DD18U); + psu_mask_write(0xFF260000, 0x00000001U, 0x00000001U); + psu_mask_write(0xFF0A0284, 0x03FFFFFFU, 0x00012000U); + psu_mask_write(0xFF0A0288, 0x03FFFFFFU, 0x00012000U); + psu_mask_write(0xFF0A0010, 0xFFFFFFFFU, 0xDFFF2000U); + mask_delay(1); + psu_mask_write(0xFF0A0010, 0xFFFFFFFFU, 0xDFFF0000U); + mask_delay(5); + psu_mask_write(0xFF0A0010, 0xFFFFFFFFU, 0xDFFF2000U); + psu_mask_write(0xFF0A0284, 0x03FFFFFFU, 0x00012000U); + psu_mask_write(0xFF0A0288, 0x03FFFFFFU, 0x00012000U); + psu_mask_write(0xFF0A0014, 0x03FF03FFU, 0x03FE0001U); + + mask_delay(1); + psu_mask_write(0xFF0A0014, 0x03FF03FFU, 0x03FE0000U); + + mask_delay(5); + psu_mask_write(0xFF0A0284, 0x03FFFFFFU, 0x00012000U); + psu_mask_write(0xFF0A0288, 0x03FFFFFFU, 0x00012000U); + psu_mask_write(0xFF0A0014, 0x03FF03FFU, 0x03FE0000U); + + return 1; +} + +static unsigned long psu_serdes_init_data(void) +{ + psu_mask_write(0xFD410000, 0x0000001FU, 0x0000000DU); + psu_mask_write(0xFD410004, 0x0000001FU, 0x0000000DU); + psu_mask_write(0xFD410008, 0x0000001FU, 0x00000008U); + psu_mask_write(0xFD402860, 0x00000080U, 0x00000080U); + psu_mask_write(0xFD402864, 0x00000081U, 0x00000001U); + psu_mask_write(0xFD402868, 0x00000080U, 0x00000080U); + psu_mask_write(0xFD40A094, 0x00000010U, 0x00000010U); + psu_mask_write(0xFD40A368, 0x000000FFU, 0x00000038U); + psu_mask_write(0xFD40A36C, 0x00000007U, 0x00000003U); + psu_mask_write(0xFD40A370, 0x000000FFU, 0x000000F4U); + psu_mask_write(0xFD40A374, 0x000000FFU, 0x00000031U); + psu_mask_write(0xFD40A378, 0x000000FFU, 0x00000002U); + psu_mask_write(0xFD40A37C, 0x00000033U, 0x00000030U); + psu_mask_write(0xFD40906C, 0x00000003U, 0x00000003U); + psu_mask_write(0xFD4080F4, 0x00000003U, 0x00000003U); + psu_mask_write(0xFD4010CC, 0x00000020U, 0x00000020U); + psu_mask_write(0xFD4050CC, 0x00000020U, 0x00000020U); + psu_mask_write(0xFD4090CC, 0x00000020U, 0x00000020U); + psu_mask_write(0xFD401074, 0x00000010U, 0x00000010U); + psu_mask_write(0xFD405074, 0x00000010U, 0x00000010U); + psu_mask_write(0xFD409074, 0x00000010U, 0x00000010U); + psu_mask_write(0xFD40D074, 0x00000010U, 0x00000010U); + psu_mask_write(0xFD40189C, 0x00000080U, 0x00000080U); + psu_mask_write(0xFD4018F8, 0x000000FFU, 0x00000064U); + psu_mask_write(0xFD4018FC, 0x000000FFU, 0x00000064U); + psu_mask_write(0xFD401990, 0x000000FFU, 0x00000011U); + psu_mask_write(0xFD401924, 0x000000FFU, 0x00000004U); + psu_mask_write(0xFD401928, 0x000000FFU, 0x000000FEU); + psu_mask_write(0xFD401900, 0x000000FFU, 0x00000064U); + psu_mask_write(0xFD40192C, 0x000000FFU, 0x00000000U); + psu_mask_write(0xFD401980, 0x000000FFU, 0x000000FFU); + psu_mask_write(0xFD401914, 0x000000FFU, 0x000000F7U); + psu_mask_write(0xFD401918, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD401940, 0x000000FFU, 0x000000F7U); + psu_mask_write(0xFD401944, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD401994, 0x00000007U, 0x00000007U); + psu_mask_write(0xFD40589C, 0x00000080U, 0x00000080U); + psu_mask_write(0xFD4058F8, 0x000000FFU, 0x00000064U); + psu_mask_write(0xFD4058FC, 0x000000FFU, 0x00000064U); + psu_mask_write(0xFD405990, 0x000000FFU, 0x00000011U); + psu_mask_write(0xFD405924, 0x000000FFU, 0x00000004U); + psu_mask_write(0xFD405928, 0x000000FFU, 0x000000FEU); + psu_mask_write(0xFD405900, 0x000000FFU, 0x00000064U); + psu_mask_write(0xFD40592C, 0x000000FFU, 0x00000000U); + psu_mask_write(0xFD405980, 0x000000FFU, 0x000000FFU); + psu_mask_write(0xFD405914, 0x000000FFU, 0x000000F7U); + psu_mask_write(0xFD405918, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD405940, 0x000000FFU, 0x000000F7U); + psu_mask_write(0xFD405944, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD405994, 0x00000007U, 0x00000007U); + psu_mask_write(0xFD40989C, 0x00000080U, 0x00000080U); + psu_mask_write(0xFD4098F8, 0x000000FFU, 0x0000001AU); + psu_mask_write(0xFD4098FC, 0x000000FFU, 0x0000001AU); + psu_mask_write(0xFD409990, 0x000000FFU, 0x00000010U); + psu_mask_write(0xFD409924, 0x000000FFU, 0x000000FEU); + psu_mask_write(0xFD409928, 0x000000FFU, 0x00000000U); + psu_mask_write(0xFD409900, 0x000000FFU, 0x0000001AU); + psu_mask_write(0xFD40992C, 0x000000FFU, 0x00000000U); + psu_mask_write(0xFD409980, 0x000000FFU, 0x000000FFU); + psu_mask_write(0xFD409914, 0x000000FFU, 0x000000F7U); + psu_mask_write(0xFD409918, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD409940, 0x000000FFU, 0x000000F7U); + psu_mask_write(0xFD409944, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD409994, 0x00000007U, 0x00000007U); + psu_mask_write(0xFD40D994, 0x00000007U, 0x00000007U); + psu_mask_write(0xFD40107C, 0x0000000FU, 0x00000001U); + psu_mask_write(0xFD40507C, 0x0000000FU, 0x00000001U); + psu_mask_write(0xFD40907C, 0x0000000FU, 0x00000001U); + psu_mask_write(0xFD40D07C, 0x0000000FU, 0x00000001U); + psu_mask_write(0xFD4019A4, 0x000000FFU, 0x000000FFU); + psu_mask_write(0xFD401038, 0x00000040U, 0x00000040U); + psu_mask_write(0xFD40102C, 0x00000040U, 0x00000040U); + psu_mask_write(0xFD4059A4, 0x000000FFU, 0x000000FFU); + psu_mask_write(0xFD405038, 0x00000040U, 0x00000040U); + psu_mask_write(0xFD40502C, 0x00000040U, 0x00000040U); + psu_mask_write(0xFD4099A4, 0x000000FFU, 0x000000FFU); + psu_mask_write(0xFD409038, 0x00000040U, 0x00000040U); + psu_mask_write(0xFD40902C, 0x00000040U, 0x00000040U); + psu_mask_write(0xFD40D9A4, 0x000000FFU, 0x000000FFU); + psu_mask_write(0xFD40D038, 0x00000040U, 0x00000040U); + psu_mask_write(0xFD40D02C, 0x00000040U, 0x00000040U); + psu_mask_write(0xFD4019AC, 0x00000003U, 0x00000000U); + psu_mask_write(0xFD4059AC, 0x00000003U, 0x00000000U); + psu_mask_write(0xFD4099AC, 0x00000003U, 0x00000000U); + psu_mask_write(0xFD40D9AC, 0x00000003U, 0x00000000U); + psu_mask_write(0xFD401978, 0x00000010U, 0x00000010U); + psu_mask_write(0xFD405978, 0x00000010U, 0x00000010U); + psu_mask_write(0xFD409978, 0x00000010U, 0x00000010U); + psu_mask_write(0xFD40D978, 0x00000010U, 0x00000010U); + psu_mask_write(0xFD3D001C, 0xFFFFFFFFU, 0x00000001U); + psu_mask_write(0xFD410010, 0x00000077U, 0x00000011U); + psu_mask_write(0xFD410014, 0x00000007U, 0x00000003U); + return 1; +} + +static unsigned long psu_resetout_init_data(void) +{ + psu_mask_write(0xFF5E023C, 0x00000400U, 0x00000000U); + psu_mask_write(0xFF9D0080, 0x00000001U, 0x00000001U); + psu_mask_write(0xFF9D007C, 0x00000001U, 0x00000000U); + psu_mask_write(0xFF5E023C, 0x00000140U, 0x00000000U); + psu_mask_write(0xFD1A0100, 0x000C0000U, 0x00000000U); + psu_mask_write(0xFE20C200, 0x00023FFFU, 0x00022457U); + psu_mask_write(0xFE20C630, 0x003FFF00U, 0x00000000U); + psu_mask_write(0xFE20C11C, 0x00000600U, 0x00000600U); + psu_mask_write(0xFE20C12C, 0x00004000U, 0x00004000U); + psu_mask_write(0xFD480064, 0x00000200U, 0x00000200U); + psu_mask_write(0xFD48001C, 0x0000FFFFU, 0x00000000U); + psu_mask_write(0xFD480020, 0x0000FFFFU, 0x00000000U); + psu_mask_write(0xFD480024, 0x0000FFFFU, 0x00000000U); + psu_mask_write(0xFD480028, 0x0000FFFFU, 0x00000000U); + psu_mask_write(0xFD48002C, 0x0000FFFFU, 0x0000FFFFU); + psu_mask_write(0xFD480030, 0x0000FFFFU, 0x000000FFU); + psu_mask_write(0xFD480034, 0x0000FFFFU, 0x00000000U); + psu_mask_write(0xFD480038, 0x0000FFFFU, 0x0000FFFFU); + psu_mask_write(0xFD48003C, 0x0000FFFFU, 0x0000FFF0U); + psu_mask_write(0xFD480040, 0x0000FFFFU, 0x0000FFF0U); + psu_mask_write(0xFD480044, 0x0000FFFFU, 0x0000FFF1U); + psu_mask_write(0xFD480048, 0x0000FFFFU, 0x0000FFF1U); + psu_mask_write(0xFD48006C, 0x00000738U, 0x00000100U); + psu_mask_write(0xFD4800C8, 0x0000FFF0U, 0x00000040U); + psu_mask_write(0xFD4801A4, 0x000007FFU, 0x000000CDU); + psu_mask_write(0xFD4801A8, 0x00003FFFU, 0x00000624U); + psu_mask_write(0xFD4801AC, 0x000007FFU, 0x00000018U); + psu_mask_write(0xFD4801B0, 0x000007FFU, 0x000000B5U); + psu_mask_write(0xFD4801B4, 0x0000FFFFU, 0x00007E20U); + psu_mask_write(0xFD480088, 0x000000FFU, 0x00000001U); + psu_mask_write(0xFD4800D4, 0x000000FFU, 0x00000060U); + psu_mask_write(0xFD4800A4, 0x000003FFU, 0x00000000U); + psu_mask_write(0xFD480184, 0x00000FFFU, 0x00000082U); + psu_mask_write(0xFD480190, 0x00000040U, 0x00000000U); + psu_mask_write(0xFD480194, 0x0000FFE2U, 0x0000FFE2U); + psu_mask_write(0xFD480094, 0x00007E00U, 0x00004A00U); + psu_mask_write(0xFD480174, 0x0000FFFFU, 0x00009000U); + psu_mask_write(0xFD480200, 0xFFFFFFFFU, 0x10EED021U); + psu_mask_write(0xFD480204, 0xFFFFFFFFU, 0x10EE0007U); + psu_mask_write(0xFD480208, 0x000000FFU, 0x00000000U); + psu_mask_write(0xFD480060, 0x0000FFFFU, 0x00000400U); + psu_mask_write(0xFD480064, 0x000001FFU, 0x00000106U); + psu_mask_write(0xFD480010, 0x00001000U, 0x00000000U); + psu_mask_write(0xFD480164, 0x00001FFEU, 0x00000000U); + psu_mask_write(0xFD48013C, 0x00000020U, 0x00000000U); + psu_mask_write(0xFD4800AC, 0x00000100U, 0x00000000U); + psu_mask_write(0xFD4800C0, 0x000007FFU, 0x00000000U); + psu_mask_write(0xFD4800B8, 0x0000FFFFU, 0x00000000U); + psu_mask_write(0xFD4800BC, 0x00001FFFU, 0x00000000U); + psu_mask_write(0xFD4800B0, 0x0000FFFFU, 0x00000000U); + psu_mask_write(0xFD4800B4, 0x0000FFF8U, 0x00000000U); + psu_mask_write(0xFD48031C, 0x00000002U, 0x00000000U); + psu_mask_write(0xFD48008C, 0x0000B000U, 0x00008000U); + psu_mask_write(0xFD1A0100, 0x00020000U, 0x00000000U); + psu_mask_write(0xFF0A0014, 0x03FF03FFU, 0x03FE0001U); + mask_poll(0xFD4023E4, 0x00000010U); + mask_poll(0xFD40A3E4, 0x00000010U); + + return 1; +} + +static unsigned long psu_resetin_init_data(void) +{ + psu_mask_write(0xFF5E023C, 0x00000540U, 0x00000540U); + psu_mask_write(0xFD1A0100, 0x000E0000U, 0x000E0000U); + + return 1; +} + +static unsigned long psu_afi_config(void) +{ + psu_mask_write(0xFD1A0100, 0x00001F80U, 0x00000000U); + psu_mask_write(0xFF5E023C, 0x00080000U, 0x00000000U); + psu_mask_write(0xFD615000, 0x00000300U, 0x00000200U); + psu_mask_write(0xFD360000, 0x00000003U, 0x00000000U); + psu_mask_write(0xFD370000, 0x00000003U, 0x00000000U); + psu_mask_write(0xFD380000, 0x00000003U, 0x00000000U); + psu_mask_write(0xFD390000, 0x00000003U, 0x00000000U); + psu_mask_write(0xFD3A0000, 0x00000003U, 0x00000000U); + psu_mask_write(0xFD3B0000, 0x00000003U, 0x00000000U); + psu_mask_write(0xFD360014, 0x00000003U, 0x00000000U); + psu_mask_write(0xFD370014, 0x00000003U, 0x00000000U); + psu_mask_write(0xFD380014, 0x00000003U, 0x00000000U); + psu_mask_write(0xFD390014, 0x00000003U, 0x00000000U); + psu_mask_write(0xFD3A0014, 0x00000003U, 0x00000000U); + psu_mask_write(0xFD3B0014, 0x00000003U, 0x00000000U); + + return 1; +} + +static unsigned long psu_ddr_phybringup_data(void) +{ + unsigned int regval = 0; + unsigned int pll_retry = 10; + unsigned int pll_locked = 0; + + while ((pll_retry > 0) && (!pll_locked)) { + Xil_Out32(0xFD080004, 0x00040010); + Xil_Out32(0xFD080004, 0x00040011); + + while ((Xil_In32(0xFD080030) & 0x1) != 1) + ; + pll_locked = (Xil_In32(0xFD080030) & 0x80000000) + >> 31; + pll_locked &= (Xil_In32(0xFD0807E0) & 0x10000) + >> 16; + pll_locked &= (Xil_In32(0xFD0809E0) & 0x10000) + >> 16; + pll_locked &= (Xil_In32(0xFD080BE0) & 0x10000) + >> 16; + pll_locked &= (Xil_In32(0xFD080DE0) & 0x10000) + >> 16; + pll_retry--; + } + Xil_Out32(0xFD0800C4, Xil_In32(0xFD0800C4) | (pll_retry << 16)); + if (!pll_locked) + return 0; + + Xil_Out32(0xFD080004U, 0x00040063U); + + while ((Xil_In32(0xFD080030U) & 0x0000000FU) != 0x0000000FU) + ; + prog_reg(0xFD080004U, 0x00000001U, 0x00000000U, 0x00000001U); + + while ((Xil_In32(0xFD080030U) & 0x000000FFU) != 0x0000001FU) + ; + Xil_Out32(0xFD0701B0U, 0x00000001U); + Xil_Out32(0xFD070320U, 0x00000001U); + while ((Xil_In32(0xFD070004U) & 0x0000000FU) != 0x00000001U) + ; + prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000001U); + Xil_Out32(0xFD080004, 0x0004FE01); + regval = Xil_In32(0xFD080030); + while (regval != 0x80000FFF) + regval = Xil_In32(0xFD080030); + regval = ((Xil_In32(0xFD080030) & 0x1FFF0000) >> 18); + if (regval != 0) + return 0; + + Xil_Out32(0xFD080200U, 0x100091C7U); + int cur_R006_tREFPRD; + + cur_R006_tREFPRD = (Xil_In32(0xFD080018U) & 0x0003FFFFU) >> 0x00000000U; + prog_reg(0xFD080018, 0x3FFFF, 0x0, cur_R006_tREFPRD); + + prog_reg(0xFD08001CU, 0x00000018U, 0x00000003U, 0x00000003U); + prog_reg(0xFD08142CU, 0x00000030U, 0x00000004U, 0x00000003U); + prog_reg(0xFD08146CU, 0x00000030U, 0x00000004U, 0x00000003U); + prog_reg(0xFD0814ACU, 0x00000030U, 0x00000004U, 0x00000003U); + prog_reg(0xFD0814ECU, 0x00000030U, 0x00000004U, 0x00000003U); + prog_reg(0xFD08152CU, 0x00000030U, 0x00000004U, 0x00000003U); + + Xil_Out32(0xFD080004, 0x00060001); + regval = Xil_In32(0xFD080030); + while ((regval & 0x80004001) != 0x80004001) + regval = Xil_In32(0xFD080030); + + prog_reg(0xFD08001CU, 0x00000018U, 0x00000003U, 0x00000000U); + prog_reg(0xFD08142CU, 0x00000030U, 0x00000004U, 0x00000000U); + prog_reg(0xFD08146CU, 0x00000030U, 0x00000004U, 0x00000000U); + prog_reg(0xFD0814ACU, 0x00000030U, 0x00000004U, 0x00000000U); + prog_reg(0xFD0814ECU, 0x00000030U, 0x00000004U, 0x00000000U); + prog_reg(0xFD08152CU, 0x00000030U, 0x00000004U, 0x00000000U); + + Xil_Out32(0xFD080200U, 0x800091C7U); + prog_reg(0xFD080018, 0x3FFFF, 0x0, cur_R006_tREFPRD); + + Xil_Out32(0xFD080004, 0x0000C001); + regval = Xil_In32(0xFD080030); + while ((regval & 0x80000C01) != 0x80000C01) + regval = Xil_In32(0xFD080030); + + Xil_Out32(0xFD070180U, 0x01000040U); + Xil_Out32(0xFD070060U, 0x00000000U); + prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000000U); + + return 1; +} + +static int serdes_enb_coarse_saturation(void) +{ + Xil_Out32(0xFD402094, 0x00000010); + Xil_Out32(0xFD406094, 0x00000010); + Xil_Out32(0xFD40A094, 0x00000010); + Xil_Out32(0xFD40E094, 0x00000010); + return 1; +} + +static int serdes_fixcal_code(void) +{ + int maskstatus = 1; + unsigned int rdata = 0; + unsigned int match_pmos_code[23]; + unsigned int match_nmos_code[23]; + unsigned int match_ical_code[7]; + unsigned int match_rcal_code[7]; + unsigned int p_code = 0; + unsigned int n_code = 0; + unsigned int i_code = 0; + unsigned int r_code = 0; + unsigned int repeat_count = 0; + unsigned int L3_TM_CALIB_DIG20 = 0; + unsigned int L3_TM_CALIB_DIG19 = 0; + unsigned int L3_TM_CALIB_DIG18 = 0; + unsigned int L3_TM_CALIB_DIG16 = 0; + unsigned int L3_TM_CALIB_DIG15 = 0; + unsigned int L3_TM_CALIB_DIG14 = 0; + int i = 0; + + rdata = Xil_In32(0xFD40289C); + rdata = rdata & ~0x03; + rdata = rdata | 0x1; + Xil_Out32(0xFD40289C, rdata); + int count = 0; + + do { + if (count == 1100000) + break; + rdata = Xil_In32(0xFD402B1C); + count++; + } while ((rdata & 0x0000000E) != 0x0000000E); + + for (i = 0; i < 23; i++) { + match_pmos_code[i] = 0; + match_nmos_code[i] = 0; + } + for (i = 0; i < 7; i++) { + match_ical_code[i] = 0; + match_rcal_code[i] = 0; + } + + do { + Xil_Out32(0xFD410010, 0x00000000); + Xil_Out32(0xFD410014, 0x00000000); + + Xil_Out32(0xFD410010, 0x00000001); + Xil_Out32(0xFD410014, 0x00000000); + + maskstatus = mask_poll(0xFD40EF14, 0x2); + if (maskstatus == 0) { + xil_printf("#SERDES initialization timed out\n\r"); + return maskstatus; + } + + p_code = mask_read(0xFD40EF18, 0xFFFFFFFF); + n_code = mask_read(0xFD40EF1C, 0xFFFFFFFF); + ; + i_code = mask_read(0xFD40EF24, 0xFFFFFFFF); + r_code = mask_read(0xFD40EF28, 0xFFFFFFFF); + ; + + if (p_code >= 0x26 && p_code <= 0x3C) + match_pmos_code[p_code - 0x26] += 1; + + if (n_code >= 0x26 && n_code <= 0x3C) + match_nmos_code[n_code - 0x26] += 1; + + if (i_code >= 0xC && i_code <= 0x12) + match_ical_code[i_code - 0xc] += 1; + + if (r_code >= 0x6 && r_code <= 0xC) + match_rcal_code[r_code - 0x6] += 1; + + } while (repeat_count++ < 10); + + for (i = 0; i < 23; i++) { + if (match_pmos_code[i] >= match_pmos_code[0]) { + match_pmos_code[0] = match_pmos_code[i]; + p_code = 0x26 + i; + } + if (match_nmos_code[i] >= match_nmos_code[0]) { + match_nmos_code[0] = match_nmos_code[i]; + n_code = 0x26 + i; + } + } + + for (i = 0; i < 7; i++) { + if (match_ical_code[i] >= match_ical_code[0]) { + match_ical_code[0] = match_ical_code[i]; + i_code = 0xC + i; + } + if (match_rcal_code[i] >= match_rcal_code[0]) { + match_rcal_code[0] = match_rcal_code[i]; + r_code = 0x6 + i; + } + } + + L3_TM_CALIB_DIG20 = mask_read(0xFD40EC50, 0xFFFFFFF0); + L3_TM_CALIB_DIG20 = L3_TM_CALIB_DIG20 | 0x8 | ((p_code >> 2) & 0x7); + + L3_TM_CALIB_DIG19 = mask_read(0xFD40EC4C, 0xFFFFFF18); + L3_TM_CALIB_DIG19 = L3_TM_CALIB_DIG19 | ((p_code & 0x3) << 6) + | 0x20 | 0x4 | ((n_code >> 3) & 0x3); + + L3_TM_CALIB_DIG18 = mask_read(0xFD40EC48, 0xFFFFFF0F); + L3_TM_CALIB_DIG18 = L3_TM_CALIB_DIG18 | ((n_code & 0x7) << 5) | 0x10; + + L3_TM_CALIB_DIG16 = mask_read(0xFD40EC40, 0xFFFFFFF8); + L3_TM_CALIB_DIG16 = L3_TM_CALIB_DIG16 | ((r_code >> 1) & 0x7); + + L3_TM_CALIB_DIG15 = mask_read(0xFD40EC3C, 0xFFFFFF30); + L3_TM_CALIB_DIG15 = L3_TM_CALIB_DIG15 | ((r_code & 0x1) << 7) + | 0x40 | 0x8 | ((i_code >> 1) & 0x7); + + L3_TM_CALIB_DIG14 = mask_read(0xFD40EC38, 0xFFFFFF3F); + L3_TM_CALIB_DIG14 = L3_TM_CALIB_DIG14 | ((i_code & 0x1) << 7) | 0x40; + + Xil_Out32(0xFD40EC50, L3_TM_CALIB_DIG20); + Xil_Out32(0xFD40EC4C, L3_TM_CALIB_DIG19); + Xil_Out32(0xFD40EC48, L3_TM_CALIB_DIG18); + Xil_Out32(0xFD40EC40, L3_TM_CALIB_DIG16); + Xil_Out32(0xFD40EC3C, L3_TM_CALIB_DIG15); + Xil_Out32(0xFD40EC38, L3_TM_CALIB_DIG14); + return maskstatus; +} + +static int init_serdes(void) +{ + int status = 1; + + status &= psu_resetin_init_data(); + + status &= serdes_fixcal_code(); + status &= serdes_enb_coarse_saturation(); + + status &= psu_serdes_init_data(); + status &= psu_resetout_init_data(); + + return status; +} + +static void init_peripheral(void) +{ + psu_mask_write(0xFD5F0018, 0x8000001FU, 0x8000001FU); +} + +static void psu_init_sdio_pinmux(void) +{ + if (Xil_In32(0xFF0A0064U) & (1U << 19)) { + psu_mask_write(0xFF1800B4, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF1800B8, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF1800BC, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF1800C0, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF1800C4, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF1800C8, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF1800CC, 0x000000FEU, 0x00000000U); + + psu_mask_write(0xFF18030C, 0x00040000U, 0x00040000U); + + psu_mask_write(0xFF180320, 0x33843384U, 0x02801284U); + } else { + psu_mask_write(0xFF1800B4, 0x000000FEU, 0x00000010U); + } +} + +int psu_init(void) +{ + int status = 1; + + status &= psu_mio_init_data(); + status &= psu_peripherals_pre_init_data(); + status &= psu_pll_init_data(); + status &= psu_clock_init_data(); + status &= psu_ddr_init_data(); + status &= psu_ddr_phybringup_data(); + status &= psu_peripherals_init_data(); + status &= init_serdes(); + init_peripheral(); + + status &= psu_afi_config(); + psu_ddr_qos_init_data(); + + psu_init_sdio_pinmux(); + + if (status == 0) + return 1; + return 0; +} diff --git a/configs/xilinx_zynqmp_virt_defconfig b/configs/xilinx_zynqmp_virt_defconfig index 7886d5a38f..4f639bf58f 100644 --- a/configs/xilinx_zynqmp_virt_defconfig +++ b/configs/xilinx_zynqmp_virt_defconfig @@ -54,7 +54,7 @@ CONFIG_CMD_MTDPARTS_SHOW_NET_SIZES=y CONFIG_CMD_UBI=y CONFIG_SPL_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zcu100-revC" -CONFIG_OF_LIST="avnet-ultra96-rev1 zynqmp-a2197-revA zynqmp-e-a2197-00-revA zynqmp-g-a2197-00-revA zynqmp-m-a2197-01-revA zynqmp-m-a2197-02-revA zynqmp-m-a2197-03-revA zynqmp-p-a2197-00-revA zynqmp-zc1232-revA zynqmp-zc1254-revA zynqmp-zc1751-xm015-dc1 zynqmp-zc1751-xm016-dc2 zynqmp-zc1751-xm017-dc3 zynqmp-zc1751-xm018-dc4 zynqmp-zc1751-xm019-dc5 zynqmp-zcu100-revC zynqmp-zcu102-rev1.1 zynqmp-zcu102-rev1.0 zynqmp-zcu102-revA zynqmp-zcu102-revB zynqmp-zcu104-revA zynqmp-zcu104-revC zynqmp-zcu106-revA zynqmp-zcu111-revA zynqmp-zcu1275-revA zynqmp-zcu1275-revB zynqmp-zcu1285-revA zynqmp-zcu208-revA zynqmp-zcu216-revA" +CONFIG_OF_LIST="avnet-ultra96-rev1 zynqmp-a2197-revA zynqmp-e-a2197-00-revA zynqmp-g-a2197-00-revA zynqmp-m-a2197-01-revA zynqmp-m-a2197-02-revA zynqmp-m-a2197-03-revA zynqmp-p-a2197-00-revA zynqmp-zc1232-revA zynqmp-zc1254-revA zynqmp-zc1751-xm015-dc1 zynqmp-zc1751-xm016-dc2 zynqmp-zc1751-xm017-dc3 zynqmp-zc1751-xm018-dc4 zynqmp-zc1751-xm019-dc5 zynqmp-zcu100-revC zynqmp-zcu102-rev1.1 zynqmp-zcu102-rev1.0 zynqmp-zcu102-revA zynqmp-zcu102-revB zynqmp-zcu104-revA zynqmp-zcu104-revC zynqmp-zcu106-revA zynqmp-zcu111-revA zynqmp-zcu1275-revA zynqmp-zcu1275-revB zynqmp-zcu1285-revA zynqmp-zcu208-revA zynqmp-zcu216-revA zynqmp-topic-miamimp-xilinx-xdp-v1r1" CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_NETCONSOLE=y From 3ccea69fc495a8e6c529d6c647af4da3775dcb87 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 27 May 2020 12:50:33 +0200 Subject: [PATCH 77/79] arm64: zynqmp: Print multiboot reg in decimal It is better to print multiboot value in decimal because boot images are also composed in decimal not in hex. Signed-off-by: Michal Simek --- board/xilinx/zynqmp/zynqmp.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c index a6cd41af1a..ebb7172908 100644 --- a/board/xilinx/zynqmp/zynqmp.c +++ b/board/xilinx/zynqmp/zynqmp.c @@ -354,7 +354,7 @@ static int multi_boot(void) multiboot = readl(&csu_base->multi_boot); - printf("Multiboot:\t%x\n", multiboot); + printf("Multiboot:\t%d\n", multiboot); return 0; } From e20d88bffaa4292f2fec9e03eac91154429c6482 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Mon, 27 Apr 2020 11:26:31 +0200 Subject: [PATCH 78/79] xilinx: zynqmp: Enable pmufw config reloading PMU FW has functionality to accept and reload configuration object at run time. The patch is adding support for doing it via u-boot prompt. For example: tftpboot 100000 pmu_obj.bin zynqmp pmufw 100000 $filesize The most of pmufw configurations don't allow config reloading. Also official Xilinx PMUFW doens't support this feature properly but the patch should open a way to call PMUFW with this request. Here is example of PMUFW config fragment which enables config reloading. /* SET CONFIG SECTION */ PM_CONFIG_SET_CONFIG_SECTION_ID, /* Section ID */ PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* Permissions to set config */ Signed-off-by: Michal Simek --- board/xilinx/zynqmp/cmds.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/board/xilinx/zynqmp/cmds.c b/board/xilinx/zynqmp/cmds.c index 0f1f26986f..c0d28a73e4 100644 --- a/board/xilinx/zynqmp/cmds.c +++ b/board/xilinx/zynqmp/cmds.c @@ -130,8 +130,27 @@ static int do_zynqmp_tcm_init(struct cmd_tbl *cmdtp, int flag, int argc, } #endif +static int do_zynqmp_pmufw(struct cmd_tbl *cmdtp, int flag, int argc, + char * const argv[]) +{ + u32 addr, size; + + if (argc != cmdtp->maxargs) + return CMD_RET_USAGE; + + addr = simple_strtoul(argv[2], NULL, 16); + size = simple_strtoul(argv[3], NULL, 16); + flush_dcache_range((ulong)addr, (ulong)(addr + size)); + + zynqmp_pmufw_load_config_object((const void *)(uintptr_t)addr, + (size_t)size); + + return 0; +} + static struct cmd_tbl cmd_zynqmp_sub[] = { U_BOOT_CMD_MKENT(secure, 5, 0, do_zynqmp_verify_secure, "", ""), + U_BOOT_CMD_MKENT(pmufw, 4, 0, do_zynqmp_pmufw, "", ""), U_BOOT_CMD_MKENT(mmio_read, 3, 0, do_zynqmp_mmio_read, "", ""), U_BOOT_CMD_MKENT(mmio_write, 5, 0, do_zynqmp_mmio_write, "", ""), #ifdef CONFIG_DEFINE_TCM_OCM_MMAP @@ -184,6 +203,7 @@ static char zynqmp_help_text[] = " to be initialized. Supported modes will be\n" " lock(0)/split(1)\n" #endif + "zynqmp pmufw address size - load PMU FW configuration object\n" ; #endif From b8fd54d62f92658cbd20ca051304e13eabf24ddd Mon Sep 17 00:00:00 2001 From: Ashok Reddy Soma Date: Mon, 6 Apr 2020 07:58:30 -0600 Subject: [PATCH 79/79] common: fdt: Remove additional 4k space for fdt allocation There is no technical reason to add additional 4k space for FDT. This space is completely unused and just increase memory requirements. This is problematic on systems with limited memory resources as Xilinx Zynq CSE/ZynqMP mini and Versal mini configurations. The patch is removing additional 4k space. EFI code is using copy_fdt() which copy FDT to different location. And all boot commands in case of using U-Boot's FDT pointed by $fdtcontroladdr are copying FDT to different locations by image_setup_libfdt(). That's why in proper flow none should modified DTB used by U-Boot that's why there is no need for additional space. Signed-off-by: Ashok Reddy Soma Signed-off-by: Michal Simek Acked-by: Stephen Warren --- common/board_f.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/common/board_f.c b/common/board_f.c index 01194eaa0e..dcad551ae4 100644 --- a/common/board_f.c +++ b/common/board_f.c @@ -537,7 +537,7 @@ static int reserve_fdt(void) * will be relocated with other data. */ if (gd->fdt_blob) { - gd->fdt_size = ALIGN(fdt_totalsize(gd->fdt_blob) + 0x1000, 32); + gd->fdt_size = ALIGN(fdt_totalsize(gd->fdt_blob), 32); gd->start_addr_sp = reserve_stack_aligned(gd->fdt_size); gd->new_fdt = map_sysmem(gd->start_addr_sp, gd->fdt_size);