leandrof/u-boot
1
0
Fork 1
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Merge commit '32e0379143b433e29d76404f5f4c279067e48853' of https://github.com/tienfong/uboot_mainline

Browse Source
This commit is contained in:
Tom Rini
2022-06-17 09:35:28 -04:00
parent ee4b80a6e2 32e0379143
commit f0843e0c0a
10 changed files with 67 additions and 15 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
drivers/cache/cache-ncore.c vendored
View File

@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2019 Intel Corporation <www.intel.com>
* Copyright (C) 2019-2022 Intel Corporation <www.intel.com>
*
*/
#include <dm.h>
@@ -81,8 +81,8 @@ static void ncore_ccu_init_dirs(void __iomem *base)
hang();
}
/* Enable snoop filter, a bit per snoop filter */
setbits_le32((ulong)CCU_DIR_REG_ADDR(base, DIRUSFER, i),
/* Disable snoop filter, a bit per snoop filter */
clrbits_le32((ulong)CCU_DIR_REG_ADDR(base, DIRUSFER, i),
BIT(f));
}
}

4
drivers/ddr/altera/sdram_n5x.c
View File

@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
/*
* Copyright (C) 2020-2021 Intel Corporation <www.intel.com>
* Copyright (C) 2020-2022 Intel Corporation <www.intel.com>
*
*/

4
drivers/ddr/altera/sdram_s10.c
View File

@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2016-2018 Intel Corporation <www.intel.com>
* Copyright (C) 2016-2022 Intel Corporation <www.intel.com>
*
*/
@@ -277,7 +277,7 @@ int sdram_mmr_init_full(struct udevice *dev)
DDR_SCH_DEVTODEV);
/* assigning the SDRAM size */
unsigned long long size = sdram_calculate_size(plat);
phys_size_t size = sdram_calculate_size(plat);
/* If the size is invalid, use default Config size */
if (size <= 0)
hw_size = PHYS_SDRAM_1_SIZE;

5
drivers/ddr/altera/sdram_soc64.c
View File

@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2016-2021 Intel Corporation <www.intel.com>
* Copyright (C) 2016-2022 Intel Corporation <www.intel.com>
*
*/
@@ -239,7 +239,8 @@ phys_size_t sdram_calculate_size(struct altera_sdram_plat *plat)
{
u32 dramaddrw = hmc_readl(plat, DRAMADDRW);
phys_size_t size = 1 << (DRAMADDRW_CFG_CS_ADDR_WIDTH(dramaddrw) +
phys_size_t size = (phys_size_t)1 <<
(DRAMADDRW_CFG_CS_ADDR_WIDTH(dramaddrw) +
DRAMADDRW_CFG_BANK_GRP_ADDR_WIDTH(dramaddrw) +
DRAMADDRW_CFG_BANK_ADDR_WIDTH(dramaddrw) +
DRAMADDRW_CFG_ROW_ADDR_WIDTH(dramaddrw) +

2
drivers/ddr/altera/sdram_soc64.h
View File

@@ -53,7 +53,7 @@ struct altera_sdram_plat {
#define DDR_HMC_INTSTAT_DERRPENA_SET_MSK BIT(1)
#define DDR_HMC_INTSTAT_ADDRMTCFLG_SET_MSK BIT(16)
#define DDR_HMC_INTMODE_INTMODE_SET_MSK BIT(0)
#define DDR_HMC_RSTHANDSHAKE_MASK 0x000000ff
#define DDR_HMC_RSTHANDSHAKE_MASK 0x0000000f
#define DDR_HMC_CORE2SEQ_INT_REQ 0xF
#define DDR_HMC_SEQ2CORE_INT_RESP_MASK BIT(3)
#define DDR_HMC_HPSINTFCSEL_ENABLE_MASK 0x001f1f1f