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Merge commit '32e0379143b433e29d76404f5f4c279067e48853' of https://github.com/tienfong/uboot_mainline

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This commit is contained in:
Tom Rini
2022-06-17 09:35:28 -04:00
parent ee4b80a6e2 32e0379143
commit f0843e0c0a
10 changed files with 67 additions and 15 deletions
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11
arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi
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@@ -2,7 +2,7 @@
/*
* U-Boot additions
*
* Copyright (C) 2019 Intel Corporation <www.intel.com>
* Copyright (C) 2019-2022 Intel Corporation <www.intel.com>
*/
#include "socfpga_agilex-u-boot.dtsi"
@@ -11,6 +11,15 @@
aliases {
spi0 = &qspi;
i2c0 = &i2c1;
freeze_br0 = &freeze_controller;
};
soc {
freeze_controller: freeze_controller@f9000450 {
compatible = "altr,freeze-bridge-controller";
reg = <0xf9000450 0x00000010>;
status = "disabled";
};
};
memory {

11
arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi
View File

@@ -2,7 +2,7 @@
/*
* U-Boot additions
*
* Copyright (C) 2019-2020 Intel Corporation <www.intel.com>
* Copyright (C) 2019-2022 Intel Corporation <www.intel.com>
*/
#include "socfpga_stratix10-u-boot.dtsi"
@@ -10,6 +10,15 @@
/{
aliases {
spi0 = &qspi;
freeze_br0 = &freeze_controller;
};
soc {
freeze_controller: freeze_controller@f9000450 {
compatible = "altr,freeze-bridge-controller";
reg = <0xf9000450 0x00000010>;
status = "disabled";
};
};
};

2
arch/arm/dts/socfpga_stratix10_socdk.dts
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@@ -92,7 +92,7 @@
broken-cd;
bus-width = <4>;
drvsel = <3>;
smplsel = <0>;
smplsel = <2>;
};
&qspi {

34
arch/arm/mach-socfpga/timer_s10.c
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@@ -1,11 +1,12 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2017-2018 Intel Corporation <www.intel.com>
* Copyright (C) 2017-2022 Intel Corporation <www.intel.com>
*
*/
#include <common.h>
#include <init.h>
#include <div64.h>
#include <asm/io.h>
#include <asm/arch/timer.h>
@@ -26,3 +27,34 @@ int timer_init(void)
#endif
return 0;
}
__always_inline u64 __get_time_stamp(void)
{
u64 cntpct;
isb();
asm volatile("mrs %0, cntpct_el0" : "=r" (cntpct));
return cntpct;
}
__always_inline uint64_t __usec_to_tick(unsigned long usec)
{
u64 tick = usec;
u64 cntfrq;
asm volatile("mrs %0, cntfrq_el0" : "=r" (cntfrq));
tick *= cntfrq;
do_div(tick, 1000000);
return tick;
}
__always_inline void __udelay(unsigned long usec)
{
/* get current timestamp */
u64 tmp = __get_time_stamp() + __usec_to_tick(usec);
while (__get_time_stamp() < tmp + 1) /* loop till event */
;
}