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[PATCH] 44x: Fix problem with DDR controller setup (refresh rate)

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This patch fixes a problem with an incorrect setup for the refresh
timer of the 44x DDR controller in the file cpu/ppc4xx/sdram.c

Signed-off-by: Stefan Roese <sr@denx.de>
This commit is contained in:
Stefan Roese 2007-01-06 15:58:09 +01:00
parent f16c1da957
commit f07ae7a9da
1 changed files with 1 additions and 1 deletions
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2
cpu/ppc4xx/sdram.c
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@ -380,7 +380,7 @@ long int initdram(int board_type)
mtsdram(mem_b0cr, mb0cf[i].reg);
mtsdram(mem_tr0, 0x41094012);
mtsdram(mem_tr1, 0x80800800); /* SS=T2 SL=STAGE 3 CD=1 CT=0x00*/
mtsdram(mem_rtr, 0x7e000000); /* Interval 15.20µs @ 133MHz PLB*/
mtsdram(mem_rtr, 0x04100000); /* Interval 7.8µs @ 133MHz PLB */
mtsdram(mem_cfg1, 0x00000000); /* Self-refresh exit, disable PM*/
udelay(400); /* Delay 200 usecs (min) */