cgtqmx6eval: Add Ethernet support
cgtqmx6eval can be populated with a AR8035 or KSZ9031 depending on the board revision. Add Ethernet support. Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
This commit is contained in:
Otavio Salvador
Stefano Babic
parent
066f876bf6
commit
f02229021d
@ -27,6 +27,10 @@
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#include <power/pfuze100_pmic.h>
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#include <linux/fb.h>
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#include <ipu_pixfmt.h>
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#include <malloc.h>
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#include <miiphy.h>
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#include <netdev.h>
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#include <micrel.h>
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DECLARE_GLOBAL_DATA_PTR;
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@ -43,6 +47,11 @@ DECLARE_GLOBAL_DATA_PTR;
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#define MX6Q_QMX6_PFUZE_MUX IMX_GPIO_NR(6, 9)
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#define ENET_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
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PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
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PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
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int dram_init(void)
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{
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gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
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@ -98,6 +107,51 @@ static iomux_v3_cfg_t const usb_otg_pads[] = {
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MX6_PAD_GPIO_1__USB_OTG_ID | MUX_PAD_CTRL(NO_PAD_CTRL),
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};
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static iomux_v3_cfg_t enet_pads_ksz9031[] = {
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MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_RGMII_RXC__GPIO6_IO30 | MUX_PAD_CTRL(NO_PAD_CTRL),
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MX6_PAD_RGMII_RD0__GPIO6_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL),
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MX6_PAD_RGMII_RD1__GPIO6_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL),
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MX6_PAD_RGMII_RD2__GPIO6_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL),
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MX6_PAD_RGMII_RD3__GPIO6_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
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MX6_PAD_RGMII_RX_CTL__GPIO6_IO24 | MUX_PAD_CTRL(NO_PAD_CTRL),
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};
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static iomux_v3_cfg_t enet_pads_final_ksz9031[] = {
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MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
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};
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static iomux_v3_cfg_t enet_pads_ar8035[] = {
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MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
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};
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#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
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struct i2c_pads_info i2c_pad_info1 = {
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.scl = {
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@ -169,6 +223,159 @@ int power_init_board(void)
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return 0;
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}
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int board_eth_init(bd_t *bis)
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{
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struct phy_device *phydev;
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struct mii_dev *bus;
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unsigned short id1, id2;
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int ret;
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iomux_v3_cfg_t enet_reset = MX6_PAD_EIM_D23__GPIO3_IO23 |
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MUX_PAD_CTRL(NO_PAD_CTRL);
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/* check whether KSZ9031 or AR8035 has to be configured */
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imx_iomux_v3_setup_multiple_pads(enet_pads_ar8035,
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ARRAY_SIZE(enet_pads_ar8035));
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imx_iomux_v3_setup_pad(enet_reset);
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/* phy reset */
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gpio_direction_output(IMX_GPIO_NR(3, 23), 0);
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udelay(2000);
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gpio_set_value(IMX_GPIO_NR(3, 23), 1);
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udelay(500);
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bus = fec_get_miibus(IMX_FEC_BASE, -1);
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if (!bus)
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return -EINVAL;
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phydev = phy_find_by_mask(bus, (0xf << 4), PHY_INTERFACE_MODE_RGMII);
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if (!phydev) {
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printf("Error: phy device not found.\n");
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ret = -ENODEV;
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goto free_bus;
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}
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/* get the PHY id */
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id1 = phy_read(phydev, MDIO_DEVAD_NONE, 2);
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id2 = phy_read(phydev, MDIO_DEVAD_NONE, 3);
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if ((id1 == 0x22) && ((id2 & 0xFFF0) == 0x1620)) {
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/* re-configure for Micrel KSZ9031 */
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printf("configure Micrel KSZ9031 Ethernet Phy at address %d\n",
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phydev->addr);
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/* phy reset: gpio3-23 */
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gpio_set_value(IMX_GPIO_NR(3, 23), 0);
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gpio_set_value(IMX_GPIO_NR(6, 30), (phydev->addr >> 2));
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gpio_set_value(IMX_GPIO_NR(6, 25), 1);
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gpio_set_value(IMX_GPIO_NR(6, 27), 1);
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gpio_set_value(IMX_GPIO_NR(6, 28), 1);
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gpio_set_value(IMX_GPIO_NR(6, 29), 1);
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imx_iomux_v3_setup_multiple_pads(enet_pads_ksz9031,
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ARRAY_SIZE(enet_pads_ksz9031));
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gpio_set_value(IMX_GPIO_NR(6, 24), 1);
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udelay(500);
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gpio_set_value(IMX_GPIO_NR(3, 23), 1);
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imx_iomux_v3_setup_multiple_pads(enet_pads_final_ksz9031,
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ARRAY_SIZE(enet_pads_final_ksz9031));
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} else if ((id1 == 0x004d) && (id2 == 0xd072)) {
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/* configure Atheros AR8035 - actually nothing to do */
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printf("configure Atheros AR8035 Ethernet Phy at address %d\n",
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phydev->addr);
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} else {
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printf("Unknown Ethernet-Phy: 0x%04x 0x%04x\n", id1, id2);
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ret = -EINVAL;
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goto free_phydev;
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}
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ret = fec_probe(bis, -1, IMX_FEC_BASE, bus, phydev);
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if (ret)
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goto free_phydev;
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return 0;
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free_phydev:
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free(phydev);
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free_bus:
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free(bus);
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return ret;
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}
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int mx6_rgmii_rework(struct phy_device *phydev)
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{
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unsigned short id1, id2;
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unsigned short val;
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/* check whether KSZ9031 or AR8035 has to be configured */
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id1 = phy_read(phydev, MDIO_DEVAD_NONE, 2);
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id2 = phy_read(phydev, MDIO_DEVAD_NONE, 3);
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if ((id1 == 0x22) && ((id2 & 0xFFF0) == 0x1620)) {
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/* finalize phy configuration for Micrel KSZ9031 */
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phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, 2);
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phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, 4);
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phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, MII_KSZ9031_MOD_DATA_POST_INC_W | 0x2);
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phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, 0x0000);
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phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, 2);
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phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, 5);
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phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, MII_KSZ9031_MOD_DATA_POST_INC_W | 0x2);
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phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, MII_KSZ9031_MOD_REG);
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phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, 2);
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phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, 6);
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phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, MII_KSZ9031_MOD_DATA_POST_INC_W | 0x2);
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phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, 0xFFFF);
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phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, 2);
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phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, 8);
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phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, MII_KSZ9031_MOD_DATA_POST_INC_W | 0x2);
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phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, 0x3FFF);
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/* fix KSZ9031 link up issue */
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phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, 0x0);
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phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, 0x4);
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phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, MII_KSZ9031_MOD_DATA_NO_POST_INC);
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phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, 0x6);
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phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, MII_KSZ9031_MOD_REG);
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phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, 0x3);
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phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, MII_KSZ9031_MOD_DATA_NO_POST_INC);
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phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, 0x1A80);
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}
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if ((id1 == 0x004d) && (id2 == 0xd072)) {
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/* enable AR8035 ouput a 125MHz clk from CLK_25M */
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phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, 0x7);
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phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, MII_KSZ9031_MOD_DATA_POST_INC_RW | 0x16);
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phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, MII_KSZ9031_MOD_DATA_NO_POST_INC | 0x7);
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val = phy_read(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA);
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val &= 0xfe63;
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val |= 0x18;
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phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, val);
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/* introduce tx clock delay */
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phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
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val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
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val |= 0x0100;
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phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
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/* disable hibernation */
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phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0xb);
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val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
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phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x3c40);
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}
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return 0;
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}
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int board_phy_config(struct phy_device *phydev)
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{
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mx6_rgmii_rework(phydev);
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if (phydev->drv->config)
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phydev->drv->config(phydev);
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return 0;
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}
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static void setup_iomux_uart(void)
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{
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@ -97,6 +97,19 @@
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#define CONFIG_LBA48
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#define CONFIG_LIBATA
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/* Ethernet */
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#define CONFIG_CMD_PING
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#define CONFIG_CMD_DHCP
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#define CONFIG_CMD_MII
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#define CONFIG_FEC_MXC
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#define CONFIG_MII
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#define IMX_FEC_BASE ENET_BASE_ADDR
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#define CONFIG_FEC_XCV_TYPE RGMII
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#define CONFIG_ETHPRIME "FEC"
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#define CONFIG_FEC_MXC_PHYADDR 6
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#define CONFIG_PHYLIB
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#define CONFIG_PHY_ATHEROS
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/* Command definition */
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#define CONFIG_MXC_UART_BASE UART2_BASE
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@ -20,6 +20,10 @@
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#define MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW 0x6
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#define MII_KSZ9031_EXT_RGMII_CLOCK_SKEW 0x8
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/* Registers */
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#define MMD_ACCESS_CONTROL 0xd
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#define MMD_ACCESS_REG_DATA 0xe
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struct phy_device;
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int ksz9021_phy_extended_write(struct phy_device *phydev, int regnum, u16 val);
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int ksz9021_phy_extended_read(struct phy_device *phydev, int regnum);
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