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nxp: Migrate CONFIG_DDR_CLK_FREQ to Kconfig

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As this symbol can either be a fixed value or the function
get_board_ddr_clk, migration is tricky.  Introduce a choice of DYNAMIC
or STATIC_DDR_CLK_FREQ.  If DYNAMIC, we continue to use the board
defined get_board_ddr_clk function.  If STATIC, set CONFIG_DDR_CLK_FREQ
to that value and now include/clock_legacy.h contains the function
prototype or defines get_board_ddr_clk() to that static value.  Update
callers to test for DYNAMIC or STATIC.

Signed-off-by: Tom Rini <trini@konsulko.com>
This commit is contained in:
Tom Rini
2021-08-21 13:50:17 -04:00
parent 222d22a39a
commit efb5dab7ba
152 changed files with 166 additions and 89 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
board/freescale/common/ics307_clk.h
View File

@@ -8,7 +8,6 @@
#ifndef __ASSEMBLY__
extern unsigned long get_board_sys_clk(void);
extern unsigned long get_board_ddr_clk(void);
extern unsigned long ics307_sysclk_calculator(unsigned long out_freq);
#endif

2
board/freescale/ls1021aqds/ls1021aqds.c
View File

@@ -127,6 +127,7 @@ unsigned long get_board_sys_clk(void)
return 66666666;
}
#ifdef CONFIG_DYNAMIC_DDR_CLK_FREQ
unsigned long get_board_ddr_clk(void)
{
u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
@@ -141,6 +142,7 @@ unsigned long get_board_ddr_clk(void)
}
return 66666666;
}
#endif
int dram_init(void)
{

5
board/freescale/t102xrdb/spl.c
View File

@@ -30,11 +30,6 @@ unsigned long get_board_sys_clk(void)
return CONFIG_SYS_CLK_FREQ;
}
unsigned long get_board_ddr_clk(void)
{
return CONFIG_DDR_CLK_FREQ;
}
#if defined(CONFIG_SPL_MMC_BOOT)
#define GPIO1_SD_SEL 0x00020000
int board_mmc_getcd(struct mmc *mmc)

5
board/freescale/t102xrdb/t102xrdb.c
View File

@@ -167,11 +167,6 @@ unsigned long get_board_sys_clk(void)
return CONFIG_SYS_CLK_FREQ;
}
unsigned long get_board_ddr_clk(void)
{
return CONFIG_DDR_CLK_FREQ;
}
#ifdef CONFIG_TARGET_T1024RDB
void board_reset(void)
{

5
board/freescale/t104xrdb/spl.c
View File

@@ -30,11 +30,6 @@ unsigned long get_board_sys_clk(void)
return CONFIG_SYS_CLK_FREQ;
}
unsigned long get_board_ddr_clk(void)
{
return CONFIG_DDR_CLK_FREQ;
}
#define FSL_CORENET_CCSR_PORSR1_RCW_MASK 0xFF800000
void board_init_f(ulong bootflag)
{

5
board/freescale/t208xrdb/spl.c
View File

@@ -29,11 +29,6 @@ unsigned long get_board_sys_clk(void)
return CONFIG_SYS_CLK_FREQ;
}
unsigned long get_board_ddr_clk(void)
{
return CONFIG_DDR_CLK_FREQ;
}
void board_init_f(ulong bootflag)
{
u32 plat_ratio, sys_clk, ccb_clk;

5
board/freescale/t208xrdb/t208xrdb.c
View File

@@ -114,11 +114,6 @@ unsigned long get_board_sys_clk(void)
return CONFIG_SYS_CLK_FREQ;
}
unsigned long get_board_ddr_clk(void)
{
return CONFIG_DDR_CLK_FREQ;
}
int misc_init_r(void)
{
u8 reg;

5
board/freescale/t4rdb/spl.c
View File

@@ -35,11 +35,6 @@ unsigned long get_board_sys_clk(void)
return CONFIG_SYS_CLK_FREQ;
}
unsigned long get_board_ddr_clk(void)
{
return CONFIG_DDR_CLK_FREQ;
}
void board_init_f(ulong bootflag)
{
u32 plat_ratio, sys_clk, ccb_clk;