ColdFire: I2C fix for multiple platforms

Signed-off-by: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
This commit is contained in:
TsiChung Liew 2008-08-19 03:01:19 +06:00 committed by John Rigby
parent d53cf6a9c7
commit eec567a67e
12 changed files with 62 additions and 14 deletions

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@ -116,5 +116,9 @@ int get_clocks(void)
gd->bus_clk = gd->flb_clk;
}
#ifdef CONFIG_FSL_I2C
gd->i2c1_clk = gd->bus_clk;
#endif
return (0);
}

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@ -110,8 +110,8 @@ void cpu_init_f(void)
#endif
#ifdef CONFIG_FSL_I2C
gpio->par_feci2c &= ~(GPIO_PAR_FECI2C_SCL_MASK | GPIO_PAR_FECI2C_SDA_MASK);
gpio->par_feci2c |= (GPIO_PAR_FECI2C_SCL_I2CSCL | GPIO_PAR_FECI2C_SDA_I2CSDA);
CFG_I2C_PINMUX_REG &= CFG_I2C_PINMUX_CLR;
CFG_I2C_PINMUX_REG |= CFG_I2C_PINMUX_SET;
#endif
icache_enable();

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@ -45,5 +45,9 @@ int get_clocks(void)
gd->bus_clk = CFG_CLK;
gd->cpu_clk = (gd->bus_clk * 2);
#ifdef CONFIG_FSL_I2C
gd->i2c1_clk = gd->bus_clk;
#endif
return (0);
}

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@ -80,6 +80,15 @@ void cpu_init_f(void)
mbar_writeShort(MCFSIM_CSCR0, CFG_CSCR0);
mbar_writeLong(MCFSIM_CSMR0, CFG_CSMR0);
#ifdef CONFIG_FSL_I2C
CFG_I2C_PINMUX_REG = CFG_I2C_PINMUX_REG & CFG_I2C_PINMUX_CLR;
CFG_I2C_PINMUX_REG |= CFG_I2C_PINMUX_SET;
#ifdef CFG_I2C2_OFFSET
CFG_I2C2_PINMUX_REG &= CFG_I2C2_PINMUX_CLR;
CFG_I2C2_PINMUX_REG |= CFG_I2C2_PINMUX_SET;
#endif
#endif
/* enable instruction cache now */
icache_enable();
}
@ -322,7 +331,8 @@ void cpu_init_f(void)
#endif /* #ifndef CONFIG_MONITOR_IS_IN_RAM */
#ifdef CONFIG_FSL_I2C
gpio_reg->par_feci2c = 0x000F;
CFG_I2C_PINMUX_REG &= CFG_I2C_PINMUX_CLR;
CFG_I2C_PINMUX_REG |= CFG_I2C_PINMUX_SET;
#endif
/* enable instruction cache now */

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@ -82,5 +82,13 @@ int get_clocks (void)
#else
gd->bus_clk = gd->cpu_clk;
#endif
#ifdef CONFIG_FSL_I2C
gd->i2c1_clk = gd->bus_clk;
#ifdef CFG_I2C2_OFFSET
gd->i2c2_clk = gd->bus_clk;
#endif
#endif
return (0);
}

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@ -212,5 +212,10 @@ int get_clocks(void)
{
gd->bus_clk = clock_pll(CFG_CLK / 1000, 0) * 1000;
gd->cpu_clk = (gd->bus_clk * 3);
#ifdef CONFIG_FSL_I2C
gd->i2c1_clk = gd->bus_clk;
#endif
return (0);
}

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@ -209,5 +209,9 @@ int get_clocks(void)
#endif
}
#ifdef CONFIG_FSL_I2C
gd->i2c1_clk = gd->bus_clk;
#endif
return (0);
}

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@ -39,5 +39,10 @@ int get_clocks(void)
gd->bus_clk = CFG_CLK;
gd->cpu_clk = (gd->bus_clk * 2);
#ifdef CONFIG_FSL_I2C
gd->i2c1_clk = gd->bus_clk;
#endif
return (0);
}

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@ -72,15 +72,6 @@ typedef struct fsl_i2c {
#define I2C_DR 0xFF
#define I2C_DR_SHIFT 0
#define I2C_DR_RES ~(I2C_DR)
u8 dfsrr; /* I2C digital filter sampling rate register */
u8 res5[3];
#define I2C_DFSRR 0x3F
#define I2C_DFSRR_SHIFT 0
#define I2C_DFSRR_RES ~(I2C_DR)
/* Fill out the reserved block */
u8 res6[0xE8];
} fsl_i2c_t;
#endif /* _ASM_I2C_H_ */

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@ -102,12 +102,15 @@
/* I2C */
#define CONFIG_FSL_I2C
#define CONFIG_HARD_I2C /* I2C with hw support */
#undef CONFIG_SOFT_I2C /* I2C bit-banged */
#define CONFIG_HARD_I2C /* I2C with hw support */
#undef CONFIG_SOFT_I2C /* I2C bit-banged */
#define CFG_I2C_SPEED 80000
#define CFG_I2C_SLAVE 0x7F
#define CFG_I2C_OFFSET 0x00000300
#define CFG_IMMR CFG_MBAR
#define CFG_I2C_PINMUX_REG (gpio->par_qspi)
#define CFG_I2C_PINMUX_CLR ~(GPIO_PAR_FECI2C_SCL_MASK | GPIO_PAR_FECI2C_SDA_MASK)
#define CFG_I2C_PINMUX_SET (GPIO_PAR_FECI2C_SCL_I2CSCL | GPIO_PAR_FECI2C_SDA_I2CSDA)
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */

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@ -118,6 +118,17 @@
#define CONFIG_HOSTNAME M5253DEMO
/* I2C */
#define CONFIG_FSL_I2C
#define CONFIG_HARD_I2C /* I2C with hw support */
#define CFG_I2C_SPEED 80000
#define CFG_I2C_SLAVE 0x7F
#define CFG_I2C_OFFSET 0x00000280
#define CFG_IMMR CFG_MBAR
#define CFG_I2C_PINMUX_REG (*(u32 *) (CFG_MBAR+0x19C))
#define CFG_I2C_PINMUX_CLR (0xFFFFE7FF)
#define CFG_I2C_PINMUX_SET (0)
#define CFG_PROMPT "=> "
#define CFG_LONGHELP /* undef to save memory */

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@ -118,6 +118,9 @@
#define CFG_I2C_SLAVE 0x7F
#define CFG_I2C_OFFSET 0x00000300
#define CFG_IMMR CFG_MBAR
#define CFG_I2C_PINMUX_REG (gpio_reg->par_feci2c)
#define CFG_I2C_PINMUX_CLR (0xFFF0)
#define CFG_I2C_PINMUX_SET (0x000F)
#ifdef CONFIG_MCFFEC
#define CONFIG_ETHADDR 00:06:3b:01:41:55