blackfin: bf60x: add dma support
Add dma support for bf60x. Signed-off-by: Bob Liu <lliubbo@gmail.com> Signed-off-by: Sonic Zhang <sonic.zhang@analog.com> Signed-off-by: Sonic Zhang <sonic.adi@gmail.com>
This commit is contained in:
Bob Liu
sonic
parent
a12c51f640
commit
ee8259623e
@ -8,7 +8,12 @@
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#ifndef _BLACKFIN_DMA_H_
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#define _BLACKFIN_DMA_H_
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#include <linux/types.h>
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#ifdef __ADSPBF60x__
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#include <asm/mach-common/bits/dde.h>
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#else
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#include <asm/mach-common/bits/dma.h>
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#endif
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struct dmasg_large {
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void *next_desc_addr;
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@ -30,46 +35,70 @@ struct dmasg {
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} __attribute__((packed));
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struct dma_register {
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#ifdef __ADSPBF60x__
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void *next_desc_ptr; /* DMA Next Descriptor Pointer register */
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unsigned long start_addr; /* DMA Start address register */
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u32 start_addr; /* DMA Start address register */
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u32 config; /* DMA Configuration register */
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unsigned short cfg; /* DMA Configuration register */
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unsigned short dummy1; /* DMA Configuration register */
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u32 x_count; /* DMA x_count register */
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s32 x_modify; /* DMA x_modify register */
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u32 y_count; /* DMA y_count register */
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s32 y_modify; /* DMA y_modify register */
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u32 __pad0[2];
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unsigned long reserved;
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void *curr_desc_ptr; /* DMA Curr Descriptor Pointer register */
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void *prev_desc_ptr; /* DMA Prev Descriptor Pointer register */
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void *curr_addr; /* DMA Current Address Pointer register */
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u32 status; /* DMA irq status register */
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u32 curr_x_count; /* DMA Current x-count register */
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u32 curr_y_count; /* DMA Current y-count register */
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u32 __pad1[2];
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unsigned short x_count; /* DMA x_count register */
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unsigned short dummy2;
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u32 bw_limit; /* DMA Bandwidth Limit Count */
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u32 curr_bw_limit; /* DMA curr Bandwidth Limit Count */
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u32 bw_monitor; /* DMA Bandwidth Monitor Count */
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u32 curr_bw_monitor; /* DMA curr Bandwidth Monitor Count */
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#else
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void *next_desc_ptr; /* DMA Next Descriptor Pointer register */
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u32 start_addr; /* DMA Start address register */
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short x_modify; /* DMA x_modify register */
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unsigned short dummy3;
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u16 config; /* DMA Configuration register */
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u16 dummy1; /* DMA Configuration register */
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unsigned short y_count; /* DMA y_count register */
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unsigned short dummy4;
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u32 reserved;
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short y_modify; /* DMA y_modify register */
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unsigned short dummy5;
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u16 x_count; /* DMA x_count register */
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u16 dummy2;
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void *curr_desc_ptr; /* DMA Current Descriptor Pointer
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register */
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unsigned long curr_addr_ptr; /* DMA Current Address Pointer
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register */
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unsigned short irq_status; /* DMA irq status register */
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unsigned short dummy6;
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s16 x_modify; /* DMA x_modify register */
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u16 dummy3;
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unsigned short peripheral_map; /* DMA peripheral map register */
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unsigned short dummy7;
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u16 y_count; /* DMA y_count register */
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u16 dummy4;
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unsigned short curr_x_count; /* DMA Current x-count register */
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unsigned short dummy8;
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s16 y_modify; /* DMA y_modify register */
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u16 dummy5;
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unsigned long reserved2;
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void *curr_desc_ptr; /* DMA Current Descriptor Pointer register */
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unsigned short curr_y_count; /* DMA Current y-count register */
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unsigned short dummy9;
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u32 curr_addr_ptr; /* DMA Current Address Pointer register */
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unsigned long reserved3;
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u16 status; /* DMA irq status register */
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u16 dummy6;
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u16 peripheral_map; /* DMA peripheral map register */
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u16 dummy7;
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u16 curr_x_count; /* DMA Current x-count register */
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u16 dummy8;
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u32 reserved2;
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u16 curr_y_count; /* DMA Current y-count register */
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u16 dummy9;
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u32 reserved3;
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#endif
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};
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#endif
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@ -9,14 +9,54 @@
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#define DMAEN 0x0001 /* DMA Channel Enable */
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#define WNR 0x0002 /* Channel Direction (W/R*) */
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#define WDSIZE_8 0x0000 /* Transfer Word Size = 8 */
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#ifdef CONFIG_BF60x
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#define PSIZE_8 0x00000000 /* Transfer Word Size = 16 */
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#define PSIZE_16 0x00000010 /* Transfer Word Size = 16 */
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#define PSIZE_32 0x00000020 /* Transfer Word Size = 32 */
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#define PSIZE_64 0x00000030 /* Transfer Word Size = 32 */
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#define WDSIZE_16 0x00000100 /* Transfer Word Size = 16 */
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#define WDSIZE_32 0x00000200 /* Transfer Word Size = 32 */
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#define WDSIZE_64 0x00000300 /* Transfer Word Size = 32 */
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#define WDSIZE_128 0x00000400 /* Transfer Word Size = 32 */
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#define WDSIZE_256 0x00000500 /* Transfer Word Size = 32 */
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#define DMA2D 0x04000000 /* DMA Mode (2D/1D*) */
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#define RESTART 0x00000004 /* DMA Buffer Clear SYNC */
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#define DI_EN_X 0x00100000 /* Data Int Enable in X count */
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#define DI_EN_Y 0x00200000 /* Data Int Enable in Y count */
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#define DI_EN_P 0x00300000 /* Data Int Enable in Peri */
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#define DI_EN DI_EN_X /* Data Int Enable */
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#define NDSIZE_0 0x00000000 /* Next Desc Size = 0 */
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#define NDSIZE_1 0x00010000 /* Next Desc Size = 1 */
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#define NDSIZE_2 0x00020000 /* Next Desc Size = 2 */
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#define NDSIZE_3 0x00030000 /* Next Desc Size = 3 */
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#define NDSIZE_4 0x00040000 /* Next Desc Size = 4 */
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#define NDSIZE_5 0x00050000 /* Next Desc Size = 5 */
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#define NDSIZE_6 0x00060000 /* Next Desc Size = 6 */
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#define NDSIZE 0x00070000 /* Next Desc Size */
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#define NDSIZE_OFFSET 16 /* Next Desc Size Offset */
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#define DMAFLOW_LIST 0x00004000 /* Desc List Mode */
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#define DMAFLOW_ARRAY 0x00005000 /* Desc Array Mode */
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#define DMAFLOW_LIST_DEMAND 0x00006000 /* Desc Demand List Mode */
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#define DMAFLOW_ARRAY_DEMAND 0x00007000 /* Desc Demand Array Mode */
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#define DMA_RUN_DFETCH 0x00000100 /* DMA Channel Run (DFETCH) */
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#define DMA_RUN 0x00000200 /* DMA Channel Run */
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#define DMA_RUN_WAIT_TRIG 0x00000300 /* DMA Channel Run (WAIT TRIG)*/
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#define DMA_RUN_WAIT_ACK 0x00000400 /* DMA Channel Run (WAIT ACK) */
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#else
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#define WDSIZE_16 0x0004 /* Transfer Word Size = 16 */
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#define WDSIZE_32 0x0008 /* Transfer Word Size = 32 */
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#define PSIZE_16 WDSIZE_16
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#define PSIZE_32 WDSIZE_32
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#define DMA2D 0x0010 /* DMA Mode (2D/1D*) */
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#define RESTART 0x0020 /* DMA Buffer Clear */
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#define DI_SEL 0x0040 /* Data Interrupt Timing Select */
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#define DI_EN 0x0080 /* Data Interrupt Enable */
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#define NDSIZE 0x0F00 /* Next Descriptor bitmask */
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#define NDSIZE_0 0x0000 /* Next Descriptor Size = 0 (Stop/Autobuffer) */
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#define NDSIZE_0 0x0000 /* Next Descriptor Size = 0 */
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#define NDSIZE_1 0x0100 /* Next Descriptor Size = 1 */
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#define NDSIZE_2 0x0200 /* Next Descriptor Size = 2 */
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#define NDSIZE_3 0x0300 /* Next Descriptor Size = 3 */
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@ -26,14 +66,13 @@
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#define NDSIZE_7 0x0700 /* Next Descriptor Size = 7 */
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#define NDSIZE_8 0x0800 /* Next Descriptor Size = 8 */
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#define NDSIZE_9 0x0900 /* Next Descriptor Size = 9 */
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#define FLOW_STOP 0x0000 /* Stop Mode */
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#define FLOW_AUTO 0x1000 /* Autobuffer Mode */
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#define FLOW_ARRAY 0x4000 /* Descriptor Array Mode */
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#define FLOW_SMALL 0x6000 /* Small Model Descriptor List Mode */
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#define FLOW_LARGE 0x7000 /* Large Model Descriptor List Mode */
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#define DMAEN_P 0 /* Channel Enable */
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#define WNR_P 1 /* Channel Direction (W/R*) */
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#define WDSIZE_P 2 /* Transfer Word Size */
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#define DMA2D_P 4 /* 2D/1D* Mode */
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#define RESTART_P 5 /* Restart */
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#define DI_SEL_P 6 /* Data Interrupt Select */
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@ -45,14 +84,19 @@
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#define DFETCH 0x0004 /* DMA Descriptor Fetch Indicator */
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#define DMA_RUN 0x0008 /* DMA Channel Running Indicator */
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#endif
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#define DMAFLOW 0x7000 /* Flow Control */
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#define FLOW_STOP 0x0000 /* Stop Mode */
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#define FLOW_AUTO 0x1000 /* Autobuffer Mode */
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#define DMA_DONE_P 0 /* DMA Done Indicator */
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#define DMA_ERR_P 1 /* DMA Error Indicator */
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#define DFETCH_P 2 /* Descriptor Fetch Indicator */
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#define DMA_RUN_P 3 /* DMA Running Indicator */
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/* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP Masks */
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#define CTYPE 0x0040 /* DMA Channel Type Indicator (Memory/Peripheral*) */
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#define CTYPE_P 6 /* DMA Channel Type Indicator BIT POSITION */
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#define CTYPE 0x0040 /* DMA Channel Type (Mem/Peri) */
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#define CTYPE_P 6 /* DMA Channel Type BIT POSITION */
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#define PMAP 0xF000 /* Peripheral Mapped To This Channel */
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#endif
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@ -29,7 +29,7 @@
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#include <config.h>
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#include <asm/blackfin.h>
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#include <asm/io.h>
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#include <asm/mach-common/bits/dma.h>
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#include <asm/dma.h>
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char *strcpy(char *dest, const char *src)
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{
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@ -117,81 +117,88 @@ int strncmp(const char *cs, const char *ct, size_t count)
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return __res1;
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}
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#ifdef bfin_write_MDMA1_D0_IRQ_STATUS
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# define bfin_write_MDMA_D0_IRQ_STATUS bfin_write_MDMA1_D0_IRQ_STATUS
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# define bfin_write_MDMA_D0_START_ADDR bfin_write_MDMA1_D0_START_ADDR
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# define bfin_write_MDMA_D0_X_COUNT bfin_write_MDMA1_D0_X_COUNT
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# define bfin_write_MDMA_D0_X_MODIFY bfin_write_MDMA1_D0_X_MODIFY
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# define bfin_write_MDMA_D0_CONFIG bfin_write_MDMA1_D0_CONFIG
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# define bfin_write_MDMA_S0_START_ADDR bfin_write_MDMA1_S0_START_ADDR
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# define bfin_write_MDMA_S0_X_COUNT bfin_write_MDMA1_S0_X_COUNT
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# define bfin_write_MDMA_S0_X_MODIFY bfin_write_MDMA1_S0_X_MODIFY
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# define bfin_write_MDMA_S0_CONFIG bfin_write_MDMA1_S0_CONFIG
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# define bfin_write_MDMA_D0_IRQ_STATUS bfin_write_MDMA1_D0_IRQ_STATUS
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# define bfin_read_MDMA_D0_IRQ_STATUS bfin_read_MDMA1_D0_IRQ_STATUS
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#ifdef MDMA1_D0_NEXT_DESC_PTR
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# define MDMA_D0_NEXT_DESC_PTR MDMA1_D0_NEXT_DESC_PTR
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# define MDMA_S0_NEXT_DESC_PTR MDMA1_S0_NEXT_DESC_PTR
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#endif
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static void dma_calc_size(unsigned long ldst, unsigned long lsrc, size_t count,
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unsigned long *dshift, unsigned long *bpos)
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{
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unsigned long limit;
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#ifdef MSIZE
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limit = 6;
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*dshift = MSIZE_P;
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#else
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limit = 3;
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*dshift = WDSIZE_P;
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#endif
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*bpos = min(limit, ffs(ldst | lsrc | count)) - 1;
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}
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/* This version misbehaves for count values of 0 and 2^16+.
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* Perhaps we should detect that ? Nowhere do we actually
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* use dma memcpy for those types of lengths though ...
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*/
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void dma_memcpy_nocache(void *dst, const void *src, size_t count)
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{
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uint16_t wdsize, mod;
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struct dma_register *mdma_d0 = (void *)MDMA_D0_NEXT_DESC_PTR;
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struct dma_register *mdma_s0 = (void *)MDMA_S0_NEXT_DESC_PTR;
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unsigned long ldst = (unsigned long)dst;
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unsigned long lsrc = (unsigned long)src;
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unsigned long dshift, bpos;
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uint32_t dsize, mod;
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/* Disable DMA in case it's still running (older u-boot's did not
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* always turn them off). Do it before the if statement below so
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* we can be cheap and not do a SSYNC() due to the forced abort.
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*/
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bfin_write_MDMA_D0_CONFIG(0);
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bfin_write_MDMA_S0_CONFIG(0);
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bfin_write_MDMA_D0_IRQ_STATUS(DMA_RUN | DMA_DONE | DMA_ERR);
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bfin_write(&mdma_d0->config, 0);
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bfin_write(&mdma_s0->config, 0);
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bfin_write(&mdma_d0->status, DMA_RUN | DMA_DONE | DMA_ERR);
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/* Scratchpad cannot be a DMA source or destination */
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if (((unsigned long)src >= L1_SRAM_SCRATCH &&
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(unsigned long)src < L1_SRAM_SCRATCH_END) ||
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((unsigned long)dst >= L1_SRAM_SCRATCH &&
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(unsigned long)dst < L1_SRAM_SCRATCH_END))
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if ((lsrc >= L1_SRAM_SCRATCH && lsrc < L1_SRAM_SCRATCH_END) ||
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(ldst >= L1_SRAM_SCRATCH && ldst < L1_SRAM_SCRATCH_END))
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hang();
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if (((unsigned long)dst | (unsigned long)src | count) & 0x1) {
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wdsize = WDSIZE_8;
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mod = 1;
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} else if (((unsigned long)dst | (unsigned long)src | count) & 0x2) {
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wdsize = WDSIZE_16;
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count >>= 1;
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mod = 2;
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} else {
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wdsize = WDSIZE_32;
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count >>= 2;
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mod = 4;
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}
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dma_calc_size(ldst, lsrc, count, &dshift, &bpos);
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dsize = bpos << dshift;
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count >>= bpos;
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mod = 1 << bpos;
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#ifdef PSIZE
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dsize |= min(3, bpos) << PSIZE_P;
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#endif
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/* Copy sram functions from sdram to sram */
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/* Setup destination start address */
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bfin_write_MDMA_D0_START_ADDR(dst);
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bfin_write(&mdma_d0->start_addr, ldst);
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/* Setup destination xcount */
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bfin_write_MDMA_D0_X_COUNT(count);
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bfin_write(&mdma_d0->x_count, count);
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/* Setup destination xmodify */
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bfin_write_MDMA_D0_X_MODIFY(mod);
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bfin_write(&mdma_d0->x_modify, mod);
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/* Setup Source start address */
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bfin_write_MDMA_S0_START_ADDR(src);
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bfin_write(&mdma_s0->start_addr, lsrc);
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/* Setup Source xcount */
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bfin_write_MDMA_S0_X_COUNT(count);
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bfin_write(&mdma_s0->x_count, count);
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/* Setup Source xmodify */
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bfin_write_MDMA_S0_X_MODIFY(mod);
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bfin_write(&mdma_s0->x_modify, mod);
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/* Enable source DMA */
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bfin_write_MDMA_S0_CONFIG(wdsize | DMAEN);
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bfin_write_MDMA_D0_CONFIG(wdsize | DMAEN | WNR | DI_EN);
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bfin_write(&mdma_s0->config, dsize | DMAEN);
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bfin_write(&mdma_d0->config, dsize | DMAEN | WNR | DI_EN);
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SSYNC();
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while (!(bfin_read_MDMA_D0_IRQ_STATUS() & DMA_DONE))
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while (!(bfin_read(&mdma_d0->status) & DMA_DONE))
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continue;
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bfin_write_MDMA_D0_IRQ_STATUS(DMA_RUN | DMA_DONE | DMA_ERR);
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bfin_write_MDMA_D0_CONFIG(0);
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bfin_write_MDMA_S0_CONFIG(0);
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bfin_write(&mdma_d0->status, DMA_RUN | DMA_DONE | DMA_ERR);
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bfin_write(&mdma_d0->config, 0);
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bfin_write(&mdma_s0->config, 0);
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}
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/* We should do a dcache invalidate on the destination after the dma, but since
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* we lack such hardware capability, we'll flush/invalidate the destination
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