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sunxi: Support H3 CCU security switches

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H3's CCU includes some switches which disable non-secure access to some
of the more critical clock controls, such as MBUS, PLLs, and main
platform busses.

Configure them to enable non-secure access.

For now the only SoC that has this feature is the H3. For other
platforms just use a default (weak) empty function so things do
not break.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
This commit is contained in:
Chen-Yu Tsai 2016-01-06 15:13:07 +08:00 committed by Hans de Goede
parent 5823664fb8
commit ed80584f30
4 changed files with 26 additions and 0 deletions
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5
arch/arm/cpu/armv7/sunxi/clock.c
View File

@ -14,12 +14,17 @@
#include <asm/arch/gpio.h>
#include <asm/arch/sys_proto.h>
__weak void clock_init_sec(void)
{
}
int clock_init(void)
{
#ifdef CONFIG_SPL_BUILD
clock_init_safe();
#endif
clock_init_uart();
clock_init_sec();
return 0;
}

13
arch/arm/cpu/armv7/sunxi/clock_sun6i.c
View File

@ -45,6 +45,19 @@ void clock_init_safe(void)
}
#endif
void clock_init_sec(void)
{
#ifdef CONFIG_MACH_SUN8I_H3
struct sunxi_ccm_reg * const ccm =
(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
setbits_le32(&ccm->ccu_sec_switch,
CCM_SEC_SWITCH_MBUS_NONSEC |
CCM_SEC_SWITCH_BUS_NONSEC |
CCM_SEC_SWITCH_PLL_NONSEC);
#endif
}
void clock_init_uart(void)
{
#if CONFIG_CONS_INDEX < 5

1
arch/arm/include/asm/arch-sunxi/clock.h
View File

@ -30,6 +30,7 @@ int clock_init(void);
int clock_twi_onoff(int port, int state);
void clock_set_de_mod_clock(u32 *clk_cfg, unsigned int hz);
void clock_init_safe(void);
void clock_init_sec(void);
void clock_init_uart(void);
#endif

7
arch/arm/include/asm/arch-sunxi/clock_sun6i.h
View File

@ -137,6 +137,8 @@ struct sunxi_ccm_reg {
u32 apb1_reset_cfg; /* 0x2d0 APB1 Reset config */
u32 reserved24;
u32 apb2_reset_cfg; /* 0x2d8 APB2 Reset config */
u32 reserved25[5];
u32 ccu_sec_switch; /* 0x2f0 CCU Security Switch, H3 only */
};
/* apb2 bit field */
@ -375,6 +377,11 @@ struct sunxi_ccm_reg {
#define CCM_DE_CTRL_PLL10 (5 << 24)
#define CCM_DE_CTRL_GATE (1 << 31)
/* CCU security switch, H3 only */
#define CCM_SEC_SWITCH_MBUS_NONSEC (1 << 2)
#define CCM_SEC_SWITCH_BUS_NONSEC (1 << 1)
#define CCM_SEC_SWITCH_PLL_NONSEC (1 << 0)
#ifndef __ASSEMBLY__
void clock_set_pll1(unsigned int hz);
void clock_set_pll3(unsigned int hz);