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ppc4xx: Change Kilauea to use the common DDR2 init function

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This patch changes the kilauea and kilauea_nand (for NAND booting)
board port to not use a board specific DDR2 init routine anymore. Now
the common code from cpu/ppc4xx is used.

Thanks to Grant Erickson for all his basic work on this 405EX early
bootup.

Signed-off-by: Stefan Roese <sr@denx.de>
This commit is contained in:
Stefan Roese
2008-06-02 17:13:55 +02:00
parent 17ceb069b8
commit ec724f883e
8 changed files with 29 additions and 271 deletions
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11
cpu/ppc4xx/44x_spd_ddr2.c
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@@ -3083,6 +3083,16 @@ static void ppc440sp_sdram_register_dump(void)
*---------------------------------------------------------------------------*/
long initdram(int board_type)
{
/*
* Only run this SDRAM init code once. For NAND booting
* targets like Kilauea, we call initdram() early from the
* 4k NAND booting image (CONFIG_NAND_SPL) from nand_boot().
* Later on the NAND U-Boot image runs (CONFIG_NAND_U_BOOT)
* which calls initdram() again. This time the controller
* mustn't be reconfigured again since we're already running
* from SDRAM.
*/
#if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
unsigned long val;
/* Set Memory Bank Configuration Registers */
@@ -3178,6 +3188,7 @@ long initdram(int board_type)
#if defined(CONFIG_DDR_ECC)
ecc_init(CFG_SDRAM_BASE, CFG_MBYTES_SDRAM << 20);
#endif /* defined(CONFIG_DDR_ECC) */
#endif /* !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) */
return (CFG_MBYTES_SDRAM << 20);
}