arm64: dts: k3: Add Support for AM654 SoC
Add initial DT support for AM654 EVM that runs on A53. Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
This commit is contained in:
Lokesh Vutla
Tom Rini
parent
1e5b116ed2
commit
ea8ad1d9b6
@ -552,6 +552,8 @@ dtb-$(CONFIG_TARGET_STM32MP1) += \
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stm32mp157c-ed1.dtb \
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stm32mp157c-ev1.dtb
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dtb-$(CONFIG_SOC_K3_AM6) += k3-am654-base-board.dtb
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targets += $(dtb-y)
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# Add any required device tree compiler flags here
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31
arch/arm/dts/k3-am65-main.dtsi
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31
arch/arm/dts/k3-am65-main.dtsi
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@ -0,0 +1,31 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Device Tree Source for AM6 SoC Family Main Domain peripherals
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*
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* Copyright (C) 2016-2018 Texas Instruments Incorporated - http://www.ti.com/
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*/
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&cbass_main {
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gic500: interrupt-controller@1800000 {
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compatible = "arm,gic-v3";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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#interrupt-cells = <3>;
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interrupt-controller;
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reg = <0x01800000 0x10000>, /* GICD */
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<0x01880000 0x90000>; /* GICR */
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/*
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* vcpumntirq:
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* virtual CPU interface maintenance interrupt
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*/
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interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
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gic_its: gic-its@18200000 {
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compatible = "arm,gic-v3-its";
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reg = <0x01820000 0x10000>;
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msi-controller;
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#msi-cells = <1>;
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};
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};
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};
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87
arch/arm/dts/k3-am65.dtsi
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87
arch/arm/dts/k3-am65.dtsi
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@ -0,0 +1,87 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Device Tree Source for AM6 SoC Family
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*
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* Copyright (C) 2016-2018 Texas Instruments Incorporated - http://www.ti.com/
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*/
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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/ {
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model = "Texas Instruments K3 AM654 SoC";
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compatible = "ti,am654";
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interrupt-parent = <&gic500>;
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#address-cells = <2>;
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#size-cells = <2>;
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chosen { };
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firmware {
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optee {
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compatible = "linaro,optee-tz";
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method = "smc";
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};
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psci: psci {
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compatible = "arm,psci-1.0";
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method = "smc";
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};
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};
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a53_timer0: timer-cl0-cpu0 {
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* cntpsirq */
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<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* cntpnsirq */
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<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* cntvirq */
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<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* cnthpirq */
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};
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pmu: pmu {
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compatible = "arm,armv8-pmuv3";
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/* Recommendation from GIC500 TRM Table A.3 */
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interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
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};
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cbass_main: interconnect@100000 {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x00100000 0x00 0x00100000 0x00020000>, /* ctrl mmr */
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<0x00600000 0x00 0x00600000 0x00001100>, /* GPIO */
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<0x00900000 0x00 0x00900000 0x00012000>, /* serdes */
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<0x01000000 0x00 0x01000000 0x0af02400>, /* Most peripherals */
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<0x30800000 0x00 0x30800000 0x0bc00000>, /* MAIN NAVSS */
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/* MCUSS Range */
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<0x28380000 0x00 0x28380000 0x03880000>,
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<0x40200000 0x00 0x40200000 0x00900100>,
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<0x42040000 0x00 0x42040000 0x03ac2400>,
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<0x45100000 0x00 0x45100000 0x00c24000>,
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<0x46000000 0x00 0x46000000 0x00200000>,
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<0x47000000 0x00 0x47000000 0x00068400>;
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cbass_mcu: interconnect@28380000 {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x28380000 0x28380000 0x03880000>, /* MCU NAVSS*/
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<0x40200000 0x40200000 0x00900100>, /* First peripheral window */
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<0x42040000 0x42040000 0x03ac2400>, /* WKUP */
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<0x45100000 0x45100000 0x00c24000>, /* MMRs, remaining NAVSS */
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<0x46000000 0x46000000 0x00200000>, /* CPSW */
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<0x47000000 0x47000000 0x00068400>; /* OSPI space 1 */
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cbass_wakeup: interconnect@42040000 {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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/* WKUP Basic peripherals */
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ranges = <0x42040000 0x42040000 0x03ac2400>;
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};
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};
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};
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};
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/* Now include the peripherals for each bus segments */
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#include "k3-am65-main.dtsi"
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36
arch/arm/dts/k3-am654-base-board.dts
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36
arch/arm/dts/k3-am654-base-board.dts
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@ -0,0 +1,36 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2016-2018 Texas Instruments Incorporated - http://www.ti.com/
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*/
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/dts-v1/;
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#include "k3-am654.dtsi"
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/ {
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compatible = "ti,am654-evm", "ti,am654";
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model = "Texas Instruments AM654 Base Board";
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chosen {
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stdout-path = "serial2:115200n8";
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bootargs = "earlycon=ns16550a,mmio32,0x02800000";
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};
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memory@80000000 {
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device_type = "memory";
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/* 4G RAM */
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reg = <0x00000000 0x80000000 0x00000000 0x80000000>,
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<0x00000008 0x80000000 0x00000000 0x80000000>;
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};
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reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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secure_ddr: secure_ddr@9e800000 {
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reg = <0 0x9e800000 0 0x01800000>; /* for OP-TEE */
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alignment = <0x1000>;
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no-map;
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};
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};
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};
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115
arch/arm/dts/k3-am654.dtsi
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115
arch/arm/dts/k3-am654.dtsi
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@ -0,0 +1,115 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Device Tree Source for AM6 SoC family in Quad core configuration
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*
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* Copyright (C) 2016-2018 Texas Instruments Incorporated - http://www.ti.com/
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*/
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#include "k3-am65.dtsi"
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/ {
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu-map {
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cluster0: cluster0 {
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core0 {
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cpu = <&cpu0>;
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};
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core1 {
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cpu = <&cpu1>;
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};
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};
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cluster1: cluster1 {
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core0 {
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cpu = <&cpu2>;
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};
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core1 {
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cpu = <&cpu3>;
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};
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};
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};
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cpu0: cpu@0 {
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compatible = "arm,cortex-a53", "arm,armv8";
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reg = <0x000>;
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device_type = "cpu";
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enable-method = "psci";
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i-cache-size = <0x8000>;
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i-cache-line-size = <64>;
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i-cache-sets = <256>;
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d-cache-size = <0x8000>;
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d-cache-line-size = <64>;
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d-cache-sets = <128>;
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next-level-cache = <&L2_0>;
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};
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cpu1: cpu@1 {
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compatible = "arm,cortex-a53", "arm,armv8";
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reg = <0x001>;
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device_type = "cpu";
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enable-method = "psci";
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i-cache-size = <0x8000>;
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i-cache-line-size = <64>;
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i-cache-sets = <256>;
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d-cache-size = <0x8000>;
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d-cache-line-size = <64>;
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d-cache-sets = <128>;
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next-level-cache = <&L2_0>;
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};
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cpu2: cpu@100 {
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compatible = "arm,cortex-a53", "arm,armv8";
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reg = <0x100>;
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device_type = "cpu";
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enable-method = "psci";
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i-cache-size = <0x8000>;
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i-cache-line-size = <64>;
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i-cache-sets = <256>;
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d-cache-size = <0x8000>;
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d-cache-line-size = <64>;
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d-cache-sets = <128>;
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next-level-cache = <&L2_1>;
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};
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cpu3: cpu@101 {
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compatible = "arm,cortex-a53", "arm,armv8";
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reg = <0x101>;
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device_type = "cpu";
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enable-method = "psci";
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i-cache-size = <0x8000>;
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i-cache-line-size = <64>;
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i-cache-sets = <256>;
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d-cache-size = <0x8000>;
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d-cache-line-size = <64>;
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d-cache-sets = <128>;
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next-level-cache = <&L2_1>;
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};
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};
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L2_0: l2-cache0 {
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compatible = "cache";
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cache-level = <2>;
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cache-size = <0x80000>;
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cache-line-size = <64>;
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cache-sets = <512>;
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next-level-cache = <&msmc_l3>;
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};
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L2_1: l2-cache1 {
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compatible = "cache";
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cache-level = <2>;
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cache-size = <0x80000>;
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cache-line-size = <64>;
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cache-sets = <512>;
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next-level-cache = <&msmc_l3>;
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};
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msmc_l3: l3-cache0 {
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compatible = "cache";
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cache-level = <3>;
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};
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};
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@ -54,3 +54,15 @@ int dram_init_banksize(void)
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return 0;
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}
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#ifdef CONFIG_SPL_LOAD_FIT
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int board_fit_config_name_match(const char *name)
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{
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#ifdef CONFIG_TARGET_AM654_A53_EVM
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if (!strcmp(name, "k3-am654-base-board"))
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return 0;
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#endif
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return -1;
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}
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#endif
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