From 50b2184257c27833eece838dff5a519f07325082 Mon Sep 17 00:00:00 2001 From: Patrick Delaunay Date: Mon, 20 Jun 2022 09:50:01 +0200 Subject: [PATCH 01/10] stm32mp: simplify the STM32MP15x package parsing code Simplify the package parsing code for STM32MP15X as package can be affected with get_cpu_package() result. Signed-off-by: Patrick Delaunay Reviewed-by: Patrice Chotard --- arch/arm/mach-stm32mp/stm32mp15x.c | 15 +++------------ 1 file changed, 3 insertions(+), 12 deletions(-) diff --git a/arch/arm/mach-stm32mp/stm32mp15x.c b/arch/arm/mach-stm32mp/stm32mp15x.c index a093e6163e..660c907a6b 100644 --- a/arch/arm/mach-stm32mp/stm32mp15x.c +++ b/arch/arm/mach-stm32mp/stm32mp15x.c @@ -274,7 +274,6 @@ static void get_cpu_string_offsets(unsigned int *type, unsigned int *pkg, u32 cpu_type = get_cpu_type(); u32 ct = cpu_type & ~(BIT(7) | BIT(0)); u32 cm = ((cpu_type & BIT(7)) >> 6) | (cpu_type & BIT(0)); - u32 cp = get_cpu_package(); /* Bits 0 and 7 are the ACDF, 00:C 01:A 10:F 11:D */ switch (ct) { @@ -293,17 +292,9 @@ static void get_cpu_string_offsets(unsigned int *type, unsigned int *pkg, } /* Package */ - switch (cp) { - case STM32MP15_PKG_AA_LBGA448: - case STM32MP15_PKG_AB_LBGA354: - case STM32MP15_PKG_AC_TFBGA361: - case STM32MP15_PKG_AD_TFBGA257: - *pkg = cp; - break; - default: - *pkg = 0; - break; - } + *pkg = get_cpu_package(); + if (*pkg > STM32MP15_PKG_AA_LBGA448) + *pkg = STM32MP15_PKG_UNKNOWN; /* Revision */ switch (get_cpu_rev()) { From 0a1a755636a94da71bd79860884bc97d64fba36b Mon Sep 17 00:00:00 2001 From: Patrick Delaunay Date: Mon, 20 Jun 2022 12:36:10 +0200 Subject: [PATCH 02/10] board: stm32mp1: remove test on CONFIG_DM_REGULATOR The tests on CONFIG_DM_REGULATOR, added to avoid compilation issues, can now be removed, they are no more needed since the commit 16cc5ad0b439 ("power: regulator: add dummy helper"). Signed-off-by: Patrick Delaunay Reviewed-by: Patrice Chotard --- board/st/stm32mp1/stm32mp1.c | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/board/st/stm32mp1/stm32mp1.c b/board/st/stm32mp1/stm32mp1.c index 9496890d16..8c162b42a5 100644 --- a/board/st/stm32mp1/stm32mp1.c +++ b/board/st/stm32mp1/stm32mp1.c @@ -494,7 +494,7 @@ static void sysconf_init(void) ret = uclass_get_device_by_driver(UCLASS_PMIC, DM_DRIVER_GET(stm32mp_pwr_pmic), &pwr_dev); - if (!ret && IS_ENABLED(CONFIG_DM_REGULATOR)) { + if (!ret) { ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(stm32mp_bsec), &dev); @@ -555,9 +555,6 @@ static int board_stm32mp15x_dk2_init(void) struct gpio_desc hdmi, audio; int ret = 0; - if (!IS_ENABLED(CONFIG_DM_REGULATOR)) - return -ENODEV; - /* Fix to make I2C1 usable on DK2 for touchscreen usage in kernel */ node = ofnode_path("/soc/i2c@40012000/hdmi-transmitter@39"); if (!ofnode_valid(node)) { @@ -658,8 +655,7 @@ int board_init(void) if (board_is_stm32mp15x_dk2()) board_stm32mp15x_dk2_init(); - if (IS_ENABLED(CONFIG_DM_REGULATOR)) - regulators_enable_boot_on(_DEBUG); + regulators_enable_boot_on(_DEBUG); /* * sysconf initialisation done only when U-Boot is running in secure From 3c2db629581fbde2140a5cc6ec4f5b1f2290bda6 Mon Sep 17 00:00:00 2001 From: Patrick Delaunay Date: Tue, 26 Apr 2022 14:37:47 +0200 Subject: [PATCH 03/10] phy: stm32-usbphyc: add counter of PLL consumer Add the counter of the PLL user n_pll_cons managed by the 2 functions stm32_usbphyc_pll_enable / stm32_usbphyc_pll_disable. This counter allow to remove the function stm32_usbphyc_is_init and it is a preliminary step for ck_usbo_48m introduction. Signed-off-by: Patrick Delaunay Reviewed-by: Patrice Chotard --- drivers/phy/phy-stm32-usbphyc.c | 76 +++++++++++++++++++++------------ 1 file changed, 48 insertions(+), 28 deletions(-) diff --git a/drivers/phy/phy-stm32-usbphyc.c b/drivers/phy/phy-stm32-usbphyc.c index d7f7c37f91..bb743fe16f 100644 --- a/drivers/phy/phy-stm32-usbphyc.c +++ b/drivers/phy/phy-stm32-usbphyc.c @@ -144,6 +144,7 @@ struct stm32_usbphyc { bool init; bool powered; } phys[MAX_PHYS]; + int n_pll_cons; }; static void stm32_usbphyc_get_pll_params(u32 clk_rate, @@ -203,18 +204,6 @@ static int stm32_usbphyc_pll_init(struct stm32_usbphyc *usbphyc) return 0; } -static bool stm32_usbphyc_is_init(struct stm32_usbphyc *usbphyc) -{ - int i; - - for (i = 0; i < MAX_PHYS; i++) { - if (usbphyc->phys[i].init) - return true; - } - - return false; -} - static bool stm32_usbphyc_is_powered(struct stm32_usbphyc *usbphyc) { int i; @@ -227,18 +216,17 @@ static bool stm32_usbphyc_is_powered(struct stm32_usbphyc *usbphyc) return false; } -static int stm32_usbphyc_phy_init(struct phy *phy) +static int stm32_usbphyc_pll_enable(struct stm32_usbphyc *usbphyc) { - struct stm32_usbphyc *usbphyc = dev_get_priv(phy->dev); - struct stm32_usbphyc_phy *usbphyc_phy = usbphyc->phys + phy->id; bool pllen = readl(usbphyc->base + STM32_USBPHYC_PLL) & PLLEN ? true : false; int ret; - dev_dbg(phy->dev, "phy ID = %lu\n", phy->id); - /* Check if one phy port has already configured the pll */ - if (pllen && stm32_usbphyc_is_init(usbphyc)) - goto initialized; + /* Check if one consumer has already configured the pll */ + if (pllen && usbphyc->n_pll_cons) { + usbphyc->n_pll_cons++; + return 0; + } if (usbphyc->vdda1v1) { ret = regulator_set_enable(usbphyc->vdda1v1, true); @@ -269,23 +257,19 @@ static int stm32_usbphyc_phy_init(struct phy *phy) if (!(readl(usbphyc->base + STM32_USBPHYC_PLL) & PLLEN)) return -EIO; -initialized: - usbphyc_phy->init = true; + usbphyc->n_pll_cons++; return 0; } -static int stm32_usbphyc_phy_exit(struct phy *phy) +static int stm32_usbphyc_pll_disable(struct stm32_usbphyc *usbphyc) { - struct stm32_usbphyc *usbphyc = dev_get_priv(phy->dev); - struct stm32_usbphyc_phy *usbphyc_phy = usbphyc->phys + phy->id; int ret; - dev_dbg(phy->dev, "phy ID = %lu\n", phy->id); - usbphyc_phy->init = false; + usbphyc->n_pll_cons--; - /* Check if other phy port requires pllen */ - if (stm32_usbphyc_is_init(usbphyc)) + /* Check if other consumer requires pllen */ + if (usbphyc->n_pll_cons) return 0; clrbits_le32(usbphyc->base + STM32_USBPHYC_PLL, PLLEN); @@ -314,6 +298,42 @@ static int stm32_usbphyc_phy_exit(struct phy *phy) return 0; } +static int stm32_usbphyc_phy_init(struct phy *phy) +{ + struct stm32_usbphyc *usbphyc = dev_get_priv(phy->dev); + struct stm32_usbphyc_phy *usbphyc_phy = usbphyc->phys + phy->id; + int ret; + + dev_dbg(phy->dev, "phy ID = %lu\n", phy->id); + if (usbphyc_phy->init) + return 0; + + ret = stm32_usbphyc_pll_enable(usbphyc); + if (ret) + return log_ret(ret); + + usbphyc_phy->init = true; + + return 0; +} + +static int stm32_usbphyc_phy_exit(struct phy *phy) +{ + struct stm32_usbphyc *usbphyc = dev_get_priv(phy->dev); + struct stm32_usbphyc_phy *usbphyc_phy = usbphyc->phys + phy->id; + int ret; + + dev_dbg(phy->dev, "phy ID = %lu\n", phy->id); + if (!usbphyc_phy->init) + return 0; + + ret = stm32_usbphyc_pll_disable(usbphyc); + + usbphyc_phy->init = false; + + return log_ret(ret); +} + static int stm32_usbphyc_phy_power_on(struct phy *phy) { struct stm32_usbphyc *usbphyc = dev_get_priv(phy->dev); From 9406f9735c998a179d8ecc886ad7d5287473222f Mon Sep 17 00:00:00 2001 From: Patrick Delaunay Date: Tue, 26 Apr 2022 14:37:48 +0200 Subject: [PATCH 04/10] phy: stm32-usbphyc: usbphyc is a clock provider of ck_usbo_48m clock ck_usbo_48m is generated by usbphyc PLL and used by OTG controller for Full-Speed use cases with dedicated Full-Speed transceiver. ck_usbo_48m is available as soon as the PLL is enabled. Signed-off-by: Patrick Delaunay Reviewed-by: Patrice Chotard --- drivers/phy/phy-stm32-usbphyc.c | 79 +++++++++++++++++++++++++++++++++ 1 file changed, 79 insertions(+) diff --git a/drivers/phy/phy-stm32-usbphyc.c b/drivers/phy/phy-stm32-usbphyc.c index bb743fe16f..9f0b7d7118 100644 --- a/drivers/phy/phy-stm32-usbphyc.c +++ b/drivers/phy/phy-stm32-usbphyc.c @@ -7,6 +7,7 @@ #include #include +#include #include #include #include @@ -17,6 +18,7 @@ #include #include #include +#include #include #include #include @@ -72,6 +74,9 @@ #define PLL_INFF_MIN_RATE 19200000 /* in Hz */ #define PLL_INFF_MAX_RATE 38400000 /* in Hz */ +/* USBPHYC_CLK48 */ +#define USBPHYC_CLK48_FREQ 48000000 /* in Hz */ + enum boosting_vals { BOOST_1000_UA = 1000, BOOST_2000_UA = 2000, @@ -518,6 +523,16 @@ static const struct phy_ops stm32_usbphyc_phy_ops = { .of_xlate = stm32_usbphyc_of_xlate, }; +static int stm32_usbphyc_bind(struct udevice *dev) +{ + int ret; + + ret = device_bind_driver_to_node(dev, "stm32-usbphyc-clk", "ck_usbo_48m", + dev_ofnode(dev), NULL); + + return log_ret(ret); +} + static int stm32_usbphyc_probe(struct udevice *dev) { struct stm32_usbphyc *usbphyc = dev_get_priv(dev); @@ -611,6 +626,70 @@ U_BOOT_DRIVER(stm32_usb_phyc) = { .id = UCLASS_PHY, .of_match = stm32_usbphyc_of_match, .ops = &stm32_usbphyc_phy_ops, + .bind = stm32_usbphyc_bind, .probe = stm32_usbphyc_probe, .priv_auto = sizeof(struct stm32_usbphyc), }; + +struct stm32_usbphyc_clk { + bool enable; +}; + +static ulong stm32_usbphyc_clk48_get_rate(struct clk *clk) +{ + return USBPHYC_CLK48_FREQ; +} + +static int stm32_usbphyc_clk48_enable(struct clk *clk) +{ + struct stm32_usbphyc_clk *usbphyc_clk = dev_get_priv(clk->dev); + struct stm32_usbphyc *usbphyc; + int ret; + + if (usbphyc_clk->enable) + return 0; + + usbphyc = dev_get_priv(clk->dev->parent); + + /* ck_usbo_48m is generated by usbphyc PLL */ + ret = stm32_usbphyc_pll_enable(usbphyc); + if (ret) + return ret; + + usbphyc_clk->enable = true; + + return 0; +} + +static int stm32_usbphyc_clk48_disable(struct clk *clk) +{ + struct stm32_usbphyc_clk *usbphyc_clk = dev_get_priv(clk->dev); + struct stm32_usbphyc *usbphyc; + int ret; + + if (!usbphyc_clk->enable) + return 0; + + usbphyc = dev_get_priv(clk->dev->parent); + + ret = stm32_usbphyc_pll_disable(usbphyc); + if (ret) + return ret; + + usbphyc_clk->enable = false; + + return 0; +} + +const struct clk_ops usbphyc_clk48_ops = { + .get_rate = stm32_usbphyc_clk48_get_rate, + .enable = stm32_usbphyc_clk48_enable, + .disable = stm32_usbphyc_clk48_disable, +}; + +U_BOOT_DRIVER(stm32_usb_phyc_clk) = { + .name = "stm32-usbphyc-clk", + .id = UCLASS_CLK, + .ops = &usbphyc_clk48_ops, + .priv_auto = sizeof(struct stm32_usbphyc_clk), +}; From 06328d1411cf1167133aff0bd56472a8f67724e0 Mon Sep 17 00:00:00 2001 From: Patrick Delaunay Date: Tue, 26 Apr 2022 14:37:49 +0200 Subject: [PATCH 05/10] clk: stm32mp: handle ck_usbo_48m clock provided by USBPHYC Handle the input clock of RCC USB_PHY_48, provided by USBPHYC and named "ck_usbo_48m". Signed-off-by: Patrick Delaunay Reviewed-by: Patrice Chotard --- drivers/clk/stm32/clk-stm32mp1.c | 35 ++++++++++++++++++-------------- 1 file changed, 20 insertions(+), 15 deletions(-) diff --git a/drivers/clk/stm32/clk-stm32mp1.c b/drivers/clk/stm32/clk-stm32mp1.c index 452550066e..4f4524fcb2 100644 --- a/drivers/clk/stm32/clk-stm32mp1.c +++ b/drivers/clk/stm32/clk-stm32mp1.c @@ -962,6 +962,24 @@ static ulong stm32mp1_read_pll_freq(struct stm32mp1_clk_priv *priv, return dfout; } +static ulong stm32mp1_clk_get_by_name(const char *name) +{ + struct clk clk; + struct udevice *dev = NULL; + ulong clock = 0; + + if (!uclass_get_device_by_name(UCLASS_CLK, name, &dev)) { + if (clk_request(dev, &clk)) { + log_err("%s request", name); + } else { + clk.id = 0; + clock = clk_get_rate(&clk); + } + } + + return clock; +} + static ulong stm32mp1_clk_get(struct stm32mp1_clk_priv *priv, int p) { u32 reg; @@ -1127,24 +1145,11 @@ static ulong stm32mp1_clk_get(struct stm32mp1_clk_priv *priv, int p) break; /* other */ case _USB_PHY_48: - clock = 48000000; + clock = stm32mp1_clk_get_by_name("ck_usbo_48m"); break; case _DSI_PHY: - { - struct clk clk; - struct udevice *dev = NULL; - - if (!uclass_get_device_by_name(UCLASS_CLK, "ck_dsi_phy", - &dev)) { - if (clk_request(dev, &clk)) { - log_err("ck_dsi_phy request"); - } else { - clk.id = 0; - clock = clk_get_rate(&clk); - } - } + clock = stm32mp1_clk_get_by_name("ck_dsi_phy"); break; - } default: break; } From 5468dc82cb5b4e9dbb3d2b988810ff0b4b1781f6 Mon Sep 17 00:00:00 2001 From: Patrice Chotard Date: Wed, 24 Aug 2022 15:42:37 +0200 Subject: [PATCH 06/10] ARM: dts: stm32: Fix display-timings settings for stm32f746-disco Since commit ef4ce6df3289 "video: stm32: stm32_ltdc: fix data enable polarity" The panel display output wasn't functional anymore. Device tree display-timings de-active property value must be updated to 1. Signed-off-by: Patrice Chotard Reviewed-by: Patrick Delaunay --- arch/arm/dts/stm32f746-disco-u-boot.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/dts/stm32f746-disco-u-boot.dtsi b/arch/arm/dts/stm32f746-disco-u-boot.dtsi index f88466fa60..a4ce936d7d 100644 --- a/arch/arm/dts/stm32f746-disco-u-boot.dtsi +++ b/arch/arm/dts/stm32f746-disco-u-boot.dtsi @@ -58,7 +58,7 @@ vsync-len = <10>; hsync-active = <0>; vsync-active = <0>; - de-active = <0>; + de-active = <1>; pixelclk-active = <1>; }; }; From 78e7cda76aba824e35df7162020d0ccc3ef06e88 Mon Sep 17 00:00:00 2001 From: Patrice Chotard Date: Wed, 24 Aug 2022 15:44:40 +0200 Subject: [PATCH 07/10] configs: stm32: Enable CONFIG_DM_REGULATOR for stm32f769-disco Since commit 5bc6f8c2a97e("video: stm32: remove test on CONFIG_DM_REGULATOR") backlight was broken with the following message at boot: stm32-display-dsi dsi@40016c00: Warning: cannot get phy dsi supply stm32_display display-controller@40016800: panel panel enable backlight error -38 DM_REGULATOR flag must be enabled to fix this issue Signed-off-by: Patrice Chotard Reviewed-by: Patrick Delaunay --- configs/stm32f769-disco_defconfig | 1 + configs/stm32f769-disco_spl_defconfig | 1 + 2 files changed, 2 insertions(+) diff --git a/configs/stm32f769-disco_defconfig b/configs/stm32f769-disco_defconfig index 1333c060d1..423af7446a 100644 --- a/configs/stm32f769-disco_defconfig +++ b/configs/stm32f769-disco_defconfig @@ -50,6 +50,7 @@ CONFIG_ETH_DESIGNWARE=y CONFIG_DW_ALTDESCRIPTOR=y CONFIG_MII=y # CONFIG_PINCTRL_FULL is not set +CONFIG_DM_REGULATOR=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_STM32_QSPI=y diff --git a/configs/stm32f769-disco_spl_defconfig b/configs/stm32f769-disco_spl_defconfig index 16763e29c3..80d411a769 100644 --- a/configs/stm32f769-disco_spl_defconfig +++ b/configs/stm32f769-disco_spl_defconfig @@ -71,6 +71,7 @@ CONFIG_ETH_DESIGNWARE=y CONFIG_DW_ALTDESCRIPTOR=y CONFIG_MII=y # CONFIG_PINCTRL_FULL is not set +CONFIG_DM_REGULATOR=y CONFIG_SPL_PINCTRL=y CONFIG_SPL_RAM=y CONFIG_SPECIFY_CONSOLE_INDEX=y From 29e03c98cfe196e3339090b07566d9889774ca0e Mon Sep 17 00:00:00 2001 From: Patrice Chotard Date: Thu, 25 Aug 2022 09:14:57 +0200 Subject: [PATCH 08/10] configs: stih410-b2260: Fix SYS_HZ_CLOCK value SYS_HZ_CLOCK was wrongly set to 1GHz whereas it's set to 750MHz by default by bootrom. Signed-off-by: Patrice Chotard Reviewed-by: Grzegorz Szymaszek --- include/configs/stih410-b2260.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/configs/stih410-b2260.h b/include/configs/stih410-b2260.h index b1a011bacb..1e966a2322 100644 --- a/include/configs/stih410-b2260.h +++ b/include/configs/stih410-b2260.h @@ -14,7 +14,7 @@ #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 #define PHYS_SDRAM_1_SIZE 0x3E000000 -#define CONFIG_SYS_HZ_CLOCK 1000000000 /* 1 GHz */ +#define CONFIG_SYS_HZ_CLOCK 750000000 /* 750 MHz */ /* Environment */ From 9cccc358c4a2f539746bc98c741e714cc7d9b5d2 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 23 Aug 2022 19:27:08 +0200 Subject: [PATCH 09/10] ARM: stm32: Switch DHSOM to FMC2 EBI driver Perform long overdue conversion of ad-hoc FMC2 EBI bus initialization to upstream FMC2 EBI driver. No functional change. Signed-off-by: Marek Vasut Cc: Patrice Chotard Cc: Patrick Delaunay Reviewed-by: Patrice Chotard Reviewed-by: Patrick Delaunay --- .../dts/stm32mp15xx-dhcom-picoitx-u-boot.dtsi | 8 --- arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi | 14 ----- .../stm32mp15xx-dhcor-drc-compact-u-boot.dtsi | 16 ------ board/dhelectronics/dh_stm32mp1/board.c | 52 ------------------- configs/stm32mp15_dhcom_basic_defconfig | 1 + configs/stm32mp15_dhcor_basic_defconfig | 1 + 6 files changed, 2 insertions(+), 90 deletions(-) diff --git a/arch/arm/dts/stm32mp15xx-dhcom-picoitx-u-boot.dtsi b/arch/arm/dts/stm32mp15xx-dhcom-picoitx-u-boot.dtsi index 5bc6698f87..0bcaec5019 100644 --- a/arch/arm/dts/stm32mp15xx-dhcom-picoitx-u-boot.dtsi +++ b/arch/arm/dts/stm32mp15xx-dhcom-picoitx-u-boot.dtsi @@ -5,14 +5,6 @@ #include "stm32mp15xx-dhcom-u-boot.dtsi" -/ { - aliases { - /delete-property/ ethernet1; - }; -}; - -/delete-node/ &ks8851; - &usbotg_hs { dr_mode = "peripheral"; }; diff --git a/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi b/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi index ee747a52bb..8a7156c93b 100644 --- a/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi +++ b/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi @@ -9,8 +9,6 @@ #include "stm32mp15-ddr3-dhsom-2x2Gb-1066-binG.dtsi" #include "stm32mp15-ddr3-dhsom-2x4Gb-1066-binG.dtsi" -/delete-node/ &ksz8851; - / { aliases { i2c1 = &i2c2; @@ -21,7 +19,6 @@ spi0 = &qspi; usb0 = &usbotg_hs; eeprom0 = &eeprom0; - ethernet1 = &ks8851; }; config { @@ -30,12 +27,6 @@ dh,som-coding-gpios = <&gpiof 12 0>, <&gpiof 13 0>, <&gpiof 15 0>; dh,ddr3-coding-gpios = <&gpioz 6 0>, <&gpioz 7 0>; }; - - /* This is actually on FMC2, but we do not have bus driver for that */ - ks8851: ks8851mll@64000000 { - compatible = "micrel,ks8851-mll"; - reg = <0x64000000 0x20000>; - }; }; ðernet0 { @@ -74,11 +65,6 @@ }; &pinctrl { - /* These should bound to FMC2 bus driver, but we do not have one */ - pinctrl-0 = <&fmc_pins_b &mco2_pins_a>; - pinctrl-1 = <&fmc_sleep_pins_b &mco2_sleep_pins_a>; - pinctrl-names = "default", "sleep"; - mco2_pins_a: mco2-0 { pins { pinmux = ; /* MCO2 */ diff --git a/arch/arm/dts/stm32mp15xx-dhcor-drc-compact-u-boot.dtsi b/arch/arm/dts/stm32mp15xx-dhcor-drc-compact-u-boot.dtsi index 407fed5616..b6a6a78647 100644 --- a/arch/arm/dts/stm32mp15xx-dhcor-drc-compact-u-boot.dtsi +++ b/arch/arm/dts/stm32mp15xx-dhcor-drc-compact-u-boot.dtsi @@ -5,25 +5,16 @@ #include "stm32mp15xx-dhcor-u-boot.dtsi" -/delete-node/ &ksz8851; - / { aliases { mmc0 = &sdmmc1; mmc1 = &sdmmc2; usb0 = &usbotg_hs; - ethernet1 = &ks8851; }; config { dh,board-coding-gpios = <&gpioh 9 0>, <&gpioh 8 0>, <&gpioh 3 0>; }; - - /* This is actually on FMC2, but we do not have bus driver for that */ - ks8851: ks8851mll@64000000 { - compatible = "micrel,ks8851-mll"; - reg = <0x64000000 0x20000>; - }; }; ðernet0 { @@ -38,13 +29,6 @@ }; }; -&pinctrl { - /* These should bound to FMC2 bus driver, but we do not have one */ - pinctrl-0 = <&fmc_pins_b>; - pinctrl-1 = <&fmc_sleep_pins_b>; - pinctrl-names = "default", "sleep"; -}; - &sdmmc1 { u-boot,dm-spl; st,use-ckin; diff --git a/board/dhelectronics/dh_stm32mp1/board.c b/board/dhelectronics/dh_stm32mp1/board.c index e3c7ed1049..9188f5381e 100644 --- a/board/dhelectronics/dh_stm32mp1/board.c +++ b/board/dhelectronics/dh_stm32mp1/board.c @@ -527,56 +527,6 @@ static void sysconf_init(void) #endif } -static void board_init_fmc2(void) -{ -#define STM32_FMC2_BCR1 0x0 -#define STM32_FMC2_BTR1 0x4 -#define STM32_FMC2_BWTR1 0x104 -#define STM32_FMC2_BCR(x) ((x) * 0x8 + STM32_FMC2_BCR1) -#define STM32_FMC2_BCRx_FMCEN BIT(31) -#define STM32_FMC2_BCRx_WREN BIT(12) -#define STM32_FMC2_BCRx_RSVD BIT(7) -#define STM32_FMC2_BCRx_FACCEN BIT(6) -#define STM32_FMC2_BCRx_MWID(n) ((n) << 4) -#define STM32_FMC2_BCRx_MTYP(n) ((n) << 2) -#define STM32_FMC2_BCRx_MUXEN BIT(1) -#define STM32_FMC2_BCRx_MBKEN BIT(0) -#define STM32_FMC2_BTR(x) ((x) * 0x8 + STM32_FMC2_BTR1) -#define STM32_FMC2_BTRx_DATAHLD(n) ((n) << 30) -#define STM32_FMC2_BTRx_BUSTURN(n) ((n) << 16) -#define STM32_FMC2_BTRx_DATAST(n) ((n) << 8) -#define STM32_FMC2_BTRx_ADDHLD(n) ((n) << 4) -#define STM32_FMC2_BTRx_ADDSET(n) ((n) << 0) - -#define RCC_MP_AHB6RSTCLRR 0x218 -#define RCC_MP_AHB6RSTCLRR_FMCRST BIT(12) -#define RCC_MP_AHB6ENSETR 0x19c -#define RCC_MP_AHB6ENSETR_FMCEN BIT(12) - - const u32 bcr = STM32_FMC2_BCRx_WREN |STM32_FMC2_BCRx_RSVD | - STM32_FMC2_BCRx_FACCEN | STM32_FMC2_BCRx_MWID(1) | - STM32_FMC2_BCRx_MTYP(2) | STM32_FMC2_BCRx_MUXEN | - STM32_FMC2_BCRx_MBKEN; - const u32 btr = STM32_FMC2_BTRx_DATAHLD(3) | - STM32_FMC2_BTRx_BUSTURN(2) | - STM32_FMC2_BTRx_DATAST(0x22) | - STM32_FMC2_BTRx_ADDHLD(2) | - STM32_FMC2_BTRx_ADDSET(2); - - /* Set up FMC2 bus for KS8851-16MLL and X11 SRAM */ - writel(RCC_MP_AHB6RSTCLRR_FMCRST, STM32_RCC_BASE + RCC_MP_AHB6RSTCLRR); - writel(RCC_MP_AHB6ENSETR_FMCEN, STM32_RCC_BASE + RCC_MP_AHB6ENSETR); - - /* KS8851-16MLL -- Muxed mode */ - writel(bcr, STM32_FMC2_BASE + STM32_FMC2_BCR(1)); - writel(btr, STM32_FMC2_BASE + STM32_FMC2_BTR(1)); - /* AS7C34098 SRAM on X11 -- Muxed mode */ - writel(bcr, STM32_FMC2_BASE + STM32_FMC2_BCR(3)); - writel(btr, STM32_FMC2_BASE + STM32_FMC2_BTR(3)); - - setbits_le32(STM32_FMC2_BASE + STM32_FMC2_BCR1, STM32_FMC2_BCRx_FMCEN); -} - #ifdef CONFIG_DM_REGULATOR #define STPMIC_NVM_BUCKS_VOUT_SHR 0xfc #define STPMIC_NVM_BUCKS_VOUT_SHR_BUCK_1V2 0 @@ -671,8 +621,6 @@ int board_init(void) sysconf_init(); - board_init_fmc2(); - return 0; } diff --git a/configs/stm32mp15_dhcom_basic_defconfig b/configs/stm32mp15_dhcom_basic_defconfig index e1a557ec00..f47e70be44 100644 --- a/configs/stm32mp15_dhcom_basic_defconfig +++ b/configs/stm32mp15_dhcom_basic_defconfig @@ -108,6 +108,7 @@ CONFIG_DM_I2C=y CONFIG_SYS_I2C_STM32F7=y CONFIG_LED=y CONFIG_LED_GPIO=y +CONFIG_STM32_FMC2_EBI=y CONFIG_I2C_EEPROM=y CONFIG_SYS_I2C_EEPROM_ADDR=0x50 CONFIG_SUPPORT_EMMC_BOOT=y diff --git a/configs/stm32mp15_dhcor_basic_defconfig b/configs/stm32mp15_dhcor_basic_defconfig index 81eabeb358..02cce50691 100644 --- a/configs/stm32mp15_dhcor_basic_defconfig +++ b/configs/stm32mp15_dhcor_basic_defconfig @@ -105,6 +105,7 @@ CONFIG_DM_I2C=y CONFIG_SYS_I2C_STM32F7=y CONFIG_LED=y CONFIG_LED_GPIO=y +CONFIG_STM32_FMC2_EBI=y CONFIG_I2C_EEPROM=y CONFIG_SYS_I2C_EEPROM_ADDR=0x53 CONFIG_SUPPORT_EMMC_BOOT=y From d6ff3c9f04f744345fe77a3d82c5b5e0c07c456a Mon Sep 17 00:00:00 2001 From: Etienne Carriere Date: Mon, 5 Sep 2022 11:15:28 +0200 Subject: [PATCH 10/10] ARM: dts: stm32mp15: remove hwlocks from pinctrl MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Removes hwlocks properties from stm32mp151 pinctrl node. These locks could be used for other purpose, depending on board and software configuration hence do not enforce their use to protect pinctrl devices. This patch is an alignment with Linux device tree with v6.0 as the hwsem support wasn’t yet added in pincontrol in kernel. It avoids issues when the Linux kernel is started with the U-Boot device tree. Cc: Patrice Chotard Cc: Patrick Delaunay Signed-off-by: Etienne Carriere Reviewed-by: Patrick Delaunay --- arch/arm/dts/stm32mp151.dtsi | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm/dts/stm32mp151.dtsi b/arch/arm/dts/stm32mp151.dtsi index a5ac62c83d..767a06ef68 100644 --- a/arch/arm/dts/stm32mp151.dtsi +++ b/arch/arm/dts/stm32mp151.dtsi @@ -1663,7 +1663,6 @@ ranges = <0 0x50002000 0xa400>; interrupt-parent = <&exti>; st,syscfg = <&exti 0x60 0xff>; - hwlocks = <&hwspinlock 0>; pins-are-numbered; gpioa: gpio@50002000 { @@ -1796,7 +1795,6 @@ pins-are-numbered; interrupt-parent = <&exti>; st,syscfg = <&exti 0x60 0xff>; - hwlocks = <&hwspinlock 0>; gpioz: gpio@54004000 { gpio-controller;