diff --git a/.github/pull_request_template.md b/.github/pull_request_template.md index ae91252a00..772810460c 100644 --- a/.github/pull_request_template.md +++ b/.github/pull_request_template.md @@ -1,6 +1,6 @@ Please do not submit a Pull Request via github. Our project makes use of mailing lists for patch submission and review. For more details please -see https://www.denx.de/wiki/U-Boot/Patches +see https://u-boot.readthedocs.io/en/latest/develop/sending_patches.html The only exception to this is in order to trigger a CI loop on Azure prior to posting of patches. diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index 8e94bf8d4e..29af8c645e 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -1,7 +1,7 @@ # SPDX-License-Identifier: GPL-2.0+ -# Grab our configured image. The source for this is found at: -# https://source.denx.de/u-boot/gitlab-ci-runner +# Grab our configured image. The source for this is found +# in the u-boot tree at tools/docker/Dockerfile image: trini/u-boot-gitlab-ci-runner:jammy-20220801-09Aug2022 # We run some tests in different order, to catch some failures quicker. diff --git a/Kconfig b/Kconfig index 991b260182..c8c22555a9 100644 --- a/Kconfig +++ b/Kconfig @@ -299,7 +299,7 @@ config SYS_MALLOC_F_LEN default 0x4000 if SANDBOX || RISCV || ARCH_APPLE || ROCKCHIP_RK3368 || \ ROCKCHIP_RK3399 default 0x8000 if RCAR_GEN3 - default 0x10000 if ARCH_IMX8 || (ARCH_IMX8M && !IMX8MQ) + default 0x10000 if ARCH_IMX8 || ARCH_IMX8M default 0x2000 help Before relocation, memory is very limited on many platforms. Still, @@ -325,6 +325,7 @@ config SPL_SYS_MALLOC_F_LEN depends on SYS_MALLOC_F && SPL default 0 if !SPL_FRAMEWORK default 0x2800 if RCAR_GEN3 + default 0x2000 if IMX8MQ default SYS_MALLOC_F_LEN help In SPL memory is very limited on many platforms. Still, diff --git a/MAINTAINERS b/MAINTAINERS index 1a7a56335f..e4fd099f87 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -264,6 +264,7 @@ F: arch/arm/include/asm/arch-mx*/ F: arch/arm/include/asm/arch-vf610/ F: arch/arm/include/asm/mach-imx/ F: board/freescale/*mx*/ +F: drivers/serial/serial_mxc.c ARM HISILICON M: Peter Griffin diff --git a/Makefile b/Makefile index 0b8079cf81..b421296da2 100644 --- a/Makefile +++ b/Makefile @@ -3,7 +3,7 @@ VERSION = 2022 PATCHLEVEL = 10 SUBLEVEL = -EXTRAVERSION = -rc3 +EXTRAVERSION = -rc5 NAME = # *DOCUMENTATION* @@ -1004,22 +1004,12 @@ ifeq ($(CONFIG_INIT_SP_RELATIVE)$(CONFIG_OF_SEPARATE),yy) INPUTS-y += init_sp_bss_offset_check endif -ifeq ($(CONFIG_MPC85xx)$(CONFIG_OF_SEPARATE),yy) -INPUTS-y += u-boot-with-dtb.bin -endif - -ifeq ($(CONFIG_ARCH_ROCKCHIP),y) -# On ARM64 this target is produced by binman so we don't need this dep +ifeq ($(CONFIG_ARCH_ROCKCHIP)$(CONFIG_SPL),yy) +# Binman image dependencies ifeq ($(CONFIG_ARM64),y) -ifeq ($(CONFIG_SPL),y) -# TODO: Get binman to generate this too -INPUTS-y += u-boot-rockchip.bin -endif +INPUTS-y += u-boot.itb else -ifeq ($(CONFIG_SPL),y) -# Generate these inputs for binman which will create the output files -INPUTS-y += idbloader.img u-boot.img -endif +INPUTS-y += u-boot.img endif endif @@ -1230,9 +1220,12 @@ else ifeq ($(CONFIG_OF_SEPARATE).$(CONFIG_OF_OMIT_DTB),y.) u-boot-dtb.bin: u-boot-nodtb.bin dts/dt.dtb FORCE $(call if_changed,cat) +ifneq ($(CONFIG_MPC85XX_HAVE_RESET_VECTOR)$(CONFIG_OF_SEPARATE),yy) u-boot.bin: u-boot-dtb.bin FORCE $(call if_changed,copy) -else +endif + +else ifneq ($(CONFIG_MPC85XX_HAVE_RESET_VECTOR)$(CONFIG_OF_SEPARATE),yy) u-boot.bin: u-boot-nodtb.bin FORCE $(call if_changed,copy) endif @@ -1280,7 +1273,7 @@ spl/u-boot-spl.srec: spl/u-boot-spl FORCE OBJCOPYFLAGS_u-boot-nodtb.bin := -O binary \ $(if $(CONFIG_X86_16BIT_INIT),-R .start16 -R .resetvec) \ - $(if $(CONFIG_MPC85XX_HAVE_RESET_VECTOR),$(if $(CONFIG_OF_EMBED),,-R .bootpg -R .resetvec)) + $(if $(CONFIG_MPC85XX_HAVE_RESET_VECTOR),$(if $(CONFIG_OF_SEPARATE),-R .bootpg -R .resetvec)) binary_size_check: u-boot-nodtb.bin FORCE @file_size=$(shell wc -c u-boot-nodtb.bin | awk '{print $$1}') ; \ @@ -1445,11 +1438,7 @@ MKIMAGEFLAGS_u-boot-spl.kwb = -n $(KWD_CONFIG_FILE) \ MKIMAGEFLAGS_u-boot.pbl = -n $(srctree)/$(CONFIG_SYS_FSL_PBL_RCW:"%"=%) \ -R $(srctree)/$(CONFIG_SYS_FSL_PBL_PBI:"%"=%) -A $(ARCH) -T pblimage -ifeq ($(CONFIG_MPC85xx)$(CONFIG_OF_SEPARATE),yy) -UBOOT_BIN := u-boot-with-dtb.bin -else UBOOT_BIN := u-boot.bin -endif MKIMAGEFLAGS_u-boot-lzma.img = -A $(ARCH) -T standalone -C lzma -O u-boot \ -a $(CONFIG_SYS_TEXT_BASE) -e $(CONFIG_SYS_UBOOT_START) \ @@ -1505,29 +1494,6 @@ OBJCOPYFLAGS_u-boot-with-spl.bin = -I binary -O binary \ u-boot-with-spl.bin: $(SPL_IMAGE) $(SPL_PAYLOAD) FORCE $(call if_changed,pad_cat) -ifeq ($(CONFIG_ARCH_ROCKCHIP),y) - -# TPL + SPL -ifeq ($(CONFIG_SPL)$(CONFIG_TPL),yy) -MKIMAGEFLAGS_u-boot-tpl-rockchip.bin = -n $(CONFIG_SYS_SOC) -T rksd -tpl/u-boot-tpl-rockchip.bin: tpl/u-boot-tpl.bin FORCE - $(call if_changed,mkimage) -idbloader.img: tpl/u-boot-tpl-rockchip.bin spl/u-boot-spl.bin FORCE - $(call if_changed,cat) -else -MKIMAGEFLAGS_idbloader.img = -n $(CONFIG_SYS_SOC) -T rksd -idbloader.img: spl/u-boot-spl.bin FORCE - $(call if_changed,mkimage) -endif - -ifeq ($(CONFIG_ARM64),y) -OBJCOPYFLAGS_u-boot-rockchip.bin = -I binary -O binary \ - --pad-to=$(CONFIG_SPL_PAD_TO) --gap-fill=0xff -u-boot-rockchip.bin: idbloader.img u-boot.itb FORCE - $(call if_changed,pad_cat) -endif # CONFIG_ARM64 - -endif # CONFIG_ARCH_ROCKCHIP ifeq ($(CONFIG_ARCH_LPC32XX)$(CONFIG_SPL),yy) MKIMAGEFLAGS_lpc32xx-spl.img = -T lpc32xximage -a $(CONFIG_SPL_TEXT_BASE) @@ -1639,17 +1605,14 @@ u-boot-with-nand-spl.sfp: u-boot-spl-padx4.sfp u-boot.img FORCE endif -ifeq ($(CONFIG_MPC85xx)$(CONFIG_OF_SEPARATE),yy) -u-boot-with-dtb.bin: u-boot.bin u-boot.dtb \ - $(if $(CONFIG_MPC85XX_HAVE_RESET_VECTOR), u-boot-br.bin) FORCE +ifeq ($(CONFIG_MPC85XX_HAVE_RESET_VECTOR)$(CONFIG_OF_SEPARATE),yy) +u-boot.bin: u-boot-nodtb.bin u-boot.dtb u-boot-br.bin FORCE $(call if_changed,binman) -ifeq ($(CONFIG_MPC85XX_HAVE_RESET_VECTOR),y) OBJCOPYFLAGS_u-boot-br.bin := -O binary -j .bootpg -j .resetvec u-boot-br.bin: u-boot FORCE $(call if_changed,objcopy) endif -endif quiet_cmd_ldr = LD $@ cmd_ldr = $(LD) $(LDFLAGS_$(@F)) \ @@ -1706,12 +1669,8 @@ spl/u-boot-spl.pbl: spl/u-boot-spl.bin FORCE ifeq ($(ARCH),arm) UBOOT_BINLOAD := u-boot.img else -ifeq ($(CONFIG_MPC85xx)$(CONFIG_OF_SEPARATE),yy) -UBOOT_BINLOAD := u-boot-with-dtb.bin -else UBOOT_BINLOAD := u-boot.bin endif -endif OBJCOPYFLAGS_u-boot-with-spl-pbl.bin = -I binary -O binary --pad-to=$(CONFIG_SPL_PAD_TO) \ --gap-fill=0xff @@ -2232,7 +2191,9 @@ CLEAN_FILES += include/bmp_logo.h include/bmp_logo_data.h \ lpc32xx-* bl31.c bl31.elf bl31_*.bin image.map tispl.bin* \ idbloader.img flash.bin flash.log defconfig keep-syms-lto.c \ mkimage-out.spl.mkimage mkimage.spl.mkimage imx-boot.map \ - itb.fit.fit itb.fit.itb itb.map spl.map + itb.fit.fit itb.fit.itb itb.map spl.map mkimage-out.rom.mkimage \ + mkimage.rom.mkimage rom.map simple-bin.map simple-bin-spi.map \ + idbloader-spi.img # Directories & files removed with 'make mrproper' MRPROPER_DIRS += include/config include/generated spl tpl \ diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 03169eba8d..f3a3c0f9a9 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1986,7 +1986,7 @@ config ARCH_STM32MP config ARCH_ROCKCHIP bool "Support Rockchip SoCs" select BLK - select BINMAN if SPL_OPTEE || (SPL && !ARM64) + select BINMAN if SPL_OPTEE || SPL select DM select DM_GPIO select DM_I2C diff --git a/arch/arm/cpu/armv8/fsl-layerscape/spl.c b/arch/arm/cpu/armv8/fsl-layerscape/spl.c index 5f09ef0a4a..3a4b665f24 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/spl.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/spl.c @@ -67,11 +67,24 @@ void spl_board_init(void) #endif } +void tzpc_init(void) +{ + /* + * Mark the whole OCRAM as non-secure, otherwise DMA devices cannot + * access it. This is for example necessary for MMC boot. + */ +#ifdef TZPCR0SIZE_BASE + out_le32(TZPCR0SIZE_BASE, 0); +#endif +} + void board_init_f(ulong dummy) { int ret; icache_enable(); + tzpc_init(); + /* Clear global data */ memset((void *)gd, 0, sizeof(gd_t)); if (IS_ENABLED(CONFIG_DEBUG_UART)) diff --git a/arch/arm/cpu/armv8/sec_firmware.c b/arch/arm/cpu/armv8/sec_firmware.c index 7e6e4064ff..540436ba02 100644 --- a/arch/arm/cpu/armv8/sec_firmware.c +++ b/arch/arm/cpu/armv8/sec_firmware.c @@ -36,9 +36,6 @@ phys_addr_t sec_firmware_addr; #ifndef SEC_FIRMWARE_FIT_IMAGE #define SEC_FIRMWARE_FIT_IMAGE "firmware" #endif -#ifndef SEC_FIRMWARE_FIT_CNF_NAME -#define SEC_FIRMWARE_FIT_CNF_NAME "config-1" -#endif #ifndef SEC_FIRMWARE_TARGET_EL #define SEC_FIRMWARE_TARGET_EL 2 #endif @@ -46,46 +43,8 @@ phys_addr_t sec_firmware_addr; static int sec_firmware_get_data(const void *sec_firmware_img, const void **data, size_t *size) { - int conf_node_off, fw_node_off; - char *conf_node_name = NULL; - char *desc; - int ret; - - conf_node_name = SEC_FIRMWARE_FIT_CNF_NAME; - - conf_node_off = fit_conf_get_node(sec_firmware_img, conf_node_name); - if (conf_node_off < 0) { - printf("SEC Firmware: %s: no such config\n", conf_node_name); - return -ENOENT; - } - - fw_node_off = fit_conf_get_prop_node(sec_firmware_img, conf_node_off, - SEC_FIRMWARE_FIT_IMAGE); - if (fw_node_off < 0) { - printf("SEC Firmware: No '%s' in config\n", - SEC_FIRMWARE_FIT_IMAGE); - return -ENOLINK; - } - - /* Verify secure firmware image */ - if (!(fit_image_verify(sec_firmware_img, fw_node_off))) { - printf("SEC Firmware: Bad firmware image (bad CRC)\n"); - return -EINVAL; - } - - if (fit_image_get_data(sec_firmware_img, fw_node_off, data, size)) { - printf("SEC Firmware: Can't get %s subimage data/size", - SEC_FIRMWARE_FIT_IMAGE); - return -ENOENT; - } - - ret = fit_get_desc(sec_firmware_img, fw_node_off, &desc); - if (ret) - printf("SEC Firmware: Can't get description\n"); - else - printf("%s\n", desc); - - return ret; + return fit_get_data_conf_prop(sec_firmware_img, SEC_FIRMWARE_FIT_IMAGE, + data, size); } /* @@ -124,18 +83,15 @@ static int sec_firmware_check_copy_loadable(const void *sec_firmware_img, { phys_addr_t sec_firmware_loadable_addr = 0; int conf_node_off, ld_node_off, images; - char *conf_node_name = NULL; const void *data; size_t size; ulong load; const char *name, *str, *type; int len; - conf_node_name = SEC_FIRMWARE_FIT_CNF_NAME; - - conf_node_off = fit_conf_get_node(sec_firmware_img, conf_node_name); + conf_node_off = fit_conf_get_node(sec_firmware_img, NULL); if (conf_node_off < 0) { - printf("SEC Firmware: %s: no such config\n", conf_node_name); + puts("SEC Firmware: no config\n"); return -ENOENT; } diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 5bff2e65b7..7c40714450 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -893,6 +893,7 @@ dtb-$(CONFIG_MX6ULL) += \ imx6ull-phytec-segin-ff-rdk-emmc.dtb \ imx6ull-dart-6ul.dtb \ imx6ull-somlabs-visionsom.dtb \ + imx6ulz-bsh-smm-m2.dtb \ imx6ulz-14x14-evk.dtb dtb-$(CONFIG_ARCH_MX6) += \ @@ -972,13 +973,15 @@ dtb-$(CONFIG_ARCH_IMX8M) += \ imx8mp-venice-gw74xx.dtb \ imx8mp-verdin-wifi-dev.dtb \ imx8mq-pico-pi.dtb \ - imx8mq-kontron-pitx-imx8m.dtb + imx8mq-kontron-pitx-imx8m.dtb \ + imx8mq-librem5-r4.dtb dtb-$(CONFIG_ARCH_IMX9) += \ imx93-11x11-evk.dtb dtb-$(CONFIG_ARCH_IMXRT) += imxrt1050-evk.dtb \ - imxrt1020-evk.dtb + imxrt1020-evk.dtb \ + imxrt1170-evk.dtb \ dtb-$(CONFIG_RCAR_GEN2) += \ r8a7790-lager-u-boot.dtb \ diff --git a/arch/arm/dts/imx6ulz-bsh-smm-m2-u-boot.dtsi b/arch/arm/dts/imx6ulz-bsh-smm-m2-u-boot.dtsi new file mode 100644 index 0000000000..75dbf6ed78 --- /dev/null +++ b/arch/arm/dts/imx6ulz-bsh-smm-m2-u-boot.dtsi @@ -0,0 +1,35 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2022 BSH Hausgeraete GmbH + * + * Author: Michael Trimarchi + */ + +&{/soc} { + u-boot,dm-pre-reloc; +}; + +&aips2 { + u-boot,dm-pre-reloc; +}; + +&iomuxc { + u-boot,dm-pre-reloc; +}; + +&iomuxc_snvs { + u-boot,dm-pre-reloc; +}; + +&uart4 { + u-boot,dm-pre-reloc; +}; + +&pinctrl_uart4 { + u-boot,dm-pre-reloc; +}; + +&gpmi { + u-boot,dm-spl; + u-boot,dm-pre-reloc; +}; diff --git a/arch/arm/dts/imx6ulz-bsh-smm-m2.dts b/arch/arm/dts/imx6ulz-bsh-smm-m2.dts new file mode 100644 index 0000000000..59bcfc9a6b --- /dev/null +++ b/arch/arm/dts/imx6ulz-bsh-smm-m2.dts @@ -0,0 +1,146 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2021 BSH Hausgeraete GmbH + */ + +/dts-v1/; + +#include +#include "imx6ulz.dtsi" + +/ { + model = "BSH SMM M2"; + compatible = "bsh,imx6ulz-bsh-smm-m2", "fsl,imx6ull", "fsl,imx6ulz"; + + chosen { + stdout-path = &uart4; + }; + + usdhc2_pwrseq: usdhc2-pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&gpio2 21 GPIO_ACTIVE_LOW>; + }; +}; + +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand>; + nand-on-flash-bbt; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + uart-has-rtscts; + status = "okay"; + + bluetooth { + compatible = "brcm,bcm4330-bt"; + max-speed = <3000000>; + shutdown-gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>; + device-wakeup-gpios = <&gpio2 17 GPIO_ACTIVE_HIGH>; + host-wakeup-gpios = <&gpio2 13 GPIO_ACTIVE_HIGH>; + }; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + status = "okay"; +}; + +&usbotg1 { + dr_mode = "peripheral"; + srp-disable; + hnp-disable; + adp-disable; + status = "okay"; +}; + +&usbphy1 { + fsl,tx-d-cal = <106>; +}; + +&usdhc2 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wlan>; + bus-width = <4>; + no-1-8-v; + non-removable; + cap-power-off-card; + keep-power-in-suspend; + cap-sdio-irq; + mmc-pwrseq = <&usdhc2_pwrseq>; + status = "okay"; + + brcmf: wifi@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + interrupt-parent = <&gpio1>; + interrupts = <18 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "host-wake"; + }; +}; + +&wdog1 { + status = "okay"; +}; + +&iomuxc { + pinctrl_gpmi_nand: gpmi-nand { + fsl,pins = < + MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0xb0b1 + MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0xb0b1 + MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B 0xb0b1 + MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0xb000 + MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0xb0b1 + MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0xb0b1 + MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0xb0b1 + MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0xb0b1 + MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0xb0b1 + MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0xb0b1 + MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0xb0b1 + MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0xb0b1 + MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0xb0b1 + MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0xb0b1 + MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0xb0b1 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX6UL_PAD_UART3_TX_DATA__UART3_DCE_TX 0x1b0b1 + MX6UL_PAD_UART3_RX_DATA__UART3_DCE_RX 0x1b099 + MX6UL_PAD_UART3_RTS_B__UART3_DCE_RTS 0x1b0b1 + MX6UL_PAD_UART3_CTS_B__UART3_DCE_CTS 0x1b099 + MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0x79 /* BT_REG_ON */ + MX6UL_PAD_SD1_CLK__GPIO2_IO17 0x100b1 /* BT_DEV_WAKE out */ + MX6UL_PAD_ENET2_TX_EN__GPIO2_IO13 0x1b0b0 /* BT_HOST_WAKE in */ + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX6UL_PAD_UART4_TX_DATA__UART4_DCE_TX 0x1b0b1 + MX6UL_PAD_UART4_RX_DATA__UART4_DCE_RX 0x1b0b1 + >; + }; + + pinctrl_wlan: wlangrp { + fsl,pins = < + MX6UL_PAD_CSI_HSYNC__USDHC2_CMD 0x17059 + MX6UL_PAD_CSI_VSYNC__USDHC2_CLK 0x10059 + MX6UL_PAD_CSI_DATA00__USDHC2_DATA0 0x17059 + MX6UL_PAD_CSI_DATA01__USDHC2_DATA1 0x17059 + MX6UL_PAD_CSI_DATA02__USDHC2_DATA2 0x17059 + MX6UL_PAD_CSI_DATA03__USDHC2_DATA3 0x17059 + MX6UL_PAD_SD1_DATA3__GPIO2_IO21 0x79 /* WL_REG_ON */ + MX6UL_PAD_UART2_CTS_B__GPIO1_IO22 0x100b1 /* WL_DEV_WAKE - WiFi_GPIO_4 - WiFi FW UART */ + MX6UL_PAD_UART1_CTS_B__GPIO1_IO18 0x1b0b1 /* WL_HOST_WAKE - WIFI_GPIO_0 - OOB IRQ */ + MX6UL_PAD_ENET1_RX_EN__OSC32K_32K_OUT 0x4001b031 /* OSC 32Khz wifi clk in */ + >; + }; +}; diff --git a/arch/arm/dts/imx8mn-beacon-kit-u-boot.dtsi b/arch/arm/dts/imx8mn-beacon-kit-u-boot.dtsi index 5f83952402..0efa6862eb 100644 --- a/arch/arm/dts/imx8mn-beacon-kit-u-boot.dtsi +++ b/arch/arm/dts/imx8mn-beacon-kit-u-boot.dtsi @@ -106,6 +106,10 @@ u-boot,off-on-delay-us = <20000>; }; +&spba1 { + u-boot,dm-spl; +}; + &uart2 { u-boot,dm-spl; }; diff --git a/arch/arm/dts/imx8mp-dhcom-pdk2-u-boot.dtsi b/arch/arm/dts/imx8mp-dhcom-pdk2-u-boot.dtsi index ae838caebc..be2d4fb184 100644 --- a/arch/arm/dts/imx8mp-dhcom-pdk2-u-boot.dtsi +++ b/arch/arm/dts/imx8mp-dhcom-pdk2-u-boot.dtsi @@ -3,139 +3,4 @@ * Copyright (C) 2022 Marek Vasut */ -#include "imx8mp-u-boot.dtsi" - -/ { - aliases { - eeprom0 = &eeprom0; - eeprom1 = &eeprom1; - mmc0 = &usdhc2; /* MicroSD */ - mmc1 = &usdhc3; /* eMMC */ - mmc2 = &usdhc1; /* SDIO */ - }; - - config { - dh,ram-coding-gpios = <&gpio3 22 0>, <&gpio3 23 0>, <&gpio3 24 0>; - }; - - wdt-reboot { - compatible = "wdt-reboot"; - wdt = <&wdog1>; - u-boot,dm-spl; - }; -}; - -&buck4 { - u-boot,dm-spl; -}; - -&buck5 { - u-boot,dm-spl; -}; - -&eqos { - /delete-property/ assigned-clocks; - /delete-property/ assigned-clock-parents; - /delete-property/ assigned-clock-rates; -}; - -&gpio1 { - u-boot,dm-spl; -}; - -&gpio2 { - u-boot,dm-spl; -}; - -&gpio3 { - u-boot,dm-spl; -}; - -&gpio4 { - u-boot,dm-spl; -}; - -&gpio5 { - u-boot,dm-spl; -}; - -&i2c3 { - u-boot,dm-spl; -}; - -&pinctrl_i2c3 { - u-boot,dm-spl; -}; - -&pinctrl_i2c3_gpio { - u-boot,dm-spl; -}; - -&pinctrl_pmic { - u-boot,dm-spl; -}; - -&pinctrl_uart1 { - u-boot,dm-spl; -}; - -&pinctrl_usdhc2 { - u-boot,dm-spl; -}; - -&pinctrl_usdhc2_100mhz { - u-boot,dm-spl; -}; - -&pinctrl_usdhc2_200mhz { - u-boot,dm-spl; -}; - -&pinctrl_usdhc2_vmmc { - u-boot,dm-spl; -}; - -&pinctrl_usdhc3 { - u-boot,dm-spl; -}; - -&pinctrl_usdhc3_100mhz { - u-boot,dm-spl; -}; - -&pinctrl_usdhc3_100mhz { - u-boot,dm-spl; -}; - -&pmic { - u-boot,dm-spl; - - regulators { - u-boot,dm-spl; - }; -}; - -®_usdhc2_vmmc { - u-boot,dm-spl; -}; - -&uart1 { - u-boot,dm-spl; -}; - -/* SDIO WiFi */ -&usdhc1 { - status = "disabled"; -}; - -&usdhc2 { - u-boot,dm-spl; -}; - -&usdhc3 { - u-boot,dm-spl; -}; - -&wdog1 { - u-boot,dm-spl; -}; +#include "imx8mp-dhcom-u-boot.dtsi" diff --git a/arch/arm/dts/imx8mp-dhcom-pdk2.dts b/arch/arm/dts/imx8mp-dhcom-pdk2.dts index e95abfb3e8..c9a481ac9a 100644 --- a/arch/arm/dts/imx8mp-dhcom-pdk2.dts +++ b/arch/arm/dts/imx8mp-dhcom-pdk2.dts @@ -1,18 +1,23 @@ // SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Copyright (C) 2022 Marek Vasut + * + * DHCOM iMX8MP variant: + * DHCM-iMX8ML8-C160-R409-F1638-SPI16-GE-CAN2-SD-RTC-WBTA-ADC-T-RGB-CSI2-HS-I-01D2 + * DHCOM PCB number: 660-100 or newer + * PDK2 PCB number: 516-400 or newer */ /dts-v1/; #include -#include #include #include "imx8mp-dhcom-som.dtsi" / { model = "DH electronics i.MX8M Plus DHCOM Premium Developer Kit (2)"; - compatible = "dh,imx8mp-dhcom-pdk2", "fsl,imx8mp"; + compatible = "dh,imx8mp-dhcom-pdk2", "dh,imx8mp-dhcom-som", + "fsl,imx8mp"; chosen { stdout-path = &uart1; diff --git a/arch/arm/dts/imx8mp-dhcom-som.dtsi b/arch/arm/dts/imx8mp-dhcom-som.dtsi index 63cc6c92c4..197840d1a6 100644 --- a/arch/arm/dts/imx8mp-dhcom-som.dtsi +++ b/arch/arm/dts/imx8mp-dhcom-som.dtsi @@ -70,7 +70,7 @@ &ecspi1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi1>; - cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; + cs-gpios = <&gpio5 17 GPIO_ACTIVE_LOW>; status = "disabled"; }; @@ -415,8 +415,8 @@ pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c5>; pinctrl-1 = <&pinctrl_i2c5_gpio>; - scl-gpios = <&gpio5 26 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - sda-gpios = <&gpio5 27 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpio3 26 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio3 27 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "okay"; }; @@ -660,10 +660,10 @@ pinctrl_ecspi1: dhcom-ecspi1-grp { fsl,pins = < - MX8MP_IOMUXC_ECSPI1_SCLK__ECSPI1_SCLK 0x44 - MX8MP_IOMUXC_ECSPI1_MOSI__ECSPI1_MOSI 0x44 - MX8MP_IOMUXC_ECSPI1_MISO__ECSPI1_MISO 0x44 - MX8MP_IOMUXC_ECSPI1_SS0__GPIO5_IO09 0x40 + MX8MP_IOMUXC_I2C1_SCL__ECSPI1_SCLK 0x44 + MX8MP_IOMUXC_I2C1_SDA__ECSPI1_MOSI 0x44 + MX8MP_IOMUXC_I2C2_SCL__ECSPI1_MISO 0x44 + MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0x40 >; }; diff --git a/arch/arm/dts/imx8mp-dhcom-u-boot.dtsi b/arch/arm/dts/imx8mp-dhcom-u-boot.dtsi new file mode 100644 index 0000000000..ae838caebc --- /dev/null +++ b/arch/arm/dts/imx8mp-dhcom-u-boot.dtsi @@ -0,0 +1,141 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2022 Marek Vasut + */ + +#include "imx8mp-u-boot.dtsi" + +/ { + aliases { + eeprom0 = &eeprom0; + eeprom1 = &eeprom1; + mmc0 = &usdhc2; /* MicroSD */ + mmc1 = &usdhc3; /* eMMC */ + mmc2 = &usdhc1; /* SDIO */ + }; + + config { + dh,ram-coding-gpios = <&gpio3 22 0>, <&gpio3 23 0>, <&gpio3 24 0>; + }; + + wdt-reboot { + compatible = "wdt-reboot"; + wdt = <&wdog1>; + u-boot,dm-spl; + }; +}; + +&buck4 { + u-boot,dm-spl; +}; + +&buck5 { + u-boot,dm-spl; +}; + +&eqos { + /delete-property/ assigned-clocks; + /delete-property/ assigned-clock-parents; + /delete-property/ assigned-clock-rates; +}; + +&gpio1 { + u-boot,dm-spl; +}; + +&gpio2 { + u-boot,dm-spl; +}; + +&gpio3 { + u-boot,dm-spl; +}; + +&gpio4 { + u-boot,dm-spl; +}; + +&gpio5 { + u-boot,dm-spl; +}; + +&i2c3 { + u-boot,dm-spl; +}; + +&pinctrl_i2c3 { + u-boot,dm-spl; +}; + +&pinctrl_i2c3_gpio { + u-boot,dm-spl; +}; + +&pinctrl_pmic { + u-boot,dm-spl; +}; + +&pinctrl_uart1 { + u-boot,dm-spl; +}; + +&pinctrl_usdhc2 { + u-boot,dm-spl; +}; + +&pinctrl_usdhc2_100mhz { + u-boot,dm-spl; +}; + +&pinctrl_usdhc2_200mhz { + u-boot,dm-spl; +}; + +&pinctrl_usdhc2_vmmc { + u-boot,dm-spl; +}; + +&pinctrl_usdhc3 { + u-boot,dm-spl; +}; + +&pinctrl_usdhc3_100mhz { + u-boot,dm-spl; +}; + +&pinctrl_usdhc3_100mhz { + u-boot,dm-spl; +}; + +&pmic { + u-boot,dm-spl; + + regulators { + u-boot,dm-spl; + }; +}; + +®_usdhc2_vmmc { + u-boot,dm-spl; +}; + +&uart1 { + u-boot,dm-spl; +}; + +/* SDIO WiFi */ +&usdhc1 { + status = "disabled"; +}; + +&usdhc2 { + u-boot,dm-spl; +}; + +&usdhc3 { + u-boot,dm-spl; +}; + +&wdog1 { + u-boot,dm-spl; +}; diff --git a/arch/arm/dts/imx8mq-librem5-r4-u-boot.dtsi b/arch/arm/dts/imx8mq-librem5-r4-u-boot.dtsi new file mode 100644 index 0000000000..9d0a54a32f --- /dev/null +++ b/arch/arm/dts/imx8mq-librem5-r4-u-boot.dtsi @@ -0,0 +1,24 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) + +#include "imx8mq-u-boot.dtsi" + +&pinctrl_uart1 { + u-boot,dm-spl; +}; + +&uart1 { /* console */ + u-boot,dm-spl; +}; + +&binman { + /delete-node/ signed-hdmi; + + signed-hdmi { + filename = "signed_hdmi.bin"; + + signed-dp-imx8m { + filename = "signed_dp_imx8m.bin"; + type = "blob-ext"; + }; + }; +}; diff --git a/arch/arm/dts/imx8mq-librem5-r4.dts b/arch/arm/dts/imx8mq-librem5-r4.dts new file mode 100644 index 0000000000..cbfb49aa25 --- /dev/null +++ b/arch/arm/dts/imx8mq-librem5-r4.dts @@ -0,0 +1,35 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +// Copyright (C) 2020 Purism SPC + +/dts-v1/; + +#include "imx8mq-librem5.dtsi" + +/ { + model = "Purism Librem 5r4"; + compatible = "purism,librem5r4", "purism,librem5", "fsl,imx8mq"; +}; + +&accel_gyro { + mount-matrix = "1", "0", "0", + "0", "1", "0", + "0", "0", "-1"; +}; + +&bat { + maxim,rsns-microohm = <1667>; +}; + +&bq25895 { + ti,battery-regulation-voltage = <4200000>; /* uV */ + ti,charge-current = <1500000>; /* uA */ + ti,termination-current = <144000>; /* uA */ +}; + +&led_backlight { + led-max-microamp = <25000>; +}; + +&proximity { + proximity-near-level = <10>; +}; diff --git a/arch/arm/dts/imx8mq-librem5.dtsi b/arch/arm/dts/imx8mq-librem5.dtsi new file mode 100644 index 0000000000..60d47c7149 --- /dev/null +++ b/arch/arm/dts/imx8mq-librem5.dtsi @@ -0,0 +1,1255 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018-2020 Purism SPC + */ + +/dts-v1/; + +#include "dt-bindings/input/input.h" +#include +#include "dt-bindings/pwm/pwm.h" +#include "dt-bindings/usb/pd.h" +#include "imx8mq.dtsi" + +/ { + model = "Purism Librem 5"; + compatible = "purism,librem5", "fsl,imx8mq"; + + backlight_dsi: backlight-dsi { + compatible = "led-backlight"; + leds = <&led_backlight>; + }; + + pmic_osc: clock-pmic { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "pmic_osc"; + }; + + chosen { + stdout-path = &uart1; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_keys>; + + vol-down { + label = "VOL_DOWN"; + gpios = <&gpio1 17 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <50>; + }; + + vol-up { + label = "VOL_UP"; + gpios = <&gpio1 16 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <50>; + }; + }; + + reg_aud_1v8: regulator-audio-1v8 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audiopwr>; + regulator-name = "AUDIO_PWR_EN"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + gpio = <&gpio1 4 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_gnss: regulator-gnss { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gnsspwr>; + regulator-name = "GNSS"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio3 12 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_hub: regulator-hub { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hub_pwr>; + regulator-name = "HUB"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_lcd_1v8: regulator-lcd-1v8 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_dsien>; + regulator-name = "LCD_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <®_vdd_1v8>; + gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>; + enable-active-high; + /* Otherwise i2c3 is not functional */ + regulator-always-on; + }; + + reg_lcd_3v4: regulator-lcd-3v4 { + compatible = "regulator-fixed"; + regulator-name = "LCD_3V4"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_dsibiasen>; + vin-supply = <®_vsys_3v4>; + gpio = <&gpio1 20 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_vdd_sen: regulator-vdd-sen { + compatible = "regulator-fixed"; + regulator-name = "VDD_SEN"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_vdd_1v8: regulator-vdd-1v8 { + compatible = "regulator-fixed"; + regulator-name = "VDD_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&buck7_reg>; + }; + + reg_vdd_3v3: regulator-vdd-3v3 { + compatible = "regulator-fixed"; + regulator-name = "VDD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_vsys_3v4: regulator-vsys-3v4 { + compatible = "regulator-fixed"; + regulator-name = "VSYS_3V4"; + regulator-min-microvolt = <3400000>; + regulator-max-microvolt = <3400000>; + regulator-always-on; + }; + + reg_wifi_3v3: regulator-wifi-3v3 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wifi_pwr>; + regulator-name = "3V3_WIFI"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio3 10 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <®_vdd_3v3>; + }; + + sound { + compatible = "simple-audio-card"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hp>; + simple-audio-card,name = "Librem 5"; + simple-audio-card,format = "i2s"; + simple-audio-card,widgets = + "Headphone", "Headphones", + "Microphone", "Headset Mic", + "Microphone", "Digital Mic", + "Speaker", "Speaker"; + simple-audio-card,routing = + "Headphones", "HPOUTL", + "Headphones", "HPOUTR", + "Speaker", "SPKOUTL", + "Speaker", "SPKOUTR", + "Headset Mic", "MICBIAS", + "IN3R", "Headset Mic", + "DMICDAT", "Digital Mic"; + simple-audio-card,hp-det-gpio = <&gpio3 9 GPIO_ACTIVE_HIGH>; + + simple-audio-card,cpu { + sound-dai = <&sai2>; + }; + + simple-audio-card,codec { + sound-dai = <&codec>; + clocks = <&clk IMX8MQ_CLK_SAI2_ROOT>; + frame-master; + bitclock-master; + }; + }; + + sound-wwan { + compatible = "simple-audio-card"; + simple-audio-card,name = "Modem"; + simple-audio-card,format = "i2s"; + + simple-audio-card,cpu { + sound-dai = <&sai6>; + frame-inversion; + }; + + simple-audio-card,codec { + sound-dai = <&bm818_codec>; + frame-master; + bitclock-master; + }; + }; + + usdhc2_pwrseq: pwrseq { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_bt>, <&pinctrl_wifi_disable>; + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&gpio3 25 GPIO_ACTIVE_HIGH>, + <&gpio4 29 GPIO_ACTIVE_HIGH>; + }; + + bm818_codec: sound-wwan-codec { + compatible = "broadmobi,bm818", "option,gtm601"; + #sound-dai-cells = <0>; + }; + + vibrator { + compatible = "pwm-vibrator"; + pwms = <&pwm1 0 1000000000 0>; + pwm-names = "enable"; + vcc-supply = <®_vdd_3v3>; + }; +}; + +&A53_0 { + cpu-supply = <&buck2_reg>; +}; + +&A53_1 { + cpu-supply = <&buck2_reg>; +}; + +&A53_2 { + cpu-supply = <&buck2_reg>; +}; + +&A53_3 { + cpu-supply = <&buck2_reg>; +}; + +&ddrc { + operating-points-v2 = <&ddrc_opp_table>; + + ddrc_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-25M { + opp-hz = /bits/ 64 <25000000>; + }; + + opp-100M { + opp-hz = /bits/ 64 <100000000>; + }; + + opp-800M { + opp-hz = /bits/ 64 <800000000>; + }; + }; +}; + +&dphy { + status = "okay"; +}; + +&ecspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + nor_flash: flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <1000000>; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "protected0"; + reg = <0x0 0x30000>; + read-only; + }; + + partition@30000 { + label = "protected1"; + reg = <0x30000 0x10000>; + read-only; + }; + + partition@40000 { + label = "rw"; + reg = <0x40000 0x1C0000>; + }; + }; +}; + +&gpio1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pmic_5v>; + + pmic-5v-hog { + gpio-hog; + gpios = <1 GPIO_ACTIVE_HIGH>; + input; + lane-mapping = "pmic-5v"; + }; +}; + +&iomuxc { + pinctrl_audiopwr: audiopwrgrp { + fsl,pins = < + /* AUDIO_POWER_EN_3V3 */ + MX8MQ_IOMUXC_GPIO1_IO04_GPIO1_IO4 0x83 + >; + }; + + pinctrl_bl: blgrp { + fsl,pins = < + /* BACKLINGE_EN */ + MX8MQ_IOMUXC_NAND_DQS_GPIO3_IO14 0x83 + >; + }; + + pinctrl_bt: btgrp { + fsl,pins = < + /* BT_REG_ON */ + MX8MQ_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x83 + >; + }; + + pinctrl_charger_in: chargeringrp { + fsl,pins = < + /* CHRG_INT */ + MX8MQ_IOMUXC_NAND_CE2_B_GPIO3_IO3 0x80 + /* CHG_STATUS_B */ + MX8MQ_IOMUXC_NAND_ALE_GPIO3_IO0 0x80 + >; + }; + + pinctrl_dsibiasen: dsibiasengrp { + fsl,pins = < + /* DSI_BIAS_EN */ + MX8MQ_IOMUXC_ENET_TD1_GPIO1_IO20 0x83 + >; + }; + + pinctrl_dsien: dsiengrp { + fsl,pins = < + /* DSI_EN_3V3 */ + MX8MQ_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x83 + >; + }; + + pinctrl_dsirst: dsirstgrp { + fsl,pins = < + /* DSI_RST */ + MX8MQ_IOMUXC_ENET_RD3_GPIO1_IO29 0x83 + /* DSI_TE */ + MX8MQ_IOMUXC_ENET_RD2_GPIO1_IO28 0x83 + /* TP_RST */ + MX8MQ_IOMUXC_ENET_RX_CTL_GPIO1_IO24 0x83 + >; + }; + + pinctrl_ecspi1: ecspigrp { + fsl,pins = < + MX8MQ_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x83 + MX8MQ_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x83 + MX8MQ_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x19 + MX8MQ_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x83 + >; + }; + + pinctrl_gauge: gaugegrp { + fsl,pins = < + /* BAT_LOW */ + MX8MQ_IOMUXC_SAI5_RXC_GPIO3_IO20 0x80 + >; + }; + + pinctrl_gnsspwr: gnsspwrgrp { + fsl,pins = < + /* GPS3V3_EN */ + MX8MQ_IOMUXC_NAND_DATA06_GPIO3_IO12 0x83 + >; + }; + + pinctrl_haptic: hapticgrp { + fsl,pins = < + /* MOTO */ + MX8MQ_IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x83 + >; + }; + + pinctrl_hp: hpgrp { + fsl,pins = < + /* HEADPHONE_DET_1V8 */ + MX8MQ_IOMUXC_NAND_DATA03_GPIO3_IO9 0x180 + >; + }; + + pinctrl_hub_pwr: hubpwrgrp { + fsl,pins = < + /* HUB_PWR_3V3_EN */ + MX8MQ_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x83 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x40000026 + MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x40000026 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL 0x40000026 + MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA 0x40000026 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL 0x40000026 + MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA 0x40000026 + >; + }; + + pinctrl_i2c4: i2c4grp { + fsl,pins = < + MX8MQ_IOMUXC_I2C4_SCL_I2C4_SCL 0x40000026 + MX8MQ_IOMUXC_I2C4_SDA_I2C4_SDA 0x40000026 + >; + }; + + pinctrl_keys: keysgrp { + fsl,pins = < + /* VOL- */ + MX8MQ_IOMUXC_ENET_MDIO_GPIO1_IO17 0x01C0 + /* VOL+ */ + MX8MQ_IOMUXC_ENET_MDC_GPIO1_IO16 0x01C0 + >; + }; + + pinctrl_led_b: ledbgrp { + fsl,pins = < + /* LED_B */ + MX8MQ_IOMUXC_GPIO1_IO13_PWM2_OUT 0x06 + >; + }; + + pinctrl_led_g: ledggrp { + fsl,pins = < + /* LED_G */ + MX8MQ_IOMUXC_SAI3_MCLK_PWM4_OUT 0x06 + >; + }; + + pinctrl_led_r: ledrgrp { + fsl,pins = < + /* LED_R */ + MX8MQ_IOMUXC_SPDIF_TX_PWM3_OUT 0x06 + >; + }; + + pinctrl_mag: maggrp { + fsl,pins = < + /* INT_MAG */ + MX8MQ_IOMUXC_SAI5_RXD1_GPIO3_IO22 0x80 + >; + }; + + pinctrl_pmic: pmicgrp { + fsl,pins = < + /* PMIC_NINT */ + MX8MQ_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x80 + >; + }; + + pinctrl_pmic_5v: pmic5vgrp { + fsl,pins = < + /* PMIC_5V */ + MX8MQ_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x80 + >; + }; + + pinctrl_prox: proxgrp { + fsl,pins = < + /* INT_LIGHT */ + MX8MQ_IOMUXC_NAND_DATA01_GPIO3_IO7 0x80 + >; + }; + + pinctrl_rtc: rtcgrp { + fsl,pins = < + /* RTC_INT */ + MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x80 + >; + }; + + pinctrl_sai2: sai2grp { + fsl,pins = < + MX8MQ_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6 + MX8MQ_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6 + MX8MQ_IOMUXC_SAI2_MCLK_SAI2_MCLK 0xd6 + MX8MQ_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0xd6 + MX8MQ_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6 + >; + }; + + pinctrl_sai6: sai6grp { + fsl,pins = < + MX8MQ_IOMUXC_SAI1_RXD5_SAI6_RX_DATA0 0xd6 + MX8MQ_IOMUXC_SAI1_RXD6_SAI6_RX_SYNC 0xd6 + MX8MQ_IOMUXC_SAI1_TXD4_SAI6_RX_BCLK 0xd6 + MX8MQ_IOMUXC_SAI1_TXD5_SAI6_TX_DATA0 0xd6 + >; + }; + + pinctrl_tcpc: tcpcgrp { + fsl,pins = < + /* TCPC_INT */ + MX8MQ_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x01C0 + >; + }; + + pinctrl_touch: touchgrp { + fsl,pins = < + /* TP_INT */ + MX8MQ_IOMUXC_ENET_RD1_GPIO1_IO27 0x80 + >; + }; + + pinctrl_typec: typecgrp { + fsl,pins = < + /* TYPEC_MUX_EN */ + MX8MQ_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x83 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x49 + MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x49 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX 0x49 + MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX 0x49 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX8MQ_IOMUXC_UART3_RXD_UART3_DCE_RX 0x49 + MX8MQ_IOMUXC_UART3_TXD_UART3_DCE_TX 0x49 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX8MQ_IOMUXC_ECSPI2_SCLK_UART4_DCE_RX 0x49 + MX8MQ_IOMUXC_ECSPI2_MOSI_UART4_DCE_TX 0x49 + MX8MQ_IOMUXC_ECSPI2_MISO_UART4_DCE_CTS_B 0x49 + MX8MQ_IOMUXC_ECSPI2_SS0_UART4_DCE_RTS_B 0x49 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83 + MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3 + MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3 + MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3 + MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3 + MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3 + MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3 + MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3 + MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3 + MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3 + MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x83 + MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp100mhz { + fsl,pins = < + MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x8d + MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xcd + MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xcd + MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xcd + MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xcd + MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xcd + MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xcd + MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xcd + MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xcd + MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xcd + MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x8d + MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp200mhz { + fsl,pins = < + MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x9f + MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xdf + MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xdf + MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xdf + MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xdf + MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xdf + MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xdf + MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xdf + MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xdf + MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xdf + MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x9f + MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x80 + MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83 + MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3 + MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3 + MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3 + MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3 + MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3 + MX8MQ_IOMUXC_SD2_RESET_B_USDHC2_RESET_B 0xc1 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2grp100mhz { + fsl,pins = < + MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x80 + MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x8d + MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xcd + MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xcd + MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xcd + MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xcd + MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xcd + MX8MQ_IOMUXC_SD2_RESET_B_USDHC2_RESET_B 0xc1 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2grp200mhz { + fsl,pins = < + MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x80 + MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x9f + MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xcf + MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xcf + MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xcf + MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xcf + MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xcf + MX8MQ_IOMUXC_SD2_RESET_B_USDHC2_RESET_B 0xc1 + >; + }; + + pinctrl_wifi_disable: wifidisablegrp { + fsl,pins = < + /* WIFI_REG_ON */ + MX8MQ_IOMUXC_SAI3_RXC_GPIO4_IO29 0x83 + >; + }; + + pinctrl_wifi_pwr: wifipwrgrp { + fsl,pins = < + /* WIFI3V3_EN */ + MX8MQ_IOMUXC_NAND_DATA04_GPIO3_IO10 0x83 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + /* nWDOG */ + MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x1f + >; + }; +}; + +&i2c1 { + clock-frequency = <387000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + typec_pd: usb-pd@3f { + compatible = "ti,tps6598x"; + reg = <0x3f>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_typec>, <&pinctrl_tcpc>; + interrupt-parent = <&gpio1>; + interrupts = <10 IRQ_TYPE_LEVEL_LOW>; + interrupt-names = "irq"; + + connector { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usb_con_hs: endpoint { + remote-endpoint = <&typec_hs>; + }; + }; + + port@1 { + reg = <1>; + + usb_con_ss: endpoint { + remote-endpoint = <&typec_ss>; + }; + }; + }; + }; + }; + + pmic: pmic@4b { + compatible = "rohm,bd71837"; + reg = <0x4b>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pmic>; + clocks = <&pmic_osc>; + clock-names = "osc"; + clock-output-names = "pmic_clk"; + interrupt-parent = <&gpio1>; + interrupts = <7 IRQ_TYPE_LEVEL_LOW>; + rohm,reset-snvs-powered; + + regulators { + buck1_reg: BUCK1 { + regulator-name = "buck1"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1300000>; + regulator-boot-on; + regulator-ramp-delay = <1250>; + rohm,dvs-run-voltage = <900000>; + rohm,dvs-idle-voltage = <850000>; + rohm,dvs-suspend-voltage = <800000>; + regulator-always-on; + }; + + buck2_reg: BUCK2 { + regulator-name = "buck2"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1300000>; + regulator-boot-on; + regulator-ramp-delay = <1250>; + rohm,dvs-run-voltage = <1000000>; + rohm,dvs-idle-voltage = <900000>; + regulator-always-on; + }; + + buck3_reg: BUCK3 { + regulator-name = "buck3"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1300000>; + regulator-boot-on; + rohm,dvs-run-voltage = <900000>; + }; + + buck4_reg: BUCK4 { + regulator-name = "buck4"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1300000>; + rohm,dvs-run-voltage = <1000000>; + }; + + buck5_reg: BUCK5 { + regulator-name = "buck5"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1350000>; + regulator-boot-on; + regulator-always-on; + }; + + buck6_reg: BUCK6 { + regulator-name = "buck6"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + buck7_reg: BUCK7 { + regulator-name = "buck7"; + regulator-min-microvolt = <1605000>; + regulator-max-microvolt = <1995000>; + regulator-boot-on; + regulator-always-on; + }; + + buck8_reg: BUCK8 { + regulator-name = "buck8"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1400000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo1_reg: LDO1 { + regulator-name = "ldo1"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + /* leave on for snvs power button */ + regulator-always-on; + }; + + ldo2_reg: LDO2 { + regulator-name = "ldo2"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-boot-on; + /* leave on for snvs power button */ + regulator-always-on; + }; + + ldo3_reg: LDO3 { + regulator-name = "ldo3"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo4_reg: LDO4 { + regulator-name = "ldo4"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo5_reg: LDO5 { + /* VDD_PHY_0V9 - MIPI and HDMI domains */ + regulator-name = "ldo5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + ldo6_reg: LDO6 { + /* VDD_PHY_0V9 - MIPI, HDMI and USB domains */ + regulator-name = "ldo6"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo7_reg: LDO7 { + /* VDD_PHY_3V3 - USB domain */ + regulator-name = "ldo7"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; + + rtc@68 { + compatible = "microcrystal,rv4162"; + reg = <0x68>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rtc>; + interrupt-parent = <&gpio1>; + interrupts = <9 IRQ_TYPE_LEVEL_LOW>; + }; +}; + +&i2c2 { + clock-frequency = <387000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + magnetometer@1e { + compatible = "st,lsm9ds1-magn"; + reg = <0x1e>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mag>; + interrupt-parent = <&gpio3>; + interrupts = <22 IRQ_TYPE_LEVEL_HIGH>; + vdd-supply = <®_vdd_sen>; + vddio-supply = <®_vdd_1v8>; + }; + + regulator@3e { + compatible = "tps65132"; + reg = <0x3e>; + + reg_lcd_avdd: outp { + regulator-name = "LCD_AVDD"; + vin-supply = <®_lcd_3v4>; + }; + + reg_lcd_avee: outn { + regulator-name = "LCD_AVEE"; + vin-supply = <®_lcd_3v4>; + }; + }; + + proximity: prox@60 { + compatible = "vishay,vcnl4040"; + reg = <0x60>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_prox>; + interrupt-parent = <&gpio3>; + interrupts = <7 IRQ_TYPE_LEVEL_LOW>; + }; + + accel_gyro: accel-gyro@6a { + compatible = "st,lsm9ds1-imu"; + reg = <0x6a>; + vdd-supply = <®_vdd_sen>; + vddio-supply = <®_vdd_1v8>; + }; +}; + +&i2c3 { + clock-frequency = <387000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; + + codec: audio-codec@1a { + compatible = "wlf,wm8962"; + reg = <0x1a>; + clocks = <&clk IMX8MQ_CLK_SAI2_ROOT>; + assigned-clocks = <&clk IMX8MQ_CLK_SAI2>; + assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>; + assigned-clock-rates = <24576000>; + #sound-dai-cells = <0>; + mic-cfg = <0x200>; + DCVDD-supply = <®_aud_1v8>; + DBVDD-supply = <®_aud_1v8>; + AVDD-supply = <®_aud_1v8>; + CPVDD-supply = <®_aud_1v8>; + MICVDD-supply = <®_aud_1v8>; + PLLVDD-supply = <®_aud_1v8>; + SPKVDD1-supply = <®_vsys_3v4>; + SPKVDD2-supply = <®_vsys_3v4>; + gpio-cfg = < + 0x0000 /* n/c */ + 0x0001 /* gpio2, 1: default */ + 0x0013 /* gpio3, 2: dmicclk */ + 0x0000 /* n/c, 3: default */ + 0x8014 /* gpio5, 4: dmic_dat */ + 0x0000 /* gpio6, 5: default */ + >; + }; + + backlight@36 { + compatible = "ti,lm36922"; + reg = <0x36>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_bl>; + #address-cells = <1>; + #size-cells = <0>; + enable-gpios = <&gpio3 14 GPIO_ACTIVE_HIGH>; + vled-supply = <®_vsys_3v4>; + ti,ovp-microvolt = <25000000>; + + led_backlight: led@0 { + reg = <0>; + label = ":backlight"; + linux,default-trigger = "backlight"; + led-max-microamp = <20000>; + }; + }; + + touchscreen@38 { + compatible = "edt,edt-ft5506"; + reg = <0x38>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_touch>; + interrupt-parent = <&gpio1>; + interrupts = <27 IRQ_TYPE_EDGE_FALLING>; + touchscreen-size-x = <720>; + touchscreen-size-y = <1440>; + vcc-supply = <®_lcd_1v8>; + }; +}; + +&i2c4 { + clock-frequency = <387000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c4>; + status = "okay"; + + bat: fuel-gauge@36 { + compatible = "maxim,max17055"; + reg = <0x36>; + interrupt-parent = <&gpio3>; + interrupts = <20 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gauge>; + maxim,over-heat-temp = <700>; + maxim,over-volt = <4500>; + maxim,rsns-microohm = <5000>; + }; + + bq25895: charger@6a { + compatible = "ti,bq25895", "ti,bq25890"; + reg = <0x6a>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_charger_in>; + interrupt-parent = <&gpio3>; + interrupts = <3 IRQ_TYPE_EDGE_FALLING>; + phys = <&usb3_phy0>; + ti,precharge-current = <130000>; /* uA */ + ti,minimum-sys-voltage = <3700000>; /* uV */ + ti,boost-voltage = <5000000>; /* uV */ + ti,boost-max-current = <500000>; /* uA */ + ti,use-vinmin-threshold = <1>; /* enable VINDPM */ + ti,vinmin-threshold = <3900000>; /* uV */ + monitored-battery = <&bat>; + power-supplies = <&typec_pd>; + }; +}; + +&lcdif { + status = "okay"; +}; + +&mipi_dsi { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + lcd_panel: panel@0 { + compatible = "mantix,mlaf057we51-x"; + reg = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_dsirst>; + avdd-supply = <®_lcd_avdd>; + avee-supply = <®_lcd_avee>; + vddi-supply = <®_lcd_1v8>; + backlight = <&backlight_dsi>; + reset-gpios = <&gpio1 29 GPIO_ACTIVE_LOW>; + mantix,tp-rstn-gpios = <&gpio1 24 GPIO_ACTIVE_LOW>; + + port { + panel_in: endpoint { + remote-endpoint = <&mipi_dsi_out>; + }; + }; + }; + + ports { + port@1 { + reg = <1>; + + mipi_dsi_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; +}; + +&pgc_gpu { + power-supply = <&buck3_reg>; +}; + +&pgc_mipi { + power-supply = <&ldo5_reg>; +}; + +&pgc_vpu { + power-supply = <&buck4_reg>; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_haptic>; + status = "okay"; +}; + +&pwm2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_led_b>; + status = "okay"; +}; + +&pwm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_led_r>; + status = "okay"; +}; + +&pwm4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_led_g>; + status = "okay"; +}; + +&sai2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai2>; + assigned-clocks = <&clk IMX8MQ_CLK_SAI2>; + assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>; + assigned-clock-rates = <24576000>; + status = "okay"; +}; + +&sai6 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai6>; + assigned-clocks = <&clk IMX8MQ_CLK_SAI6>; + assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>; + assigned-clock-rates = <24576000>; + fsl,sai-synchronous-rx; + status = "okay"; +}; + +&snvs_pwrkey { + status = "okay"; +}; + +&snvs_rtc { + status = "disabled"; +}; + +&uart1 { /* console */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart2 { /* TPS - GPS - DEBUG */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; + + gnss { + compatible = "globaltop,pa6h"; + vcc-supply = <®_gnss>; + current-speed = <9600>; + }; +}; + +&uart3 { /* SMC */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + status = "okay"; +}; + +&uart4 { /* BT */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + uart-has-rtscts; + status = "okay"; +}; + +&usb3_phy0 { + status = "okay"; +}; + +&usb3_phy1 { + vbus-supply = <®_hub>; + status = "okay"; +}; + +&usb_dwc3_0 { + #address-cells = <1>; + #size-cells = <0>; + dr_mode = "otg"; + snps,dis_u3_susphy_quirk; + status = "okay"; + + port@0 { + reg = <0>; + + typec_hs: endpoint { + remote-endpoint = <&usb_con_hs>; + }; + }; + + port@1 { + reg = <1>; + + typec_ss: endpoint { + remote-endpoint = <&usb_con_ss>; + }; + }; +}; + +&usb_dwc3_1 { + dr_mode = "host"; + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + /* Microchip USB2642 */ + hub@1 { + compatible = "usb424,2640"; + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + mass-storage@1 { + compatible = "usb424,4041"; + reg = <1>; + }; + }; +}; + +&usdhc1 { + assigned-clocks = <&clk IMX8MQ_CLK_USDHC1>; + assigned-clock-rates = <400000000>; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + bus-width = <8>; + vmmc-supply = <®_vdd_3v3>; + power-supply = <®_vdd_1v8>; + non-removable; + status = "okay"; +}; + +&usdhc2 { + assigned-clocks = <&clk IMX8MQ_CLK_USDHC2>; + assigned-clock-rates = <200000000>; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>; + bus-width = <4>; + vmmc-supply = <®_wifi_3v3>; + mmc-pwrseq = <&usdhc2_pwrseq>; + post-power-on-delay-ms = <1000>; + cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; + max-frequency = <50000000>; + disable-wp; + cap-sdio-irq; + keep-power-in-suspend; + wakeup-source; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; + status = "okay"; +}; diff --git a/arch/arm/dts/imxrt1170-evk-u-boot.dtsi b/arch/arm/dts/imxrt1170-evk-u-boot.dtsi new file mode 100644 index 0000000000..88ff986ba0 --- /dev/null +++ b/arch/arm/dts/imxrt1170-evk-u-boot.dtsi @@ -0,0 +1,94 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) 2022 + * Author(s): Jesse Taube + * Giulio Benetti + */ + +/ { + chosen { + u-boot,dm-spl; + }; + + clocks { + u-boot,dm-spl; + }; + + soc { + u-boot,dm-spl; + }; +}; + +&osc { + u-boot,dm-spl; +}; + +&rcosc16M { + u-boot,dm-spl; +}; + +&osc32k { + u-boot,dm-spl; +}; + +&clks { + u-boot,dm-spl; +}; + +&gpio1 { + u-boot,dm-spl; +}; + +&gpio2 { + u-boot,dm-spl; +}; + +&gpio3 { + u-boot,dm-spl; +}; + +&gpio4 { + u-boot,dm-spl; +}; + +&gpio5 { + u-boot,dm-spl; +}; + +&gpt1 { + u-boot,dm-spl; +}; + +&lpuart1 { /* console */ + u-boot,dm-spl; +}; + +&semc { + u-boot,dm-spl; + + bank1: bank@0 { + u-boot,dm-spl; + }; +}; + +&iomuxc { + u-boot,dm-spl; + + imxrt1170-evk { + u-boot,dm-spl; + pinctrl_lpuart1: lpuart1grp { + u-boot,dm-spl; + }; + + pinctrl_usdhc0: usdhc0grp { + u-boot,dm-spl; + }; + pinctrl_semc: semcgrp { + u-boot,dm-spl; + }; + }; +}; + +&usdhc1 { + u-boot,dm-spl; +}; diff --git a/arch/arm/dts/imxrt1170-evk.dts b/arch/arm/dts/imxrt1170-evk.dts new file mode 100644 index 0000000000..c2fd0c0392 --- /dev/null +++ b/arch/arm/dts/imxrt1170-evk.dts @@ -0,0 +1,250 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) 2022 + * Author(s): Jesse Taube + * Giulio Benetti + */ + +/dts-v1/; +#include "imxrt1170.dtsi" +#include "imxrt1170-evk-u-boot.dtsi" +#include "imxrt1170-pinfunc.h" + +/ { + model = "NXP imxrt1170-evk board"; + compatible = "fsl,imxrt1170-evk", "fsl,imxrt1170"; + + chosen { + stdout-path = "serial0:115200n8"; + tick-timer = &gpt1; + }; + + memory { + device_type = "memory"; + reg = <0x20240000 0xf0000 0x80000000 0x4000000>; + + ocram: ocram@20240000 { + device_type = "memory"; + reg = <0x20240000 0xf0000>; + }; + + sdram: sdram@80000000 { + device_type = "memory"; + reg = <0x80000000 0x4000000>; + }; + }; +}; + +&lpuart1 { /* console */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart1>; + status = "okay"; +}; + +&semc { + /* + * Memory configuration from sdram datasheet IS42S16160J-6BLI + */ + fsl,sdram-mux = /bits/ 8 ; + fsl,sdram-control = /bits/ 8 ; + fsl,sdram-timing = /bits/ 8 <0x2 + 0x2 + 0xd + 0x0 + 0x8 + 0x7 + + 0x0d + 0x0b + 0x00 + 0x00 + + 0x00 + 0x0A + 0x08 + 0x09>; + + bank1: bank@0 { + fsl,base-address = <0x80000000>; + fsl,memory-size = ; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart1>; + + imxrt1170-evk { + pinctrl_lpuart1: lpuart1grp { + fsl,pins = < + IOMUXC_GPIO_AD_24_LPUART1_TXD 0xf1 + IOMUXC_GPIO_AD_25_LPUART1_RXD 0xf1 + >; + }; + + pinctrl_usdhc0: usdhc0grp { + fsl,pins = < + IOMUXC_GPIO_AD_32_USDHC1_CD_B + 0x1B000 + IOMUXC_GPIO_AD_34_USDHC1_VSELECT + 0xB069 + IOMUXC_GPIO_SD_B1_00_USDHC1_CMD + 0x17061 + IOMUXC_GPIO_SD_B1_01_USDHC1_CLK + 0x17061 + IOMUXC_GPIO_SD_B1_05_USDHC1_DATA3 + 0x17061 + IOMUXC_GPIO_SD_B1_04_USDHC1_DATA2 + 0x17061 + IOMUXC_GPIO_SD_B1_03_USDHC1_DATA1 + 0x17061 + IOMUXC_GPIO_SD_B1_02_USDHC1_DATA0 + 0x17061 + >; + }; + pinctrl_semc: semcgrp { + fsl,pins = < + IOMUXC_GPIO_EMC_B1_00_SEMC_DATA00 + 8 /* SEMC_D0 */ + IOMUXC_GPIO_EMC_B1_01_SEMC_DATA01 + 8 /* SEMC_D1 */ + IOMUXC_GPIO_EMC_B1_02_SEMC_DATA02 + 8 /* SEMC_D2 */ + IOMUXC_GPIO_EMC_B1_03_SEMC_DATA03 + 8 /* SEMC_D3 */ + IOMUXC_GPIO_EMC_B1_04_SEMC_DATA04 + 8 /* SEMC_D4 */ + IOMUXC_GPIO_EMC_B1_05_SEMC_DATA05 + 8 /* SEMC_D5 */ + IOMUXC_GPIO_EMC_B1_06_SEMC_DATA06 + 8 /* SEMC_D6 */ + IOMUXC_GPIO_EMC_B1_07_SEMC_DATA07 + 8 /* SEMC_D7 */ + IOMUXC_GPIO_EMC_B1_08_SEMC_DM00 + 8 /* SEMC_DM0 */ + IOMUXC_GPIO_EMC_B1_09_SEMC_ADDR00 + 8 /* SEMC_A0 */ + IOMUXC_GPIO_EMC_B1_10_SEMC_ADDR01 + 8 /* SEMC_A1 */ + IOMUXC_GPIO_EMC_B1_11_SEMC_ADDR02 + 8 /* SEMC_A2 */ + IOMUXC_GPIO_EMC_B1_12_SEMC_ADDR03 + 8 /* SEMC_A3 */ + IOMUXC_GPIO_EMC_B1_13_SEMC_ADDR04 + 8 /* SEMC_A4 */ + IOMUXC_GPIO_EMC_B1_14_SEMC_ADDR05 + 8 /* SEMC_A5 */ + IOMUXC_GPIO_EMC_B1_15_SEMC_ADDR06 + 8 /* SEMC_A6 */ + IOMUXC_GPIO_EMC_B1_16_SEMC_ADDR07 + 8 /* SEMC_A7 */ + IOMUXC_GPIO_EMC_B1_17_SEMC_ADDR08 + 8 /* SEMC_A8 */ + IOMUXC_GPIO_EMC_B1_18_SEMC_ADDR09 + 8 /* SEMC_A9 */ + IOMUXC_GPIO_EMC_B1_19_SEMC_ADDR11 + 8 /* SEMC_A11 */ + IOMUXC_GPIO_EMC_B1_20_SEMC_ADDR12 + 8 /* SEMC_A12 */ + IOMUXC_GPIO_EMC_B1_21_SEMC_BA0 + 8 /* SEMC_BA0 */ + IOMUXC_GPIO_EMC_B1_22_SEMC_BA1 + 8 /* SEMC_BA1 */ + IOMUXC_GPIO_EMC_B1_23_SEMC_ADDR10 + 8 /* SEMC_A10 */ + IOMUXC_GPIO_EMC_B1_24_SEMC_CAS + 8 /* SEMC_CAS */ + IOMUXC_GPIO_EMC_B1_25_SEMC_RAS + 8 /* SEMC_RAS */ + IOMUXC_GPIO_EMC_B1_26_SEMC_CLK + 8 /* SEMC_CLK */ + IOMUXC_GPIO_EMC_B1_27_SEMC_CKE + 8 /* SEMC_CKE */ + IOMUXC_GPIO_EMC_B1_28_SEMC_WE + 8 /* SEMC_WE */ + IOMUXC_GPIO_EMC_B1_29_SEMC_CS0 + 8 /* SEMC_CS0 */ + IOMUXC_GPIO_EMC_B1_30_SEMC_DATA08 + 8 /* SEMC_D8 */ + IOMUXC_GPIO_EMC_B1_31_SEMC_DATA09 + 8 /* SEMC_D9 */ + IOMUXC_GPIO_EMC_B1_32_SEMC_DATA10 + 8 /* SEMC_D10 */ + IOMUXC_GPIO_EMC_B1_33_SEMC_DATA11 + 8 /* SEMC_D11 */ + IOMUXC_GPIO_EMC_B1_34_SEMC_DATA12 + 8 /* SEMC_D12 */ + IOMUXC_GPIO_EMC_B1_35_SEMC_DATA13 + 8 /* SEMC_D13 */ + IOMUXC_GPIO_EMC_B1_36_SEMC_DATA14 + 8 /* SEMC_D14 */ + IOMUXC_GPIO_EMC_B1_37_SEMC_DATA15 + 8 /* SEMC_D15 */ + IOMUXC_GPIO_EMC_B1_08_SEMC_DM00 + 8 /* SEMC_DM00 */ + IOMUXC_GPIO_EMC_B1_38_SEMC_DM01 + 8 /* SEMC_DM01 */ + IOMUXC_GPIO_EMC_B2_08_SEMC_DM02 + 4 /* SEMC_DM02 */ + IOMUXC_GPIO_EMC_B2_17_SEMC_DM03 + 8 /* SEMC_DM03 */ + IOMUXC_GPIO_EMC_B2_00_SEMC_DATA16 + 8 /* SEMC_D16 */ + IOMUXC_GPIO_EMC_B2_01_SEMC_DATA17 + 8 /* SEMC_D17 */ + IOMUXC_GPIO_EMC_B2_02_SEMC_DATA18 + 8 /* SEMC_D18 */ + IOMUXC_GPIO_EMC_B2_03_SEMC_DATA19 + 8 /* SEMC_D19 */ + IOMUXC_GPIO_EMC_B2_04_SEMC_DATA20 + 8 /* SEMC_D20 */ + IOMUXC_GPIO_EMC_B2_05_SEMC_DATA21 + 8 /* SEMC_D21 */ + IOMUXC_GPIO_EMC_B2_06_SEMC_DATA22 + 8 /* SEMC_D22 */ + IOMUXC_GPIO_EMC_B2_07_SEMC_DATA23 + 8 /* SEMC_D23 */ + IOMUXC_GPIO_EMC_B2_09_SEMC_DATA24 + 8 /* SEMC_D24 */ + IOMUXC_GPIO_EMC_B2_10_SEMC_DATA25 + 8 /* SEMC_D25 */ + IOMUXC_GPIO_EMC_B2_11_SEMC_DATA26 + 4 /* SEMC_D26 */ + IOMUXC_GPIO_EMC_B2_12_SEMC_DATA27 + 8 /* SEMC_D27 */ + IOMUXC_GPIO_EMC_B2_13_SEMC_DATA28 + 8 /* SEMC_D28 */ + IOMUXC_GPIO_EMC_B2_14_SEMC_DATA29 + 8 /* SEMC_D29 */ + IOMUXC_GPIO_EMC_B2_15_SEMC_DATA30 + 8 /* SEMC_D30 */ + IOMUXC_GPIO_EMC_B2_16_SEMC_DATA31 + 8 /* SEMC_D31 */ + IOMUXC_GPIO_EMC_B1_39_SEMC_DQS + (IMX_PAD_SION | 8) /* SEMC_DQS */ + >; + }; + }; +}; + +&gpt1 { + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; + pinctrl-0 = <&pinctrl_usdhc0>; + pinctrl-1 = <&pinctrl_usdhc0>; + pinctrl-2 = <&pinctrl_usdhc0>; + pinctrl-3 = <&pinctrl_usdhc0>; + status = "okay"; + broken-cd; +}; diff --git a/arch/arm/dts/imxrt1170-pinfunc.h b/arch/arm/dts/imxrt1170-pinfunc.h new file mode 100644 index 0000000000..fba5483a08 --- /dev/null +++ b/arch/arm/dts/imxrt1170-pinfunc.h @@ -0,0 +1,1561 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2021 + * Author(s): Jesse Taube + */ + +#ifndef _DT_BINDINGS_PINCTRL_IMXRT1170_PINFUNC_H +#define _DT_BINDINGS_PINCTRL_IMXRT1170_PINFUNC_H + +#define IMX_PAD_SION 0x40000000 + +/* + * The pin function ID is a tuple of + * + */ + +#define IOMUXC_GPIO_LPSR_00_FLEXCAN3_TX 0x000 0x040 0x0 0x0 0x0 +#define IOMUXC_GPIO_LPSR_00_MIC_CLK 0x000 0x040 0x0 0x1 0x0 +#define IOMUXC_GPIO_LPSR_00_MQS_RIGHT 0x000 0x040 0x0 0x2 0x0 +#define IOMUXC_GPIO_LPSR_00_ARM_CM4_EVENTO 0x000 0x040 0x0 0x3 0x0 +#define IOMUXC_GPIO_LPSR_00_GPIO_MUX6_IO00 0x000 0x040 0x0 0x5 0x0 +#define IOMUXC_GPIO_LPSR_00_LPUART12_TXD 0x000 0x040 0x0B0 0x6 0x0 +#define IOMUXC_GPIO_LPSR_00_SAI4_MCLK 0x000 0x040 0x0C8 0x7 0x0 +#define IOMUXC_GPIO_LPSR_00_GPIO12_IO00 0x000 0x040 0x0 0xA 0x0 + +#define IOMUXC_GPIO_LPSR_01_FLEXCAN3_RX 0x004 0x044 0x080 0x0 0x0 +#define IOMUXC_GPIO_LPSR_01_MIC_BITSTREAM0 0x004 0x044 0x0B4 0x1 0x0 +#define IOMUXC_GPIO_LPSR_01_MQS_LEFT 0x004 0x044 0x0 0x2 0x0 +#define IOMUXC_GPIO_LPSR_01_ARM_CM4_EVENTI 0x004 0x044 0x0 0x3 0x0 +#define IOMUXC_GPIO_LPSR_01_GPIO_MUX6_IO01 0x004 0x044 0x0 0x5 0x0 +#define IOMUXC_GPIO_LPSR_01_LPUART12_RXD 0x004 0x044 0x0AC 0x6 0x0 +#define IOMUXC_GPIO_LPSR_01_GPIO12_IO01 0x004 0x044 0x0 0xA 0x0 + +#define IOMUXC_GPIO_LPSR_02_GPIO12_IO02 0x008 0x048 0x0 0xA 0x0 +#define IOMUXC_GPIO_LPSR_02_SRC_BOOT_MODE00 0x008 0x048 0x0 0x0 0x0 +#define IOMUXC_GPIO_LPSR_02_LPSPI5_SCK 0x008 0x048 0x098 0x1 0x0 +#define IOMUXC_GPIO_LPSR_02_SAI4_TX_DATA 0x008 0x048 0x0 0x2 0x0 +#define IOMUXC_GPIO_LPSR_02_MQS_RIGHT 0x008 0x048 0x0 0x3 0x0 +#define IOMUXC_GPIO_LPSR_02_GPIO_MUX6_IO02 0x008 0x048 0x0 0x5 0x0 + +#define IOMUXC_GPIO_LPSR_03_SRC_BOOT_MODE01 0x00C 0x04C 0x0 0x0 0x0 +#define IOMUXC_GPIO_LPSR_03_LPSPI5_PCS0 0x00C 0x04C 0x094 0x1 0x0 +#define IOMUXC_GPIO_LPSR_03_SAI4_TX_SYNC 0x00C 0x04C 0x0DC 0x2 0x0 +#define IOMUXC_GPIO_LPSR_03_MQS_LEFT 0x00C 0x04C 0x0 0x3 0x0 +#define IOMUXC_GPIO_LPSR_03_GPIO_MUX6_IO03 0x00C 0x04C 0x0 0x5 0x0 +#define IOMUXC_GPIO_LPSR_03_GPIO12_IO03 0x00C 0x04C 0x0 0xA 0x0 + +#define IOMUXC_GPIO_LPSR_04_LPI2C5_SDA 0x010 0x050 0x088 0x0 0x0 +#define IOMUXC_GPIO_LPSR_04_LPSPI5_SOUT 0x010 0x050 0x0A0 0x1 0x0 +#define IOMUXC_GPIO_LPSR_04_SAI4_TX_BCLK 0x010 0x050 0x0D8 0x2 0x0 +#define IOMUXC_GPIO_LPSR_04_LPUART12_RTS_B 0x010 0x050 0x0 0x3 0x0 +#define IOMUXC_GPIO_LPSR_04_GPIO_MUX6_IO04 0x010 0x050 0x0 0x5 0x0 +#define IOMUXC_GPIO_LPSR_04_LPUART11_TXD 0x010 0x050 0x0A8 0x6 0x0 +#define IOMUXC_GPIO_LPSR_04_GPIO12_IO04 0x010 0x050 0x0 0xA 0x0 + +#define IOMUXC_GPIO_LPSR_05_GPIO12_IO05 0x014 0x054 0x0 0xA 0x0 +#define IOMUXC_GPIO_LPSR_05_LPI2C5_SCL 0x014 0x054 0x084 0x0 0x0 +#define IOMUXC_GPIO_LPSR_05_LPSPI5_SIN 0x014 0x054 0x09C 0x1 0x0 +#define IOMUXC_GPIO_LPSR_05_SAI4_MCLK 0x014 0x054 0x0C8 0x2 0x1 +#define IOMUXC_GPIO_LPSR_05_LPUART12_CTS_B 0x014 0x054 0x0 0x3 0x0 +#define IOMUXC_GPIO_LPSR_05_GPIO_MUX6_IO05 0x014 0x054 0x0 0x5 0x0 +#define IOMUXC_GPIO_LPSR_05_LPUART11_RXD 0x014 0x054 0x0A4 0x6 0x0 +#define IOMUXC_GPIO_LPSR_05_NMI_GLUE_NMI 0x014 0x054 0x0C4 0x7 0x0 + +#define IOMUXC_GPIO_LPSR_06_LPI2C6_SDA 0x018 0x058 0x090 0x0 0x0 +#define IOMUXC_GPIO_LPSR_06_SAI4_RX_DATA 0x018 0x058 0x0D0 0x2 0x0 +#define IOMUXC_GPIO_LPSR_06_LPUART12_TXD 0x018 0x058 0x0B0 0x3 0x1 +#define IOMUXC_GPIO_LPSR_06_LPSPI6_PCS3 0x018 0x058 0x0 0x4 0x0 +#define IOMUXC_GPIO_LPSR_06_GPIO_MUX6_IO06 0x018 0x058 0x0 0x5 0x0 +#define IOMUXC_GPIO_LPSR_06_FLEXCAN3_TX 0x018 0x058 0x0 0x6 0x0 +#define IOMUXC_GPIO_LPSR_06_PIT2_TRIGGER3 0x018 0x058 0x0 0x7 0x0 +#define IOMUXC_GPIO_LPSR_06_LPSPI5_PCS1 0x018 0x058 0x0 0x8 0x0 +#define IOMUXC_GPIO_LPSR_06_GPIO12_IO06 0x018 0x058 0x0 0xA 0x0 + +#define IOMUXC_GPIO_LPSR_07_LPI2C6_SCL 0x01C 0x05C 0x08C 0x0 0x0 +#define IOMUXC_GPIO_LPSR_07_SAI4_RX_BCLK 0x01C 0x05C 0x0CC 0x2 0x0 +#define IOMUXC_GPIO_LPSR_07_LPUART12_RXD 0x01C 0x05C 0x0AC 0x3 0x1 +#define IOMUXC_GPIO_LPSR_07_LPSPI6_PCS2 0x01C 0x05C 0x0 0x4 0x0 +#define IOMUXC_GPIO_LPSR_07_GPIO_MUX6_IO07 0x01C 0x05C 0x0 0x5 0x0 +#define IOMUXC_GPIO_LPSR_07_FLEXCAN3_RX 0x01C 0x05C 0x080 0x6 0x1 +#define IOMUXC_GPIO_LPSR_07_PIT2_TRIGGER2 0x01C 0x05C 0x0 0x7 0x0 +#define IOMUXC_GPIO_LPSR_07_LPSPI5_PCS2 0x01C 0x05C 0x0 0x8 0x0 +#define IOMUXC_GPIO_LPSR_07_GPIO12_IO07 0x01C 0x05C 0x0 0xA 0x0 + +#define IOMUXC_GPIO_LPSR_08_GPIO12_IO08 0x020 0x060 0x0 0xA 0x0 +#define IOMUXC_GPIO_LPSR_08_LPUART11_TXD 0x020 0x060 0x0A8 0x0 0x1 +#define IOMUXC_GPIO_LPSR_08_FLEXCAN3_TX 0x020 0x060 0x0 0x1 0x0 +#define IOMUXC_GPIO_LPSR_08_SAI4_RX_SYNC 0x020 0x060 0x0D4 0x2 0x0 +#define IOMUXC_GPIO_LPSR_08_MIC_CLK 0x020 0x060 0x0 0x3 0x0 +#define IOMUXC_GPIO_LPSR_08_LPSPI6_PCS1 0x020 0x060 0x0 0x4 0x0 +#define IOMUXC_GPIO_LPSR_08_GPIO_MUX6_IO08 0x020 0x060 0x0 0x5 0x0 +#define IOMUXC_GPIO_LPSR_08_LPI2C5_SDA 0x020 0x060 0x088 0x6 0x1 +#define IOMUXC_GPIO_LPSR_08_PIT2_TRIGGER1 0x020 0x060 0x0 0x7 0x0 +#define IOMUXC_GPIO_LPSR_08_LPSPI5_PCS3 0x020 0x060 0x0 0x8 0x0 + +#define IOMUXC_GPIO_LPSR_09_GPIO12_IO09 0x024 0x064 0x0 0xA 0x0 +#define IOMUXC_GPIO_LPSR_09_LPUART11_RXD 0x024 0x064 0x0A4 0x0 0x1 +#define IOMUXC_GPIO_LPSR_09_FLEXCAN3_RX 0x024 0x064 0x080 0x1 0x2 +#define IOMUXC_GPIO_LPSR_09_PIT2_TRIGGER0 0x024 0x064 0x0 0x2 0x0 +#define IOMUXC_GPIO_LPSR_09_MIC_BITSTREAM0 0x024 0x064 0x0B4 0x3 0x1 +#define IOMUXC_GPIO_LPSR_09_LPSPI6_PCS0 0x024 0x064 0x0 0x4 0x0 +#define IOMUXC_GPIO_LPSR_09_GPIO_MUX6_IO09 0x024 0x064 0x0 0x5 0x0 +#define IOMUXC_GPIO_LPSR_09_LPI2C5_SCL 0x024 0x064 0x084 0x6 0x1 +#define IOMUXC_GPIO_LPSR_09_SAI4_TX_DATA 0x024 0x064 0x0 0x7 0x0 + +#define IOMUXC_GPIO_LPSR_10_GPIO12_IO10 0x028 0x068 0x0 0xA 0x0 +#define IOMUXC_GPIO_LPSR_10_JTAG_MUX_TRSTB 0x028 0x068 0x0 0x0 0x0 +#define IOMUXC_GPIO_LPSR_10_LPUART11_CTS_B 0x028 0x068 0x0 0x1 0x0 +#define IOMUXC_GPIO_LPSR_10_LPI2C6_SDA 0x028 0x068 0x090 0x2 0x1 +#define IOMUXC_GPIO_LPSR_10_MIC_BITSTREAM1 0x028 0x068 0x0B8 0x3 0x0 +#define IOMUXC_GPIO_LPSR_10_LPSPI6_SCK 0x028 0x068 0x0 0x4 0x0 +#define IOMUXC_GPIO_LPSR_10_GPIO_MUX6_IO10 0x028 0x068 0x0 0x5 0x0 +#define IOMUXC_GPIO_LPSR_10_LPI2C5_SCLS 0x028 0x068 0x0 0x6 0x0 +#define IOMUXC_GPIO_LPSR_10_SAI4_TX_SYNC 0x028 0x068 0x0DC 0x7 0x1 +#define IOMUXC_GPIO_LPSR_10_LPUART12_TXD 0x028 0x068 0x0B0 0x8 0x2 + +#define IOMUXC_GPIO_LPSR_11_JTAG_MUX_TDO 0x02C 0x06C 0x0 0x0 0x0 +#define IOMUXC_GPIO_LPSR_11_LPUART11_RTS_B 0x02C 0x06C 0x0 0x1 0x0 +#define IOMUXC_GPIO_LPSR_11_LPI2C6_SCL 0x02C 0x06C 0x08C 0x2 0x1 +#define IOMUXC_GPIO_LPSR_11_MIC_BITSTREAM2 0x02C 0x06C 0x0BC 0x3 0x0 +#define IOMUXC_GPIO_LPSR_11_LPSPI6_SOUT 0x02C 0x06C 0x0 0x4 0x0 +#define IOMUXC_GPIO_LPSR_11_GPIO_MUX6_IO11 0x02C 0x06C 0x0 0x5 0x0 +#define IOMUXC_GPIO_LPSR_11_LPI2C5_SDAS 0x02C 0x06C 0x0 0x6 0x0 +#define IOMUXC_GPIO_LPSR_11_ARM_TRACE_SWO 0x02C 0x06C 0x0 0x7 0x0 +#define IOMUXC_GPIO_LPSR_11_LPUART12_RXD 0x02C 0x06C 0x0AC 0x8 0x2 +#define IOMUXC_GPIO_LPSR_11_GPIO12_IO11 0x02C 0x06C 0x0 0xA 0x0 + +#define IOMUXC_GPIO_LPSR_12_GPIO12_IO12 0x030 0x070 0x0 0xA 0x0 +#define IOMUXC_GPIO_LPSR_12_JTAG_MUX_TDI 0x030 0x070 0x0 0x0 0x0 +#define IOMUXC_GPIO_LPSR_12_PIT2_TRIGGER0 0x030 0x070 0x0 0x1 0x0 +#define IOMUXC_GPIO_LPSR_12_MIC_BITSTREAM3 0x030 0x070 0x0C0 0x3 0x0 +#define IOMUXC_GPIO_LPSR_12_LPSPI6_SIN 0x030 0x070 0x0 0x4 0x0 +#define IOMUXC_GPIO_LPSR_12_GPIO_MUX6_IO12 0x030 0x070 0x0 0x5 0x0 +#define IOMUXC_GPIO_LPSR_12_LPI2C5_HREQ 0x030 0x070 0x0 0x6 0x0 +#define IOMUXC_GPIO_LPSR_12_SAI4_TX_BCLK 0x030 0x070 0x0D8 0x7 0x1 +#define IOMUXC_GPIO_LPSR_12_LPSPI5_SCK 0x030 0x070 0x098 0x8 0x1 + +#define IOMUXC_GPIO_LPSR_13_GPIO12_IO13 0x034 0x074 0x0 0xA 0x0 +#define IOMUXC_GPIO_LPSR_13_JTAG_MUX_MOD 0x034 0x074 0x0 0x0 0x0 +#define IOMUXC_GPIO_LPSR_13_MIC_BITSTREAM1 0x034 0x074 0x0B8 0x1 0x1 +#define IOMUXC_GPIO_LPSR_13_PIT2_TRIGGER1 0x034 0x074 0x0 0x2 0x0 +#define IOMUXC_GPIO_LPSR_13_GPIO_MUX6_IO13 0x034 0x074 0x0 0x5 0x0 +#define IOMUXC_GPIO_LPSR_13_SAI4_RX_DATA 0x034 0x074 0x0D0 0x7 0x1 +#define IOMUXC_GPIO_LPSR_13_LPSPI5_PCS0 0x034 0x074 0x094 0x8 0x1 + +#define IOMUXC_GPIO_LPSR_14_JTAG_MUX_TCK 0x038 0x078 0x0 0x0 0x0 +#define IOMUXC_GPIO_LPSR_14_MIC_BITSTREAM2 0x038 0x078 0x0BC 0x1 0x1 +#define IOMUXC_GPIO_LPSR_14_PIT2_TRIGGER2 0x038 0x078 0x0 0x2 0x0 +#define IOMUXC_GPIO_LPSR_14_GPIO_MUX6_IO14 0x038 0x078 0x0 0x5 0x0 +#define IOMUXC_GPIO_LPSR_14_SAI4_RX_BCLK 0x038 0x078 0x0CC 0x7 0x1 +#define IOMUXC_GPIO_LPSR_14_LPSPI5_SOUT 0x038 0x078 0x0A0 0x8 0x1 +#define IOMUXC_GPIO_LPSR_14_GPIO12_IO14 0x038 0x078 0x0 0xA 0x0 + +#define IOMUXC_GPIO_LPSR_15_GPIO12_IO15 0x03C 0x07C 0x0 0xA 0x0 +#define IOMUXC_GPIO_LPSR_15_JTAG_MUX_TMS 0x03C 0x07C 0x0 0x0 0x0 +#define IOMUXC_GPIO_LPSR_15_MIC_BITSTREAM3 0x03C 0x07C 0x0C0 0x1 0x1 +#define IOMUXC_GPIO_LPSR_15_PIT2_TRIGGER3 0x03C 0x07C 0x0 0x2 0x0 +#define IOMUXC_GPIO_LPSR_15_GPIO_MUX6_IO15 0x03C 0x07C 0x0 0x5 0x0 +#define IOMUXC_GPIO_LPSR_15_SAI4_RX_SYNC 0x03C 0x07C 0x0D4 0x7 0x1 +#define IOMUXC_GPIO_LPSR_15_LPSPI5_SIN 0x03C 0x07C 0x09C 0x8 0x1 + +#define IOMUXC_WAKEUP_DIG_GPIO13_IO00 0x40C94000 0x40C94040 0x0 0x5 0x0 +#define IOMUXC_WAKEUP_DIG_NMI_GLUE_NMI 0x40C94000 0x40C94040 0x0C4 0x7 0x1 + +#define IOMUXC_PMIC_ON_REQ_DIG_SNVS_LP_PMIC_ON_REQ 0x40C94004 0x40C94044 0x0 0x0 0x0 +#define IOMUXC_PMIC_ON_REQ_DIG_GPIO13_IO01 0x40C94004 0x40C94044 0x0 0x5 0x0 + +#define IOMUXC_PMIC_STBY_REQ_DIG_CCM_PMIC_VSTBY_REQ 0x40C94008 0x40C94048 0x0 0x0 0x0 +#define IOMUXC_PMIC_STBY_REQ_DIG_GPIO13_IO02 0x40C94008 0x40C94048 0x0 0x5 0x0 + +#define IOMUXC_GPIO_SNVS_00_DIG_SNVS_TAMPER0 0x40C9400C 0x40C9404C 0x0 0x0 0x0 +#define IOMUXC_GPIO_SNVS_00_DIG_GPIO13_IO03 0x40C9400C 0x40C9404C 0x0 0x5 0x0 + +#define IOMUXC_GPIO_SNVS_01_DIG_SNVS_TAMPER1 0x40C94010 0x40C94050 0x0 0x0 0x0 +#define IOMUXC_GPIO_SNVS_01_DIG_GPIO13_IO04 0x40C94010 0x40C94050 0x0 0x5 0x0 + +#define IOMUXC_GPIO_SNVS_02_DIG_SNVS_TAMPER2 0x40C94014 0x40C94054 0x0 0x0 0x0 +#define IOMUXC_GPIO_SNVS_02_DIG_GPIO13_IO05 0x40C94014 0x40C94054 0x0 0x5 0x0 + +#define IOMUXC_GPIO_SNVS_03_DIG_SNVS_TAMPER3 0x40C94018 0x40C94058 0x0 0x0 0x0 +#define IOMUXC_GPIO_SNVS_03_DIG_GPIO13_IO06 0x40C94018 0x40C94058 0x0 0x5 0x0 + +#define IOMUXC_GPIO_SNVS_04_DIG_SNVS_TAMPER4 0x40C9401C 0x40C9405C 0x0 0x0 0x0 +#define IOMUXC_GPIO_SNVS_04_DIG_GPIO13_IO07 0x40C9401C 0x40C9405C 0x0 0x5 0x0 + +#define IOMUXC_GPIO_SNVS_05_DIG_SNVS_TAMPER5 0x40C94020 0x40C94060 0x0 0x0 0x0 +#define IOMUXC_GPIO_SNVS_05_DIG_GPIO13_IO08 0x40C94020 0x40C94060 0x0 0x5 0x0 + +#define IOMUXC_GPIO_SNVS_06_DIG_SNVS_TAMPER6 0x40C94024 0x40C94064 0x0 0x0 0x0 +#define IOMUXC_GPIO_SNVS_06_DIG_GPIO13_IO09 0x40C94024 0x40C94064 0x0 0x5 0x0 + +#define IOMUXC_GPIO_SNVS_07_DIG_SNVS_TAMPER7 0x40C94028 0x40C94068 0x0 0x0 0x0 +#define IOMUXC_GPIO_SNVS_07_DIG_GPIO13_IO10 0x40C94028 0x40C94068 0x0 0x5 0x0 + +#define IOMUXC_GPIO_SNVS_08_DIG_SNVS_TAMPER8 0x40C9402C 0x40C9406C 0x0 0x0 0x0 +#define IOMUXC_GPIO_SNVS_08_DIG_GPIO13_IO11 0x40C9402C 0x40C9406C 0x0 0x5 0x0 + +#define IOMUXC_GPIO_SNVS_09_DIG_SNVS_TAMPER9 0x40C94030 0x40C94070 0x0 0x0 0x0 +#define IOMUXC_GPIO_SNVS_09_DIG_GPIO13_IO12 0x40C94030 0x40C94070 0x0 0x5 0x0 + +#define IOMUXC_TEST_MODE_DIG 0x0 0x40C94034 0x0 0x0 0x0 + +#define IOMUXC_POR_B_DIG 0x0 0x40C94038 0x0 0x0 0x0 + +#define IOMUXC_ONOFF_DIG 0x0 0x40C9403C 0x0 0x0 0x0 + +#define IOMUXC_GPIO_EMC_B1_00_SEMC_DATA00 0x010 0x254 0x0 0x0 0x0 +#define IOMUXC_GPIO_EMC_B1_00_FLEXPWM4_PWM0_A 0x010 0x254 0x0 0x1 0x0 +#define IOMUXC_GPIO_EMC_B1_00_GPIO_MUX1_IO00 0x010 0x254 0x0 0x5 0x0 +#define IOMUXC_GPIO_EMC_B1_00_FLEXIO1_D00 0x010 0x254 0x0 0x8 0x0 +#define IOMUXC_GPIO_EMC_B1_00_GPIO7_IO00 0x010 0x254 0x0 0xA 0x0 + +#define IOMUXC_GPIO_EMC_B1_01_GPIO7_IO01 0x014 0x258 0x0 0xA 0x0 +#define IOMUXC_GPIO_EMC_B1_01_SEMC_DATA01 0x014 0x258 0x0 0x0 0x0 +#define IOMUXC_GPIO_EMC_B1_01_FLEXPWM4_PWM0_B 0x014 0x258 0x0 0x1 0x0 +#define IOMUXC_GPIO_EMC_B1_01_GPIO_MUX1_IO01 0x014 0x258 0x0 0x5 0x0 +#define IOMUXC_GPIO_EMC_B1_01_FLEXIO1_D01 0x014 0x258 0x0 0x8 0x0 + +#define IOMUXC_GPIO_EMC_B1_02_SEMC_DATA02 0x018 0x25C 0x0 0x0 0x0 +#define IOMUXC_GPIO_EMC_B1_02_FLEXPWM4_PWM1_A 0x018 0x25C 0x0 0x1 0x0 +#define IOMUXC_GPIO_EMC_B1_02_GPIO_MUX1_IO02 0x018 0x25C 0x0 0x5 0x0 +#define IOMUXC_GPIO_EMC_B1_02_FLEXIO1_D02 0x018 0x25C 0x0 0x8 0x0 +#define IOMUXC_GPIO_EMC_B1_02_GPIO7_IO02 0x018 0x25C 0x0 0xA 0x0 + +#define IOMUXC_GPIO_EMC_B1_03_SEMC_DATA03 0x01C 0x260 0x0 0x0 0x0 +#define IOMUXC_GPIO_EMC_B1_03_FLEXPWM4_PWM1_B 0x01C 0x260 0x0 0x1 0x0 +#define IOMUXC_GPIO_EMC_B1_03_GPIO_MUX1_IO03 0x01C 0x260 0x0 0x5 0x0 +#define IOMUXC_GPIO_EMC_B1_03_FLEXIO1_D03 0x01C 0x260 0x0 0x8 0x0 +#define IOMUXC_GPIO_EMC_B1_03_GPIO7_IO03 0x01C 0x260 0x0 0xA 0x0 + +#define IOMUXC_GPIO_EMC_B1_04_GPIO7_IO04 0x020 0x264 0x0 0xA 0x0 +#define IOMUXC_GPIO_EMC_B1_04_SEMC_DATA04 0x020 0x264 0x0 0x0 0x0 +#define IOMUXC_GPIO_EMC_B1_04_FLEXPWM4_PWM2_A 0x020 0x264 0x0 0x1 0x0 +#define IOMUXC_GPIO_EMC_B1_04_GPIO_MUX1_IO04 0x020 0x264 0x0 0x5 0x0 +#define IOMUXC_GPIO_EMC_B1_04_FLEXIO1_D04 0x020 0x264 0x0 0x8 0x0 + +#define IOMUXC_GPIO_EMC_B1_05_SEMC_DATA05 0x024 0x268 0x0 0x0 0x0 +#define IOMUXC_GPIO_EMC_B1_05_FLEXPWM4_PWM2_B 0x024 0x268 0x0 0x1 0x0 +#define IOMUXC_GPIO_EMC_B1_05_GPIO_MUX1_IO05 0x024 0x268 0x0 0x5 0x0 +#define IOMUXC_GPIO_EMC_B1_05_FLEXIO1_D05 0x024 0x268 0x0 0x8 0x0 +#define IOMUXC_GPIO_EMC_B1_05_GPIO7_IO05 0x024 0x268 0x0 0xA 0x0 + +#define IOMUXC_GPIO_EMC_B1_06_SEMC_DATA06 0x028 0x26C 0x0 0x0 0x0 +#define IOMUXC_GPIO_EMC_B1_06_FLEXPWM2_PWM0_A 0x028 0x26C 0x518 0x1 0x0 +#define IOMUXC_GPIO_EMC_B1_06_GPIO_MUX1_IO06 0x028 0x26C 0x0 0x5 0x0 +#define IOMUXC_GPIO_EMC_B1_06_FLEXIO1_D06 0x028 0x26C 0x0 0x8 0x0 +#define IOMUXC_GPIO_EMC_B1_06_GPIO7_IO06 0x028 0x26C 0x0 0xA 0x0 + +#define IOMUXC_GPIO_EMC_B1_07_GPIO7_IO07 0x02C 0x270 0x0 0xA 0x0 +#define IOMUXC_GPIO_EMC_B1_07_SEMC_DATA07 0x02C 0x270 0x0 0x0 0x0 +#define IOMUXC_GPIO_EMC_B1_07_FLEXPWM2_PWM0_B 0x02C 0x270 0x524 0x1 0x0 +#define IOMUXC_GPIO_EMC_B1_07_GPIO_MUX1_IO07 0x02C 0x270 0x0 0x5 0x0 +#define IOMUXC_GPIO_EMC_B1_07_FLEXIO1_D07 0x02C 0x270 0x0 0x8 0x0 + +#define IOMUXC_GPIO_EMC_B1_08_SEMC_DM00 0x030 0x274 0x0 0x0 0x0 +#define IOMUXC_GPIO_EMC_B1_08_FLEXPWM2_PWM1_A 0x030 0x274 0x51C 0x1 0x0 +#define IOMUXC_GPIO_EMC_B1_08_GPIO_MUX1_IO08 0x030 0x274 0x0 0x5 0x0 +#define IOMUXC_GPIO_EMC_B1_08_FLEXIO1_D08 0x030 0x274 0x0 0x8 0x0 +#define IOMUXC_GPIO_EMC_B1_08_GPIO7_IO08 0x030 0x274 0x0 0xA 0x0 + +#define IOMUXC_GPIO_EMC_B1_09_SEMC_ADDR00 0x034 0x278 0x0 0x0 0x0 +#define IOMUXC_GPIO_EMC_B1_09_FLEXPWM2_PWM1_B 0x034 0x278 0x528 0x1 0x0 +#define IOMUXC_GPIO_EMC_B1_09_GPT5_CAPTURE1 0x034 0x278 0x0 0x2 0x0 +#define IOMUXC_GPIO_EMC_B1_09_GPIO_MUX1_IO09 0x034 0x278 0x0 0x5 0x0 +#define IOMUXC_GPIO_EMC_B1_09_FLEXIO1_D09 0x034 0x278 0x0 0x8 0x0 +#define IOMUXC_GPIO_EMC_B1_09_GPIO7_IO09 0x034 0x278 0x0 0xA 0x0 + +#define IOMUXC_GPIO_EMC_B1_10_SEMC_ADDR01 0x038 0x27C 0x0 0x0 0x0 +#define IOMUXC_GPIO_EMC_B1_10_FLEXPWM2_PWM2_A 0x038 0x27C 0x520 0x1 0x0 +#define IOMUXC_GPIO_EMC_B1_10_GPT5_CAPTURE2 0x038 0x27C 0x0 0x2 0x0 +#define IOMUXC_GPIO_EMC_B1_10_GPIO_MUX1_IO10 0x038 0x27C 0x0 0x5 0x0 +#define IOMUXC_GPIO_EMC_B1_10_FLEXIO1_D10 0x038 0x27C 0x0 0x8 0x0 +#define IOMUXC_GPIO_EMC_B1_10_GPIO7_IO10 0x038 0x27C 0x0 0xA 0x0 + +#define IOMUXC_GPIO_EMC_B1_11_GPIO7_IO11 0x03C 0x280 0x0 0xA 0x0 +#define IOMUXC_GPIO_EMC_B1_11_SEMC_ADDR02 0x03C 0x280 0x0 0x0 0x0 +#define IOMUXC_GPIO_EMC_B1_11_FLEXPWM2_PWM2_B 0x03C 0x280 0x52C 0x1 0x0 +#define IOMUXC_GPIO_EMC_B1_11_GPT5_COMPARE1 0x03C 0x280 0x0 0x2 0x0 +#define IOMUXC_GPIO_EMC_B1_11_GPIO_MUX1_IO11 0x03C 0x280 0x0 0x5 0x0 +#define IOMUXC_GPIO_EMC_B1_11_FLEXIO1_D11 0x03C 0x280 0x0 0x8 0x0 + +#define IOMUXC_GPIO_EMC_B1_12_SEMC_ADDR03 0x040 0x284 0x0 0x0 0x0 +#define IOMUXC_GPIO_EMC_B1_12_XBAR1_INOUT04 0x040 0x284 0x0 0x1 0x0 +#define IOMUXC_GPIO_EMC_B1_12_GPT5_COMPARE2 0x040 0x284 0x0 0x2 0x0 +#define IOMUXC_GPIO_EMC_B1_12_GPIO_MUX1_IO12 0x040 0x284 0x0 0x5 0x0 +#define IOMUXC_GPIO_EMC_B1_12_FLEXIO1_D12 0x040 0x284 0x0 0x8 0x0 +#define IOMUXC_GPIO_EMC_B1_12_GPIO7_IO12 0x040 0x284 0x0 0xA 0x0 + +#define IOMUXC_GPIO_EMC_B1_13_SEMC_ADDR04 0x044 0x288 0x0 0x0 0x0 +#define IOMUXC_GPIO_EMC_B1_13_XBAR1_INOUT05 0x044 0x288 0x0 0x1 0x0 +#define IOMUXC_GPIO_EMC_B1_13_GPT5_COMPARE3 0x044 0x288 0x0 0x2 0x0 +#define IOMUXC_GPIO_EMC_B1_13_GPIO_MUX1_IO13 0x044 0x288 0x0 0x5 0x0 +#define IOMUXC_GPIO_EMC_B1_13_FLEXIO1_D13 0x044 0x288 0x0 0x8 0x0 +#define IOMUXC_GPIO_EMC_B1_13_GPIO7_IO13 0x044 0x288 0x0 0xA 0x0 + +#define IOMUXC_GPIO_EMC_B1_14_GPIO7_IO14 0x048 0x28C 0x0 0xA 0x0 +#define IOMUXC_GPIO_EMC_B1_14_SEMC_ADDR05 0x048 0x28C 0x0 0x0 0x0 +#define IOMUXC_GPIO_EMC_B1_14_XBAR1_INOUT06 0x048 0x28C 0x0 0x1 0x0 +#define IOMUXC_GPIO_EMC_B1_14_GPT5_CLK 0x048 0x28C 0x0 0x2 0x0 +#define IOMUXC_GPIO_EMC_B1_14_GPIO_MUX1_IO14 0x048 0x28C 0x0 0x5 0x0 +#define IOMUXC_GPIO_EMC_B1_14_FLEXIO1_D14 0x048 0x28C 0x0 0x8 0x0 + +#define IOMUXC_GPIO_EMC_B1_15_SEMC_ADDR06 0x04C 0x290 0x0 0x0 0x0 +#define IOMUXC_GPIO_EMC_B1_15_XBAR1_INOUT07 0x04C 0x290 0x0 0x1 0x0 +#define IOMUXC_GPIO_EMC_B1_15_GPIO_MUX1_IO15 0x04C 0x290 0x0 0x5 0x0 +#define IOMUXC_GPIO_EMC_B1_15_FLEXIO1_D15 0x04C 0x290 0x0 0x8 0x0 +#define IOMUXC_GPIO_EMC_B1_15_GPIO7_IO15 0x04C 0x290 0x0 0xA 0x0 + +#define IOMUXC_GPIO_EMC_B1_16_SEMC_ADDR07 0x050 0x294 0x0 0x0 0x0 +#define IOMUXC_GPIO_EMC_B1_16_XBAR1_INOUT08 0x050 0x294 0x0 0x1 0x0 +#define IOMUXC_GPIO_EMC_B1_16_GPIO_MUX1_IO16 0x050 0x294 0x0 0x5 0x0 +#define IOMUXC_GPIO_EMC_B1_16_FLEXIO1_D16 0x050 0x294 0x0 0x8 0x0 +#define IOMUXC_GPIO_EMC_B1_16_GPIO7_IO16 0x050 0x294 0x0 0xA 0x0 + +#define IOMUXC_GPIO_EMC_B1_17_GPIO7_IO17 0x054 0x298 0x0 0xA 0x0 +#define IOMUXC_GPIO_EMC_B1_17_SEMC_ADDR08 0x054 0x298 0x0 0x0 0x0 +#define IOMUXC_GPIO_EMC_B1_17_FLEXPWM4_PWM3_A 0x054 0x298 0x0 0x1 0x0 +#define IOMUXC_GPIO_EMC_B1_17_TMR1_TIMER0 0x054 0x298 0x63C 0x2 0x0 +#define IOMUXC_GPIO_EMC_B1_17_GPIO_MUX1_IO17 0x054 0x298 0x0 0x5 0x0 +#define IOMUXC_GPIO_EMC_B1_17_FLEXIO1_D17 0x054 0x298 0x0 0x8 0x0 + +#define IOMUXC_GPIO_EMC_B1_18_SEMC_ADDR09 0x058 0x29C 0x0 0x0 0x0 +#define IOMUXC_GPIO_EMC_B1_18_FLEXPWM4_PWM3_B 0x058 0x29C 0x0 0x1 0x0 +#define IOMUXC_GPIO_EMC_B1_18_TMR2_TIMER0 0x058 0x29C 0x648 0x2 0x0 +#define IOMUXC_GPIO_EMC_B1_18_GPIO_MUX1_IO18 0x058 0x29C 0x0 0x5 0x0 +#define IOMUXC_GPIO_EMC_B1_18_FLEXIO1_D18 0x058 0x29C 0x0 0x8 0x0 +#define IOMUXC_GPIO_EMC_B1_18_GPIO7_IO18 0x058 0x29C 0x0 0xA 0x0 + +#define IOMUXC_GPIO_EMC_B1_19_SEMC_ADDR11 0x05C 0x2A0 0x0 0x0 0x0 +#define IOMUXC_GPIO_EMC_B1_19_FLEXPWM2_PWM3_A 0x05C 0x2A0 0x0 0x1 0x0 +#define IOMUXC_GPIO_EMC_B1_19_TMR3_TIMER0 0x05C 0x2A0 0x654 0x2 0x0 +#define IOMUXC_GPIO_EMC_B1_19_GPIO_MUX1_IO19 0x05C 0x2A0 0x0 0x5 0x0 +#define IOMUXC_GPIO_EMC_B1_19_FLEXIO1_D19 0x05C 0x2A0 0x0 0x8 0x0 +#define IOMUXC_GPIO_EMC_B1_19_GPIO7_IO19 0x05C 0x2A0 0x0 0xA 0x0 + +#define IOMUXC_GPIO_EMC_B1_20_SEMC_ADDR12 0x060 0x2A4 0x0 0x0 0x0 +#define IOMUXC_GPIO_EMC_B1_20_FLEXPWM2_PWM3_B 0x060 0x2A4 0x0 0x1 0x0 +#define IOMUXC_GPIO_EMC_B1_20_TMR4_TIMER0 0x060 0x2A4 0x660 0x2 0x0 +#define IOMUXC_GPIO_EMC_B1_20_GPIO_MUX1_IO20 0x060 0x2A4 0x0 0x5 0x0 +#define IOMUXC_GPIO_EMC_B1_20_FLEXIO1_D20 0x060 0x2A4 0x0 0x8 0x0 +#define IOMUXC_GPIO_EMC_B1_20_GPIO7_IO20 0x060 0x2A4 0x0 0xA 0x0 + +#define IOMUXC_GPIO_EMC_B1_21_GPIO7_IO21 0x064 0x2A8 0x0 0xA 0x0 +#define IOMUXC_GPIO_EMC_B1_21_SEMC_BA0 0x064 0x2A8 0x0 0x0 0x0 +#define IOMUXC_GPIO_EMC_B1_21_FLEXPWM3_PWM3_A 0x064 0x2A8 0x53C 0x1 0x0 +#define IOMUXC_GPIO_EMC_B1_21_GPIO_MUX1_IO21 0x064 0x2A8 0x0 0x5 0x0 +#define IOMUXC_GPIO_EMC_B1_21_FLEXIO1_D21 0x064 0x2A8 0x0 0x8 0x0 + +#define IOMUXC_GPIO_EMC_B1_22_GPIO7_IO22 0x068 0x2AC 0x0 0xA 0x0 +#define IOMUXC_GPIO_EMC_B1_22_SEMC_BA1 0x068 0x2AC 0x0 0x0 0x0 +#define IOMUXC_GPIO_EMC_B1_22_FLEXPWM3_PWM3_B 0x068 0x2AC 0x54C 0x1 0x0 +#define IOMUXC_GPIO_EMC_B1_22_GPIO_MUX1_IO22 0x068 0x2AC 0x0 0x5 0x0 +#define IOMUXC_GPIO_EMC_B1_22_FLEXIO1_D22 0x068 0x2AC 0x0 0x8 0x0 + +#define IOMUXC_GPIO_EMC_B1_23_SEMC_ADDR10 0x06C 0x2B0 0x0 0x0 0x0 +#define IOMUXC_GPIO_EMC_B1_23_FLEXPWM1_PWM0_A 0x06C 0x2B0 0x500 0x1 0x0 +#define IOMUXC_GPIO_EMC_B1_23_GPIO_MUX1_IO23 0x06C 0x2B0 0x0 0x5 0x0 +#define IOMUXC_GPIO_EMC_B1_23_FLEXIO1_D23 0x06C 0x2B0 0x0 0x8 0x0 +#define IOMUXC_GPIO_EMC_B1_23_GPIO7_IO23 0x06C 0x2B0 0x0 0xA 0x0 + +#define IOMUXC_GPIO_EMC_B1_24_GPIO7_IO24 0x070 0x2B4 0x0 0xA 0x0 +#define IOMUXC_GPIO_EMC_B1_24_SEMC_CAS 0x070 0x2B4 0x0 0x0 0x0 +#define IOMUXC_GPIO_EMC_B1_24_FLEXPWM1_PWM0_B 0x070 0x2B4 0x50C 0x1 0x0 +#define IOMUXC_GPIO_EMC_B1_24_GPIO_MUX1_IO24 0x070 0x2B4 0x0 0x5 0x0 +#define IOMUXC_GPIO_EMC_B1_24_FLEXIO1_D24 0x070 0x2B4 0x0 0x8 0x0 + +#define IOMUXC_GPIO_EMC_B1_25_GPIO7_IO25 0x074 0x2B8 0x0 0xA 0x0 +#define IOMUXC_GPIO_EMC_B1_25_SEMC_RAS 0x074 0x2B8 0x0 0x0 0x0 +#define IOMUXC_GPIO_EMC_B1_25_FLEXPWM1_PWM1_A 0x074 0x2B8 0x504 0x1 0x0 +#define IOMUXC_GPIO_EMC_B1_25_GPIO_MUX1_IO25 0x074 0x2B8 0x0 0x5 0x0 +#define IOMUXC_GPIO_EMC_B1_25_FLEXIO1_D25 0x074 0x2B8 0x0 0x8 0x0 + +#define IOMUXC_GPIO_EMC_B1_26_SEMC_CLK 0x078 0x2BC 0x0 0x0 0x0 +#define IOMUXC_GPIO_EMC_B1_26_FLEXPWM1_PWM1_B 0x078 0x2BC 0x510 0x1 0x0 +#define IOMUXC_GPIO_EMC_B1_26_GPIO_MUX1_IO26 0x078 0x2BC 0x0 0x5 0x0 +#define IOMUXC_GPIO_EMC_B1_26_FLEXIO1_D26 0x078 0x2BC 0x0 0x8 0x0 +#define IOMUXC_GPIO_EMC_B1_26_GPIO7_IO26 0x078 0x2BC 0x0 0xA 0x0 + +#define IOMUXC_GPIO_EMC_B1_27_GPIO7_IO27 0x07C 0x2C0 0x0 0xA 0x0 +#define IOMUXC_GPIO_EMC_B1_27_SEMC_CKE 0x07C 0x2C0 0x0 0x0 0x0 +#define IOMUXC_GPIO_EMC_B1_27_FLEXPWM1_PWM2_A 0x07C 0x2C0 0x508 0x1 0x0 +#define IOMUXC_GPIO_EMC_B1_27_GPIO_MUX1_IO27 0x07C 0x2C0 0x0 0x5 0x0 +#define IOMUXC_GPIO_EMC_B1_27_FLEXIO1_D27 0x07C 0x2C0 0x0 0x8 0x0 + +#define IOMUXC_GPIO_EMC_B1_28_GPIO7_IO28 0x080 0x2C4 0x0 0xA 0x0 +#define IOMUXC_GPIO_EMC_B1_28_SEMC_WE 0x080 0x2C4 0x0 0x0 0x0 +#define IOMUXC_GPIO_EMC_B1_28_FLEXPWM1_PWM2_B 0x080 0x2C4 0x514 0x1 0x0 +#define IOMUXC_GPIO_EMC_B1_28_GPIO_MUX1_IO28 0x080 0x2C4 0x0 0x5 0x0 +#define IOMUXC_GPIO_EMC_B1_28_FLEXIO1_D28 0x080 0x2C4 0x0 0x8 0x0 + +#define IOMUXC_GPIO_EMC_B1_29_SEMC_CS0 0x084 0x2C8 0x0 0x0 0x0 +#define IOMUXC_GPIO_EMC_B1_29_FLEXPWM3_PWM0_A 0x084 0x2C8 0x530 0x1 0x0 +#define IOMUXC_GPIO_EMC_B1_29_GPIO_MUX1_IO29 0x084 0x2C8 0x0 0x5 0x0 +#define IOMUXC_GPIO_EMC_B1_29_FLEXIO1_D29 0x084 0x2C8 0x0 0x8 0x0 +#define IOMUXC_GPIO_EMC_B1_29_GPIO7_IO29 0x084 0x2C8 0x0 0xA 0x0 + +#define IOMUXC_GPIO_EMC_B1_30_SEMC_DATA08 0x088 0x2CC 0x0 0x0 0x0 +#define IOMUXC_GPIO_EMC_B1_30_FLEXPWM3_PWM0_B 0x088 0x2CC 0x540 0x1 0x0 +#define IOMUXC_GPIO_EMC_B1_30_GPIO_MUX1_IO30 0x088 0x2CC 0x0 0x5 0x0 +#define IOMUXC_GPIO_EMC_B1_30_FLEXIO1_D30 0x088 0x2CC 0x0 0x8 0x0 +#define IOMUXC_GPIO_EMC_B1_30_GPIO7_IO30 0x088 0x2CC 0x0 0xA 0x0 + +#define IOMUXC_GPIO_EMC_B1_31_GPIO7_IO31 0x08C 0x2D0 0x0 0xA 0x0 +#define IOMUXC_GPIO_EMC_B1_31_SEMC_DATA09 0x08C 0x2D0 0x0 0x0 0x0 +#define IOMUXC_GPIO_EMC_B1_31_FLEXPWM3_PWM1_A 0x08C 0x2D0 0x534 0x1 0x0 +#define IOMUXC_GPIO_EMC_B1_31_GPIO_MUX1_IO31 0x08C 0x2D0 0x0 0x5 0x0 +#define IOMUXC_GPIO_EMC_B1_31_FLEXIO1_D31 0x08C 0x2D0 0x0 0x8 0x0 + +#define IOMUXC_GPIO_EMC_B1_32_GPIO8_IO00 0x090 0x2D4 0x0 0xA 0x0 +#define IOMUXC_GPIO_EMC_B1_32_SEMC_DATA10 0x090 0x2D4 0x0 0x0 0x0 +#define IOMUXC_GPIO_EMC_B1_32_FLEXPWM3_PWM1_B 0x090 0x2D4 0x544 0x1 0x0 +#define IOMUXC_GPIO_EMC_B1_32_GPIO_MUX2_IO00 0x090 0x2D4 0x0 0x5 0x0 + +#define IOMUXC_GPIO_EMC_B1_33_SEMC_DATA11 0x094 0x2D8 0x0 0x0 0x0 +#define IOMUXC_GPIO_EMC_B1_33_FLEXPWM3_PWM2_A 0x094 0x2D8 0x538 0x1 0x0 +#define IOMUXC_GPIO_EMC_B1_33_GPIO_MUX2_IO01 0x094 0x2D8 0x0 0x5 0x0 +#define IOMUXC_GPIO_EMC_B1_33_GPIO8_IO01 0x094 0x2D8 0x0 0xA 0x0 + +#define IOMUXC_GPIO_EMC_B1_34_GPIO8_IO02 0x098 0x2DC 0x0 0xA 0x0 +#define IOMUXC_GPIO_EMC_B1_34_SEMC_DATA12 0x098 0x2DC 0x0 0x0 0x0 +#define IOMUXC_GPIO_EMC_B1_34_FLEXPWM3_PWM2_B 0x098 0x2DC 0x548 0x1 0x0 +#define IOMUXC_GPIO_EMC_B1_34_GPIO_MUX2_IO02 0x098 0x2DC 0x0 0x5 0x0 + +#define IOMUXC_GPIO_EMC_B1_35_GPIO8_IO03 0x09C 0x2E0 0x0 0xA 0x0 +#define IOMUXC_GPIO_EMC_B1_35_SEMC_DATA13 0x09C 0x2E0 0x0 0x0 0x0 +#define IOMUXC_GPIO_EMC_B1_35_XBAR1_INOUT09 0x09C 0x2E0 0x0 0x1 0x0 +#define IOMUXC_GPIO_EMC_B1_35_GPIO_MUX2_IO03 0x09C 0x2E0 0x0 0x5 0x0 + +#define IOMUXC_GPIO_EMC_B1_36_SEMC_DATA14 0x0A0 0x2E4 0x0 0x0 0x0 +#define IOMUXC_GPIO_EMC_B1_36_XBAR1_INOUT10 0x0A0 0x2E4 0x0 0x1 0x0 +#define IOMUXC_GPIO_EMC_B1_36_GPIO_MUX2_IO04 0x0A0 0x2E4 0x0 0x5 0x0 +#define IOMUXC_GPIO_EMC_B1_36_GPIO8_IO04 0x0A0 0x2E4 0x0 0xA 0x0 + +#define IOMUXC_GPIO_EMC_B1_37_GPIO8_IO05 0x0A4 0x2E8 0x0 0xA 0x0 +#define IOMUXC_GPIO_EMC_B1_37_SEMC_DATA15 0x0A4 0x2E8 0x0 0x0 0x0 +#define IOMUXC_GPIO_EMC_B1_37_XBAR1_INOUT11 0x0A4 0x2E8 0x0 0x1 0x0 +#define IOMUXC_GPIO_EMC_B1_37_GPIO_MUX2_IO05 0x0A4 0x2E8 0x0 0x5 0x0 + +#define IOMUXC_GPIO_EMC_B1_38_GPIO8_IO06 0x0A8 0x2EC 0x0 0xA 0x0 +#define IOMUXC_GPIO_EMC_B1_38_SEMC_DM01 0x0A8 0x2EC 0x0 0x0 0x0 +#define IOMUXC_GPIO_EMC_B1_38_FLEXPWM1_PWM3_A 0x0A8 0x2EC 0x0 0x1 0x0 +#define IOMUXC_GPIO_EMC_B1_38_TMR1_TIMER1 0x0A8 0x2EC 0x640 0x2 0x0 +#define IOMUXC_GPIO_EMC_B1_38_GPIO_MUX2_IO06 0x0A8 0x2EC 0x0 0x5 0x0 + +#define IOMUXC_GPIO_EMC_B1_39_SEMC_DQS 0x0AC 0x2F0 0x0 0x0 0x0 +#define IOMUXC_GPIO_EMC_B1_39_FLEXPWM1_PWM3_B 0x0AC 0x2F0 0x0 0x1 0x0 +#define IOMUXC_GPIO_EMC_B1_39_TMR2_TIMER1 0x0AC 0x2F0 0x64C 0x2 0x0 +#define IOMUXC_GPIO_EMC_B1_39_GPIO_MUX2_IO07 0x0AC 0x2F0 0x0 0x5 0x0 +#define IOMUXC_GPIO_EMC_B1_39_GPIO8_IO07 0x0AC 0x2F0 0x0 0xA 0x0 + +#define IOMUXC_GPIO_EMC_B1_40_SEMC_RDY 0x0B0 0x2F4 0x0 0x0 0x0 +#define IOMUXC_GPIO_EMC_B1_40_XBAR1_INOUT12 0x0B0 0x2F4 0x0 0x1 0x0 +#define IOMUXC_GPIO_EMC_B1_40_MQS_RIGHT 0x0B0 0x2F4 0x0 0x2 0x0 +#define IOMUXC_GPIO_EMC_B1_40_LPUART6_TXD 0x0B0 0x2F4 0x0 0x3 0x0 +#define IOMUXC_GPIO_EMC_B1_40_GPIO_MUX2_IO08 0x0B0 0x2F4 0x0 0x5 0x0 +#define IOMUXC_GPIO_EMC_B1_40_ENET_1G_MDC 0x0B0 0x2F4 0x0 0x7 0x0 +#define IOMUXC_GPIO_EMC_B1_40_CCM_CLKO1 0x0B0 0x2F4 0x0 0x9 0x0 +#define IOMUXC_GPIO_EMC_B1_40_GPIO8_IO08 0x0B0 0x2F4 0x0 0xA 0x0 + +#define IOMUXC_GPIO_EMC_B1_41_GPIO8_IO09 0x0B4 0x2F8 0x0 0xA 0x0 +#define IOMUXC_GPIO_EMC_B1_41_SEMC_CSX00 0x0B4 0x2F8 0x0 0x0 0x0 +#define IOMUXC_GPIO_EMC_B1_41_XBAR1_INOUT13 0x0B4 0x2F8 0x0 0x1 0x0 +#define IOMUXC_GPIO_EMC_B1_41_MQS_LEFT 0x0B4 0x2F8 0x0 0x2 0x0 +#define IOMUXC_GPIO_EMC_B1_41_LPUART6_RXD 0x0B4 0x2F8 0x0 0x3 0x0 +#define IOMUXC_GPIO_EMC_B1_41_FLEXSPI2_B_DATA07 0x0B4 0x2F8 0x0 0x4 0x0 +#define IOMUXC_GPIO_EMC_B1_41_GPIO_MUX2_IO09 0x0B4 0x2F8 0x0 0x5 0x0 +#define IOMUXC_GPIO_EMC_B1_41_ENET_1G_MDIO 0x0B4 0x2F8 0x4C8 0x7 0x0 +#define IOMUXC_GPIO_EMC_B1_41_CCM_CLKO2 0x0B4 0x2F8 0x0 0x9 0x0 + +#define IOMUXC_GPIO_EMC_B2_00_SEMC_DATA16 0x0B8 0x2FC 0x0 0x0 0x0 +#define IOMUXC_GPIO_EMC_B2_00_CCM_ENET_REF_CLK_25M 0x0B8 0x2FC 0x0 0x1 0x0 +#define IOMUXC_GPIO_EMC_B2_00_TMR3_TIMER1 0x0B8 0x2FC 0x658 0x2 0x0 +#define IOMUXC_GPIO_EMC_B2_00_LPUART6_CTS_B 0x0B8 0x2FC 0x0 0x3 0x0 +#define IOMUXC_GPIO_EMC_B2_00_FLEXSPI2_B_DATA06 0x0B8 0x2FC 0x0 0x4 0x0 +#define IOMUXC_GPIO_EMC_B2_00_GPIO_MUX2_IO10 0x0B8 0x2FC 0x0 0x5 0x0 +#define IOMUXC_GPIO_EMC_B2_00_XBAR1_INOUT20 0x0B8 0x2FC 0x6D8 0x6 0x0 +#define IOMUXC_GPIO_EMC_B2_00_ENET_QOS_1588_EVENT1_OUT 0x0B8 0x2FC 0x0 0x7 0x0 +#define IOMUXC_GPIO_EMC_B2_00_LPSPI1_SCK 0x0B8 0x2FC 0x5D0 0x8 0x0 +#define IOMUXC_GPIO_EMC_B2_00_LPI2C2_SCL 0x0B8 0x2FC 0x5B4 0x9 0x0 +#define IOMUXC_GPIO_EMC_B2_00_GPIO8_IO10 0x0B8 0x2FC 0x0 0xA 0x0 +#define IOMUXC_GPIO_EMC_B2_00_FLEXPWM3_PWM0_A 0x0B8 0x2FC 0x530 0xB 0x1 + +#define IOMUXC_GPIO_EMC_B2_01_SEMC_DATA17 0x0BC 0x300 0x0 0x0 0x0 +#define IOMUXC_GPIO_EMC_B2_01_USDHC2_CD_B 0x0BC 0x300 0x6D0 0x1 0x0 +#define IOMUXC_GPIO_EMC_B2_01_TMR4_TIMER1 0x0BC 0x300 0x664 0x2 0x0 +#define IOMUXC_GPIO_EMC_B2_01_LPUART6_RTS_B 0x0BC 0x300 0x0 0x3 0x0 +#define IOMUXC_GPIO_EMC_B2_01_FLEXSPI2_B_DATA05 0x0BC 0x300 0x0 0x4 0x0 +#define IOMUXC_GPIO_EMC_B2_01_GPIO_MUX2_IO11 0x0BC 0x300 0x0 0x5 0x0 +#define IOMUXC_GPIO_EMC_B2_01_XBAR1_INOUT21 0x0BC 0x300 0x6DC 0x6 0x0 +#define IOMUXC_GPIO_EMC_B2_01_ENET_QOS_1588_EVENT1_IN 0x0BC 0x300 0x0 0x7 0x0 +#define IOMUXC_GPIO_EMC_B2_01_LPSPI1_PCS0 0x0BC 0x300 0x5CC 0x8 0x0 +#define IOMUXC_GPIO_EMC_B2_01_LPI2C2_SDA 0x0BC 0x300 0x5B8 0x9 0x0 +#define IOMUXC_GPIO_EMC_B2_01_GPIO8_IO11 0x0BC 0x300 0x0 0xA 0x0 +#define IOMUXC_GPIO_EMC_B2_01_FLEXPWM3_PWM0_B 0x0BC 0x300 0x540 0xB 0x1 + +#define IOMUXC_GPIO_EMC_B2_02_SEMC_DATA18 0x0C0 0x304 0x0 0x0 0x0 +#define IOMUXC_GPIO_EMC_B2_02_USDHC2_WP 0x0C0 0x304 0x6D4 0x1 0x0 +#define IOMUXC_GPIO_EMC_B2_02_VIDEO_MUX_CSI_DATA23 0x0C0 0x304 0x0 0x3 0x0 +#define IOMUXC_GPIO_EMC_B2_02_FLEXSPI2_B_DATA04 0x0C0 0x304 0x0 0x4 0x0 +#define IOMUXC_GPIO_EMC_B2_02_GPIO_MUX2_IO12 0x0C0 0x304 0x0 0x5 0x0 +#define IOMUXC_GPIO_EMC_B2_02_XBAR1_INOUT22 0x0C0 0x304 0x6E0 0x6 0x0 +#define IOMUXC_GPIO_EMC_B2_02_ENET_QOS_1588_EVENT1_AUX_IN 0x0C0 0x304 0x0 0x7 0x0 +#define IOMUXC_GPIO_EMC_B2_02_LPSPI1_SOUT 0x0C0 0x304 0x5D8 0x8 0x0 +#define IOMUXC_GPIO_EMC_B2_02_GPIO8_IO12 0x0C0 0x304 0x0 0xA 0x0 +#define IOMUXC_GPIO_EMC_B2_02_FLEXPWM3_PWM1_A 0x0C0 0x304 0x534 0xB 0x1 + +#define IOMUXC_GPIO_EMC_B2_03_SEMC_DATA19 0x0C4 0x308 0x0 0x0 0x0 +#define IOMUXC_GPIO_EMC_B2_03_USDHC2_VSELECT 0x0C4 0x308 0x0 0x1 0x0 +#define IOMUXC_GPIO_EMC_B2_03_VIDEO_MUX_CSI_DATA22 0x0C4 0x308 0x0 0x3 0x0 +#define IOMUXC_GPIO_EMC_B2_03_FLEXSPI2_B_DATA03 0x0C4 0x308 0x0 0x4 0x0 +#define IOMUXC_GPIO_EMC_B2_03_GPIO_MUX2_IO13 0x0C4 0x308 0x0 0x5 0x0 +#define IOMUXC_GPIO_EMC_B2_03_XBAR1_INOUT23 0x0C4 0x308 0x6E4 0x6 0x0 +#define IOMUXC_GPIO_EMC_B2_03_ENET_1G_TX_DATA03 0x0C4 0x308 0x0 0x7 0x0 +#define IOMUXC_GPIO_EMC_B2_03_LPSPI1_SIN 0x0C4 0x308 0x5D4 0x8 0x0 +#define IOMUXC_GPIO_EMC_B2_03_GPIO8_IO13 0x0C4 0x308 0x0 0xA 0x0 +#define IOMUXC_GPIO_EMC_B2_03_FLEXPWM3_PWM1_B 0x0C4 0x308 0x544 0xB 0x1 + +#define IOMUXC_GPIO_EMC_B2_04_SEMC_DATA20 0x0C8 0x30C 0x0 0x0 0x0 +#define IOMUXC_GPIO_EMC_B2_04_USDHC2_RESET_B 0x0C8 0x30C 0x0 0x1 0x0 +#define IOMUXC_GPIO_EMC_B2_04_SAI2_MCLK 0x0C8 0x30C 0x0 0x2 0x0 +#define IOMUXC_GPIO_EMC_B2_04_VIDEO_MUX_CSI_DATA21 0x0C8 0x30C 0x0 0x3 0x0 +#define IOMUXC_GPIO_EMC_B2_04_FLEXSPI2_B_DATA02 0x0C8 0x30C 0x0 0x4 0x0 +#define IOMUXC_GPIO_EMC_B2_04_GPIO_MUX2_IO14 0x0C8 0x30C 0x0 0x5 0x0 +#define IOMUXC_GPIO_EMC_B2_04_XBAR1_INOUT24 0x0C8 0x30C 0x6E8 0x6 0x0 +#define IOMUXC_GPIO_EMC_B2_04_ENET_1G_TX_DATA02 0x0C8 0x30C 0x0 0x7 0x0 +#define IOMUXC_GPIO_EMC_B2_04_LPSPI3_SCK 0x0C8 0x30C 0x600 0x8 0x0 +#define IOMUXC_GPIO_EMC_B2_04_GPIO8_IO14 0x0C8 0x30C 0x0 0xA 0x0 +#define IOMUXC_GPIO_EMC_B2_04_FLEXPWM3_PWM2_A 0x0C8 0x30C 0x538 0xB 0x1 + +#define IOMUXC_GPIO_EMC_B2_05_SEMC_DATA21 0x0CC 0x310 0x0 0x0 0x0 +#define IOMUXC_GPIO_EMC_B2_05_GPT3_CLK 0x0CC 0x310 0x598 0x1 0x0 +#define IOMUXC_GPIO_EMC_B2_05_SAI2_RX_SYNC 0x0CC 0x310 0x0 0x2 0x0 +#define IOMUXC_GPIO_EMC_B2_05_VIDEO_MUX_CSI_DATA20 0x0CC 0x310 0x0 0x3 0x0 +#define IOMUXC_GPIO_EMC_B2_05_FLEXSPI2_B_DATA01 0x0CC 0x310 0x0 0x4 0x0 +#define IOMUXC_GPIO_EMC_B2_05_GPIO_MUX2_IO15 0x0CC 0x310 0x0 0x5 0x0 +#define IOMUXC_GPIO_EMC_B2_05_XBAR1_INOUT25 0x0CC 0x310 0x6EC 0x6 0x0 +#define IOMUXC_GPIO_EMC_B2_05_ENET_1G_RX_CLK 0x0CC 0x310 0x4CC 0x7 0x0 +#define IOMUXC_GPIO_EMC_B2_05_LPSPI3_PCS0 0x0CC 0x310 0x5F0 0x8 0x0 +#define IOMUXC_GPIO_EMC_B2_05_PIT1_TRIGGER0 0x0CC 0x310 0x0 0x9 0x0 +#define IOMUXC_GPIO_EMC_B2_05_GPIO8_IO15 0x0CC 0x310 0x0 0xA 0x0 +#define IOMUXC_GPIO_EMC_B2_05_FLEXPWM3_PWM2_B 0x0CC 0x310 0x548 0xB 0x1 + +#define IOMUXC_GPIO_EMC_B2_06_SEMC_DATA22 0x0D0 0x314 0x0 0x0 0x0 +#define IOMUXC_GPIO_EMC_B2_06_GPT3_CAPTURE1 0x0D0 0x314 0x590 0x1 0x0 +#define IOMUXC_GPIO_EMC_B2_06_GPIO8_IO16 0x0D0 0x314 0x0 0xA 0x0 +#define IOMUXC_GPIO_EMC_B2_06_SAI2_RX_BCLK 0x0D0 0x314 0x0 0x2 0x0 +#define IOMUXC_GPIO_EMC_B2_06_FLEXPWM3_PWM3_A 0x0D0 0x314 0x53C 0xB 0x1 +#define IOMUXC_GPIO_EMC_B2_06_VIDEO_MUX_CSI_DATA19 0x0D0 0x314 0x0 0x3 0x0 +#define IOMUXC_GPIO_EMC_B2_06_FLEXSPI2_B_DATA00 0x0D0 0x314 0x0 0x4 0x0 +#define IOMUXC_GPIO_EMC_B2_06_GPIO_MUX2_IO16 0x0D0 0x314 0x0 0x5 0x0 +#define IOMUXC_GPIO_EMC_B2_06_XBAR1_INOUT26 0x0D0 0x314 0x6F0 0x6 0x0 +#define IOMUXC_GPIO_EMC_B2_06_ENET_1G_TX_ER 0x0D0 0x314 0x0 0x7 0x0 +#define IOMUXC_GPIO_EMC_B2_06_LPSPI3_SOUT 0x0D0 0x314 0x608 0x8 0x0 +#define IOMUXC_GPIO_EMC_B2_06_PIT1_TRIGGER1 0x0D0 0x314 0x0 0x9 0x0 + +#define IOMUXC_GPIO_EMC_B2_07_SEMC_DATA23 0x0D4 0x318 0x0 0x0 0x0 +#define IOMUXC_GPIO_EMC_B2_07_GPT3_CAPTURE2 0x0D4 0x318 0x594 0x1 0x0 +#define IOMUXC_GPIO_EMC_B2_07_SAI2_RX_DATA 0x0D4 0x318 0x0 0x2 0x0 +#define IOMUXC_GPIO_EMC_B2_07_VIDEO_MUX_CSI_DATA18 0x0D4 0x318 0x0 0x3 0x0 +#define IOMUXC_GPIO_EMC_B2_07_FLEXSPI2_B_DQS 0x0D4 0x318 0x0 0x4 0x0 +#define IOMUXC_GPIO_EMC_B2_07_GPIO_MUX2_IO17 0x0D4 0x318 0x0 0x5 0x0 +#define IOMUXC_GPIO_EMC_B2_07_XBAR1_INOUT27 0x0D4 0x318 0x6F4 0x6 0x0 +#define IOMUXC_GPIO_EMC_B2_07_ENET_1G_RX_DATA03 0x0D4 0x318 0x4DC 0x7 0x0 +#define IOMUXC_GPIO_EMC_B2_07_LPSPI3_SIN 0x0D4 0x318 0x604 0x8 0x0 +#define IOMUXC_GPIO_EMC_B2_07_PIT1_TRIGGER2 0x0D4 0x318 0x0 0x9 0x0 +#define IOMUXC_GPIO_EMC_B2_07_GPIO8_IO17 0x0D4 0x318 0x0 0xA 0x0 +#define IOMUXC_GPIO_EMC_B2_07_FLEXPWM3_PWM3_B 0x0D4 0x318 0x54C 0xB 0x1 + +#define IOMUXC_GPIO_EMC_B2_08_SEMC_DM02 0x0D8 0x31C 0x0 0x0 0x0 +#define IOMUXC_GPIO_EMC_B2_08_GPT3_COMPARE1 0x0D8 0x31C 0x0 0x1 0x0 +#define IOMUXC_GPIO_EMC_B2_08_SAI2_TX_DATA 0x0D8 0x31C 0x0 0x2 0x0 +#define IOMUXC_GPIO_EMC_B2_08_VIDEO_MUX_CSI_DATA17 0x0D8 0x31C 0x0 0x3 0x0 +#define IOMUXC_GPIO_EMC_B2_08_FLEXSPI2_B_SS0_B 0x0D8 0x31C 0x0 0x4 0x0 +#define IOMUXC_GPIO_EMC_B2_08_GPIO_MUX2_IO18 0x0D8 0x31C 0x0 0x5 0x0 +#define IOMUXC_GPIO_EMC_B2_08_XBAR1_INOUT28 0x0D8 0x31C 0x6F8 0x6 0x0 +#define IOMUXC_GPIO_EMC_B2_08_ENET_1G_RX_DATA02 0x0D8 0x31C 0x4D8 0x7 0x0 +#define IOMUXC_GPIO_EMC_B2_08_LPSPI3_PCS1 0x0D8 0x31C 0x5F4 0x8 0x0 +#define IOMUXC_GPIO_EMC_B2_08_PIT1_TRIGGER3 0x0D8 0x31C 0x0 0x9 0x0 +#define IOMUXC_GPIO_EMC_B2_08_GPIO8_IO18 0x0D8 0x31C 0x0 0xA 0x0 + +#define IOMUXC_GPIO_EMC_B2_09_GPIO8_IO19 0x0DC 0x320 0x0 0xA 0x0 +#define IOMUXC_GPIO_EMC_B2_09_SEMC_DATA24 0x0DC 0x320 0x0 0x0 0x0 +#define IOMUXC_GPIO_EMC_B2_09_GPT3_COMPARE2 0x0DC 0x320 0x0 0x1 0x0 +#define IOMUXC_GPIO_EMC_B2_09_SAI2_TX_BCLK 0x0DC 0x320 0x0 0x2 0x0 +#define IOMUXC_GPIO_EMC_B2_09_VIDEO_MUX_CSI_DATA16 0x0DC 0x320 0x0 0x3 0x0 +#define IOMUXC_GPIO_EMC_B2_09_FLEXSPI2_B_SCLK 0x0DC 0x320 0x0 0x4 0x0 +#define IOMUXC_GPIO_EMC_B2_09_GPIO_MUX2_IO19 0x0DC 0x320 0x0 0x5 0x0 +#define IOMUXC_GPIO_EMC_B2_09_XBAR1_INOUT29 0x0DC 0x320 0x6FC 0x6 0x0 +#define IOMUXC_GPIO_EMC_B2_09_ENET_1G_CRS 0x0DC 0x320 0x0 0x7 0x0 +#define IOMUXC_GPIO_EMC_B2_09_LPSPI3_PCS2 0x0DC 0x320 0x5F8 0x8 0x0 +#define IOMUXC_GPIO_EMC_B2_09_TMR1_TIMER0 0x0DC 0x320 0x63C 0x9 0x1 + +#define IOMUXC_GPIO_EMC_B2_10_GPIO8_IO20 0x0E0 0x324 0x0 0xA 0x0 +#define IOMUXC_GPIO_EMC_B2_10_SEMC_DATA25 0x0E0 0x324 0x0 0x0 0x0 +#define IOMUXC_GPIO_EMC_B2_10_GPT3_COMPARE3 0x0E0 0x324 0x0 0x1 0x0 +#define IOMUXC_GPIO_EMC_B2_10_SAI2_TX_SYNC 0x0E0 0x324 0x0 0x2 0x0 +#define IOMUXC_GPIO_EMC_B2_10_VIDEO_MUX_CSI_FIELD 0x0E0 0x324 0x0 0x3 0x0 +#define IOMUXC_GPIO_EMC_B2_10_FLEXSPI2_A_SCLK 0x0E0 0x324 0x58C 0x4 0x0 +#define IOMUXC_GPIO_EMC_B2_10_GPIO_MUX2_IO20 0x0E0 0x324 0x0 0x5 0x0 +#define IOMUXC_GPIO_EMC_B2_10_XBAR1_INOUT30 0x0E0 0x324 0x700 0x6 0x0 +#define IOMUXC_GPIO_EMC_B2_10_ENET_1G_COL 0x0E0 0x324 0x0 0x7 0x0 +#define IOMUXC_GPIO_EMC_B2_10_LPSPI3_PCS3 0x0E0 0x324 0x5FC 0x8 0x0 +#define IOMUXC_GPIO_EMC_B2_10_TMR1_TIMER1 0x0E0 0x324 0x640 0x9 0x1 + +#define IOMUXC_GPIO_EMC_B2_11_SEMC_DATA26 0x0E4 0x328 0x0 0x0 0x0 +#define IOMUXC_GPIO_EMC_B2_11_SPDIF_IN 0x0E4 0x328 0x6B4 0x1 0x0 +#define IOMUXC_GPIO_EMC_B2_11_ENET_1G_TX_DATA00 0x0E4 0x328 0x0 0x2 0x0 +#define IOMUXC_GPIO_EMC_B2_11_SAI3_RX_SYNC 0x0E4 0x328 0x0 0x3 0x0 +#define IOMUXC_GPIO_EMC_B2_11_FLEXSPI2_A_SS0_B 0x0E4 0x328 0x0 0x4 0x0 +#define IOMUXC_GPIO_EMC_B2_11_GPIO_MUX2_IO21 0x0E4 0x328 0x0 0x5 0x0 +#define IOMUXC_GPIO_EMC_B2_11_XBAR1_INOUT31 0x0E4 0x328 0x704 0x6 0x0 +#define IOMUXC_GPIO_EMC_B2_11_EMVSIM1_IO 0x0E4 0x328 0x69C 0x8 0x0 +#define IOMUXC_GPIO_EMC_B2_11_TMR1_TIMER2 0x0E4 0x328 0x644 0x9 0x0 +#define IOMUXC_GPIO_EMC_B2_11_GPIO8_IO21 0x0E4 0x328 0x0 0xA 0x0 + +#define IOMUXC_GPIO_EMC_B2_12_SEMC_DATA27 0x0E8 0x32C 0x0 0x0 0x0 +#define IOMUXC_GPIO_EMC_B2_12_SPDIF_OUT 0x0E8 0x32C 0x0 0x1 0x0 +#define IOMUXC_GPIO_EMC_B2_12_ENET_1G_TX_DATA01 0x0E8 0x32C 0x0 0x2 0x0 +#define IOMUXC_GPIO_EMC_B2_12_SAI3_RX_BCLK 0x0E8 0x32C 0x0 0x3 0x0 +#define IOMUXC_GPIO_EMC_B2_12_FLEXSPI2_A_DQS 0x0E8 0x32C 0x0 0x4 0x0 +#define IOMUXC_GPIO_EMC_B2_12_GPIO_MUX2_IO22 0x0E8 0x32C 0x0 0x5 0x0 +#define IOMUXC_GPIO_EMC_B2_12_XBAR1_INOUT32 0x0E8 0x32C 0x708 0x6 0x0 +#define IOMUXC_GPIO_EMC_B2_12_EMVSIM1_CLK 0x0E8 0x32C 0x0 0x8 0x0 +#define IOMUXC_GPIO_EMC_B2_12_TMR1_TIMER3 0x0E8 0x32C 0x0 0x9 0x0 +#define IOMUXC_GPIO_EMC_B2_12_GPIO8_IO22 0x0E8 0x32C 0x0 0xA 0x0 + +#define IOMUXC_GPIO_EMC_B2_13_GPIO8_IO23 0x0EC 0x330 0x0 0xA 0x0 +#define IOMUXC_GPIO_EMC_B2_13_SEMC_DATA28 0x0EC 0x330 0x0 0x0 0x0 +#define IOMUXC_GPIO_EMC_B2_13_ENET_1G_TX_EN 0x0EC 0x330 0x0 0x2 0x0 +#define IOMUXC_GPIO_EMC_B2_13_SAI3_RX_DATA 0x0EC 0x330 0x0 0x3 0x0 +#define IOMUXC_GPIO_EMC_B2_13_FLEXSPI2_A_DATA00 0x0EC 0x330 0x57C 0x4 0x0 +#define IOMUXC_GPIO_EMC_B2_13_GPIO_MUX2_IO23 0x0EC 0x330 0x0 0x5 0x0 +#define IOMUXC_GPIO_EMC_B2_13_XBAR1_INOUT33 0x0EC 0x330 0x70C 0x6 0x0 +#define IOMUXC_GPIO_EMC_B2_13_EMVSIM1_RST 0x0EC 0x330 0x0 0x8 0x0 +#define IOMUXC_GPIO_EMC_B2_13_TMR2_TIMER0 0x0EC 0x330 0x648 0x9 0x1 + +#define IOMUXC_GPIO_EMC_B2_14_SEMC_DATA29 0x0F0 0x334 0x0 0x0 0x0 +#define IOMUXC_GPIO_EMC_B2_14_ENET_1G_TX_CLK_IO 0x0F0 0x334 0x4E8 0x2 0x0 +#define IOMUXC_GPIO_EMC_B2_14_SAI3_TX_DATA 0x0F0 0x334 0x0 0x3 0x0 +#define IOMUXC_GPIO_EMC_B2_14_FLEXSPI2_A_DATA01 0x0F0 0x334 0x580 0x4 0x0 +#define IOMUXC_GPIO_EMC_B2_14_GPIO_MUX2_IO24 0x0F0 0x334 0x0 0x5 0x0 +#define IOMUXC_GPIO_EMC_B2_14_XBAR1_INOUT34 0x0F0 0x334 0x710 0x6 0x0 +#define IOMUXC_GPIO_EMC_B2_14_SFA_ipp_do_atx_clk_under_test 0x0F0 0x334 0x0 0x7 0x0 +#define IOMUXC_GPIO_EMC_B2_14_EMVSIM1_SVEN 0x0F0 0x334 0x0 0x8 0x0 +#define IOMUXC_GPIO_EMC_B2_14_TMR2_TIMER1 0x0F0 0x334 0x64C 0x9 0x1 +#define IOMUXC_GPIO_EMC_B2_14_GPIO8_IO24 0x0F0 0x334 0x0 0xA 0x0 + +#define IOMUXC_GPIO_EMC_B2_15_SEMC_DATA30 0x0F4 0x338 0x0 0x0 0x0 +#define IOMUXC_GPIO_EMC_B2_15_ENET_1G_RX_DATA00 0x0F4 0x338 0x4D0 0x2 0x0 +#define IOMUXC_GPIO_EMC_B2_15_SAI3_TX_BCLK 0x0F4 0x338 0x0 0x3 0x0 +#define IOMUXC_GPIO_EMC_B2_15_FLEXSPI2_A_DATA02 0x0F4 0x338 0x584 0x4 0x0 +#define IOMUXC_GPIO_EMC_B2_15_GPIO_MUX2_IO25 0x0F4 0x338 0x0 0x5 0x0 +#define IOMUXC_GPIO_EMC_B2_15_XBAR1_INOUT35 0x0F4 0x338 0x714 0x6 0x0 +#define IOMUXC_GPIO_EMC_B2_15_EMVSIM1_PD 0x0F4 0x338 0x6A0 0x8 0x0 +#define IOMUXC_GPIO_EMC_B2_15_TMR2_TIMER2 0x0F4 0x338 0x650 0x9 0x0 +#define IOMUXC_GPIO_EMC_B2_15_GPIO8_IO25 0x0F4 0x338 0x0 0xA 0x0 + +#define IOMUXC_GPIO_EMC_B2_16_GPIO8_IO26 0x0F8 0x33C 0x0 0xA 0x0 +#define IOMUXC_GPIO_EMC_B2_16_SEMC_DATA31 0x0F8 0x33C 0x0 0x0 0x0 +#define IOMUXC_GPIO_EMC_B2_16_XBAR1_INOUT14 0x0F8 0x33C 0x0 0x1 0x0 +#define IOMUXC_GPIO_EMC_B2_16_ENET_1G_RX_DATA01 0x0F8 0x33C 0x4D4 0x2 0x0 +#define IOMUXC_GPIO_EMC_B2_16_SAI3_TX_SYNC 0x0F8 0x33C 0x0 0x3 0x0 +#define IOMUXC_GPIO_EMC_B2_16_FLEXSPI2_A_DATA03 0x0F8 0x33C 0x588 0x4 0x0 +#define IOMUXC_GPIO_EMC_B2_16_GPIO_MUX2_IO26 0x0F8 0x33C 0x0 0x5 0x0 +#define IOMUXC_GPIO_EMC_B2_16_EMVSIM1_POWER_FAIL 0x0F8 0x33C 0x6A4 0x8 0x0 +#define IOMUXC_GPIO_EMC_B2_16_TMR2_TIMER3 0x0F8 0x33C 0x0 0x9 0x0 + +#define IOMUXC_GPIO_EMC_B2_17_SEMC_DM03 0x0FC 0x340 0x0 0x0 0x0 +#define IOMUXC_GPIO_EMC_B2_17_XBAR1_INOUT15 0x0FC 0x340 0x0 0x1 0x0 +#define IOMUXC_GPIO_EMC_B2_17_ENET_1G_RX_EN 0x0FC 0x340 0x4E0 0x2 0x0 +#define IOMUXC_GPIO_EMC_B2_17_SAI3_MCLK 0x0FC 0x340 0x0 0x3 0x0 +#define IOMUXC_GPIO_EMC_B2_17_FLEXSPI2_A_DATA04 0x0FC 0x340 0x0 0x4 0x0 +#define IOMUXC_GPIO_EMC_B2_17_GPIO_MUX2_IO27 0x0FC 0x340 0x0 0x5 0x0 +#define IOMUXC_GPIO_EMC_B2_17_WDOG1_ANY 0x0FC 0x340 0x0 0x8 0x0 +#define IOMUXC_GPIO_EMC_B2_17_TMR3_TIMER0 0x0FC 0x340 0x654 0x9 0x1 +#define IOMUXC_GPIO_EMC_B2_17_GPIO8_IO27 0x0FC 0x340 0x0 0xA 0x0 + +#define IOMUXC_GPIO_EMC_B2_18_SEMC_DQS4 0x100 0x344 0x0 0x0 0x0 +#define IOMUXC_GPIO_EMC_B2_18_XBAR1_INOUT16 0x100 0x344 0x0 0x1 0x0 +#define IOMUXC_GPIO_EMC_B2_18_ENET_1G_RX_ER 0x100 0x344 0x4E4 0x2 0x0 +#define IOMUXC_GPIO_EMC_B2_18_EWM_OUT_B 0x100 0x344 0x0 0x3 0x0 +#define IOMUXC_GPIO_EMC_B2_18_FLEXSPI2_A_DATA05 0x100 0x344 0x0 0x4 0x0 +#define IOMUXC_GPIO_EMC_B2_18_GPIO_MUX2_IO28 0x100 0x344 0x0 0x5 0x0 +#define IOMUXC_GPIO_EMC_B2_18_FLEXSPI1_A_DQS 0x100 0x344 0x550 0x6 0x0 +#define IOMUXC_GPIO_EMC_B2_18_WDOG1_B 0x100 0x344 0x0 0x8 0x0 +#define IOMUXC_GPIO_EMC_B2_18_TMR3_TIMER1 0x100 0x344 0x658 0x9 0x1 +#define IOMUXC_GPIO_EMC_B2_18_GPIO8_IO28 0x100 0x344 0x0 0xA 0x0 + +#define IOMUXC_GPIO_EMC_B2_19_GPIO8_IO29 0x104 0x348 0x0 0xA 0x0 +#define IOMUXC_GPIO_EMC_B2_19_SEMC_CLKX00 0x104 0x348 0x0 0x0 0x0 +#define IOMUXC_GPIO_EMC_B2_19_ENET_MDC 0x104 0x348 0x0 0x1 0x0 +#define IOMUXC_GPIO_EMC_B2_19_ENET_1G_MDC 0x104 0x348 0x0 0x2 0x0 +#define IOMUXC_GPIO_EMC_B2_19_ENET_1G_REF_CLK 0x104 0x348 0x4C4 0x3 0x0 +#define IOMUXC_GPIO_EMC_B2_19_FLEXSPI2_A_DATA06 0x104 0x348 0x0 0x4 0x0 +#define IOMUXC_GPIO_EMC_B2_19_GPIO_MUX2_IO29 0x104 0x348 0x0 0x5 0x0 +#define IOMUXC_GPIO_EMC_B2_19_ENET_QOS_MDC 0x104 0x348 0x0 0x8 0x0 +#define IOMUXC_GPIO_EMC_B2_19_TMR3_TIMER2 0x104 0x348 0x65C 0x9 0x0 + +#define IOMUXC_GPIO_EMC_B2_20_GPIO8_IO30 0x108 0x34C 0x0 0xA 0x0 +#define IOMUXC_GPIO_EMC_B2_20_SEMC_CLKX01 0x108 0x34C 0x0 0x0 0x0 +#define IOMUXC_GPIO_EMC_B2_20_ENET_MDIO 0x108 0x34C 0x4AC 0x1 0x0 +#define IOMUXC_GPIO_EMC_B2_20_ENET_1G_MDIO 0x108 0x34C 0x4C8 0x2 0x1 +#define IOMUXC_GPIO_EMC_B2_20_ENET_QOS_REF_CLK 0x108 0x34C 0x4A0 0x3 0x0 +#define IOMUXC_GPIO_EMC_B2_20_FLEXSPI2_A_DATA07 0x108 0x34C 0x0 0x4 0x0 +#define IOMUXC_GPIO_EMC_B2_20_GPIO_MUX2_IO30 0x108 0x34C 0x0 0x5 0x0 +#define IOMUXC_GPIO_EMC_B2_20_ENET_QOS_MDIO 0x108 0x34C 0x4EC 0x8 0x0 +#define IOMUXC_GPIO_EMC_B2_20_TMR3_TIMER3 0x108 0x34C 0x0 0x9 0x0 + +#define IOMUXC_GPIO_AD_00_GPIO8_IO31 0x10C 0x350 0x0 0xA 0x0 +#define IOMUXC_GPIO_AD_00_EMVSIM1_IO 0x10C 0x350 0x69C 0x0 0x1 +#define IOMUXC_GPIO_AD_00_FLEXCAN2_TX 0x10C 0x350 0x0 0x1 0x0 +#define IOMUXC_GPIO_AD_00_ENET_1G_1588_EVENT1_IN 0x10C 0x350 0x0 0x2 0x0 +#define IOMUXC_GPIO_AD_00_GPT2_CAPTURE1 0x10C 0x350 0x0 0x3 0x0 +#define IOMUXC_GPIO_AD_00_FLEXPWM1_PWM0_A 0x10C 0x350 0x500 0x4 0x1 +#define IOMUXC_GPIO_AD_00_GPIO_MUX2_IO31 0x10C 0x350 0x0 0x5 0x0 +#define IOMUXC_GPIO_AD_00_LPUART7_TXD 0x10C 0x350 0x630 0x6 0x0 +#define IOMUXC_GPIO_AD_00_FLEXIO2_D00 0x10C 0x350 0x0 0x8 0x0 +#define IOMUXC_GPIO_AD_00_FLEXSPI2_B_SS1_B 0x10C 0x350 0x0 0x9 0x0 + +#define IOMUXC_GPIO_AD_01_GPIO9_IO00 0x110 0x354 0x0 0xA 0x0 +#define IOMUXC_GPIO_AD_01_EMVSIM1_CLK 0x110 0x354 0x0 0x0 0x0 +#define IOMUXC_GPIO_AD_01_FLEXCAN2_RX 0x110 0x354 0x49C 0x1 0x0 +#define IOMUXC_GPIO_AD_01_ENET_1G_1588_EVENT1_OUT 0x110 0x354 0x0 0x2 0x0 +#define IOMUXC_GPIO_AD_01_GPT2_CAPTURE2 0x110 0x354 0x0 0x3 0x0 +#define IOMUXC_GPIO_AD_01_FLEXPWM1_PWM0_B 0x110 0x354 0x50C 0x4 0x1 +#define IOMUXC_GPIO_AD_01_GPIO_MUX3_IO00 0x110 0x354 0x0 0x5 0x0 +#define IOMUXC_GPIO_AD_01_LPUART7_RXD 0x110 0x354 0x62C 0x6 0x0 +#define IOMUXC_GPIO_AD_01_FLEXIO2_D01 0x110 0x354 0x0 0x8 0x0 +#define IOMUXC_GPIO_AD_01_FLEXSPI2_A_SS1_B 0x110 0x354 0x0 0x9 0x0 + +#define IOMUXC_GPIO_AD_02_GPIO9_IO01 0x114 0x358 0x0 0xA 0x0 +#define IOMUXC_GPIO_AD_02_EMVSIM1_RST 0x114 0x358 0x0 0x0 0x0 +#define IOMUXC_GPIO_AD_02_LPUART7_CTS_B 0x114 0x358 0x0 0x1 0x0 +#define IOMUXC_GPIO_AD_02_ENET_1G_1588_EVENT2_IN 0x114 0x358 0x0 0x2 0x0 +#define IOMUXC_GPIO_AD_02_GPT2_COMPARE1 0x114 0x358 0x0 0x3 0x0 +#define IOMUXC_GPIO_AD_02_FLEXPWM1_PWM1_A 0x114 0x358 0x504 0x4 0x1 +#define IOMUXC_GPIO_AD_02_GPIO_MUX3_IO01 0x114 0x358 0x0 0x5 0x0 +#define IOMUXC_GPIO_AD_02_LPUART8_TXD 0x114 0x358 0x638 0x6 0x0 +#define IOMUXC_GPIO_AD_02_FLEXIO2_D02 0x114 0x358 0x0 0x8 0x0 +#define IOMUXC_GPIO_AD_02_VIDEO_MUX_EXT_DCIC1 0x114 0x358 0x0 0x9 0x0 + +#define IOMUXC_GPIO_AD_03_GPIO9_IO02 0x118 0x35C 0x0 0xA 0x0 +#define IOMUXC_GPIO_AD_03_EMVSIM1_SVEN 0x118 0x35C 0x0 0x0 0x0 +#define IOMUXC_GPIO_AD_03_LPUART7_RTS_B 0x118 0x35C 0x0 0x1 0x0 +#define IOMUXC_GPIO_AD_03_ENET_1G_1588_EVENT2_OUT 0x118 0x35C 0x0 0x2 0x0 +#define IOMUXC_GPIO_AD_03_GPT2_COMPARE2 0x118 0x35C 0x0 0x3 0x0 +#define IOMUXC_GPIO_AD_03_FLEXPWM1_PWM1_B 0x118 0x35C 0x510 0x4 0x1 +#define IOMUXC_GPIO_AD_03_GPIO_MUX3_IO02 0x118 0x35C 0x0 0x5 0x0 +#define IOMUXC_GPIO_AD_03_LPUART8_RXD 0x118 0x35C 0x634 0x6 0x0 +#define IOMUXC_GPIO_AD_03_FLEXIO2_D03 0x118 0x35C 0x0 0x8 0x0 +#define IOMUXC_GPIO_AD_03_VIDEO_MUX_EXT_DCIC2 0x118 0x35C 0x0 0x9 0x0 + +#define IOMUXC_GPIO_AD_04_EMVSIM1_PD 0x11C 0x360 0x6A0 0x0 0x1 +#define IOMUXC_GPIO_AD_04_LPUART8_CTS_B 0x11C 0x360 0x0 0x1 0x0 +#define IOMUXC_GPIO_AD_04_ENET_1G_1588_EVENT3_IN 0x11C 0x360 0x0 0x2 0x0 +#define IOMUXC_GPIO_AD_04_GPT2_COMPARE3 0x11C 0x360 0x0 0x3 0x0 +#define IOMUXC_GPIO_AD_04_FLEXPWM1_PWM2_A 0x11C 0x360 0x508 0x4 0x1 +#define IOMUXC_GPIO_AD_04_GPIO_MUX3_IO03 0x11C 0x360 0x0 0x5 0x0 +#define IOMUXC_GPIO_AD_04_WDOG1_B 0x11C 0x360 0x0 0x6 0x0 +#define IOMUXC_GPIO_AD_04_FLEXIO2_D04 0x11C 0x360 0x0 0x8 0x0 +#define IOMUXC_GPIO_AD_04_TMR4_TIMER0 0x11C 0x360 0x660 0x9 0x1 +#define IOMUXC_GPIO_AD_04_GPIO9_IO03 0x11C 0x360 0x0 0xA 0x0 + +#define IOMUXC_GPIO_AD_05_EMVSIM1_POWER_FAIL 0x120 0x364 0x6A4 0x0 0x1 +#define IOMUXC_GPIO_AD_05_LPUART8_RTS_B 0x120 0x364 0x0 0x1 0x0 +#define IOMUXC_GPIO_AD_05_ENET_1G_1588_EVENT3_OUT 0x120 0x364 0x0 0x2 0x0 +#define IOMUXC_GPIO_AD_05_GPT2_CLK 0x120 0x364 0x0 0x3 0x0 +#define IOMUXC_GPIO_AD_05_FLEXPWM1_PWM2_B 0x120 0x364 0x514 0x4 0x1 +#define IOMUXC_GPIO_AD_05_GPIO_MUX3_IO04 0x120 0x364 0x0 0x5 0x0 +#define IOMUXC_GPIO_AD_05_WDOG2_B 0x120 0x364 0x0 0x6 0x0 +#define IOMUXC_GPIO_AD_05_FLEXIO2_D05 0x120 0x364 0x0 0x8 0x0 +#define IOMUXC_GPIO_AD_05_TMR4_TIMER1 0x120 0x364 0x664 0x9 0x1 +#define IOMUXC_GPIO_AD_05_GPIO9_IO04 0x120 0x364 0x0 0xA 0x0 + +#define IOMUXC_GPIO_AD_06_USB_OTG2_OC 0x124 0x368 0x6B8 0x0 0x0 +#define IOMUXC_GPIO_AD_06_FLEXCAN1_TX 0x124 0x368 0x0 0x1 0x0 +#define IOMUXC_GPIO_AD_06_EMVSIM2_IO 0x124 0x368 0x6A8 0x2 0x0 +#define IOMUXC_GPIO_AD_06_GPT3_CAPTURE1 0x124 0x368 0x590 0x3 0x1 +#define IOMUXC_GPIO_AD_06_VIDEO_MUX_CSI_DATA15 0x124 0x368 0x0 0x4 0x0 +#define IOMUXC_GPIO_AD_06_GPIO_MUX3_IO05 0x124 0x368 0x0 0x5 0x0 +#define IOMUXC_GPIO_AD_06_ENET_1588_EVENT1_IN 0x124 0x368 0x0 0x6 0x0 +#define IOMUXC_GPIO_AD_06_FLEXIO2_D06 0x124 0x368 0x0 0x8 0x0 +#define IOMUXC_GPIO_AD_06_TMR4_TIMER2 0x124 0x368 0x668 0x9 0x0 +#define IOMUXC_GPIO_AD_06_GPIO9_IO05 0x124 0x368 0x0 0xA 0x0 +#define IOMUXC_GPIO_AD_06_FLEXPWM1_PWM0_X 0x124 0x368 0x0 0xB 0x0 + +#define IOMUXC_GPIO_AD_07_USB_OTG2_PWR 0x128 0x36C 0x0 0x0 0x0 +#define IOMUXC_GPIO_AD_07_FLEXCAN1_RX 0x128 0x36C 0x498 0x1 0x0 +#define IOMUXC_GPIO_AD_07_EMVSIM2_CLK 0x128 0x36C 0x0 0x2 0x0 +#define IOMUXC_GPIO_AD_07_GPT3_CAPTURE2 0x128 0x36C 0x594 0x3 0x1 +#define IOMUXC_GPIO_AD_07_VIDEO_MUX_CSI_DATA14 0x128 0x36C 0x0 0x4 0x0 +#define IOMUXC_GPIO_AD_07_GPIO_MUX3_IO06 0x128 0x36C 0x0 0x5 0x0 +#define IOMUXC_GPIO_AD_07_ENET_1588_EVENT1_OUT 0x128 0x36C 0x0 0x6 0x0 +#define IOMUXC_GPIO_AD_07_FLEXIO2_D07 0x128 0x36C 0x0 0x8 0x0 +#define IOMUXC_GPIO_AD_07_TMR4_TIMER3 0x128 0x36C 0x0 0x9 0x0 +#define IOMUXC_GPIO_AD_07_GPIO9_IO06 0x128 0x36C 0x0 0xA 0x0 +#define IOMUXC_GPIO_AD_07_FLEXPWM1_PWM1_X 0x128 0x36C 0x0 0xB 0x0 + +#define IOMUXC_GPIO_AD_08_USBPHY2_OTG_ID 0x12C 0x370 0x6C4 0x0 0x0 +#define IOMUXC_GPIO_AD_08_LPI2C1_SCL 0x12C 0x370 0x5AC 0x1 0x0 +#define IOMUXC_GPIO_AD_08_EMVSIM2_RST 0x12C 0x370 0x0 0x2 0x0 +#define IOMUXC_GPIO_AD_08_GPT3_COMPARE1 0x12C 0x370 0x0 0x3 0x0 +#define IOMUXC_GPIO_AD_08_VIDEO_MUX_CSI_DATA13 0x12C 0x370 0x0 0x4 0x0 +#define IOMUXC_GPIO_AD_08_GPIO_MUX3_IO07 0x12C 0x370 0x0 0x5 0x0 +#define IOMUXC_GPIO_AD_08_ENET_1588_EVENT2_IN 0x12C 0x370 0x0 0x6 0x0 +#define IOMUXC_GPIO_AD_08_FLEXIO2_D08 0x12C 0x370 0x0 0x8 0x0 +#define IOMUXC_GPIO_AD_08_GPIO9_IO07 0x12C 0x370 0x0 0xA 0x0 +#define IOMUXC_GPIO_AD_08_FLEXPWM1_PWM2_X 0x12C 0x370 0x0 0xB 0x0 + +#define IOMUXC_GPIO_AD_09_USBPHY1_OTG_ID 0x130 0x374 0x6C0 0x0 0x0 +#define IOMUXC_GPIO_AD_09_LPI2C1_SDA 0x130 0x374 0x5B0 0x1 0x0 +#define IOMUXC_GPIO_AD_09_EMVSIM2_SVEN 0x130 0x374 0x0 0x2 0x0 +#define IOMUXC_GPIO_AD_09_GPT3_COMPARE2 0x130 0x374 0x0 0x3 0x0 +#define IOMUXC_GPIO_AD_09_VIDEO_MUX_CSI_DATA12 0x130 0x374 0x0 0x4 0x0 +#define IOMUXC_GPIO_AD_09_GPIO_MUX3_IO08 0x130 0x374 0x0 0x5 0x0 +#define IOMUXC_GPIO_AD_09_ENET_1588_EVENT2_OUT 0x130 0x374 0x0 0x6 0x0 +#define IOMUXC_GPIO_AD_09_FLEXIO2_D09 0x130 0x374 0x0 0x8 0x0 +#define IOMUXC_GPIO_AD_09_GPIO9_IO08 0x130 0x374 0x0 0xA 0x0 +#define IOMUXC_GPIO_AD_09_FLEXPWM1_PWM3_X 0x130 0x374 0x0 0xB 0x0 + +#define IOMUXC_GPIO_AD_10_USB_OTG1_PWR 0x134 0x378 0x0 0x0 0x0 +#define IOMUXC_GPIO_AD_10_LPI2C1_SCLS 0x134 0x378 0x0 0x1 0x0 +#define IOMUXC_GPIO_AD_10_EMVSIM2_PD 0x134 0x378 0x6AC 0x2 0x0 +#define IOMUXC_GPIO_AD_10_GPT3_COMPARE3 0x134 0x378 0x0 0x3 0x0 +#define IOMUXC_GPIO_AD_10_VIDEO_MUX_CSI_DATA11 0x134 0x378 0x0 0x4 0x0 +#define IOMUXC_GPIO_AD_10_GPIO_MUX3_IO09 0x134 0x378 0x0 0x5 0x0 +#define IOMUXC_GPIO_AD_10_ENET_1588_EVENT3_IN 0x134 0x378 0x0 0x6 0x0 +#define IOMUXC_GPIO_AD_10_FLEXIO2_D10 0x134 0x378 0x0 0x8 0x0 +#define IOMUXC_GPIO_AD_10_GPIO9_IO09 0x134 0x378 0x0 0xA 0x0 +#define IOMUXC_GPIO_AD_10_FLEXPWM2_PWM0_X 0x134 0x378 0x0 0xB 0x0 + +#define IOMUXC_GPIO_AD_11_USB_OTG1_OC 0x138 0x37C 0x6BC 0x0 0x0 +#define IOMUXC_GPIO_AD_11_LPI2C1_SDAS 0x138 0x37C 0x0 0x1 0x0 +#define IOMUXC_GPIO_AD_11_EMVSIM2_POWER_FAIL 0x138 0x37C 0x6B0 0x2 0x0 +#define IOMUXC_GPIO_AD_11_GPT3_CLK 0x138 0x37C 0x598 0x3 0x1 +#define IOMUXC_GPIO_AD_11_VIDEO_MUX_CSI_DATA10 0x138 0x37C 0x0 0x4 0x0 +#define IOMUXC_GPIO_AD_11_GPIO_MUX3_IO10 0x138 0x37C 0x0 0x5 0x0 +#define IOMUXC_GPIO_AD_11_ENET_1588_EVENT3_OUT 0x138 0x37C 0x0 0x6 0x0 +#define IOMUXC_GPIO_AD_11_FLEXIO2_D11 0x138 0x37C 0x0 0x8 0x0 +#define IOMUXC_GPIO_AD_11_GPIO9_IO10 0x138 0x37C 0x0 0xA 0x0 +#define IOMUXC_GPIO_AD_11_FLEXPWM2_PWM1_X 0x138 0x37C 0x0 0xB 0x0 + +#define IOMUXC_GPIO_AD_12_SPDIF_LOCK 0x13C 0x380 0x0 0x0 0x0 +#define IOMUXC_GPIO_AD_12_LPI2C1_HREQ 0x13C 0x380 0x0 0x1 0x0 +#define IOMUXC_GPIO_AD_12_GPT1_CAPTURE1 0x13C 0x380 0x0 0x2 0x0 +#define IOMUXC_GPIO_AD_12_FLEXSPI1_B_DATA03 0x13C 0x380 0x570 0x3 0x0 +#define IOMUXC_GPIO_AD_12_VIDEO_MUX_CSI_PIXCLK 0x13C 0x380 0x0 0x4 0x0 +#define IOMUXC_GPIO_AD_12_GPIO_MUX3_IO11 0x13C 0x380 0x0 0x5 0x0 +#define IOMUXC_GPIO_AD_12_ENET_TX_DATA03 0x13C 0x380 0x0 0x6 0x0 +#define IOMUXC_GPIO_AD_12_FLEXIO2_D12 0x13C 0x380 0x0 0x8 0x0 +#define IOMUXC_GPIO_AD_12_EWM_OUT_B 0x13C 0x380 0x0 0x9 0x0 +#define IOMUXC_GPIO_AD_12_GPIO9_IO11 0x13C 0x380 0x0 0xA 0x0 +#define IOMUXC_GPIO_AD_12_FLEXPWM2_PWM2_X 0x13C 0x380 0x0 0xB 0x0 + +#define IOMUXC_GPIO_AD_13_SPDIF_SR_CLK 0x140 0x384 0x0 0x0 0x0 +#define IOMUXC_GPIO_AD_13_PIT1_TRIGGER0 0x140 0x384 0x0 0x1 0x0 +#define IOMUXC_GPIO_AD_13_GPT1_CAPTURE2 0x140 0x384 0x0 0x2 0x0 +#define IOMUXC_GPIO_AD_13_FLEXSPI1_B_DATA02 0x140 0x384 0x56C 0x3 0x0 +#define IOMUXC_GPIO_AD_13_VIDEO_MUX_CSI_MCLK 0x140 0x384 0x0 0x4 0x0 +#define IOMUXC_GPIO_AD_13_GPIO_MUX3_IO12 0x140 0x384 0x0 0x5 0x0 +#define IOMUXC_GPIO_AD_13_ENET_TX_DATA02 0x140 0x384 0x0 0x6 0x0 +#define IOMUXC_GPIO_AD_13_FLEXIO2_D13 0x140 0x384 0x0 0x8 0x0 +#define IOMUXC_GPIO_AD_13_REF_CLK_32K 0x140 0x384 0x0 0x9 0x0 +#define IOMUXC_GPIO_AD_13_GPIO9_IO12 0x140 0x384 0x0 0xA 0x0 +#define IOMUXC_GPIO_AD_13_FLEXPWM2_PWM3_X 0x140 0x384 0x0 0xB 0x0 + +#define IOMUXC_GPIO_AD_14_SPDIF_EXT_CLK 0x144 0x388 0x0 0x0 0x0 +#define IOMUXC_GPIO_AD_14_REF_CLK_24M 0x144 0x388 0x0 0x1 0x0 +#define IOMUXC_GPIO_AD_14_GPT1_COMPARE1 0x144 0x388 0x0 0x2 0x0 +#define IOMUXC_GPIO_AD_14_FLEXSPI1_B_DATA01 0x144 0x388 0x568 0x3 0x0 +#define IOMUXC_GPIO_AD_14_VIDEO_MUX_CSI_VSYNC 0x144 0x388 0x0 0x4 0x0 +#define IOMUXC_GPIO_AD_14_GPIO_MUX3_IO13 0x144 0x388 0x0 0x5 0x0 +#define IOMUXC_GPIO_AD_14_ENET_RX_CLK 0x144 0x388 0x0 0x6 0x0 +#define IOMUXC_GPIO_AD_14_FLEXIO2_D14 0x144 0x388 0x0 0x8 0x0 +#define IOMUXC_GPIO_AD_14_CCM_ENET_REF_CLK_25M 0x144 0x388 0x0 0x9 0x0 +#define IOMUXC_GPIO_AD_14_GPIO9_IO13 0x144 0x388 0x0 0xA 0x0 +#define IOMUXC_GPIO_AD_14_FLEXPWM3_PWM0_X 0x144 0x388 0x0 0xB 0x0 + +#define IOMUXC_GPIO_AD_15_GPIO9_IO14 0x148 0x38C 0x0 0xA 0x0 +#define IOMUXC_GPIO_AD_15_FLEXPWM3_PWM1_X 0x148 0x38C 0x0 0xB 0x0 +#define IOMUXC_GPIO_AD_15_SPDIF_IN 0x148 0x38C 0x6B4 0x0 0x1 +#define IOMUXC_GPIO_AD_15_LPUART10_TXD 0x148 0x38C 0x628 0x1 0x0 +#define IOMUXC_GPIO_AD_15_GPT1_COMPARE2 0x148 0x38C 0x0 0x2 0x0 +#define IOMUXC_GPIO_AD_15_FLEXSPI1_B_DATA00 0x148 0x38C 0x564 0x3 0x0 +#define IOMUXC_GPIO_AD_15_VIDEO_MUX_CSI_HSYNC 0x148 0x38C 0x0 0x4 0x0 +#define IOMUXC_GPIO_AD_15_GPIO_MUX3_IO14 0x148 0x38C 0x0 0x5 0x0 +#define IOMUXC_GPIO_AD_15_ENET_TX_ER 0x148 0x38C 0x0 0x6 0x0 +#define IOMUXC_GPIO_AD_15_FLEXIO2_D15 0x148 0x38C 0x0 0x8 0x0 + +#define IOMUXC_GPIO_AD_16_SPDIF_OUT 0x14C 0x390 0x0 0x0 0x0 +#define IOMUXC_GPIO_AD_16_LPUART10_RXD 0x14C 0x390 0x624 0x1 0x0 +#define IOMUXC_GPIO_AD_16_GPT1_COMPARE3 0x14C 0x390 0x0 0x2 0x0 +#define IOMUXC_GPIO_AD_16_FLEXSPI1_B_SCLK 0x14C 0x390 0x578 0x3 0x0 +#define IOMUXC_GPIO_AD_16_VIDEO_MUX_CSI_DATA09 0x14C 0x390 0x0 0x4 0x0 +#define IOMUXC_GPIO_AD_16_GPIO_MUX3_IO15 0x14C 0x390 0x0 0x5 0x0 +#define IOMUXC_GPIO_AD_16_ENET_RX_DATA03 0x14C 0x390 0x0 0x6 0x0 +#define IOMUXC_GPIO_AD_16_FLEXIO2_D16 0x14C 0x390 0x0 0x8 0x0 +#define IOMUXC_GPIO_AD_16_ENET_1G_MDC 0x14C 0x390 0x0 0x9 0x0 +#define IOMUXC_GPIO_AD_16_GPIO9_IO15 0x14C 0x390 0x0 0xA 0x0 +#define IOMUXC_GPIO_AD_16_FLEXPWM3_PWM2_X 0x14C 0x390 0x0 0xB 0x0 + +#define IOMUXC_GPIO_AD_17_SAI1_MCLK 0x150 0x394 0x66C 0x0 0x0 +#define IOMUXC_GPIO_AD_17_ACMP1_OUT 0x150 0x394 0x0 0x1 0x0 +#define IOMUXC_GPIO_AD_17_GPT1_CLK 0x150 0x394 0x0 0x2 0x0 +#define IOMUXC_GPIO_AD_17_FLEXSPI1_A_DQS 0x150 0x394 0x550 0x3 0x1 +#define IOMUXC_GPIO_AD_17_VIDEO_MUX_CSI_DATA08 0x150 0x394 0x0 0x4 0x0 +#define IOMUXC_GPIO_AD_17_GPIO_MUX3_IO16 0x150 0x394 0x0 0x5 0x0 +#define IOMUXC_GPIO_AD_17_ENET_RX_DATA02 0x150 0x394 0x0 0x6 0x0 +#define IOMUXC_GPIO_AD_17_FLEXIO2_D17 0x150 0x394 0x0 0x8 0x0 +#define IOMUXC_GPIO_AD_17_ENET_1G_MDIO 0x150 0x394 0x4C8 0x9 0x2 +#define IOMUXC_GPIO_AD_17_GPIO9_IO16 0x150 0x394 0x0 0xA 0x0 +#define IOMUXC_GPIO_AD_17_FLEXPWM3_PWM3_X 0x150 0x394 0x0 0xB 0x0 + +#define IOMUXC_GPIO_AD_18_GPIO9_IO17 0x154 0x398 0x0 0xA 0x0 +#define IOMUXC_GPIO_AD_18_FLEXPWM4_PWM0_X 0x154 0x398 0x0 0xB 0x0 +#define IOMUXC_GPIO_AD_18_SAI1_RX_SYNC 0x154 0x398 0x678 0x0 0x0 +#define IOMUXC_GPIO_AD_18_ACMP2_OUT 0x154 0x398 0x0 0x1 0x0 +#define IOMUXC_GPIO_AD_18_LPSPI1_PCS1 0x154 0x398 0x0 0x2 0x0 +#define IOMUXC_GPIO_AD_18_FLEXSPI1_A_SS0_B 0x154 0x398 0x0 0x3 0x0 +#define IOMUXC_GPIO_AD_18_VIDEO_MUX_CSI_DATA07 0x154 0x398 0x0 0x4 0x0 +#define IOMUXC_GPIO_AD_18_GPIO_MUX3_IO17 0x154 0x398 0x0 0x5 0x0 +#define IOMUXC_GPIO_AD_18_ENET_CRS 0x154 0x398 0x0 0x6 0x0 +#define IOMUXC_GPIO_AD_18_FLEXIO2_D18 0x154 0x398 0x0 0x8 0x0 +#define IOMUXC_GPIO_AD_18_LPI2C2_SCL 0x154 0x398 0x5B4 0x9 0x1 + +#define IOMUXC_GPIO_AD_19_SAI1_RX_BCLK 0x158 0x39C 0x670 0x0 0x0 +#define IOMUXC_GPIO_AD_19_ACMP3_OUT 0x158 0x39C 0x0 0x1 0x0 +#define IOMUXC_GPIO_AD_19_LPSPI1_PCS2 0x158 0x39C 0x0 0x2 0x0 +#define IOMUXC_GPIO_AD_19_FLEXSPI1_A_SCLK 0x158 0x39C 0x574 0x3 0x0 +#define IOMUXC_GPIO_AD_19_VIDEO_MUX_CSI_DATA06 0x158 0x39C 0x0 0x4 0x0 +#define IOMUXC_GPIO_AD_19_GPIO_MUX3_IO18 0x158 0x39C 0x0 0x5 0x0 +#define IOMUXC_GPIO_AD_19_ENET_COL 0x158 0x39C 0x0 0x6 0x0 +#define IOMUXC_GPIO_AD_19_FLEXIO2_D19 0x158 0x39C 0x0 0x8 0x0 +#define IOMUXC_GPIO_AD_19_LPI2C2_SDA 0x158 0x39C 0x5B8 0x9 0x1 +#define IOMUXC_GPIO_AD_19_GPIO9_IO18 0x158 0x39C 0x0 0xA 0x0 +#define IOMUXC_GPIO_AD_19_FLEXPWM4_PWM1_X 0x158 0x39C 0x0 0xB 0x0 + +#define IOMUXC_GPIO_AD_20_SAI1_RX_DATA00 0x15C 0x3A0 0x674 0x0 0x0 +#define IOMUXC_GPIO_AD_20_ACMP4_OUT 0x15C 0x3A0 0x0 0x1 0x0 +#define IOMUXC_GPIO_AD_20_LPSPI1_PCS3 0x15C 0x3A0 0x0 0x2 0x0 +#define IOMUXC_GPIO_AD_20_FLEXSPI1_A_DATA00 0x15C 0x3A0 0x554 0x3 0x0 +#define IOMUXC_GPIO_AD_20_VIDEO_MUX_CSI_DATA05 0x15C 0x3A0 0x0 0x4 0x0 +#define IOMUXC_GPIO_AD_20_GPIO_MUX3_IO19 0x15C 0x3A0 0x0 0x5 0x0 +#define IOMUXC_GPIO_AD_20_KPP_ROW07 0x15C 0x3A0 0x5A8 0x6 0x0 +#define IOMUXC_GPIO_AD_20_FLEXIO2_D20 0x15C 0x3A0 0x0 0x8 0x0 +#define IOMUXC_GPIO_AD_20_ENET_QOS_1588_EVENT2_OUT 0x15C 0x3A0 0x0 0x9 0x0 +#define IOMUXC_GPIO_AD_20_GPIO9_IO19 0x15C 0x3A0 0x0 0xA 0x0 +#define IOMUXC_GPIO_AD_20_FLEXPWM4_PWM2_X 0x15C 0x3A0 0x0 0xB 0x0 + +#define IOMUXC_GPIO_AD_21_SAI1_TX_DATA00 0x160 0x3A4 0x0 0x0 0x0 +#define IOMUXC_GPIO_AD_21_LPSPI2_PCS1 0x160 0x3A4 0x5E0 0x2 0x0 +#define IOMUXC_GPIO_AD_21_FLEXSPI1_A_DATA01 0x160 0x3A4 0x558 0x3 0x0 +#define IOMUXC_GPIO_AD_21_VIDEO_MUX_CSI_DATA04 0x160 0x3A4 0x0 0x4 0x0 +#define IOMUXC_GPIO_AD_21_GPIO_MUX3_IO20 0x160 0x3A4 0x0 0x5 0x0 +#define IOMUXC_GPIO_AD_21_KPP_COL07 0x160 0x3A4 0x5A0 0x6 0x0 +#define IOMUXC_GPIO_AD_21_FLEXIO2_D21 0x160 0x3A4 0x0 0x8 0x0 +#define IOMUXC_GPIO_AD_21_ENET_QOS_1588_EVENT2_IN 0x160 0x3A4 0x0 0x9 0x0 +#define IOMUXC_GPIO_AD_21_GPIO9_IO20 0x160 0x3A4 0x0 0xA 0x0 +#define IOMUXC_GPIO_AD_21_FLEXPWM4_PWM3_X 0x160 0x3A4 0x0 0xB 0x0 + +#define IOMUXC_GPIO_AD_22_GPIO9_IO21 0x164 0x3A8 0x0 0xA 0x0 +#define IOMUXC_GPIO_AD_22_SAI1_TX_BCLK 0x164 0x3A8 0x67C 0x0 0x0 +#define IOMUXC_GPIO_AD_22_LPSPI2_PCS2 0x164 0x3A8 0x0 0x2 0x0 +#define IOMUXC_GPIO_AD_22_FLEXSPI1_A_DATA02 0x164 0x3A8 0x55C 0x3 0x0 +#define IOMUXC_GPIO_AD_22_VIDEO_MUX_CSI_DATA03 0x164 0x3A8 0x0 0x4 0x0 +#define IOMUXC_GPIO_AD_22_GPIO_MUX3_IO21 0x164 0x3A8 0x0 0x5 0x0 +#define IOMUXC_GPIO_AD_22_KPP_ROW06 0x164 0x3A8 0x5A4 0x6 0x0 +#define IOMUXC_GPIO_AD_22_FLEXIO2_D22 0x164 0x3A8 0x0 0x8 0x0 +#define IOMUXC_GPIO_AD_22_ENET_QOS_1588_EVENT3_OUT 0x164 0x3A8 0x0 0x9 0x0 + +#define IOMUXC_GPIO_AD_23_SAI1_TX_SYNC 0x168 0x3AC 0x680 0x0 0x0 +#define IOMUXC_GPIO_AD_23_LPSPI2_PCS3 0x168 0x3AC 0x0 0x2 0x0 +#define IOMUXC_GPIO_AD_23_FLEXSPI1_A_DATA03 0x168 0x3AC 0x560 0x3 0x0 +#define IOMUXC_GPIO_AD_23_VIDEO_MUX_CSI_DATA02 0x168 0x3AC 0x0 0x4 0x0 +#define IOMUXC_GPIO_AD_23_GPIO_MUX3_IO22 0x168 0x3AC 0x0 0x5 0x0 +#define IOMUXC_GPIO_AD_23_KPP_COL06 0x168 0x3AC 0x59C 0x6 0x0 +#define IOMUXC_GPIO_AD_23_FLEXIO2_D23 0x168 0x3AC 0x0 0x8 0x0 +#define IOMUXC_GPIO_AD_23_ENET_QOS_1588_EVENT3_IN 0x168 0x3AC 0x0 0x9 0x0 +#define IOMUXC_GPIO_AD_23_GPIO9_IO22 0x168 0x3AC 0x0 0xA 0x0 + +#define IOMUXC_GPIO_AD_24_LPUART1_TXD 0x16C 0x3B0 0x620 0x0 0x0 +#define IOMUXC_GPIO_AD_24_LPSPI2_SCK 0x16C 0x3B0 0x5E4 0x1 0x0 +#define IOMUXC_GPIO_AD_24_VIDEO_MUX_CSI_DATA00 0x16C 0x3B0 0x0 0x2 0x0 +#define IOMUXC_GPIO_AD_24_ENET_RX_EN 0x16C 0x3B0 0x4B8 0x3 0x0 +#define IOMUXC_GPIO_AD_24_FLEXPWM2_PWM0_A 0x16C 0x3B0 0x518 0x4 0x1 +#define IOMUXC_GPIO_AD_24_GPIO_MUX3_IO23 0x16C 0x3B0 0x0 0x5 0x0 +#define IOMUXC_GPIO_AD_24_KPP_ROW05 0x16C 0x3B0 0x0 0x6 0x0 +#define IOMUXC_GPIO_AD_24_FLEXIO2_D24 0x16C 0x3B0 0x0 0x8 0x0 +#define IOMUXC_GPIO_AD_24_LPI2C4_SCL 0x16C 0x3B0 0x5C4 0x9 0x0 +#define IOMUXC_GPIO_AD_24_GPIO9_IO23 0x16C 0x3B0 0x0 0xA 0x0 + +#define IOMUXC_GPIO_AD_25_GPIO9_IO24 0x170 0x3B4 0x0 0xA 0x0 +#define IOMUXC_GPIO_AD_25_LPUART1_RXD 0x170 0x3B4 0x61C 0x0 0x0 +#define IOMUXC_GPIO_AD_25_LPSPI2_PCS0 0x170 0x3B4 0x5DC 0x1 0x0 +#define IOMUXC_GPIO_AD_25_VIDEO_MUX_CSI_DATA01 0x170 0x3B4 0x0 0x2 0x0 +#define IOMUXC_GPIO_AD_25_ENET_RX_ER 0x170 0x3B4 0x4BC 0x3 0x0 +#define IOMUXC_GPIO_AD_25_FLEXPWM2_PWM0_B 0x170 0x3B4 0x524 0x4 0x1 +#define IOMUXC_GPIO_AD_25_GPIO_MUX3_IO24 0x170 0x3B4 0x0 0x5 0x0 +#define IOMUXC_GPIO_AD_25_KPP_COL05 0x170 0x3B4 0x0 0x6 0x0 +#define IOMUXC_GPIO_AD_25_FLEXIO2_D25 0x170 0x3B4 0x0 0x8 0x0 +#define IOMUXC_GPIO_AD_25_LPI2C4_SDA 0x170 0x3B4 0x5C8 0x9 0x0 + +#define IOMUXC_GPIO_AD_26_LPUART1_CTS_B 0x174 0x3B8 0x0 0x0 0x0 +#define IOMUXC_GPIO_AD_26_LPSPI2_SOUT 0x174 0x3B8 0x5EC 0x1 0x0 +#define IOMUXC_GPIO_AD_26_SEMC_CSX01 0x174 0x3B8 0x0 0x2 0x0 +#define IOMUXC_GPIO_AD_26_ENET_RX_DATA00 0x174 0x3B8 0x4B0 0x3 0x0 +#define IOMUXC_GPIO_AD_26_FLEXPWM2_PWM1_A 0x174 0x3B8 0x51C 0x4 0x1 +#define IOMUXC_GPIO_AD_26_GPIO_MUX3_IO25 0x174 0x3B8 0x0 0x5 0x0 +#define IOMUXC_GPIO_AD_26_KPP_ROW04 0x174 0x3B8 0x0 0x6 0x0 +#define IOMUXC_GPIO_AD_26_FLEXIO2_D26 0x174 0x3B8 0x0 0x8 0x0 +#define IOMUXC_GPIO_AD_26_ENET_QOS_MDC 0x174 0x3B8 0x0 0x9 0x0 +#define IOMUXC_GPIO_AD_26_GPIO9_IO25 0x174 0x3B8 0x0 0xA 0x0 +#define IOMUXC_GPIO_AD_26_USDHC2_CD_B 0x174 0x3B8 0x6D0 0xB 0x1 + +#define IOMUXC_GPIO_AD_27_LPUART1_RTS_B 0x178 0x3BC 0x0 0x0 0x0 +#define IOMUXC_GPIO_AD_27_LPSPI2_SIN 0x178 0x3BC 0x5E8 0x1 0x0 +#define IOMUXC_GPIO_AD_27_SEMC_CSX02 0x178 0x3BC 0x0 0x2 0x0 +#define IOMUXC_GPIO_AD_27_ENET_RX_DATA01 0x178 0x3BC 0x4B4 0x3 0x0 +#define IOMUXC_GPIO_AD_27_FLEXPWM2_PWM1_B 0x178 0x3BC 0x528 0x4 0x1 +#define IOMUXC_GPIO_AD_27_GPIO_MUX3_IO26 0x178 0x3BC 0x0 0x5 0x0 +#define IOMUXC_GPIO_AD_27_KPP_COL04 0x178 0x3BC 0x0 0x6 0x0 +#define IOMUXC_GPIO_AD_27_FLEXIO2_D27 0x178 0x3BC 0x0 0x8 0x0 +#define IOMUXC_GPIO_AD_27_ENET_QOS_MDIO 0x178 0x3BC 0x4EC 0x9 0x1 +#define IOMUXC_GPIO_AD_27_GPIO9_IO26 0x178 0x3BC 0x0 0xA 0x0 +#define IOMUXC_GPIO_AD_27_USDHC2_WP 0x178 0x3BC 0x6D4 0xB 0x1 + +#define IOMUXC_GPIO_AD_28_GPIO9_IO27 0x17C 0x3C0 0x0 0xA 0x0 +#define IOMUXC_GPIO_AD_28_USDHC2_VSELECT 0x17C 0x3C0 0x0 0xB 0x0 +#define IOMUXC_GPIO_AD_28_LPSPI1_SCK 0x17C 0x3C0 0x5D0 0x0 0x1 +#define IOMUXC_GPIO_AD_28_LPUART5_TXD 0x17C 0x3C0 0x0 0x1 0x0 +#define IOMUXC_GPIO_AD_28_SEMC_CSX03 0x17C 0x3C0 0x0 0x2 0x0 +#define IOMUXC_GPIO_AD_28_ENET_TX_EN 0x17C 0x3C0 0x0 0x3 0x0 +#define IOMUXC_GPIO_AD_28_FLEXPWM2_PWM2_A 0x17C 0x3C0 0x520 0x4 0x1 +#define IOMUXC_GPIO_AD_28_GPIO_MUX3_IO27 0x17C 0x3C0 0x0 0x5 0x0 +#define IOMUXC_GPIO_AD_28_KPP_ROW03 0x17C 0x3C0 0x0 0x6 0x0 +#define IOMUXC_GPIO_AD_28_FLEXIO2_D28 0x17C 0x3C0 0x0 0x8 0x0 +#define IOMUXC_GPIO_AD_28_VIDEO_MUX_EXT_DCIC1 0x17C 0x3C0 0x0 0x9 0x0 + +#define IOMUXC_GPIO_AD_29_LPSPI1_PCS0 0x180 0x3C4 0x5CC 0x0 0x1 +#define IOMUXC_GPIO_AD_29_LPUART5_RXD 0x180 0x3C4 0x0 0x1 0x0 +#define IOMUXC_GPIO_AD_29_ENET_REF_CLK 0x180 0x3C4 0x4A8 0x2 0x0 +#define IOMUXC_GPIO_AD_29_ENET_TX_CLK 0x180 0x3C4 0x4C0 0x3 0x0 +#define IOMUXC_GPIO_AD_29_FLEXPWM2_PWM2_B 0x180 0x3C4 0x52C 0x4 0x1 +#define IOMUXC_GPIO_AD_29_GPIO_MUX3_IO28 0x180 0x3C4 0x0 0x5 0x0 +#define IOMUXC_GPIO_AD_29_KPP_COL03 0x180 0x3C4 0x0 0x6 0x0 +#define IOMUXC_GPIO_AD_29_FLEXIO2_D29 0x180 0x3C4 0x0 0x8 0x0 +#define IOMUXC_GPIO_AD_29_VIDEO_MUX_EXT_DCIC2 0x180 0x3C4 0x0 0x9 0x0 +#define IOMUXC_GPIO_AD_29_GPIO9_IO28 0x180 0x3C4 0x0 0xA 0x0 +#define IOMUXC_GPIO_AD_29_USDHC2_RESET_B 0x180 0x3C4 0x0 0xB 0x0 + +#define IOMUXC_GPIO_AD_30_LPSPI1_SOUT 0x184 0x3C8 0x5D8 0x0 0x1 +#define IOMUXC_GPIO_AD_30_USB_OTG2_OC 0x184 0x3C8 0x6B8 0x1 0x1 +#define IOMUXC_GPIO_AD_30_FLEXCAN2_TX 0x184 0x3C8 0x0 0x2 0x0 +#define IOMUXC_GPIO_AD_30_ENET_TX_DATA00 0x184 0x3C8 0x0 0x3 0x0 +#define IOMUXC_GPIO_AD_30_LPUART3_TXD 0x184 0x3C8 0x0 0x4 0x0 +#define IOMUXC_GPIO_AD_30_GPIO_MUX3_IO29 0x184 0x3C8 0x0 0x5 0x0 +#define IOMUXC_GPIO_AD_30_KPP_ROW02 0x184 0x3C8 0x0 0x6 0x0 +#define IOMUXC_GPIO_AD_30_FLEXIO2_D30 0x184 0x3C8 0x0 0x8 0x0 +#define IOMUXC_GPIO_AD_30_WDOG2_RESET_B_DEB 0x184 0x3C8 0x0 0x9 0x0 +#define IOMUXC_GPIO_AD_30_GPIO9_IO29 0x184 0x3C8 0x0 0xA 0x0 + +#define IOMUXC_GPIO_AD_31_LPSPI1_SIN 0x188 0x3CC 0x5D4 0x0 0x1 +#define IOMUXC_GPIO_AD_31_USB_OTG2_PWR 0x188 0x3CC 0x0 0x1 0x0 +#define IOMUXC_GPIO_AD_31_FLEXCAN2_RX 0x188 0x3CC 0x49C 0x2 0x1 +#define IOMUXC_GPIO_AD_31_ENET_TX_DATA01 0x188 0x3CC 0x0 0x3 0x0 +#define IOMUXC_GPIO_AD_31_LPUART3_RXD 0x188 0x3CC 0x0 0x4 0x0 +#define IOMUXC_GPIO_AD_31_GPIO_MUX3_IO30 0x188 0x3CC 0x0 0x5 0x0 +#define IOMUXC_GPIO_AD_31_KPP_COL02 0x188 0x3CC 0x0 0x6 0x0 +#define IOMUXC_GPIO_AD_31_FLEXIO2_D31 0x188 0x3CC 0x0 0x8 0x0 +#define IOMUXC_GPIO_AD_31_WDOG1_RESET_B_DEB 0x188 0x3CC 0x0 0x9 0x0 +#define IOMUXC_GPIO_AD_31_GPIO9_IO30 0x188 0x3CC 0x0 0xA 0x0 + +#define IOMUXC_GPIO_AD_32_GPIO9_IO31 0x18C 0x3D0 0x0 0xA 0x0 +#define IOMUXC_GPIO_AD_32_LPI2C1_SCL 0x18C 0x3D0 0x5AC 0x0 0x1 +#define IOMUXC_GPIO_AD_32_USBPHY2_OTG_ID 0x18C 0x3D0 0x6C4 0x1 0x1 +#define IOMUXC_GPIO_AD_32_PGMC_PMIC_RDY 0x18C 0x3D0 0x0 0x2 0x0 +#define IOMUXC_GPIO_AD_32_ENET_MDC 0x18C 0x3D0 0x0 0x3 0x0 +#define IOMUXC_GPIO_AD_32_USDHC1_CD_B 0x18C 0x3D0 0x6C8 0x4 0x0 +#define IOMUXC_GPIO_AD_32_GPIO_MUX3_IO31 0x18C 0x3D0 0x0 0x5 0x0 +#define IOMUXC_GPIO_AD_32_KPP_ROW01 0x18C 0x3D0 0x0 0x6 0x0 +#define IOMUXC_GPIO_AD_32_LPUART10_TXD 0x18C 0x3D0 0x628 0x8 0x1 +#define IOMUXC_GPIO_AD_32_ENET_1G_MDC 0x18C 0x3D0 0x0 0x9 0x0 + +#define IOMUXC_GPIO_AD_33_LPI2C1_SDA 0x190 0x3D4 0x5B0 0x0 0x1 +#define IOMUXC_GPIO_AD_33_USBPHY1_OTG_ID 0x190 0x3D4 0x6C0 0x1 0x1 +#define IOMUXC_GPIO_AD_33_XBAR1_INOUT17 0x190 0x3D4 0x0 0x2 0x0 +#define IOMUXC_GPIO_AD_33_ENET_MDIO 0x190 0x3D4 0x4AC 0x3 0x1 +#define IOMUXC_GPIO_AD_33_USDHC1_WP 0x190 0x3D4 0x6CC 0x4 0x0 +#define IOMUXC_GPIO_AD_33_GPIO_MUX4_IO00 0x190 0x3D4 0x0 0x5 0x0 +#define IOMUXC_GPIO_AD_33_KPP_COL01 0x190 0x3D4 0x0 0x6 0x0 +#define IOMUXC_GPIO_AD_33_LPUART10_RXD 0x190 0x3D4 0x624 0x8 0x1 +#define IOMUXC_GPIO_AD_33_ENET_1G_MDIO 0x190 0x3D4 0x4C8 0x9 0x3 +#define IOMUXC_GPIO_AD_33_GPIO10_IO00 0x190 0x3D4 0x0 0xA 0x0 + +#define IOMUXC_GPIO_AD_34_ENET_1G_1588_EVENT0_IN 0x194 0x3D8 0x0 0x0 0x0 +#define IOMUXC_GPIO_AD_34_USB_OTG1_PWR 0x194 0x3D8 0x0 0x1 0x0 +#define IOMUXC_GPIO_AD_34_XBAR1_INOUT18 0x194 0x3D8 0x0 0x2 0x0 +#define IOMUXC_GPIO_AD_34_ENET_1588_EVENT0_IN 0x194 0x3D8 0x0 0x3 0x0 +#define IOMUXC_GPIO_AD_34_USDHC1_VSELECT 0x194 0x3D8 0x0 0x4 0x0 +#define IOMUXC_GPIO_AD_34_GPIO_MUX4_IO01 0x194 0x3D8 0x0 0x5 0x0 +#define IOMUXC_GPIO_AD_34_KPP_ROW00 0x194 0x3D8 0x0 0x6 0x0 +#define IOMUXC_GPIO_AD_34_LPUART10_CTS_B 0x194 0x3D8 0x0 0x8 0x0 +#define IOMUXC_GPIO_AD_34_WDOG1_ANY 0x194 0x3D8 0x0 0x9 0x0 +#define IOMUXC_GPIO_AD_34_GPIO10_IO01 0x194 0x3D8 0x0 0xA 0x0 + +#define IOMUXC_GPIO_AD_35_GPIO10_IO02 0x198 0x3DC 0x0 0xA 0x0 +#define IOMUXC_GPIO_AD_35_ENET_1G_1588_EVENT0_OUT 0x198 0x3DC 0x0 0x0 0x0 +#define IOMUXC_GPIO_AD_35_USB_OTG1_OC 0x198 0x3DC 0x6BC 0x1 0x1 +#define IOMUXC_GPIO_AD_35_XBAR1_INOUT19 0x198 0x3DC 0x0 0x2 0x0 +#define IOMUXC_GPIO_AD_35_ENET_1588_EVENT0_OUT 0x198 0x3DC 0x0 0x3 0x0 +#define IOMUXC_GPIO_AD_35_USDHC1_RESET_B 0x198 0x3DC 0x0 0x4 0x0 +#define IOMUXC_GPIO_AD_35_GPIO_MUX4_IO02 0x198 0x3DC 0x0 0x5 0x0 +#define IOMUXC_GPIO_AD_35_KPP_COL00 0x198 0x3DC 0x0 0x6 0x0 +#define IOMUXC_GPIO_AD_35_LPUART10_RTS_B 0x198 0x3DC 0x0 0x8 0x0 +#define IOMUXC_GPIO_AD_35_FLEXSPI1_B_SS1_B 0x198 0x3DC 0x0 0x9 0x0 + +#define IOMUXC_GPIO_SD_B1_00_USDHC1_CMD 0x19C 0x3E0 0x0 0x0 0x0 +#define IOMUXC_GPIO_SD_B1_00_XBAR1_INOUT20 0x19C 0x3E0 0x6D8 0x2 0x1 +#define IOMUXC_GPIO_SD_B1_00_GPT4_CAPTURE1 0x19C 0x3E0 0x0 0x3 0x0 +#define IOMUXC_GPIO_SD_B1_00_GPIO_MUX4_IO03 0x19C 0x3E0 0x0 0x5 0x0 +#define IOMUXC_GPIO_SD_B1_00_FLEXSPI2_A_SS0_B 0x19C 0x3E0 0x0 0x6 0x0 +#define IOMUXC_GPIO_SD_B1_00_KPP_ROW07 0x19C 0x3E0 0x5A8 0x8 0x1 +#define IOMUXC_GPIO_SD_B1_00_GPIO10_IO03 0x19C 0x3E0 0x0 0xA 0x0 + +#define IOMUXC_GPIO_SD_B1_01_USDHC1_CLK 0x1A0 0x3E4 0x0 0x0 0x0 +#define IOMUXC_GPIO_SD_B1_01_XBAR1_INOUT21 0x1A0 0x3E4 0x6DC 0x2 0x1 +#define IOMUXC_GPIO_SD_B1_01_GPT4_CAPTURE2 0x1A0 0x3E4 0x0 0x3 0x0 +#define IOMUXC_GPIO_SD_B1_01_GPIO_MUX4_IO04 0x1A0 0x3E4 0x0 0x5 0x0 +#define IOMUXC_GPIO_SD_B1_01_FLEXSPI2_A_SCLK 0x1A0 0x3E4 0x58C 0x6 0x1 +#define IOMUXC_GPIO_SD_B1_01_KPP_COL07 0x1A0 0x3E4 0x5A0 0x8 0x1 +#define IOMUXC_GPIO_SD_B1_01_GPIO10_IO04 0x1A0 0x3E4 0x0 0xA 0x0 + +#define IOMUXC_GPIO_SD_B1_02_GPIO10_IO05 0x1A4 0x3E8 0x0 0xA 0x0 +#define IOMUXC_GPIO_SD_B1_02_USDHC1_DATA0 0x1A4 0x3E8 0x0 0x0 0x0 +#define IOMUXC_GPIO_SD_B1_02_XBAR1_INOUT22 0x1A4 0x3E8 0x6E0 0x2 0x1 +#define IOMUXC_GPIO_SD_B1_02_GPT4_COMPARE1 0x1A4 0x3E8 0x0 0x3 0x0 +#define IOMUXC_GPIO_SD_B1_02_GPIO_MUX4_IO05 0x1A4 0x3E8 0x0 0x5 0x0 +#define IOMUXC_GPIO_SD_B1_02_FLEXSPI2_A_DATA00 0x1A4 0x3E8 0x57C 0x6 0x1 +#define IOMUXC_GPIO_SD_B1_02_KPP_ROW06 0x1A4 0x3E8 0x5A4 0x8 0x1 +#define IOMUXC_GPIO_SD_B1_02_FLEXSPI1_A_SS1_B 0x1A4 0x3E8 0x0 0x9 0x0 + +#define IOMUXC_GPIO_SD_B1_03_USDHC1_DATA1 0x1A8 0x3EC 0x0 0x0 0x0 +#define IOMUXC_GPIO_SD_B1_03_XBAR1_INOUT23 0x1A8 0x3EC 0x6E4 0x2 0x1 +#define IOMUXC_GPIO_SD_B1_03_GPT4_COMPARE2 0x1A8 0x3EC 0x0 0x3 0x0 +#define IOMUXC_GPIO_SD_B1_03_GPIO_MUX4_IO06 0x1A8 0x3EC 0x0 0x5 0x0 +#define IOMUXC_GPIO_SD_B1_03_FLEXSPI2_A_DATA01 0x1A8 0x3EC 0x580 0x6 0x1 +#define IOMUXC_GPIO_SD_B1_03_KPP_COL06 0x1A8 0x3EC 0x59C 0x8 0x1 +#define IOMUXC_GPIO_SD_B1_03_FLEXSPI1_B_SS1_B 0x1A8 0x3EC 0x0 0x9 0x0 +#define IOMUXC_GPIO_SD_B1_03_GPIO10_IO06 0x1A8 0x3EC 0x0 0xA 0x0 + +#define IOMUXC_GPIO_SD_B1_04_USDHC1_DATA2 0x1AC 0x3F0 0x0 0x0 0x0 +#define IOMUXC_GPIO_SD_B1_04_XBAR1_INOUT24 0x1AC 0x3F0 0x6E8 0x2 0x1 +#define IOMUXC_GPIO_SD_B1_04_GPT4_COMPARE3 0x1AC 0x3F0 0x0 0x3 0x0 +#define IOMUXC_GPIO_SD_B1_04_GPIO_MUX4_IO07 0x1AC 0x3F0 0x0 0x5 0x0 +#define IOMUXC_GPIO_SD_B1_04_FLEXSPI2_A_DATA02 0x1AC 0x3F0 0x584 0x6 0x1 +#define IOMUXC_GPIO_SD_B1_04_FLEXSPI1_B_SS0_B 0x1AC 0x3F0 0x0 0x8 0x0 +#define IOMUXC_GPIO_SD_B1_04_ENET_QOS_1588_EVENT2_AUX_IN 0x1AC 0x3F0 0x0 0x9 0x0 +#define IOMUXC_GPIO_SD_B1_04_GPIO10_IO07 0x1AC 0x3F0 0x0 0xA 0x0 + +#define IOMUXC_GPIO_SD_B1_05_GPIO10_IO08 0x1B0 0x3F4 0x0 0xA 0x0 +#define IOMUXC_GPIO_SD_B1_05_USDHC1_DATA3 0x1B0 0x3F4 0x0 0x0 0x0 +#define IOMUXC_GPIO_SD_B1_05_XBAR1_INOUT25 0x1B0 0x3F4 0x6EC 0x2 0x1 +#define IOMUXC_GPIO_SD_B1_05_GPT4_CLK 0x1B0 0x3F4 0x0 0x3 0x0 +#define IOMUXC_GPIO_SD_B1_05_GPIO_MUX4_IO08 0x1B0 0x3F4 0x0 0x5 0x0 +#define IOMUXC_GPIO_SD_B1_05_FLEXSPI2_A_DATA03 0x1B0 0x3F4 0x588 0x6 0x1 +#define IOMUXC_GPIO_SD_B1_05_FLEXSPI1_B_DQS 0x1B0 0x3F4 0x0 0x8 0x0 +#define IOMUXC_GPIO_SD_B1_05_ENET_QOS_1588_EVENT3_AUX_IN 0x1B0 0x3F4 0x0 0x9 0x0 + +#define IOMUXC_GPIO_SD_B2_00_GPIO10_IO09 0x1B4 0x3F8 0x0 0xA 0x0 +#define IOMUXC_GPIO_SD_B2_00_USDHC2_DATA3 0x1B4 0x3F8 0x0 0x0 0x0 +#define IOMUXC_GPIO_SD_B2_00_FLEXSPI1_B_DATA03 0x1B4 0x3F8 0x570 0x1 0x1 +#define IOMUXC_GPIO_SD_B2_00_ENET_1G_RX_EN 0x1B4 0x3F8 0x4E0 0x2 0x1 +#define IOMUXC_GPIO_SD_B2_00_LPUART9_TXD 0x1B4 0x3F8 0x0 0x3 0x0 +#define IOMUXC_GPIO_SD_B2_00_LPSPI4_SCK 0x1B4 0x3F8 0x610 0x4 0x0 +#define IOMUXC_GPIO_SD_B2_00_GPIO_MUX4_IO09 0x1B4 0x3F8 0x0 0x5 0x0 + +#define IOMUXC_GPIO_SD_B2_01_USDHC2_DATA2 0x1B8 0x3FC 0x0 0x0 0x0 +#define IOMUXC_GPIO_SD_B2_01_FLEXSPI1_B_DATA02 0x1B8 0x3FC 0x56C 0x1 0x1 +#define IOMUXC_GPIO_SD_B2_01_ENET_1G_RX_CLK 0x1B8 0x3FC 0x4CC 0x2 0x1 +#define IOMUXC_GPIO_SD_B2_01_LPUART9_RXD 0x1B8 0x3FC 0x0 0x3 0x0 +#define IOMUXC_GPIO_SD_B2_01_LPSPI4_PCS0 0x1B8 0x3FC 0x60C 0x4 0x0 +#define IOMUXC_GPIO_SD_B2_01_GPIO_MUX4_IO10 0x1B8 0x3FC 0x0 0x5 0x0 +#define IOMUXC_GPIO_SD_B2_01_GPIO10_IO10 0x1B8 0x3FC 0x0 0xA 0x0 + +#define IOMUXC_GPIO_SD_B2_02_GPIO10_IO11 0x1BC 0x400 0x0 0xA 0x0 +#define IOMUXC_GPIO_SD_B2_02_USDHC2_DATA1 0x1BC 0x400 0x0 0x0 0x0 +#define IOMUXC_GPIO_SD_B2_02_FLEXSPI1_B_DATA01 0x1BC 0x400 0x568 0x1 0x1 +#define IOMUXC_GPIO_SD_B2_02_ENET_1G_RX_DATA00 0x1BC 0x400 0x4D0 0x2 0x1 +#define IOMUXC_GPIO_SD_B2_02_LPUART9_CTS_B 0x1BC 0x400 0x0 0x3 0x0 +#define IOMUXC_GPIO_SD_B2_02_LPSPI4_SOUT 0x1BC 0x400 0x618 0x4 0x0 +#define IOMUXC_GPIO_SD_B2_02_GPIO_MUX4_IO11 0x1BC 0x400 0x0 0x5 0x0 + +#define IOMUXC_GPIO_SD_B2_03_GPIO10_IO12 0x1C0 0x404 0x0 0xA 0x0 +#define IOMUXC_GPIO_SD_B2_03_USDHC2_DATA0 0x1C0 0x404 0x0 0x0 0x0 +#define IOMUXC_GPIO_SD_B2_03_FLEXSPI1_B_DATA00 0x1C0 0x404 0x564 0x1 0x1 +#define IOMUXC_GPIO_SD_B2_03_ENET_1G_RX_DATA01 0x1C0 0x404 0x4D4 0x2 0x1 +#define IOMUXC_GPIO_SD_B2_03_LPUART9_RTS_B 0x1C0 0x404 0x0 0x3 0x0 +#define IOMUXC_GPIO_SD_B2_03_LPSPI4_SIN 0x1C0 0x404 0x614 0x4 0x0 +#define IOMUXC_GPIO_SD_B2_03_GPIO_MUX4_IO12 0x1C0 0x404 0x0 0x5 0x0 + +#define IOMUXC_GPIO_SD_B2_04_USDHC2_CLK 0x1C4 0x408 0x0 0x0 0x0 +#define IOMUXC_GPIO_SD_B2_04_FLEXSPI1_B_SCLK 0x1C4 0x408 0x578 0x1 0x1 +#define IOMUXC_GPIO_SD_B2_04_ENET_1G_RX_DATA02 0x1C4 0x408 0x4D8 0x2 0x1 +#define IOMUXC_GPIO_SD_B2_04_FLEXSPI1_A_SS1_B 0x1C4 0x408 0x0 0x3 0x0 +#define IOMUXC_GPIO_SD_B2_04_LPSPI4_PCS1 0x1C4 0x408 0x0 0x4 0x0 +#define IOMUXC_GPIO_SD_B2_04_GPIO_MUX4_IO13 0x1C4 0x408 0x0 0x5 0x0 +#define IOMUXC_GPIO_SD_B2_04_GPIO10_IO13 0x1C4 0x408 0x0 0xA 0x0 + +#define IOMUXC_GPIO_SD_B2_05_GPIO10_IO14 0x1C8 0x40C 0x0 0xA 0x0 +#define IOMUXC_GPIO_SD_B2_05_USDHC2_CMD 0x1C8 0x40C 0x0 0x0 0x0 +#define IOMUXC_GPIO_SD_B2_05_FLEXSPI1_A_DQS 0x1C8 0x40C 0x550 0x1 0x2 +#define IOMUXC_GPIO_SD_B2_05_ENET_1G_RX_DATA03 0x1C8 0x40C 0x4DC 0x2 0x1 +#define IOMUXC_GPIO_SD_B2_05_FLEXSPI1_B_SS0_B 0x1C8 0x40C 0x0 0x3 0x0 +#define IOMUXC_GPIO_SD_B2_05_LPSPI4_PCS2 0x1C8 0x40C 0x0 0x4 0x0 +#define IOMUXC_GPIO_SD_B2_05_GPIO_MUX4_IO14 0x1C8 0x40C 0x0 0x5 0x0 + +#define IOMUXC_GPIO_SD_B2_06_GPIO10_IO15 0x1CC 0x410 0x0 0xA 0x0 +#define IOMUXC_GPIO_SD_B2_06_USDHC2_RESET_B 0x1CC 0x410 0x0 0x0 0x0 +#define IOMUXC_GPIO_SD_B2_06_FLEXSPI1_A_SS0_B 0x1CC 0x410 0x0 0x1 0x0 +#define IOMUXC_GPIO_SD_B2_06_ENET_1G_TX_DATA03 0x1CC 0x410 0x0 0x2 0x0 +#define IOMUXC_GPIO_SD_B2_06_LPSPI4_PCS3 0x1CC 0x410 0x0 0x3 0x0 +#define IOMUXC_GPIO_SD_B2_06_GPT6_CAPTURE1 0x1CC 0x410 0x0 0x4 0x0 +#define IOMUXC_GPIO_SD_B2_06_GPIO_MUX4_IO15 0x1CC 0x410 0x0 0x5 0x0 + +#define IOMUXC_GPIO_SD_B2_07_USDHC2_STROBE 0x1D0 0x414 0x0 0x0 0x0 +#define IOMUXC_GPIO_SD_B2_07_FLEXSPI1_A_SCLK 0x1D0 0x414 0x574 0x1 0x1 +#define IOMUXC_GPIO_SD_B2_07_ENET_1G_TX_DATA02 0x1D0 0x414 0x0 0x2 0x0 +#define IOMUXC_GPIO_SD_B2_07_LPUART3_CTS_B 0x1D0 0x414 0x0 0x3 0x0 +#define IOMUXC_GPIO_SD_B2_07_GPT6_CAPTURE2 0x1D0 0x414 0x0 0x4 0x0 +#define IOMUXC_GPIO_SD_B2_07_GPIO_MUX4_IO16 0x1D0 0x414 0x0 0x5 0x0 +#define IOMUXC_GPIO_SD_B2_07_LPSPI2_SCK 0x1D0 0x414 0x5E4 0x6 0x1 +#define IOMUXC_GPIO_SD_B2_07_ENET_TX_ER 0x1D0 0x414 0x0 0x8 0x0 +#define IOMUXC_GPIO_SD_B2_07_ENET_QOS_REF_CLK 0x1D0 0x414 0x4A0 0x9 0x1 +#define IOMUXC_GPIO_SD_B2_07_GPIO10_IO16 0x1D0 0x414 0x0 0xA 0x0 + +#define IOMUXC_GPIO_SD_B2_08_GPIO10_IO17 0x1D4 0x418 0x0 0xA 0x0 +#define IOMUXC_GPIO_SD_B2_08_USDHC2_DATA4 0x1D4 0x418 0x0 0x0 0x0 +#define IOMUXC_GPIO_SD_B2_08_FLEXSPI1_A_DATA00 0x1D4 0x418 0x554 0x1 0x1 +#define IOMUXC_GPIO_SD_B2_08_ENET_1G_TX_DATA01 0x1D4 0x418 0x0 0x2 0x0 +#define IOMUXC_GPIO_SD_B2_08_LPUART3_RTS_B 0x1D4 0x418 0x0 0x3 0x0 +#define IOMUXC_GPIO_SD_B2_08_GPT6_COMPARE1 0x1D4 0x418 0x0 0x4 0x0 +#define IOMUXC_GPIO_SD_B2_08_GPIO_MUX4_IO17 0x1D4 0x418 0x0 0x5 0x0 +#define IOMUXC_GPIO_SD_B2_08_LPSPI2_PCS0 0x1D4 0x418 0x5DC 0x6 0x1 + +#define IOMUXC_GPIO_SD_B2_09_GPIO10_IO18 0x1D8 0x41C 0x0 0xA 0x0 +#define IOMUXC_GPIO_SD_B2_09_USDHC2_DATA5 0x1D8 0x41C 0x0 0x0 0x0 +#define IOMUXC_GPIO_SD_B2_09_FLEXSPI1_A_DATA01 0x1D8 0x41C 0x558 0x1 0x1 +#define IOMUXC_GPIO_SD_B2_09_ENET_1G_TX_DATA00 0x1D8 0x41C 0x0 0x2 0x0 +#define IOMUXC_GPIO_SD_B2_09_LPUART5_CTS_B 0x1D8 0x41C 0x0 0x3 0x0 +#define IOMUXC_GPIO_SD_B2_09_GPT6_COMPARE2 0x1D8 0x41C 0x0 0x4 0x0 +#define IOMUXC_GPIO_SD_B2_09_GPIO_MUX4_IO18 0x1D8 0x41C 0x0 0x5 0x0 +#define IOMUXC_GPIO_SD_B2_09_LPSPI2_SOUT 0x1D8 0x41C 0x5EC 0x6 0x1 + +#define IOMUXC_GPIO_SD_B2_10_GPIO10_IO19 0x1DC 0x420 0x0 0xA 0x0 +#define IOMUXC_GPIO_SD_B2_10_USDHC2_DATA6 0x1DC 0x420 0x0 0x0 0x0 +#define IOMUXC_GPIO_SD_B2_10_FLEXSPI1_A_DATA02 0x1DC 0x420 0x55C 0x1 0x1 +#define IOMUXC_GPIO_SD_B2_10_ENET_1G_TX_EN 0x1DC 0x420 0x0 0x2 0x0 +#define IOMUXC_GPIO_SD_B2_10_LPUART5_RTS_B 0x1DC 0x420 0x0 0x3 0x0 +#define IOMUXC_GPIO_SD_B2_10_GPT6_COMPARE3 0x1DC 0x420 0x0 0x4 0x0 +#define IOMUXC_GPIO_SD_B2_10_GPIO_MUX4_IO19 0x1DC 0x420 0x0 0x5 0x0 +#define IOMUXC_GPIO_SD_B2_10_LPSPI2_SIN 0x1DC 0x420 0x5E8 0x6 0x1 + +#define IOMUXC_GPIO_SD_B2_11_USDHC2_DATA7 0x1E0 0x424 0x0 0x0 0x0 +#define IOMUXC_GPIO_SD_B2_11_FLEXSPI1_A_DATA03 0x1E0 0x424 0x560 0x1 0x1 +#define IOMUXC_GPIO_SD_B2_11_ENET_1G_TX_CLK_IO 0x1E0 0x424 0x4E8 0x2 0x1 +#define IOMUXC_GPIO_SD_B2_11_ENET_1G_REF_CLK 0x1E0 0x424 0x4C4 0x3 0x1 +#define IOMUXC_GPIO_SD_B2_11_GPT6_CLK 0x1E0 0x424 0x0 0x4 0x0 +#define IOMUXC_GPIO_SD_B2_11_GPIO_MUX4_IO20 0x1E0 0x424 0x0 0x5 0x0 +#define IOMUXC_GPIO_SD_B2_11_LPSPI2_PCS1 0x1E0 0x424 0x5E0 0x6 0x1 +#define IOMUXC_GPIO_SD_B2_11_GPIO10_IO20 0x1E0 0x424 0x0 0xA 0x0 + +#define IOMUXC_GPIO_DISP_B1_00_VIDEO_MUX_LCDIF_CLK 0x1E4 0x428 0x0 0x0 0x0 +#define IOMUXC_GPIO_DISP_B1_00_ENET_1G_RX_EN 0x1E4 0x428 0x4E0 0x1 0x2 +#define IOMUXC_GPIO_DISP_B1_00_TMR1_TIMER0 0x1E4 0x428 0x63C 0x3 0x2 +#define IOMUXC_GPIO_DISP_B1_00_XBAR1_INOUT26 0x1E4 0x428 0x6F0 0x4 0x1 +#define IOMUXC_GPIO_DISP_B1_00_GPIO_MUX4_IO21 0x1E4 0x428 0x0 0x5 0x0 +#define IOMUXC_GPIO_DISP_B1_00_ENET_QOS_RX_EN 0x1E4 0x428 0x4F8 0x8 0x0 +#define IOMUXC_GPIO_DISP_B1_00_GPIO10_IO21 0x1E4 0x428 0x0 0xA 0x0 + +#define IOMUXC_GPIO_DISP_B1_01_VIDEO_MUX_LCDIF_ENABLE 0x1E8 0x42C 0x0 0x0 0x0 +#define IOMUXC_GPIO_DISP_B1_01_ENET_1G_RX_CLK 0x1E8 0x42C 0x4CC 0x1 0x2 +#define IOMUXC_GPIO_DISP_B1_01_ENET_1G_RX_ER 0x1E8 0x42C 0x4E4 0x2 0x1 +#define IOMUXC_GPIO_DISP_B1_01_TMR1_TIMER1 0x1E8 0x42C 0x640 0x3 0x2 +#define IOMUXC_GPIO_DISP_B1_01_XBAR1_INOUT27 0x1E8 0x42C 0x6F4 0x4 0x1 +#define IOMUXC_GPIO_DISP_B1_01_GPIO_MUX4_IO22 0x1E8 0x42C 0x0 0x5 0x0 +#define IOMUXC_GPIO_DISP_B1_01_ENET_QOS_RX_CLK 0x1E8 0x42C 0x0 0x8 0x0 +#define IOMUXC_GPIO_DISP_B1_01_ENET_QOS_RX_ER 0x1E8 0x42C 0x4FC 0x9 0x0 +#define IOMUXC_GPIO_DISP_B1_01_GPIO10_IO22 0x1E8 0x42C 0x0 0xA 0x0 + +#define IOMUXC_GPIO_DISP_B1_02_GPIO10_IO23 0x1EC 0x430 0x0 0xA 0x0 +#define IOMUXC_GPIO_DISP_B1_02_VIDEO_MUX_LCDIF_HSYNC 0x1EC 0x430 0x0 0x0 0x0 +#define IOMUXC_GPIO_DISP_B1_02_ENET_1G_RX_DATA00 0x1EC 0x430 0x4D0 0x1 0x2 +#define IOMUXC_GPIO_DISP_B1_02_LPI2C3_SCL 0x1EC 0x430 0x5BC 0x2 0x0 +#define IOMUXC_GPIO_DISP_B1_02_TMR1_TIMER2 0x1EC 0x430 0x644 0x3 0x1 +#define IOMUXC_GPIO_DISP_B1_02_XBAR1_INOUT28 0x1EC 0x430 0x6F8 0x4 0x1 +#define IOMUXC_GPIO_DISP_B1_02_GPIO_MUX4_IO23 0x1EC 0x430 0x0 0x5 0x0 +#define IOMUXC_GPIO_DISP_B1_02_ENET_QOS_RX_DATA00 0x1EC 0x430 0x4F0 0x8 0x0 +#define IOMUXC_GPIO_DISP_B1_02_LPUART1_TXD 0x1EC 0x430 0x620 0x9 0x1 + +#define IOMUXC_GPIO_DISP_B1_03_VIDEO_MUX_LCDIF_VSYNC 0x1F0 0x434 0x0 0x0 0x0 +#define IOMUXC_GPIO_DISP_B1_03_ENET_1G_RX_DATA01 0x1F0 0x434 0x4D4 0x1 0x2 +#define IOMUXC_GPIO_DISP_B1_03_LPI2C3_SDA 0x1F0 0x434 0x5C0 0x2 0x0 +#define IOMUXC_GPIO_DISP_B1_03_TMR2_TIMER0 0x1F0 0x434 0x648 0x3 0x2 +#define IOMUXC_GPIO_DISP_B1_03_XBAR1_INOUT29 0x1F0 0x434 0x6FC 0x4 0x1 +#define IOMUXC_GPIO_DISP_B1_03_GPIO_MUX4_IO24 0x1F0 0x434 0x0 0x5 0x0 +#define IOMUXC_GPIO_DISP_B1_03_ENET_QOS_RX_DATA01 0x1F0 0x434 0x4F4 0x8 0x0 +#define IOMUXC_GPIO_DISP_B1_03_LPUART1_RXD 0x1F0 0x434 0x61C 0x9 0x1 +#define IOMUXC_GPIO_DISP_B1_03_GPIO10_IO24 0x1F0 0x434 0x0 0xA 0x0 + +#define IOMUXC_GPIO_DISP_B1_04_VIDEO_MUX_LCDIF_DATA00 0x1F4 0x438 0x0 0x0 0x0 +#define IOMUXC_GPIO_DISP_B1_04_ENET_1G_RX_DATA02 0x1F4 0x438 0x4D8 0x1 0x2 +#define IOMUXC_GPIO_DISP_B1_04_LPUART4_RXD 0x1F4 0x438 0x0 0x2 0x0 +#define IOMUXC_GPIO_DISP_B1_04_TMR2_TIMER1 0x1F4 0x438 0x64C 0x3 0x2 +#define IOMUXC_GPIO_DISP_B1_04_XBAR1_INOUT30 0x1F4 0x438 0x700 0x4 0x1 +#define IOMUXC_GPIO_DISP_B1_04_GPIO_MUX4_IO25 0x1F4 0x438 0x0 0x5 0x0 +#define IOMUXC_GPIO_DISP_B1_04_ENET_QOS_RX_DATA02 0x1F4 0x438 0x0 0x8 0x0 +#define IOMUXC_GPIO_DISP_B1_04_LPSPI3_SCK 0x1F4 0x438 0x600 0x9 0x1 +#define IOMUXC_GPIO_DISP_B1_04_GPIO10_IO25 0x1F4 0x438 0x0 0xA 0x0 + +#define IOMUXC_GPIO_DISP_B1_05_GPIO10_IO26 0x1F8 0x43C 0x0 0xA 0x0 +#define IOMUXC_GPIO_DISP_B1_05_VIDEO_MUX_LCDIF_DATA01 0x1F8 0x43C 0x0 0x0 0x0 +#define IOMUXC_GPIO_DISP_B1_05_ENET_1G_RX_DATA03 0x1F8 0x43C 0x4DC 0x1 0x2 +#define IOMUXC_GPIO_DISP_B1_05_LPUART4_CTS_B 0x1F8 0x43C 0x0 0x2 0x0 +#define IOMUXC_GPIO_DISP_B1_05_TMR2_TIMER2 0x1F8 0x43C 0x650 0x3 0x1 +#define IOMUXC_GPIO_DISP_B1_05_XBAR1_INOUT31 0x1F8 0x43C 0x704 0x4 0x1 +#define IOMUXC_GPIO_DISP_B1_05_GPIO_MUX4_IO26 0x1F8 0x43C 0x0 0x5 0x0 +#define IOMUXC_GPIO_DISP_B1_05_ENET_QOS_RX_DATA03 0x1F8 0x43C 0x0 0x8 0x0 +#define IOMUXC_GPIO_DISP_B1_05_LPSPI3_SIN 0x1F8 0x43C 0x604 0x9 0x1 + +#define IOMUXC_GPIO_DISP_B1_06_VIDEO_MUX_LCDIF_DATA02 0x1FC 0x440 0x0 0x0 0x0 +#define IOMUXC_GPIO_DISP_B1_06_ENET_1G_TX_DATA03 0x1FC 0x440 0x0 0x1 0x0 +#define IOMUXC_GPIO_DISP_B1_06_LPUART4_TXD 0x1FC 0x440 0x0 0x2 0x0 +#define IOMUXC_GPIO_DISP_B1_06_TMR3_TIMER0 0x1FC 0x440 0x654 0x3 0x2 +#define IOMUXC_GPIO_DISP_B1_06_XBAR1_INOUT32 0x1FC 0x440 0x708 0x4 0x1 +#define IOMUXC_GPIO_DISP_B1_06_GPIO_MUX4_IO27 0x1FC 0x440 0x0 0x5 0x0 +#define IOMUXC_GPIO_DISP_B1_06_SRC_BT_CFG00 0x1FC 0x440 0x0 0x6 0x0 +#define IOMUXC_GPIO_DISP_B1_06_ENET_QOS_TX_DATA03 0x1FC 0x440 0x0 0x8 0x0 +#define IOMUXC_GPIO_DISP_B1_06_LPSPI3_SOUT 0x1FC 0x440 0x608 0x9 0x1 +#define IOMUXC_GPIO_DISP_B1_06_GPIO10_IO27 0x1FC 0x440 0x0 0xA 0x0 + +#define IOMUXC_GPIO_DISP_B1_07_VIDEO_MUX_LCDIF_DATA03 0x200 0x444 0x0 0x0 0x0 +#define IOMUXC_GPIO_DISP_B1_07_ENET_1G_TX_DATA02 0x200 0x444 0x0 0x1 0x0 +#define IOMUXC_GPIO_DISP_B1_07_LPUART4_RTS_B 0x200 0x444 0x0 0x2 0x0 +#define IOMUXC_GPIO_DISP_B1_07_TMR3_TIMER1 0x200 0x444 0x658 0x3 0x2 +#define IOMUXC_GPIO_DISP_B1_07_XBAR1_INOUT33 0x200 0x444 0x70C 0x4 0x1 +#define IOMUXC_GPIO_DISP_B1_07_GPIO_MUX4_IO28 0x200 0x444 0x0 0x5 0x0 +#define IOMUXC_GPIO_DISP_B1_07_SRC_BT_CFG01 0x200 0x444 0x0 0x6 0x0 +#define IOMUXC_GPIO_DISP_B1_07_ENET_QOS_TX_DATA02 0x200 0x444 0x0 0x8 0x0 +#define IOMUXC_GPIO_DISP_B1_07_LPSPI3_PCS0 0x200 0x444 0x5F0 0x9 0x1 +#define IOMUXC_GPIO_DISP_B1_07_GPIO10_IO28 0x200 0x444 0x0 0xA 0x0 + +#define IOMUXC_GPIO_DISP_B1_08_GPIO10_IO29 0x204 0x448 0x0 0xA 0x0 +#define IOMUXC_GPIO_DISP_B1_08_VIDEO_MUX_LCDIF_DATA04 0x204 0x448 0x0 0x0 0x0 +#define IOMUXC_GPIO_DISP_B1_08_ENET_1G_TX_DATA01 0x204 0x448 0x0 0x1 0x0 +#define IOMUXC_GPIO_DISP_B1_08_USDHC1_CD_B 0x204 0x448 0x6C8 0x2 0x1 +#define IOMUXC_GPIO_DISP_B1_08_TMR3_TIMER2 0x204 0x448 0x65C 0x3 0x1 +#define IOMUXC_GPIO_DISP_B1_08_XBAR1_INOUT34 0x204 0x448 0x710 0x4 0x1 +#define IOMUXC_GPIO_DISP_B1_08_GPIO_MUX4_IO29 0x204 0x448 0x0 0x5 0x0 +#define IOMUXC_GPIO_DISP_B1_08_SRC_BT_CFG02 0x204 0x448 0x0 0x6 0x0 +#define IOMUXC_GPIO_DISP_B1_08_ENET_QOS_TX_DATA01 0x204 0x448 0x0 0x8 0x0 +#define IOMUXC_GPIO_DISP_B1_08_LPSPI3_PCS1 0x204 0x448 0x5F4 0x9 0x1 + +#define IOMUXC_GPIO_DISP_B1_09_VIDEO_MUX_LCDIF_DATA05 0x208 0x44C 0x0 0x0 0x0 +#define IOMUXC_GPIO_DISP_B1_09_ENET_1G_TX_DATA00 0x208 0x44C 0x0 0x1 0x0 +#define IOMUXC_GPIO_DISP_B1_09_USDHC1_WP 0x208 0x44C 0x6CC 0x2 0x1 +#define IOMUXC_GPIO_DISP_B1_09_TMR4_TIMER0 0x208 0x44C 0x660 0x3 0x2 +#define IOMUXC_GPIO_DISP_B1_09_XBAR1_INOUT35 0x208 0x44C 0x714 0x4 0x1 +#define IOMUXC_GPIO_DISP_B1_09_GPIO_MUX4_IO30 0x208 0x44C 0x0 0x5 0x0 +#define IOMUXC_GPIO_DISP_B1_09_SRC_BT_CFG03 0x208 0x44C 0x0 0x6 0x0 +#define IOMUXC_GPIO_DISP_B1_09_ENET_QOS_TX_DATA00 0x208 0x44C 0x0 0x8 0x0 +#define IOMUXC_GPIO_DISP_B1_09_LPSPI3_PCS2 0x208 0x44C 0x5F8 0x9 0x1 +#define IOMUXC_GPIO_DISP_B1_09_GPIO10_IO30 0x208 0x44C 0x0 0xA 0x0 + +#define IOMUXC_GPIO_DISP_B1_10_VIDEO_MUX_LCDIF_DATA06 0x20C 0x450 0x0 0x0 0x0 +#define IOMUXC_GPIO_DISP_B1_10_ENET_1G_TX_EN 0x20C 0x450 0x0 0x1 0x0 +#define IOMUXC_GPIO_DISP_B1_10_USDHC1_RESET_B 0x20C 0x450 0x0 0x2 0x0 +#define IOMUXC_GPIO_DISP_B1_10_TMR4_TIMER1 0x20C 0x450 0x664 0x3 0x2 +#define IOMUXC_GPIO_DISP_B1_10_XBAR1_INOUT36 0x20C 0x450 0x0 0x4 0x0 +#define IOMUXC_GPIO_DISP_B1_10_GPIO_MUX4_IO31 0x20C 0x450 0x0 0x5 0x0 +#define IOMUXC_GPIO_DISP_B1_10_SRC_BT_CFG04 0x20C 0x450 0x0 0x6 0x0 +#define IOMUXC_GPIO_DISP_B1_10_ENET_QOS_TX_EN 0x20C 0x450 0x0 0x8 0x0 +#define IOMUXC_GPIO_DISP_B1_10_LPSPI3_PCS3 0x20C 0x450 0x5FC 0x9 0x1 +#define IOMUXC_GPIO_DISP_B1_10_GPIO10_IO31 0x20C 0x450 0x0 0xA 0x0 + +#define IOMUXC_GPIO_DISP_B1_11_VIDEO_MUX_LCDIF_DATA07 0x210 0x454 0x0 0x0 0x0 +#define IOMUXC_GPIO_DISP_B1_11_ENET_1G_TX_CLK_IO 0x210 0x454 0x4E8 0x1 0x2 +#define IOMUXC_GPIO_DISP_B1_11_ENET_1G_REF_CLK 0x210 0x454 0x4C4 0x2 0x2 +#define IOMUXC_GPIO_DISP_B1_11_TMR4_TIMER2 0x210 0x454 0x668 0x3 0x1 +#define IOMUXC_GPIO_DISP_B1_11_XBAR1_INOUT37 0x210 0x454 0x0 0x4 0x0 +#define IOMUXC_GPIO_DISP_B1_11_GPIO_MUX5_IO00 0x210 0x454 0x0 0x5 0x0 +#define IOMUXC_GPIO_DISP_B1_11_SRC_BT_CFG05 0x210 0x454 0x0 0x6 0x0 +#define IOMUXC_GPIO_DISP_B1_11_ENET_QOS_TX_CLK 0x210 0x454 0x4A4 0x8 0x0 +#define IOMUXC_GPIO_DISP_B1_11_ENET_QOS_REF_CLK 0x210 0x454 0x4A0 0x9 0x2 +#define IOMUXC_GPIO_DISP_B1_11_GPIO11_IO00 0x210 0x454 0x0 0xA 0x0 + +#define IOMUXC_GPIO_DISP_B2_00_GPIO11_IO01 0x214 0x458 0x0 0xA 0x0 +#define IOMUXC_GPIO_DISP_B2_00_VIDEO_MUX_LCDIF_DATA08 0x214 0x458 0x0 0x0 0x0 +#define IOMUXC_GPIO_DISP_B2_00_WDOG1_B 0x214 0x458 0x0 0x1 0x0 +#define IOMUXC_GPIO_DISP_B2_00_MQS_RIGHT 0x214 0x458 0x0 0x2 0x0 +#define IOMUXC_GPIO_DISP_B2_00_ENET_1G_TX_ER 0x214 0x458 0x0 0x3 0x0 +#define IOMUXC_GPIO_DISP_B2_00_SAI1_TX_DATA03 0x214 0x458 0x0 0x4 0x0 +#define IOMUXC_GPIO_DISP_B2_00_GPIO_MUX5_IO01 0x214 0x458 0x0 0x5 0x0 +#define IOMUXC_GPIO_DISP_B2_00_SRC_BT_CFG06 0x214 0x458 0x0 0x6 0x0 +#define IOMUXC_GPIO_DISP_B2_00_ENET_QOS_TX_ER 0x214 0x458 0x0 0x8 0x0 + +#define IOMUXC_GPIO_DISP_B2_01_VIDEO_MUX_LCDIF_DATA09 0x218 0x45C 0x0 0x0 0x0 +#define IOMUXC_GPIO_DISP_B2_01_USDHC1_VSELECT 0x218 0x45C 0x0 0x1 0x0 +#define IOMUXC_GPIO_DISP_B2_01_MQS_LEFT 0x218 0x45C 0x0 0x2 0x0 +#define IOMUXC_GPIO_DISP_B2_01_WDOG2_B 0x218 0x45C 0x0 0x3 0x0 +#define IOMUXC_GPIO_DISP_B2_01_SAI1_TX_DATA02 0x218 0x45C 0x0 0x4 0x0 +#define IOMUXC_GPIO_DISP_B2_01_GPIO_MUX5_IO02 0x218 0x45C 0x0 0x5 0x0 +#define IOMUXC_GPIO_DISP_B2_01_SRC_BT_CFG07 0x218 0x45C 0x0 0x6 0x0 +#define IOMUXC_GPIO_DISP_B2_01_EWM_OUT_B 0x218 0x45C 0x0 0x8 0x0 +#define IOMUXC_GPIO_DISP_B2_01_CCM_ENET_REF_CLK_25M 0x218 0x45C 0x0 0x9 0x0 +#define IOMUXC_GPIO_DISP_B2_01_GPIO11_IO02 0x218 0x45C 0x0 0xA 0x0 + +#define IOMUXC_GPIO_DISP_B2_02_GPIO11_IO03 0x21C 0x460 0x0 0xA 0x0 +#define IOMUXC_GPIO_DISP_B2_02_VIDEO_MUX_LCDIF_DATA10 0x21C 0x460 0x0 0x0 0x0 +#define IOMUXC_GPIO_DISP_B2_02_ENET_TX_DATA00 0x21C 0x460 0x0 0x1 0x0 +#define IOMUXC_GPIO_DISP_B2_02_PIT1_TRIGGER3 0x21C 0x460 0x0 0x2 0x0 +#define IOMUXC_GPIO_DISP_B2_02_ARM_TRACE00 0x21C 0x460 0x0 0x3 0x0 +#define IOMUXC_GPIO_DISP_B2_02_SAI1_TX_DATA01 0x21C 0x460 0x0 0x4 0x0 +#define IOMUXC_GPIO_DISP_B2_02_GPIO_MUX5_IO03 0x21C 0x460 0x0 0x5 0x0 +#define IOMUXC_GPIO_DISP_B2_02_SRC_BT_CFG08 0x21C 0x460 0x0 0x6 0x0 +#define IOMUXC_GPIO_DISP_B2_02_ENET_QOS_TX_DATA00 0x21C 0x460 0x0 0x8 0x0 + +#define IOMUXC_GPIO_DISP_B2_03_GPIO11_IO04 0x220 0x464 0x0 0xA 0x0 +#define IOMUXC_GPIO_DISP_B2_03_VIDEO_MUX_LCDIF_DATA11 0x220 0x464 0x0 0x0 0x0 +#define IOMUXC_GPIO_DISP_B2_03_ENET_TX_DATA01 0x220 0x464 0x0 0x1 0x0 +#define IOMUXC_GPIO_DISP_B2_03_PIT1_TRIGGER2 0x220 0x464 0x0 0x2 0x0 +#define IOMUXC_GPIO_DISP_B2_03_ARM_TRACE01 0x220 0x464 0x0 0x3 0x0 +#define IOMUXC_GPIO_DISP_B2_03_SAI1_MCLK 0x220 0x464 0x66C 0x4 0x1 +#define IOMUXC_GPIO_DISP_B2_03_GPIO_MUX5_IO04 0x220 0x464 0x0 0x5 0x0 +#define IOMUXC_GPIO_DISP_B2_03_SRC_BT_CFG09 0x220 0x464 0x0 0x6 0x0 +#define IOMUXC_GPIO_DISP_B2_03_ENET_QOS_TX_DATA01 0x220 0x464 0x0 0x8 0x0 + +#define IOMUXC_GPIO_DISP_B2_04_VIDEO_MUX_LCDIF_DATA12 0x224 0x468 0x0 0x0 0x0 +#define IOMUXC_GPIO_DISP_B2_04_ENET_TX_EN 0x224 0x468 0x0 0x1 0x0 +#define IOMUXC_GPIO_DISP_B2_04_PIT1_TRIGGER1 0x224 0x468 0x0 0x2 0x0 +#define IOMUXC_GPIO_DISP_B2_04_ARM_TRACE02 0x224 0x468 0x0 0x3 0x0 +#define IOMUXC_GPIO_DISP_B2_04_SAI1_RX_SYNC 0x224 0x468 0x678 0x4 0x1 +#define IOMUXC_GPIO_DISP_B2_04_GPIO_MUX5_IO05 0x224 0x468 0x0 0x5 0x0 +#define IOMUXC_GPIO_DISP_B2_04_SRC_BT_CFG10 0x224 0x468 0x0 0x6 0x0 +#define IOMUXC_GPIO_DISP_B2_04_ENET_QOS_TX_EN 0x224 0x468 0x0 0x8 0x0 +#define IOMUXC_GPIO_DISP_B2_04_GPIO11_IO05 0x224 0x468 0x0 0xA 0x0 + +#define IOMUXC_GPIO_DISP_B2_05_GPIO11_IO06 0x228 0x46C 0x0 0xA 0x0 +#define IOMUXC_GPIO_DISP_B2_05_VIDEO_MUX_LCDIF_DATA13 0x228 0x46C 0x0 0x0 0x0 +#define IOMUXC_GPIO_DISP_B2_05_ENET_TX_CLK 0x228 0x46C 0x4C0 0x1 0x1 +#define IOMUXC_GPIO_DISP_B2_05_ENET_REF_CLK 0x228 0x46C 0x4A8 0x2 0x1 +#define IOMUXC_GPIO_DISP_B2_05_ARM_TRACE03 0x228 0x46C 0x0 0x3 0x0 +#define IOMUXC_GPIO_DISP_B2_05_SAI1_RX_BCLK 0x228 0x46C 0x670 0x4 0x1 +#define IOMUXC_GPIO_DISP_B2_05_GPIO_MUX5_IO06 0x228 0x46C 0x0 0x5 0x0 +#define IOMUXC_GPIO_DISP_B2_05_SRC_BT_CFG11 0x228 0x46C 0x0 0x6 0x0 +#define IOMUXC_GPIO_DISP_B2_05_ENET_QOS_TX_CLK 0x228 0x46C 0x4A4 0x8 0x1 + +#define IOMUXC_GPIO_DISP_B2_06_GPIO11_IO07 0x22C 0x470 0x0 0xA 0x0 +#define IOMUXC_GPIO_DISP_B2_06_VIDEO_MUX_LCDIF_DATA14 0x22C 0x470 0x0 0x0 0x0 +#define IOMUXC_GPIO_DISP_B2_06_ENET_RX_DATA00 0x22C 0x470 0x4B0 0x1 0x1 +#define IOMUXC_GPIO_DISP_B2_06_LPUART7_TXD 0x22C 0x470 0x630 0x2 0x1 +#define IOMUXC_GPIO_DISP_B2_06_ARM_TRACE_CLK 0x22C 0x470 0x0 0x3 0x0 +#define IOMUXC_GPIO_DISP_B2_06_SAI1_RX_DATA00 0x22C 0x470 0x674 0x4 0x1 +#define IOMUXC_GPIO_DISP_B2_06_GPIO_MUX5_IO07 0x22C 0x470 0x0 0x5 0x0 +#define IOMUXC_GPIO_DISP_B2_06_ENET_QOS_RX_DATA00 0x22C 0x470 0x4F0 0x8 0x1 + +#define IOMUXC_GPIO_DISP_B2_07_VIDEO_MUX_LCDIF_DATA15 0x230 0x474 0x0 0x0 0x0 +#define IOMUXC_GPIO_DISP_B2_07_ENET_RX_DATA01 0x230 0x474 0x4B4 0x1 0x1 +#define IOMUXC_GPIO_DISP_B2_07_LPUART7_RXD 0x230 0x474 0x62C 0x2 0x1 +#define IOMUXC_GPIO_DISP_B2_07_ARM_TRACE_SWO 0x230 0x474 0x0 0x3 0x0 +#define IOMUXC_GPIO_DISP_B2_07_SAI1_TX_DATA00 0x230 0x474 0x0 0x4 0x0 +#define IOMUXC_GPIO_DISP_B2_07_GPIO_MUX5_IO08 0x230 0x474 0x0 0x5 0x0 +#define IOMUXC_GPIO_DISP_B2_07_ENET_QOS_RX_DATA01 0x230 0x474 0x4F4 0x8 0x1 +#define IOMUXC_GPIO_DISP_B2_07_GPIO11_IO08 0x230 0x474 0x0 0xA 0x0 + +#define IOMUXC_GPIO_DISP_B2_08_GPIO11_IO09 0x234 0x478 0x0 0xA 0x0 +#define IOMUXC_GPIO_DISP_B2_08_VIDEO_MUX_LCDIF_DATA16 0x234 0x478 0x0 0x0 0x0 +#define IOMUXC_GPIO_DISP_B2_08_ENET_RX_EN 0x234 0x478 0x4B8 0x1 0x1 +#define IOMUXC_GPIO_DISP_B2_08_LPUART8_TXD 0x234 0x478 0x638 0x2 0x1 +#define IOMUXC_GPIO_DISP_B2_08_ARM_CM7_EVENTO 0x234 0x478 0x0 0x3 0x0 +#define IOMUXC_GPIO_DISP_B2_08_SAI1_TX_BCLK 0x234 0x478 0x67C 0x4 0x1 +#define IOMUXC_GPIO_DISP_B2_08_GPIO_MUX5_IO09 0x234 0x478 0x0 0x5 0x0 +#define IOMUXC_GPIO_DISP_B2_08_ENET_QOS_RX_EN 0x234 0x478 0x4F8 0x8 0x1 +#define IOMUXC_GPIO_DISP_B2_08_LPUART1_TXD 0x234 0x478 0x620 0x9 0x2 + +#define IOMUXC_GPIO_DISP_B2_09_GPIO11_IO10 0x238 0x47C 0x0 0xA 0x0 +#define IOMUXC_GPIO_DISP_B2_09_VIDEO_MUX_LCDIF_DATA17 0x238 0x47C 0x0 0x0 0x0 +#define IOMUXC_GPIO_DISP_B2_09_ENET_RX_ER 0x238 0x47C 0x4BC 0x1 0x1 +#define IOMUXC_GPIO_DISP_B2_09_LPUART8_RXD 0x238 0x47C 0x634 0x2 0x1 +#define IOMUXC_GPIO_DISP_B2_09_ARM_CM7_EVENTI 0x238 0x47C 0x0 0x3 0x0 +#define IOMUXC_GPIO_DISP_B2_09_SAI1_TX_SYNC 0x238 0x47C 0x680 0x4 0x1 +#define IOMUXC_GPIO_DISP_B2_09_GPIO_MUX5_IO10 0x238 0x47C 0x0 0x5 0x0 +#define IOMUXC_GPIO_DISP_B2_09_ENET_QOS_RX_ER 0x238 0x47C 0x4FC 0x8 0x1 +#define IOMUXC_GPIO_DISP_B2_09_LPUART1_RXD 0x238 0x47C 0x61C 0x9 0x2 + +#define IOMUXC_GPIO_DISP_B2_10_GPIO11_IO11 0x23C 0x480 0x0 0xA 0x0 +#define IOMUXC_GPIO_DISP_B2_10_VIDEO_MUX_LCDIF_DATA18 0x23C 0x480 0x0 0x0 0x0 +#define IOMUXC_GPIO_DISP_B2_10_EMVSIM2_IO 0x23C 0x480 0x6A8 0x1 0x1 +#define IOMUXC_GPIO_DISP_B2_10_LPUART2_TXD 0x23C 0x480 0x0 0x2 0x0 +#define IOMUXC_GPIO_DISP_B2_10_WDOG2_RESET_B_DEB 0x23C 0x480 0x0 0x3 0x0 +#define IOMUXC_GPIO_DISP_B2_10_XBAR1_INOUT38 0x23C 0x480 0x0 0x4 0x0 +#define IOMUXC_GPIO_DISP_B2_10_GPIO_MUX5_IO11 0x23C 0x480 0x0 0x5 0x0 +#define IOMUXC_GPIO_DISP_B2_10_LPI2C3_SCL 0x23C 0x480 0x5BC 0x6 0x1 +#define IOMUXC_GPIO_DISP_B2_10_ENET_QOS_RX_ER 0x23C 0x480 0x4FC 0x8 0x2 +#define IOMUXC_GPIO_DISP_B2_10_SPDIF_IN 0x23C 0x480 0x6B4 0x9 0x2 + +#define IOMUXC_GPIO_DISP_B2_11_VIDEO_MUX_LCDIF_DATA19 0x240 0x484 0x0 0x0 0x0 +#define IOMUXC_GPIO_DISP_B2_11_EMVSIM2_CLK 0x240 0x484 0x0 0x1 0x0 +#define IOMUXC_GPIO_DISP_B2_11_LPUART2_RXD 0x240 0x484 0x0 0x2 0x0 +#define IOMUXC_GPIO_DISP_B2_11_WDOG1_RESET_B_DEB 0x240 0x484 0x0 0x3 0x0 +#define IOMUXC_GPIO_DISP_B2_11_XBAR1_INOUT39 0x240 0x484 0x0 0x4 0x0 +#define IOMUXC_GPIO_DISP_B2_11_GPIO_MUX5_IO12 0x240 0x484 0x0 0x5 0x0 +#define IOMUXC_GPIO_DISP_B2_11_LPI2C3_SDA 0x240 0x484 0x5C0 0x6 0x1 +#define IOMUXC_GPIO_DISP_B2_11_ENET_QOS_CRS 0x240 0x484 0x0 0x8 0x0 +#define IOMUXC_GPIO_DISP_B2_11_SPDIF_OUT 0x240 0x484 0x0 0x9 0x0 +#define IOMUXC_GPIO_DISP_B2_11_GPIO11_IO12 0x240 0x484 0x0 0xA 0x0 + +#define IOMUXC_GPIO_DISP_B2_12_GPIO11_IO13 0x244 0x488 0x0 0xA 0x0 +#define IOMUXC_GPIO_DISP_B2_12_VIDEO_MUX_LCDIF_DATA20 0x244 0x488 0x0 0x0 0x0 +#define IOMUXC_GPIO_DISP_B2_12_EMVSIM2_RST 0x244 0x488 0x0 0x1 0x0 +#define IOMUXC_GPIO_DISP_B2_12_FLEXCAN1_TX 0x244 0x488 0x0 0x2 0x0 +#define IOMUXC_GPIO_DISP_B2_12_LPUART2_CTS_B 0x244 0x488 0x0 0x3 0x0 +#define IOMUXC_GPIO_DISP_B2_12_XBAR1_INOUT40 0x244 0x488 0x0 0x4 0x0 +#define IOMUXC_GPIO_DISP_B2_12_GPIO_MUX5_IO13 0x244 0x488 0x0 0x5 0x0 +#define IOMUXC_GPIO_DISP_B2_12_LPI2C4_SCL 0x244 0x488 0x5C4 0x6 0x1 +#define IOMUXC_GPIO_DISP_B2_12_ENET_QOS_COL 0x244 0x488 0x0 0x8 0x0 +#define IOMUXC_GPIO_DISP_B2_12_LPSPI4_SCK 0x244 0x488 0x610 0x9 0x1 + +#define IOMUXC_GPIO_DISP_B2_13_GPIO11_IO14 0x248 0x48C 0x0 0xA 0x0 +#define IOMUXC_GPIO_DISP_B2_13_VIDEO_MUX_LCDIF_DATA21 0x248 0x48C 0x0 0x0 0x0 +#define IOMUXC_GPIO_DISP_B2_13_EMVSIM2_SVEN 0x248 0x48C 0x0 0x1 0x0 +#define IOMUXC_GPIO_DISP_B2_13_FLEXCAN1_RX 0x248 0x48C 0x498 0x2 0x1 +#define IOMUXC_GPIO_DISP_B2_13_LPUART2_RTS_B 0x248 0x48C 0x0 0x3 0x0 +#define IOMUXC_GPIO_DISP_B2_13_ENET_REF_CLK 0x248 0x48C 0x4A8 0x4 0x2 +#define IOMUXC_GPIO_DISP_B2_13_GPIO_MUX5_IO14 0x248 0x48C 0x0 0x5 0x0 +#define IOMUXC_GPIO_DISP_B2_13_LPI2C4_SDA 0x248 0x48C 0x5C8 0x6 0x1 +#define IOMUXC_GPIO_DISP_B2_13_ENET_QOS_1588_EVENT0_OUT 0x248 0x48C 0x0 0x8 0x0 +#define IOMUXC_GPIO_DISP_B2_13_LPSPI4_SIN 0x248 0x48C 0x614 0x9 0x1 + +#define IOMUXC_GPIO_DISP_B2_14_GPIO_MUX5_IO15 0x24C 0x490 0x0 0x5 0x0 +#define IOMUXC_GPIO_DISP_B2_14_FLEXCAN1_TX 0x24C 0x490 0x0 0x6 0x0 +#define IOMUXC_GPIO_DISP_B2_14_ENET_QOS_1588_EVENT0_IN 0x24C 0x490 0x0 0x8 0x0 +#define IOMUXC_GPIO_DISP_B2_14_LPSPI4_SOUT 0x24C 0x490 0x618 0x9 0x1 +#define IOMUXC_GPIO_DISP_B2_14_GPIO11_IO15 0x24C 0x490 0x0 0xA 0x0 +#define IOMUXC_GPIO_DISP_B2_14_VIDEO_MUX_LCDIF_DATA22 0x24C 0x490 0x0 0x0 0x0 +#define IOMUXC_GPIO_DISP_B2_14_EMVSIM2_PD 0x24C 0x490 0x6AC 0x1 0x1 +#define IOMUXC_GPIO_DISP_B2_14_WDOG2_B 0x24C 0x490 0x0 0x2 0x0 +#define IOMUXC_GPIO_DISP_B2_14_VIDEO_MUX_EXT_DCIC1 0x24C 0x490 0x0 0x3 0x0 +#define IOMUXC_GPIO_DISP_B2_14_ENET_1G_REF_CLK 0x24C 0x490 0x4C4 0x4 0x3 + +#define IOMUXC_GPIO_DISP_B2_15_VIDEO_MUX_LCDIF_DATA23 0x250 0x494 0x0 0x0 0x0 +#define IOMUXC_GPIO_DISP_B2_15_EMVSIM2_POWER_FAIL 0x250 0x494 0x6B0 0x1 0x1 +#define IOMUXC_GPIO_DISP_B2_15_WDOG1_B 0x250 0x494 0x0 0x2 0x0 +#define IOMUXC_GPIO_DISP_B2_15_VIDEO_MUX_EXT_DCIC2 0x250 0x494 0x0 0x3 0x0 +#define IOMUXC_GPIO_DISP_B2_15_PIT1_TRIGGER0 0x250 0x494 0x0 0x4 0x0 +#define IOMUXC_GPIO_DISP_B2_15_GPIO_MUX5_IO16 0x250 0x494 0x0 0x5 0x0 +#define IOMUXC_GPIO_DISP_B2_15_FLEXCAN1_RX 0x250 0x494 0x498 0x6 0x2 +#define IOMUXC_GPIO_DISP_B2_15_ENET_QOS_1588_EVENT0_AUX_IN 0x250 0x494 0x0 0x8 0x0 +#define IOMUXC_GPIO_DISP_B2_15_LPSPI4_PCS0 0x250 0x494 0x60C 0x9 0x1 +#define IOMUXC_GPIO_DISP_B2_15_GPIO11_IO16 0x250 0x494 0x0 0xA 0x0 + +#endif /* _DT_BINDINGS_PINCTRL_IMXRT1170_PINFUNC_H */ diff --git a/arch/arm/dts/imxrt1170.dtsi b/arch/arm/dts/imxrt1170.dtsi new file mode 100644 index 0000000000..2de775f043 --- /dev/null +++ b/arch/arm/dts/imxrt1170.dtsi @@ -0,0 +1,257 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) 2022 + * Author(s): Jesse Taube + * Giulio Benetti + */ + +#include "armv7-m.dtsi" +#include +#include +#include +#include + +/ { + #address-cells = <1>; + #size-cells = <1>; + + aliases { + gpio0 = &gpio1; + gpio1 = &gpio2; + gpio2 = &gpio3; + gpio3 = &gpio4; + gpio4 = &gpio5; + gpio5 = &gpio6; + gpio6 = &gpio7; + gpio7 = &gpio8; + gpio8 = &gpio9; + gpio9 = &gpio10; + gpio10 = &gpio11; + gpio11 = &gpio12; + gpio12 = &gpio13; + mmc0 = &usdhc1; + serial0 = &lpuart1; + }; + + clocks { + osc: osc { + compatible = "fsl,imx-osc", "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + }; + + rcosc16M: rcosc16M { + compatible = "fsl,imx-osc", "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <16000000>; + }; + + osc32k: osc32k { + compatible = "fsl,imx-osc", "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + }; + + }; + + soc { + semc: semc@400d4000 { + compatible = "fsl,imxrt-semc"; + reg = <0x400d4000 0x4000>; + interrupts = <132>; + clocks = <&clks IMXRT1170_CLK_SEMC>; + pinctrl-0 = <&pinctrl_semc>; + pinctrl-names = "default"; + status = "okay"; + }; + + lpuart1: serial@4007c000 { + compatible = "fsl,imxrt-lpuart"; + reg = <0x4007c000 0x4000>; + interrupts = <20>; + clocks = <&clks IMXRT1170_CLK_LPUART1>; + clock-names = "per"; + status = "disabled"; + }; + + iomuxc: iomuxc@400e8000 { + compatible = "fsl,imxrt-iomuxc"; + reg = <0x400e8000 0x4000>; + fsl,mux_mask = <0x7>; + }; + + anatop: anatop@40c84000 { + compatible = "fsl,imxrt-anatop"; + reg = <0x40c84000 0x4000>; + }; + + clks: ccm@40cc0000 { + compatible = "fsl,imxrt1170-ccm"; + reg = <0x40cc0000 0x4000>; + #clock-cells = <1>; + }; + + usdhc1: usdhc@40418000 { + compatible = "fsl,imxrt-usdhc"; + reg = <0x40418000 0x10000>; + interrupts = <133>; + clocks = <&clks IMXRT1170_CLK_USDHC1>; + clock-names = "per"; + bus-width = <4>; + fsl,tuning-start-tap = <20>; + fsl,tuning-step= <2>; + status = "disabled"; + }; + + gpio1: gpio@4012c000 { + compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio"; + reg = <0x4012c000 0x4000>; + interrupts = <100>, + <101>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio2: gpio@40130000 { + compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio"; + reg = <0x40130000 0x4000>; + interrupts = <102>, + <103>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio3: gpio@40134000 { + compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio"; + reg = <0x40134000 0x4000>; + interrupts = <104>, + <105>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio4: gpio@40138000 { + compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio"; + reg = <0x40138000 0x4000>; + interrupts = <106>, + <107>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio5: gpio@4013c000 { + compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio"; + reg = <0x4013c000 0x4000>; + interrupts = <108>, + <109>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio6: gpio@40140000 { + compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio"; + reg = <0x40140000 0x4000>; + interrupts = <61>, + <62>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio7: gpio@40c5c000 { + compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio"; + reg = <0x40c5c000 0x4000>; + interrupts = <99>, + <99>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio8: gpio@40c60000 { + compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio"; + reg = <0x40c60000 0x4000>; + interrupts = <99>, + <99>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio9: gpio@40c64000 { + compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio"; + reg = <0x40c64000 0x4000>; + interrupts = <99>, + <99>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio10: gpio@40c68000 { + compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio"; + reg = <0x40c68000 0x4000>; + interrupts = <99>, + <99>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio11: gpio@40c6c000 { + compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio"; + reg = <0x40c6c000 0x4000>; + interrupts = <99>, + <99>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio12: gpio@40c70000 { + compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio"; + reg = <0x40c70000 0x4000>; + interrupts = <61>, + <62>; // only cm4 + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio13: gpio@40ca0000 { + compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio"; + reg = <0x40ca0000 0x4000>; + interrupts = <93>, + <93>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpt1: gpt1@400ec000 { + compatible = "fsl,imxrt-gpt"; + reg = <0x400ec000 0x4000>; + interrupts = <119>; + clocks = <&clks IMXRT1170_CLK_GPT1>; + status = "disabled"; + }; + }; +}; diff --git a/arch/arm/dts/px30-u-boot.dtsi b/arch/arm/dts/px30-u-boot.dtsi index f102b2aef4..462eaf68f8 100644 --- a/arch/arm/dts/px30-u-boot.dtsi +++ b/arch/arm/dts/px30-u-boot.dtsi @@ -3,6 +3,8 @@ * (C) Copyright 2019 Rockchip Electronics Co., Ltd */ +#include "rockchip-u-boot.dtsi" + / { aliases { mmc0 = &emmc; diff --git a/arch/arm/dts/r7s72100-gr-peach-u-boot.dts b/arch/arm/dts/r7s72100-gr-peach-u-boot.dts index f48121a9a8..5b176a9acd 100644 --- a/arch/arm/dts/r7s72100-gr-peach-u-boot.dts +++ b/arch/arm/dts/r7s72100-gr-peach-u-boot.dts @@ -46,8 +46,8 @@ }; - rpc: rpc@ee200000 { - compatible = "renesas,rpc-r7s72100", "renesas,rpc"; + rpc: spi@ee200000 { + compatible = "renesas,r7s72100-rpc-if"; reg = <0x3fefa000 0x100>, <0x18000000 0x08000000>; bank-width = <2>; num-cs = <1>; diff --git a/arch/arm/dts/r8a774c0-u-boot.dtsi b/arch/arm/dts/r8a774c0-u-boot.dtsi index af1c86171b..d29610676c 100644 --- a/arch/arm/dts/r8a774c0-u-boot.dtsi +++ b/arch/arm/dts/r8a774c0-u-boot.dtsi @@ -10,8 +10,8 @@ / { soc { - rpc: rpc@ee200000 { - compatible = "renesas,rcar-gen3-rpc", "renesas,rpc-r8a774c0"; + rpc: spi@ee200000 { + compatible = "renesas,r8a774c0-rpc-if", "renesas,rcar-gen3-rpc-if"; reg = <0 0xee200000 0 0x100>, <0 0x08000000 0 0x04000000>; clocks = <&cpg CPG_MOD 917>; bank-width = <2>; diff --git a/arch/arm/dts/r8a77950-u-boot.dtsi b/arch/arm/dts/r8a77950-u-boot.dtsi index 5a11651464..2306c7bab8 100644 --- a/arch/arm/dts/r8a77950-u-boot.dtsi +++ b/arch/arm/dts/r8a77950-u-boot.dtsi @@ -13,8 +13,8 @@ / { soc { - rpc: rpc@ee200000 { - compatible = "renesas,rpc-r8a7795", "renesas,rpc"; + rpc: spi@ee200000 { + compatible = "renesas,r8a7795-rpc-if", "renesas,rcar-gen3-rpc-if"; reg = <0 0xee200000 0 0x100>, <0 0x08000000 0 0>; clocks = <&cpg CPG_MOD 917>; bank-width = <2>; diff --git a/arch/arm/dts/r8a77960-u-boot.dtsi b/arch/arm/dts/r8a77960-u-boot.dtsi index f1cae1c359..f64e5a416b 100644 --- a/arch/arm/dts/r8a77960-u-boot.dtsi +++ b/arch/arm/dts/r8a77960-u-boot.dtsi @@ -13,8 +13,8 @@ / { soc { - rpc: rpc@ee200000 { - compatible = "renesas,rpc-r8a7796", "renesas,rpc"; + rpc: spi@ee200000 { + compatible = "renesas,r8a7796-rpc-if", "renesas,rcar-gen3-rpc-if"; reg = <0 0xee200000 0 0x100>, <0 0x08000000 0 0>; clocks = <&cpg CPG_MOD 917>; bank-width = <2>; diff --git a/arch/arm/dts/r8a77965-u-boot.dtsi b/arch/arm/dts/r8a77965-u-boot.dtsi index 9cc6f20537..c4abcc5a9b 100644 --- a/arch/arm/dts/r8a77965-u-boot.dtsi +++ b/arch/arm/dts/r8a77965-u-boot.dtsi @@ -13,8 +13,8 @@ / { soc { - rpc: rpc@ee200000 { - compatible = "renesas,rpc-r8a77965", "renesas,rpc"; + rpc: spi@ee200000 { + compatible = "renesas,r8a77965-rpc-if", "renesas,rcar-gen3-rpc-if"; reg = <0 0xee200000 0 0x100>, <0 0x08000000 0 0>; clocks = <&cpg CPG_MOD 917>; bank-width = <2>; diff --git a/arch/arm/dts/r8a77970-u-boot.dtsi b/arch/arm/dts/r8a77970-u-boot.dtsi index ac3c6be4ad..614caa9e9c 100644 --- a/arch/arm/dts/r8a77970-u-boot.dtsi +++ b/arch/arm/dts/r8a77970-u-boot.dtsi @@ -13,8 +13,8 @@ / { soc { - rpc: rpc@ee200000 { - compatible = "renesas,rpc-r8a77970", "renesas,rpc"; + rpc: spi@ee200000 { + compatible = "renesas,r8a77970-rpc-if", "renesas,rcar-gen3-rpc-if"; reg = <0 0xee200000 0 0x100>, <0 0x08000000 0 0>; clocks = <&cpg CPG_MOD 917>; bank-width = <2>; diff --git a/arch/arm/dts/r8a77980-u-boot.dtsi b/arch/arm/dts/r8a77980-u-boot.dtsi index 365d40ac49..54f01c926d 100644 --- a/arch/arm/dts/r8a77980-u-boot.dtsi +++ b/arch/arm/dts/r8a77980-u-boot.dtsi @@ -13,8 +13,8 @@ / { soc { - rpc: rpc@ee200000 { - compatible = "renesas,rpc-r8a77980", "renesas,rpc"; + rpc: spi@ee200000 { + compatible = "renesas,r8a77980-rpc-if", "renesas,rcar-gen3-rpc-if"; reg = <0 0xee200000 0 0x100>, <0 0x08000000 0 0>; clocks = <&cpg CPG_MOD 917>; bank-width = <2>; diff --git a/arch/arm/dts/r8a77990-u-boot.dtsi b/arch/arm/dts/r8a77990-u-boot.dtsi index 6655abe875..50bbbe1864 100644 --- a/arch/arm/dts/r8a77990-u-boot.dtsi +++ b/arch/arm/dts/r8a77990-u-boot.dtsi @@ -9,8 +9,8 @@ / { soc { - rpc: rpc@ee200000 { - compatible = "renesas,rpc-r8a77990", "renesas,rpc"; + rpc: spi@ee200000 { + compatible = "renesas,r8a77990-rpc-if", "renesas,rcar-gen3-rpc-if"; reg = <0 0xee200000 0 0x100>, <0 0x08000000 0 0>; clocks = <&cpg CPG_MOD 917>; bank-width = <2>; diff --git a/arch/arm/dts/r8a77995-u-boot.dtsi b/arch/arm/dts/r8a77995-u-boot.dtsi index 0917a80f09..347b59ac42 100644 --- a/arch/arm/dts/r8a77995-u-boot.dtsi +++ b/arch/arm/dts/r8a77995-u-boot.dtsi @@ -9,8 +9,8 @@ / { soc { - rpc: rpc@ee200000 { - compatible = "renesas,rpc-r8a77995", "renesas,rpc"; + rpc: spi@ee200000 { + compatible = "renesas,r8a77995-rpc-if", "renesas,rcar-gen3-rpc-if"; reg = <0 0xee200000 0 0x100>, <0 0x08000000 0 0>; clocks = <&cpg CPG_MOD 917>; bank-width = <2>; diff --git a/arch/arm/dts/r8a779a0-u-boot.dtsi b/arch/arm/dts/r8a779a0-u-boot.dtsi index 83dbe3f20e..9f2772a948 100644 --- a/arch/arm/dts/r8a779a0-u-boot.dtsi +++ b/arch/arm/dts/r8a779a0-u-boot.dtsi @@ -10,7 +10,7 @@ / { soc { rpc: spi@ee200000 { - compatible = "renesas,rpc-r8a779a0", "renesas,rcar-gen3-rpc"; + compatible = "renesas,r8a779a0-rpc-if", "renesas,rcar-gen3-rpc-if"; reg = <0 0xee200000 0 0x200>, <0 0x08000000 0 0x04000000>; clocks = <&cpg CPG_MOD 629>; bank-width = <2>; diff --git a/arch/arm/dts/rk3288-u-boot.dtsi b/arch/arm/dts/rk3288-u-boot.dtsi index 9eb696b141..e411445ed6 100644 --- a/arch/arm/dts/rk3288-u-boot.dtsi +++ b/arch/arm/dts/rk3288-u-boot.dtsi @@ -56,7 +56,7 @@ }; }; -#ifdef CONFIG_ROCKCHIP_SPI_IMAGE +#if defined(CONFIG_ROCKCHIP_SPI_IMAGE) && defined(CONFIG_HAS_ROM) &binman { rom { filename = "u-boot.rom"; diff --git a/arch/arm/dts/rk3288.dtsi b/arch/arm/dts/rk3288.dtsi index 9fb6d86bc1..53ee760b98 100644 --- a/arch/arm/dts/rk3288.dtsi +++ b/arch/arm/dts/rk3288.dtsi @@ -109,48 +109,48 @@ ports = <&vopl_out>, <&vopb_out>; }; - sdmmc: dwmmc@ff0c0000 { + sdmmc: mmc@ff0c0000 { compatible = "rockchip,rk3288-dw-mshc"; max-frequency = <150000000>; clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; - clock-names = "biu", "ciu", "ciu_drv", "ciu_sample"; + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; fifo-depth = <0x100>; interrupts = ; reg = <0xff0c0000 0x4000>; status = "disabled"; }; - sdio0: dwmmc@ff0d0000 { + sdio0: mmc@ff0d0000 { compatible = "rockchip,rk3288-dw-mshc"; max-frequency = <150000000>; clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>, <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>; - clock-names = "biu", "ciu", "ciu_drv", "ciu_sample"; + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; fifo-depth = <0x100>; interrupts = ; reg = <0xff0d0000 0x4000>; status = "disabled"; }; - sdio1: dwmmc@ff0e0000 { + sdio1: mmc@ff0e0000 { compatible = "rockchip,rk3288-dw-mshc"; max-frequency = <150000000>; clocks = <&cru HCLK_SDIO1>, <&cru SCLK_SDIO1>, <&cru SCLK_SDIO1_DRV>, <&cru SCLK_SDIO1_SAMPLE>; - clock-names = "biu", "ciu", "ciu_drv", "ciu_sample"; + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; fifo-depth = <0x100>; interrupts = ; reg = <0xff0e0000 0x4000>; status = "disabled"; }; - emmc: dwmmc@ff0f0000 { + emmc: mmc@ff0f0000 { compatible = "rockchip,rk3288-dw-mshc"; max-frequency = <150000000>; clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; - clock-names = "biu", "ciu", "ciu_drv", "ciu_sample"; + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; fifo-depth = <0x100>; interrupts = ; reg = <0xff0f0000 0x4000>; diff --git a/arch/arm/dts/rk3308-u-boot.dtsi b/arch/arm/dts/rk3308-u-boot.dtsi index 4bfad31fba..ab5bfc2ce9 100644 --- a/arch/arm/dts/rk3308-u-boot.dtsi +++ b/arch/arm/dts/rk3308-u-boot.dtsi @@ -3,6 +3,8 @@ *(C) Copyright 2019 Rockchip Electronics Co., Ltd */ +#include "rockchip-u-boot.dtsi" + / { aliases { mmc0 = &emmc; diff --git a/arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi b/arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi index 95f2652494..16c33735eb 100644 --- a/arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi +++ b/arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi @@ -3,6 +3,8 @@ * Copyright (c) 2020 Theobroma Systems Design und Consulting GmbH */ +#include "rockchip-u-boot.dtsi" + / { chosen { u-boot,spl-boot-order = &sdmmc; diff --git a/arch/arm/dts/rk3328-u-boot.dtsi b/arch/arm/dts/rk3328-u-boot.dtsi index 1633558264..d4a7540a92 100644 --- a/arch/arm/dts/rk3328-u-boot.dtsi +++ b/arch/arm/dts/rk3328-u-boot.dtsi @@ -3,6 +3,8 @@ * (C) Copyright 2019 Rockchip Electronics Co., Ltd */ +#include "rockchip-u-boot.dtsi" + / { aliases { mmc0 = &emmc; diff --git a/arch/arm/dts/rk3368-u-boot.dtsi b/arch/arm/dts/rk3368-u-boot.dtsi index 2767c2678d..811d59ac34 100644 --- a/arch/arm/dts/rk3368-u-boot.dtsi +++ b/arch/arm/dts/rk3368-u-boot.dtsi @@ -4,6 +4,7 @@ */ #include +#include "rockchip-u-boot.dtsi" / { dmc: dmc@ff610000 { diff --git a/arch/arm/dts/rk3399-u-boot.dtsi b/arch/arm/dts/rk3399-u-boot.dtsi index 716b9a433a..3c1a15fe51 100644 --- a/arch/arm/dts/rk3399-u-boot.dtsi +++ b/arch/arm/dts/rk3399-u-boot.dtsi @@ -60,7 +60,7 @@ }; -#ifdef CONFIG_ROCKCHIP_SPI_IMAGE +#if defined(CONFIG_ROCKCHIP_SPI_IMAGE) && defined(CONFIG_HAS_ROM) &binman { rom { filename = "u-boot.rom"; diff --git a/arch/arm/dts/rk3568-u-boot.dtsi b/arch/arm/dts/rk3568-u-boot.dtsi index 5a80dda275..fa9b6ae23b 100644 --- a/arch/arm/dts/rk3568-u-boot.dtsi +++ b/arch/arm/dts/rk3568-u-boot.dtsi @@ -3,6 +3,8 @@ * (C) Copyright 2021 Rockchip Electronics Co., Ltd */ +#include "rockchip-u-boot.dtsi" + / { aliases { mmc0 = &sdhci; diff --git a/arch/arm/dts/rockchip-u-boot.dtsi b/arch/arm/dts/rockchip-u-boot.dtsi index eae3ee715d..584f21eb5b 100644 --- a/arch/arm/dts/rockchip-u-boot.dtsi +++ b/arch/arm/dts/rockchip-u-boot.dtsi @@ -17,13 +17,57 @@ filename = "u-boot-rockchip.bin"; pad-byte = <0xff>; - blob { + mkimage { filename = "idbloader.img"; + args = "-n", CONFIG_SYS_SOC, "-T", "rksd"; +#ifdef CONFIG_TPL + multiple-data-files; + + u-boot-tpl { + }; +#endif + u-boot-spl { + }; }; +#ifdef CONFIG_ARM64 + blob { + filename = "u-boot.itb"; +#else u-boot-img { +#endif offset = ; }; }; + +#ifdef CONFIG_ROCKCHIP_SPI_IMAGE + simple-bin-spi { + filename = "u-boot-rockchip-spi.bin"; + pad-byte = <0xff>; + + mkimage { + filename = "idbloader-spi.img"; + args = "-n", CONFIG_SYS_SOC, "-T", "rkspi"; +#ifdef CONFIG_TPL + multiple-data-files; + + u-boot-tpl { + }; +#endif + u-boot-spl { + }; + }; + +#ifdef CONFIG_ARM64 + blob { + filename = "u-boot.itb"; +#else + u-boot-img { +#endif + /* Sync with u-boot,spl-payload-offset if present */ + offset = ; + }; + }; +#endif }; #endif diff --git a/arch/arm/dts/stm32f746-disco-u-boot.dtsi b/arch/arm/dts/stm32f746-disco-u-boot.dtsi index f88466fa60..a4ce936d7d 100644 --- a/arch/arm/dts/stm32f746-disco-u-boot.dtsi +++ b/arch/arm/dts/stm32f746-disco-u-boot.dtsi @@ -58,7 +58,7 @@ vsync-len = <10>; hsync-active = <0>; vsync-active = <0>; - de-active = <0>; + de-active = <1>; pixelclk-active = <1>; }; }; diff --git a/arch/arm/dts/stm32mp151.dtsi b/arch/arm/dts/stm32mp151.dtsi index a5ac62c83d..767a06ef68 100644 --- a/arch/arm/dts/stm32mp151.dtsi +++ b/arch/arm/dts/stm32mp151.dtsi @@ -1663,7 +1663,6 @@ ranges = <0 0x50002000 0xa400>; interrupt-parent = <&exti>; st,syscfg = <&exti 0x60 0xff>; - hwlocks = <&hwspinlock 0>; pins-are-numbered; gpioa: gpio@50002000 { @@ -1796,7 +1795,6 @@ pins-are-numbered; interrupt-parent = <&exti>; st,syscfg = <&exti 0x60 0xff>; - hwlocks = <&hwspinlock 0>; gpioz: gpio@54004000 { gpio-controller; diff --git a/arch/arm/dts/stm32mp15xx-dhcom-picoitx-u-boot.dtsi b/arch/arm/dts/stm32mp15xx-dhcom-picoitx-u-boot.dtsi index 5bc6698f87..0bcaec5019 100644 --- a/arch/arm/dts/stm32mp15xx-dhcom-picoitx-u-boot.dtsi +++ b/arch/arm/dts/stm32mp15xx-dhcom-picoitx-u-boot.dtsi @@ -5,14 +5,6 @@ #include "stm32mp15xx-dhcom-u-boot.dtsi" -/ { - aliases { - /delete-property/ ethernet1; - }; -}; - -/delete-node/ &ks8851; - &usbotg_hs { dr_mode = "peripheral"; }; diff --git a/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi b/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi index ee747a52bb..8a7156c93b 100644 --- a/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi +++ b/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi @@ -9,8 +9,6 @@ #include "stm32mp15-ddr3-dhsom-2x2Gb-1066-binG.dtsi" #include "stm32mp15-ddr3-dhsom-2x4Gb-1066-binG.dtsi" -/delete-node/ &ksz8851; - / { aliases { i2c1 = &i2c2; @@ -21,7 +19,6 @@ spi0 = &qspi; usb0 = &usbotg_hs; eeprom0 = &eeprom0; - ethernet1 = &ks8851; }; config { @@ -30,12 +27,6 @@ dh,som-coding-gpios = <&gpiof 12 0>, <&gpiof 13 0>, <&gpiof 15 0>; dh,ddr3-coding-gpios = <&gpioz 6 0>, <&gpioz 7 0>; }; - - /* This is actually on FMC2, but we do not have bus driver for that */ - ks8851: ks8851mll@64000000 { - compatible = "micrel,ks8851-mll"; - reg = <0x64000000 0x20000>; - }; }; ðernet0 { @@ -74,11 +65,6 @@ }; &pinctrl { - /* These should bound to FMC2 bus driver, but we do not have one */ - pinctrl-0 = <&fmc_pins_b &mco2_pins_a>; - pinctrl-1 = <&fmc_sleep_pins_b &mco2_sleep_pins_a>; - pinctrl-names = "default", "sleep"; - mco2_pins_a: mco2-0 { pins { pinmux = ; /* MCO2 */ diff --git a/arch/arm/dts/stm32mp15xx-dhcor-drc-compact-u-boot.dtsi b/arch/arm/dts/stm32mp15xx-dhcor-drc-compact-u-boot.dtsi index 407fed5616..b6a6a78647 100644 --- a/arch/arm/dts/stm32mp15xx-dhcor-drc-compact-u-boot.dtsi +++ b/arch/arm/dts/stm32mp15xx-dhcor-drc-compact-u-boot.dtsi @@ -5,25 +5,16 @@ #include "stm32mp15xx-dhcor-u-boot.dtsi" -/delete-node/ &ksz8851; - / { aliases { mmc0 = &sdmmc1; mmc1 = &sdmmc2; usb0 = &usbotg_hs; - ethernet1 = &ks8851; }; config { dh,board-coding-gpios = <&gpioh 9 0>, <&gpioh 8 0>, <&gpioh 3 0>; }; - - /* This is actually on FMC2, but we do not have bus driver for that */ - ks8851: ks8851mll@64000000 { - compatible = "micrel,ks8851-mll"; - reg = <0x64000000 0x20000>; - }; }; ðernet0 { @@ -38,13 +29,6 @@ }; }; -&pinctrl { - /* These should bound to FMC2 bus driver, but we do not have one */ - pinctrl-0 = <&fmc_pins_b>; - pinctrl-1 = <&fmc_sleep_pins_b>; - pinctrl-names = "default", "sleep"; -}; - &sdmmc1 { u-boot,dm-spl; st,use-ckin; diff --git a/arch/arm/include/asm/arch-imx/cpu.h b/arch/arm/include/asm/arch-imx/cpu.h index d54e6e6335..a666271fc1 100644 --- a/arch/arm/include/asm/arch-imx/cpu.h +++ b/arch/arm/include/asm/arch-imx/cpu.h @@ -56,6 +56,7 @@ #define MXC_CPU_IMXRT1020 0xB4 /* dummy ID */ #define MXC_CPU_IMXRT1050 0xB6 /* dummy ID */ +#define MXC_CPU_IMXRT1170 0xBA /* dummy ID */ #define MXC_CPU_MX7ULP 0xE1 /* Temporally hard code */ #define MXC_CPU_VF610 0xF6 /* dummy ID */ diff --git a/arch/arm/include/asm/pl310.h b/arch/arm/include/asm/pl310.h index f69e9e45f8..9d4cd68ee4 100644 --- a/arch/arm/include/asm/pl310.h +++ b/arch/arm/include/asm/pl310.h @@ -7,13 +7,12 @@ #ifndef _PL310_H_ #define _PL310_H_ -#include - /* Register bit fields */ #define PL310_AUX_CTRL_ASSOCIATIVITY_MASK (1 << 16) #define L2X0_DYNAMIC_CLK_GATING_EN (1 << 1) #define L2X0_STNDBY_MODE_EN (1 << 0) #define L2X0_CTRL_EN 1 +#define L2X0_CTRL_OFF 0x100 #define L310_SHARED_ATT_OVERRIDE_ENABLE (1 << 22) #define L310_AUX_CTRL_DATA_PREFETCH_MASK (1 << 28) @@ -27,6 +26,10 @@ #define L2X0_CACHE_ID_RTL_MASK 0x3f #define L2X0_CACHE_ID_RTL_R3P2 0x8 +#ifndef __ASSEMBLY__ + +#include + struct pl310_regs { u32 pl310_cache_id; u32 pl310_cache_type; @@ -87,3 +90,5 @@ void pl310_inval_range(u32 start, u32 end); void pl310_clean_inval_range(u32 start, u32 end); #endif + +#endif diff --git a/arch/arm/lib/semihosting.c b/arch/arm/lib/semihosting.c index dbea2b06fb..01d652a6b8 100644 --- a/arch/arm/lib/semihosting.c +++ b/arch/arm/lib/semihosting.c @@ -32,12 +32,12 @@ static noinline long smh_trap(unsigned int sysnum, void *addr) { register long result asm("r0"); #if defined(CONFIG_ARM64) - asm volatile ("hlt #0xf000" : "=r" (result) : "0"(sysnum), "r"(addr)); + asm volatile ("hlt #0xf000" : "=r" (result) : "0"(sysnum), "r"(addr) : "memory"); #elif defined(CONFIG_CPU_V7M) - asm volatile ("bkpt #0xAB" : "=r" (result) : "0"(sysnum), "r"(addr)); + asm volatile ("bkpt #0xAB" : "=r" (result) : "0"(sysnum), "r"(addr) : "memory"); #else /* Note - untested placeholder */ - asm volatile ("svc #0x123456" : "=r" (result) : "0"(sysnum), "r"(addr)); + asm volatile ("svc #0x123456" : "=r" (result) : "0"(sysnum), "r"(addr) : "memory"); #endif return result; } diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig index 979b30ae39..3470160990 100644 --- a/arch/arm/mach-imx/imx8m/Kconfig +++ b/arch/arm/mach-imx/imx8m/Kconfig @@ -269,6 +269,14 @@ config TARGET_IMX8MP_RSB3720A1_6G select IMX8MP select SUPPORT_SPL select IMX8M_LPDDR4 + +config TARGET_LIBREM5 + bool "Purism Librem5 Phone" + select BINMAN + select IMX8MQ + select SUPPORT_SPL + select IMX8M_LPDDR4 + endchoice source "board/advantech/imx8mp_rsb3720a1/Kconfig" @@ -290,6 +298,7 @@ source "board/kontron/sl-mx8mm/Kconfig" source "board/menlo/mx8menlo/Kconfig" source "board/phytec/phycore_imx8mm/Kconfig" source "board/phytec/phycore_imx8mp/Kconfig" +source "board/purism/librem5/Kconfig" source "board/ronetix/imx8mq-cm/Kconfig" source "board/technexion/pico-imx8mq/Kconfig" source "board/variscite/imx8mn_var_som/Kconfig" diff --git a/arch/arm/mach-imx/imxrt/Kconfig b/arch/arm/mach-imx/imxrt/Kconfig index 8c89133965..c1d6b09e77 100644 --- a/arch/arm/mach-imx/imxrt/Kconfig +++ b/arch/arm/mach-imx/imxrt/Kconfig @@ -12,6 +12,10 @@ config IMXRT1050 bool select IMXRT +config IMXRT1170 + bool + select IMXRT + config SYS_SOC default "imxrt" @@ -27,9 +31,14 @@ config TARGET_IMXRT1050_EVK bool "Support imxrt1050 EVK board" select IMXRT1050 +config TARGET_IMXRT1170_EVK + bool "Support imxrt1170 EVK board" + select IMXRT1170 + endchoice source "board/freescale/imxrt1020-evk/Kconfig" source "board/freescale/imxrt1050-evk/Kconfig" +source "board/freescale/imxrt1170-evk/Kconfig" endif diff --git a/arch/arm/mach-imx/imxrt/soc.c b/arch/arm/mach-imx/imxrt/soc.c index ba015992ee..34162a3976 100644 --- a/arch/arm/mach-imx/imxrt/soc.c +++ b/arch/arm/mach-imx/imxrt/soc.c @@ -43,6 +43,8 @@ u32 get_cpu_rev(void) return MXC_CPU_IMXRT1020 << 12; #elif defined(CONFIG_IMXRT1050) return MXC_CPU_IMXRT1050 << 12; +#elif defined(CONFIG_IMXRT1170) + return MXC_CPU_IMXRT1170 << 12; #else #error This IMXRT SoC is not supported #endif diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig index ec560fe257..c7a03e5042 100644 --- a/arch/arm/mach-imx/mx6/Kconfig +++ b/arch/arm/mach-imx/mx6/Kconfig @@ -466,6 +466,17 @@ config TARGET_MX6ULL_14X14_EVK select DM_THERMAL imply CMD_DM +config TARGET_MX6ULZ_SMM_M2 + bool "Support imx6ulz_smm_m2" + depends on MX6ULL + select DM + select DM_GPIO + select DM_I2C + select DM_SERIAL + select DM_MTD + select DM_THERMAL + select SUPPORT_SPL + config TARGET_MYS_6ULX bool "MYiR MYS-6ULX" depends on MX6ULL @@ -680,6 +691,7 @@ source "board/ge/b1x5v2/Kconfig" source "board/aristainetos/Kconfig" source "board/armadeus/opos6uldev/Kconfig" source "board/boundary/nitrogen6x/Kconfig" +source "board/bsh/imx6ulz_smm_m2/Kconfig" source "board/bticino/mamoj/Kconfig" source "board/compulab/cm_fx6/Kconfig" source "board/dhelectronics/dh_imx6/Kconfig" diff --git a/arch/arm/mach-imx/spl_imx_romapi.c b/arch/arm/mach-imx/spl_imx_romapi.c index cc3c1251dc..07bf07beee 100644 --- a/arch/arm/mach-imx/spl_imx_romapi.c +++ b/arch/arm/mach-imx/spl_imx_romapi.c @@ -288,7 +288,7 @@ static int spl_romapi_load_image_stream(struct spl_image_info *spl_image, } imagesize = img_info_size(phdr); - printf("Find img info 0x&%p, size %d\n", phdr, imagesize); + printf("Find img info 0x%p, size %d\n", phdr, imagesize); if (p - phdr < imagesize) { imagesize -= p - phdr; diff --git a/arch/arm/mach-kirkwood/cpu.c b/arch/arm/mach-kirkwood/cpu.c index 80f893ab36..df3e8f1178 100644 --- a/arch/arm/mach-kirkwood/cpu.c +++ b/arch/arm/mach-kirkwood/cpu.c @@ -52,7 +52,7 @@ unsigned int kw_winctrl_calcsize(unsigned int sizeval) return (0x0000ffff & j); } -static struct mbus_win windows[] = { +static const struct mbus_win windows[] = { /* Window 0: PCIE MEM address space */ { KW_DEFADR_PCI_MEM, KW_DEFADR_PCI_MEM_SIZE, KWCPU_TARGET_PCIE, KWCPU_ATTR_PCIE_MEM }, diff --git a/arch/arm/mach-kirkwood/include/mach/cpu.h b/arch/arm/mach-kirkwood/include/mach/cpu.h index d8639c6035..9eec786fe8 100644 --- a/arch/arm/mach-kirkwood/include/mach/cpu.h +++ b/arch/arm/mach-kirkwood/include/mach/cpu.h @@ -150,7 +150,7 @@ struct kwgpio_registers { unsigned int mvebu_sdram_bar(enum memory_bank bank); unsigned int mvebu_sdram_bs(enum memory_bank bank); void mvebu_sdram_size_adjust(enum memory_bank bank); -int mvebu_mbus_probe(struct mbus_win windows[], int count); +int mvebu_mbus_probe(const struct mbus_win windows[], int count); void mvebu_config_gpio(unsigned int gpp0_oe_val, unsigned int gpp1_oe_val, unsigned int gpp0_oe, unsigned int gpp1_oe); int kw_config_mpp(unsigned int mpp0_7, unsigned int mpp8_15, diff --git a/arch/arm/mach-mvebu/cpu.c b/arch/arm/mach-mvebu/cpu.c index 1457af1d6a..1f8cdf8744 100644 --- a/arch/arm/mach-mvebu/cpu.c +++ b/arch/arm/mach-mvebu/cpu.c @@ -20,7 +20,7 @@ #define DDR_BASE_CS_OFF(n) (0x0000 + ((n) << 3)) #define DDR_SIZE_CS_OFF(n) (0x0004 + ((n) << 3)) -static struct mbus_win windows[] = { +static const struct mbus_win windows[] = { /* SPI */ { MBUS_SPI_BASE, MBUS_SPI_SIZE, CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_SPIFLASH }, @@ -445,19 +445,6 @@ static void setup_usb_phys(void) */ int arch_cpu_init(void) { - struct pl310_regs *const pl310 = - (struct pl310_regs *)CONFIG_SYS_PL310_BASE; - - if (IS_ENABLED(CONFIG_ARMADA_38X)) { - /* - * To fully release / unlock this area from cache, we need - * to flush all caches and disable the L2 cache. - */ - icache_disable(); - dcache_disable(); - clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); - } - /* * We need to call mvebu_mbus_probe() before calling * update_sdram_window_sizes() as it disables all previously @@ -663,7 +650,7 @@ void enable_caches(void) * ethernet driver (mvpp2). So lets keep the d-cache disabled * until this is solved. */ - if (IS_ENABLED(CONFIG_ARMADA_375)) { + if (!IS_ENABLED(CONFIG_ARMADA_375)) { /* Enable D-cache. I-cache is already enabled in start.S */ dcache_enable(); } @@ -671,12 +658,20 @@ void enable_caches(void) void v7_outer_cache_enable(void) { - if (IS_ENABLED(CONFIG_ARMADA_XP)) { - struct pl310_regs *const pl310 = - (struct pl310_regs *)CONFIG_SYS_PL310_BASE; - u32 u; + struct pl310_regs *const pl310 = + (struct pl310_regs *)CONFIG_SYS_PL310_BASE; - /* The L2 cache is already disabled at this point */ + /* The L2 cache is already disabled at this point */ + + /* + * For now L2 cache will be enabled only for Armada XP and Armada 38x. + * It can be enabled also for other SoCs after testing that it works fine. + */ + if (!IS_ENABLED(CONFIG_ARMADA_XP) && !IS_ENABLED(CONFIG_ARMADA_38X)) + return; + + if (IS_ENABLED(CONFIG_ARMADA_XP)) { + u32 u; /* * For Aurora cache in no outer mode, enable via the CP15 @@ -687,10 +682,10 @@ void v7_outer_cache_enable(void) asm volatile("mcr p15, 1, %0, c15, c2, 0" : : "r" (u)); isb(); - - /* Enable the L2 cache */ - setbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); } + + /* Enable the L2 cache */ + setbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); } void v7_outer_cache_disable(void) diff --git a/arch/arm/mach-mvebu/include/mach/cpu.h b/arch/arm/mach-mvebu/include/mach/cpu.h index d9fa1f32aa..b127fce865 100644 --- a/arch/arm/mach-mvebu/include/mach/cpu.h +++ b/arch/arm/mach-mvebu/include/mach/cpu.h @@ -128,7 +128,7 @@ struct sar_freq_modes { unsigned int mvebu_sdram_bar(enum memory_bank bank); unsigned int mvebu_sdram_bs(enum memory_bank bank); void mvebu_sdram_size_adjust(enum memory_bank bank); -int mvebu_mbus_probe(struct mbus_win windows[], int count); +int mvebu_mbus_probe(const struct mbus_win windows[], int count); u32 mvebu_get_nand_clock(void); void __noreturn return_to_bootrom(void); diff --git a/arch/arm/mach-mvebu/lowlevel.S b/arch/arm/mach-mvebu/lowlevel.S index 2491310eb0..60c2072c35 100644 --- a/arch/arm/mach-mvebu/lowlevel.S +++ b/arch/arm/mach-mvebu/lowlevel.S @@ -2,6 +2,8 @@ #include #include +#include +#include ENTRY(arch_very_early_init) #ifdef CONFIG_ARMADA_38X @@ -10,10 +12,36 @@ ENTRY(arch_very_early_init) * register address on Armada 38x. Without this the SDRAM * located at >= 0x4000.0000 is also not accessible, as its * still locked to cache. + * + * So to fully release / unlock this area from cache, we need + * to first flush all caches, then disable the MMU and + * disable the L2 cache. */ + + /* Invalidate L1 I/D */ + mov r0, #0 @ set up for MCR + mcr p15, 0, r0, c8, c7, 0 @ invalidate TLBs + mcr p15, 0, r0, c7, c5, 0 @ invalidate icache + mcr p15, 0, r0, c7, c5, 6 @ invalidate BP array + mcr p15, 0, r0, c7, c10, 4 @ DSB + mcr p15, 0, r0, c7, c5, 4 @ ISB + + /* Disable MMU */ mrc p15, 0, r0, c1, c0, 0 - bic r0, #1 + bic r0, #CR_M mcr p15, 0, r0, c1, c0, 0 + + /* + * Disable L2 cache + * + * NOTE: Internal registers are still at address INTREG_BASE_ADDR_REG + * but CONFIG_SYS_PL310_BASE is already calculated from base + * address SOC_REGS_PHY_BASE. + */ + ldr r1, =(CONFIG_SYS_PL310_BASE - SOC_REGS_PHY_BASE + INTREG_BASE_ADDR_REG) + ldr r0, [r1, #L2X0_CTRL_OFF] + bic r0, #L2X0_CTRL_EN + str r0, [r1, #L2X0_CTRL_OFF] #endif /* Move internal registers from INTREG_BASE_ADDR_REG to SOC_REGS_PHY_BASE */ diff --git a/arch/arm/mach-mvebu/mbus.c b/arch/arm/mach-mvebu/mbus.c index 7092f6cc10..959ca8e926 100644 --- a/arch/arm/mach-mvebu/mbus.c +++ b/arch/arm/mach-mvebu/mbus.c @@ -469,7 +469,7 @@ int mbus_dt_setup_win(u32 base, u32 size, u8 target, u8 attr) return 0; } -int mvebu_mbus_probe(struct mbus_win windows[], int count) +int mvebu_mbus_probe(const struct mbus_win windows[], int count) { int win; int ret; diff --git a/arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.c b/arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.c index 2e467b546d..943ae01942 100644 --- a/arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.c +++ b/arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.c @@ -105,7 +105,7 @@ struct serdes_unit_data { u8 serdes_unit_num; }; -static struct serdes_unit_data serdes_type_to_unit_info[] = { +static const struct serdes_unit_data serdes_type_to_unit_info[] = { {PEX_UNIT_ID, 0,}, {PEX_UNIT_ID, 1,}, {PEX_UNIT_ID, 2,}, diff --git a/arch/arm/mach-mvebu/system-controller.c b/arch/arm/mach-mvebu/system-controller.c index ea858b269e..e90aff0c33 100644 --- a/arch/arm/mach-mvebu/system-controller.c +++ b/arch/arm/mach-mvebu/system-controller.c @@ -86,7 +86,7 @@ static const struct udevice_id mvebu_reset_of_match[] = { { }, }; -static struct reset_ops mvebu_reset_ops = { +static const struct reset_ops mvebu_reset_ops = { .of_xlate = mvebu_reset_of_xlate, .request = mvebu_reset_request, .rfree = mvebu_reset_free, diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index c561a77e6a..b46cea2f91 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -425,12 +425,10 @@ config SPL_MMC config ROCKCHIP_SPI_IMAGE bool "Build a SPI image for rockchip" - depends on HAS_ROM help Some Rockchip SoCs support booting from SPI flash. Enable this - option to produce a 4MB SPI-flash image (called u-boot.rom) - containing U-Boot. The image is built by binman. U-Boot sits near - the start of the image. + option to produce a SPI-flash image containing U-Boot. The image + is built by binman. U-Boot sits near the start of the image. config LNX_KRNL_IMG_TEXT_OFFSET_BASE default SYS_TEXT_BASE diff --git a/arch/arm/mach-rockchip/rk3308/rk3308.c b/arch/arm/mach-rockchip/rk3308/rk3308.c index 70fe0d0ac3..dd9109b7c3 100644 --- a/arch/arm/mach-rockchip/rk3308/rk3308.c +++ b/arch/arm/mach-rockchip/rk3308/rk3308.c @@ -8,6 +8,7 @@ #include #include #include +#include #include #include #include @@ -142,6 +143,11 @@ enum { #define GPIO0_A4 4 +const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = { + [BROM_BOOTSOURCE_EMMC] = "/mmc@ff490000", + [BROM_BOOTSOURCE_SD] = "/mmc@ff480000", +}; + int rk_board_init(void) { static struct rk3308_grf * const grf = (void *)GRF_BASE; diff --git a/arch/arm/mach-rockchip/rk3399/rk3399.c b/arch/arm/mach-rockchip/rk3399/rk3399.c index 01a05599cd..21db03b961 100644 --- a/arch/arm/mach-rockchip/rk3399/rk3399.c +++ b/arch/arm/mach-rockchip/rk3399/rk3399.c @@ -27,7 +27,7 @@ DECLARE_GLOBAL_DATA_PTR; #define GRF_BASE 0xff770000 const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = { - [BROM_BOOTSOURCE_EMMC] = "/sdhci@fe330000", + [BROM_BOOTSOURCE_EMMC] = "/mmc@fe330000", [BROM_BOOTSOURCE_SPINOR] = "/spi@ff1d0000/flash@0", [BROM_BOOTSOURCE_SD] = "/mmc@fe320000", }; @@ -180,9 +180,9 @@ const char *spl_decode_boot_device(u32 boot_device) u32 boot_device; const char *ofpath; } spl_boot_devices_tbl[] = { - { BOOT_DEVICE_MMC1, "/mmc@fe320000" }, - { BOOT_DEVICE_MMC2, "/sdhci@fe330000" }, - { BOOT_DEVICE_SPI, "/spi@ff1d0000" }, + { BOOT_DEVICE_MMC2, "/mmc@fe320000" }, + { BOOT_DEVICE_MMC1, "/mmc@fe330000" }, + { BOOT_DEVICE_SPI, "/spi@ff1d0000/flash@0" }, }; for (i = 0; i < ARRAY_SIZE(spl_boot_devices_tbl); ++i) diff --git a/arch/arm/mach-stm32mp/stm32mp15x.c b/arch/arm/mach-stm32mp/stm32mp15x.c index a093e6163e..660c907a6b 100644 --- a/arch/arm/mach-stm32mp/stm32mp15x.c +++ b/arch/arm/mach-stm32mp/stm32mp15x.c @@ -274,7 +274,6 @@ static void get_cpu_string_offsets(unsigned int *type, unsigned int *pkg, u32 cpu_type = get_cpu_type(); u32 ct = cpu_type & ~(BIT(7) | BIT(0)); u32 cm = ((cpu_type & BIT(7)) >> 6) | (cpu_type & BIT(0)); - u32 cp = get_cpu_package(); /* Bits 0 and 7 are the ACDF, 00:C 01:A 10:F 11:D */ switch (ct) { @@ -293,17 +292,9 @@ static void get_cpu_string_offsets(unsigned int *type, unsigned int *pkg, } /* Package */ - switch (cp) { - case STM32MP15_PKG_AA_LBGA448: - case STM32MP15_PKG_AB_LBGA354: - case STM32MP15_PKG_AC_TFBGA361: - case STM32MP15_PKG_AD_TFBGA257: - *pkg = cp; - break; - default: - *pkg = 0; - break; - } + *pkg = get_cpu_package(); + if (*pkg > STM32MP15_PKG_AA_LBGA448) + *pkg = STM32MP15_PKG_UNKNOWN; /* Revision */ switch (get_cpu_rev()) { diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig index 2cb5dae736..3b518c2695 100644 --- a/arch/powerpc/Kconfig +++ b/arch/powerpc/Kconfig @@ -21,7 +21,7 @@ config MPC85xx select SYS_FSL_DDR select SYS_FSL_DDR_BE select SYS_FSL_IFC_BE - select BINMAN if OF_SEPARATE + select BINMAN if MPC85XX_HAVE_RESET_VECTOR && OF_SEPARATE imply CMD_HASH imply CMD_IRQ imply USB_EHCI_HCD if USB diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig index 085ddd8439..27f069a1fb 100644 --- a/arch/powerpc/cpu/mpc85xx/Kconfig +++ b/arch/powerpc/cpu/mpc85xx/Kconfig @@ -15,7 +15,7 @@ config CMD_ERRATA config FSL_PREPBL_ESDHC_BOOT_SECTOR bool "Generate QorIQ pre-PBL eSDHC boot sector" depends on MPC85xx - depends on SYS_EXTRA_OPTIONS = SDCARD + depends on SDCARD help With this option final image would have prepended QorIQ pre-PBL eSDHC boot sector suitable for SD card images. This boot sector instruct diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c index 1b6cdc4df0..14d5c560bf 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu.c +++ b/arch/powerpc/cpu/mpc85xx/cpu.c @@ -44,7 +44,9 @@ __board_reset(void) { /* Do nothing */ } +void board_reset_prepare(void) __attribute__((weak, alias("__board_reset"))); void board_reset(void) __attribute__((weak, alias("__board_reset"))); +void board_reset_last(void) __attribute__((weak, alias("__board_reset"))); int checkcpu (void) { @@ -319,12 +321,18 @@ int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) #else volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + /* Call board-specific preparation for reset */ + board_reset_prepare(); + /* Attempt board-specific reset */ board_reset(); /* Next try asserting HRESET_REQ */ out_be32(&gur->rstcr, 0x2); udelay(100); + + /* Attempt last-stage board-specific reset */ + board_reset_last(); #endif return 1; diff --git a/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds b/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds index e881537452..f28826c5d1 100644 --- a/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds +++ b/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds @@ -58,10 +58,17 @@ SECTIONS __ex_table : { *(__ex_table) } __stop___ex_table = .; - . = ALIGN(8); + . = ALIGN(4); __init_begin = .; __init_end = .; _end = .; + +#if CONFIG_IS_ENABLED(SYS_MPC85XX_NO_RESETVEC) +#if defined(CONFIG_SDCARD) && !defined(CONFIG_SYS_MMC_U_BOOT_OFFS) + mmc_u_boot_offs = .; +#endif +#endif + #ifdef CONFIG_SPL_SKIP_RELOCATE . = ALIGN(4); __bss_start = .; @@ -94,6 +101,9 @@ SECTIONS .resetvec IMAGE_TEXT_BASE + RESET_VECTOR_OFFSET : { KEEP(*(.resetvec)) } = 0xffff +#if defined(CONFIG_SDCARD) && !defined(CONFIG_SYS_MMC_U_BOOT_OFFS) + mmc_u_boot_offs = .; +#endif #endif #ifndef CONFIG_SPL_SKIP_RELOCATE diff --git a/arch/powerpc/dts/kmcent2-u-boot.dtsi b/arch/powerpc/dts/kmcent2-u-boot.dtsi index ab76a9f122..eeaa688b65 100644 --- a/arch/powerpc/dts/kmcent2-u-boot.dtsi +++ b/arch/powerpc/dts/kmcent2-u-boot.dtsi @@ -76,7 +76,7 @@ }; binman { - filename = "u-boot-with-dtb.bin"; + filename = "u-boot.bin"; skip-at-start = ; sort-by-offset; pad-byte = <0xff>; diff --git a/arch/powerpc/dts/u-boot.dtsi b/arch/powerpc/dts/u-boot.dtsi index 67de476a45..6588bb7fa5 100644 --- a/arch/powerpc/dts/u-boot.dtsi +++ b/arch/powerpc/dts/u-boot.dtsi @@ -5,9 +5,11 @@ #include +#if defined(CONFIG_MPC85XX_HAVE_RESET_VECTOR) && defined(CONFIG_OF_SEPARATE) + / { binman { - filename = "u-boot-with-dtb.bin"; + filename = "u-boot.bin"; skip-at-start = ; sort-by-offset; pad-byte = <0xff>; @@ -19,17 +21,15 @@ }; u-boot-dtb-with-ucode { -#ifdef CONFIG_MPC85xx align = <4>; -#endif }; -#ifdef CONFIG_MPC85XX_HAVE_RESET_VECTOR #ifndef CONFIG_RESET_VECTOR_ADDRESS #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc #endif powerpc-mpc85xx-bootpg-resetvec { offset = <(CONFIG_RESET_VECTOR_ADDRESS - 0xffc)>; }; -#endif }; }; + +#endif diff --git a/arch/riscv/dts/fu740-c000-u-boot.dtsi b/arch/riscv/dts/fu740-c000-u-boot.dtsi index a6f7a0873e..917e9bf163 100644 --- a/arch/riscv/dts/fu740-c000-u-boot.dtsi +++ b/arch/riscv/dts/fu740-c000-u-boot.dtsi @@ -7,11 +7,11 @@ / { cpus { - assigned-clocks = <&prci PRCI_CLK_COREPLL>; + assigned-clocks = <&prci FU740_PRCI_CLK_COREPLL>; assigned-clock-rates = <1200000000>; u-boot,dm-spl; cpu0: cpu@0 { - clocks = <&prci PRCI_CLK_COREPLL>; + clocks = <&prci FU740_PRCI_CLK_COREPLL>; u-boot,dm-spl; status = "okay"; cpu0_intc: interrupt-controller { @@ -19,28 +19,28 @@ }; }; cpu1: cpu@1 { - clocks = <&prci PRCI_CLK_COREPLL>; + clocks = <&prci FU740_PRCI_CLK_COREPLL>; u-boot,dm-spl; cpu1_intc: interrupt-controller { u-boot,dm-spl; }; }; cpu2: cpu@2 { - clocks = <&prci PRCI_CLK_COREPLL>; + clocks = <&prci FU740_PRCI_CLK_COREPLL>; u-boot,dm-spl; cpu2_intc: interrupt-controller { u-boot,dm-spl; }; }; cpu3: cpu@3 { - clocks = <&prci PRCI_CLK_COREPLL>; + clocks = <&prci FU740_PRCI_CLK_COREPLL>; u-boot,dm-spl; cpu3_intc: interrupt-controller { u-boot,dm-spl; }; }; cpu4: cpu@4 { - clocks = <&prci PRCI_CLK_COREPLL>; + clocks = <&prci FU740_PRCI_CLK_COREPLL>; u-boot,dm-spl; cpu4_intc: interrupt-controller { u-boot,dm-spl; @@ -76,7 +76,7 @@ reg = <0x0 0x100b0000 0x0 0x0800 0x0 0x100b2000 0x0 0x2000 0x0 0x100b8000 0x0 0x1000>; - clocks = <&prci PRCI_CLK_DDRPLL>; + clocks = <&prci FU740_PRCI_CLK_DDRPLL>; clock-frequency = <933333324>; u-boot,dm-spl; }; @@ -100,7 +100,7 @@ }; ð0 { - assigned-clocks = <&prci PRCI_CLK_GEMGXLPLL>; + assigned-clocks = <&prci FU740_PRCI_CLK_GEMGXLPLL>; assigned-clock-rates = <125125000>; }; diff --git a/arch/riscv/dts/fu740-c000.dtsi b/arch/riscv/dts/fu740-c000.dtsi index 649efe400a..7b77c13496 100644 --- a/arch/riscv/dts/fu740-c000.dtsi +++ b/arch/riscv/dts/fu740-c000.dtsi @@ -1,10 +1,9 @@ // SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* Copyright (c) 2020-2021 SiFive, Inc */ +/* Copyright (c) 2020 SiFive, Inc */ /dts-v1/; #include -#include / { #address-cells = <2>; @@ -139,20 +138,21 @@ soc { #address-cells = <2>; #size-cells = <2>; - compatible = "sifive,fu740-c000", "sifive,fu740", "simple-bus"; + compatible = "simple-bus"; ranges; plic0: interrupt-controller@c000000 { #interrupt-cells = <1>; - compatible = "sifive,plic-1.0.0"; + #address-cells = <0>; + compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0"; reg = <0x0 0xc000000 0x0 0x4000000>; riscv,ndev = <69>; interrupt-controller; - interrupts-extended = < - &cpu0_intc 0xffffffff - &cpu1_intc 0xffffffff &cpu1_intc 9 - &cpu2_intc 0xffffffff &cpu2_intc 9 - &cpu3_intc 0xffffffff &cpu3_intc 9 - &cpu4_intc 0xffffffff &cpu4_intc 9>; + interrupts-extended = + <&cpu0_intc 0xffffffff>, + <&cpu1_intc 0xffffffff>, <&cpu1_intc 9>, + <&cpu2_intc 0xffffffff>, <&cpu2_intc 9>, + <&cpu3_intc 0xffffffff>, <&cpu3_intc 9>, + <&cpu4_intc 0xffffffff>, <&cpu4_intc 9>; }; prci: clock-controller@10000000 { compatible = "sifive,fu740-c000-prci"; @@ -166,7 +166,7 @@ reg = <0x0 0x10010000 0x0 0x1000>; interrupt-parent = <&plic0>; interrupts = <39>; - clocks = <&prci PRCI_CLK_PCLK>; + clocks = <&prci FU740_PRCI_CLK_PCLK>; status = "disabled"; }; uart1: serial@10011000 { @@ -174,7 +174,7 @@ reg = <0x0 0x10011000 0x0 0x1000>; interrupt-parent = <&plic0>; interrupts = <40>; - clocks = <&prci PRCI_CLK_PCLK>; + clocks = <&prci FU740_PRCI_CLK_PCLK>; status = "disabled"; }; i2c0: i2c@10030000 { @@ -182,7 +182,7 @@ reg = <0x0 0x10030000 0x0 0x1000>; interrupt-parent = <&plic0>; interrupts = <52>; - clocks = <&prci PRCI_CLK_PCLK>; + clocks = <&prci FU740_PRCI_CLK_PCLK>; reg-shift = <2>; reg-io-width = <1>; #address-cells = <1>; @@ -194,7 +194,7 @@ reg = <0x0 0x10031000 0x0 0x1000>; interrupt-parent = <&plic0>; interrupts = <53>; - clocks = <&prci PRCI_CLK_PCLK>; + clocks = <&prci FU740_PRCI_CLK_PCLK>; reg-shift = <2>; reg-io-width = <1>; #address-cells = <1>; @@ -203,22 +203,22 @@ }; qspi0: spi@10040000 { compatible = "sifive,fu740-c000-spi", "sifive,spi0"; - reg = <0x0 0x10040000 0x0 0x1000 - 0x0 0x20000000 0x0 0x10000000>; + reg = <0x0 0x10040000 0x0 0x1000>, + <0x0 0x20000000 0x0 0x10000000>; interrupt-parent = <&plic0>; interrupts = <41>; - clocks = <&prci PRCI_CLK_PCLK>; + clocks = <&prci FU740_PRCI_CLK_PCLK>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; qspi1: spi@10041000 { compatible = "sifive,fu740-c000-spi", "sifive,spi0"; - reg = <0x0 0x10041000 0x0 0x1000 - 0x0 0x30000000 0x0 0x10000000>; + reg = <0x0 0x10041000 0x0 0x1000>, + <0x0 0x30000000 0x0 0x10000000>; interrupt-parent = <&plic0>; interrupts = <42>; - clocks = <&prci PRCI_CLK_PCLK>; + clocks = <&prci FU740_PRCI_CLK_PCLK>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -228,7 +228,7 @@ reg = <0x0 0x10050000 0x0 0x1000>; interrupt-parent = <&plic0>; interrupts = <43>; - clocks = <&prci PRCI_CLK_PCLK>; + clocks = <&prci FU740_PRCI_CLK_PCLK>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -237,12 +237,12 @@ compatible = "sifive,fu540-c000-gem"; interrupt-parent = <&plic0>; interrupts = <55>; - reg = <0x0 0x10090000 0x0 0x2000 - 0x0 0x100a0000 0x0 0x1000>; + reg = <0x0 0x10090000 0x0 0x2000>, + <0x0 0x100a0000 0x0 0x1000>; local-mac-address = [00 00 00 00 00 00]; clock-names = "pclk", "hclk"; - clocks = <&prci PRCI_CLK_GEMGXLPLL>, - <&prci PRCI_CLK_GEMGXLPLL>; + clocks = <&prci FU740_PRCI_CLK_GEMGXLPLL>, + <&prci FU740_PRCI_CLK_GEMGXLPLL>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -251,8 +251,8 @@ compatible = "sifive,fu740-c000-pwm", "sifive,pwm0"; reg = <0x0 0x10020000 0x0 0x1000>; interrupt-parent = <&plic0>; - interrupts = <44 45 46 47>; - clocks = <&prci PRCI_CLK_PCLK>; + interrupts = <44>, <45>, <46>, <47>; + clocks = <&prci FU740_PRCI_CLK_PCLK>; #pwm-cells = <3>; status = "disabled"; }; @@ -260,8 +260,8 @@ compatible = "sifive,fu740-c000-pwm", "sifive,pwm0"; reg = <0x0 0x10021000 0x0 0x1000>; interrupt-parent = <&plic0>; - interrupts = <48 49 50 51>; - clocks = <&prci PRCI_CLK_PCLK>; + interrupts = <48>, <49>, <50>, <51>; + clocks = <&prci FU740_PRCI_CLK_PCLK>; #pwm-cells = <3>; status = "disabled"; }; @@ -273,7 +273,7 @@ cache-size = <2097152>; cache-unified; interrupt-parent = <&plic0>; - interrupts = <19 21 22 20>; + interrupts = <19>, <21>, <22>, <20>; reg = <0x0 0x2010000 0x0 0x1000>; }; gpio: gpio@10060000 { @@ -287,28 +287,27 @@ #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; - clocks = <&prci PRCI_CLK_PCLK>; + clocks = <&prci FU740_PRCI_CLK_PCLK>; status = "disabled"; }; pcie@e00000000 { - #address-cells = <3>; - #interrupt-cells = <1>; - #num-lanes = <8>; - #size-cells = <2>; compatible = "sifive,fu740-pcie"; - reg = <0xe 0x00000000 0x1 0x0 - 0xd 0xf0000000 0x0 0x10000000 - 0x0 0x100d0000 0x0 0x1000>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + reg = <0xe 0x00000000 0x0 0x80000000>, + <0xd 0xf0000000 0x0 0x10000000>, + <0x0 0x100d0000 0x0 0x1000>; reg-names = "dbi", "config", "mgmt"; device_type = "pci"; dma-coherent; bus-range = <0x0 0xff>; - ranges = <0x81000000 0x0 0x60080000 0x0 0x60080000 0x0 0x10000 - 0x82000000 0x0 0x60090000 0x0 0x60090000 0x0 0xff70000 - 0x82000000 0x0 0x70000000 0x0 0x70000000 0x0 0x1000000 - 0xc3000000 0x20 0x00000000 0x20 0x00000000 0x20 0x00000000>; + ranges = <0x81000000 0x0 0x60080000 0x0 0x60080000 0x0 0x10000>, /* I/O */ + <0x82000000 0x0 0x60090000 0x0 0x60090000 0x0 0xff70000>, /* mem */ + <0x82000000 0x0 0x70000000 0x0 0x70000000 0x0 0x1000000>, /* mem */ + <0xc3000000 0x20 0x00000000 0x20 0x00000000 0x20 0x00000000>; /* mem prefetchable */ num-lanes = <0x8>; - interrupts = <56 57 58 59 60 61 62 63 64>; + interrupts = <56>, <57>, <58>, <59>, <60>, <61>, <62>, <63>, <64>; interrupt-names = "msi", "inta", "intb", "intc", "intd"; interrupt-parent = <&plic0>; interrupt-map-mask = <0x0 0x0 0x0 0x7>; @@ -316,13 +315,11 @@ <0x0 0x0 0x0 0x2 &plic0 58>, <0x0 0x0 0x0 0x3 &plic0 59>, <0x0 0x0 0x0 0x4 &plic0 60>; + clock-names = "pcie_aux"; + clocks = <&prci FU740_PRCI_CLK_PCIE_AUX>; pwren-gpios = <&gpio 5 0>; reset-gpios = <&gpio 8 0>; - clocks = <&prci PRCI_CLK_PCIEAUX>; - clock-names = "pcieaux"; - resets = <&prci PRCI_RST_PCIE_POWER_UP_N>; - reset-names = "rst_n"; - + resets = <&prci 4>; status = "okay"; }; }; diff --git a/arch/riscv/dts/hifive-unmatched-a00.dts b/arch/riscv/dts/hifive-unmatched-a00.dts index b44e8c160d..c4ed9efdff 100644 --- a/arch/riscv/dts/hifive-unmatched-a00.dts +++ b/arch/riscv/dts/hifive-unmatched-a00.dts @@ -1,5 +1,5 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* Copyright (c) 2019-2021 SiFive, Inc */ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* Copyright (c) 2020 SiFive, Inc */ #include "fu740-c000.dtsi" #include @@ -9,8 +9,6 @@ #define RTCCLK_FREQ 1000000 / { - #address-cells = <2>; - #size-cells = <2>; model = "SiFive HiFive Unmatched A00"; compatible = "sifive,hifive-unmatched-a00", "sifive,fu740-c000", "sifive,fu740"; @@ -28,9 +26,6 @@ reg = <0x0 0x80000000 0x4 0x00000000>; }; - soc { - }; - hfclk: hfclk { #clock-cells = <0>; compatible = "fixed-clock"; @@ -65,10 +60,21 @@ temperature-sensor@4c { compatible = "ti,tmp451"; reg = <0x4c>; + vcc-supply = <&vdd_bpro>; interrupt-parent = <&gpio>; interrupts = <6 IRQ_TYPE_LEVEL_LOW>; }; + eeprom@54 { + compatible = "microchip,24c02", "atmel,24c02"; + reg = <0x54>; + vcc-supply = <&vdd_bpro>; + label = "board-id"; + pagesize = <16>; + read-only; + size = <256>; + }; + pmic@58 { compatible = "dlg,da9063"; reg = <0x58>; @@ -76,48 +82,44 @@ interrupts = <1 IRQ_TYPE_LEVEL_LOW>; interrupt-controller; - regulators { - vdd_bcore1: bcore1 { - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - regulator-min-microamp = <5000000>; - regulator-max-microamp = <5000000>; - regulator-always-on; - }; + onkey { + compatible = "dlg,da9063-onkey"; + }; - vdd_bcore2: bcore2 { + rtc { + compatible = "dlg,da9063-rtc"; + }; + + wdt { + compatible = "dlg,da9063-watchdog"; + }; + + regulators { + vdd_bcore: bcores-merged { regulator-min-microvolt = <1050000>; regulator-max-microvolt = <1050000>; - regulator-min-microamp = <5000000>; - regulator-max-microamp = <5000000>; + regulator-min-microamp = <4800000>; + regulator-max-microamp = <4800000>; regulator-always-on; }; vdd_bpro: bpro { regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; - regulator-min-microamp = <2500000>; - regulator-max-microamp = <2500000>; + regulator-min-microamp = <2400000>; + regulator-max-microamp = <2400000>; regulator-always-on; }; vdd_bperi: bperi { - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; + regulator-min-microvolt = <1060000>; + regulator-max-microvolt = <1060000>; regulator-min-microamp = <1500000>; regulator-max-microamp = <1500000>; regulator-always-on; }; - vdd_bmem: bmem { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-min-microamp = <3000000>; - regulator-max-microamp = <3000000>; - regulator-always-on; - }; - - vdd_bio: bio { + vdd_bmem_bio: bmem-bio-merged { regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1200000>; regulator-min-microamp = <3000000>; @@ -128,86 +130,66 @@ vdd_ldo1: ldo1 { regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; - regulator-min-microamp = <100000>; - regulator-max-microamp = <100000>; regulator-always-on; }; vdd_ldo2: ldo2 { regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; - regulator-min-microamp = <200000>; - regulator-max-microamp = <200000>; regulator-always-on; }; vdd_ldo3: ldo3 { regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; - regulator-min-microamp = <200000>; - regulator-max-microamp = <200000>; regulator-always-on; }; vdd_ldo4: ldo4 { regulator-min-microvolt = <2500000>; regulator-max-microvolt = <2500000>; - regulator-min-microamp = <200000>; - regulator-max-microamp = <200000>; regulator-always-on; }; vdd_ldo5: ldo5 { regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; - regulator-min-microamp = <100000>; - regulator-max-microamp = <100000>; regulator-always-on; }; vdd_ldo6: ldo6 { regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; - regulator-min-microamp = <200000>; - regulator-max-microamp = <200000>; regulator-always-on; }; vdd_ldo7: ldo7 { regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; - regulator-min-microamp = <200000>; - regulator-max-microamp = <200000>; regulator-always-on; }; vdd_ldo8: ldo8 { regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; - regulator-min-microamp = <200000>; - regulator-max-microamp = <200000>; regulator-always-on; }; vdd_ld09: ldo9 { regulator-min-microvolt = <1050000>; regulator-max-microvolt = <1050000>; - regulator-min-microamp = <200000>; - regulator-max-microamp = <200000>; + regulator-always-on; }; vdd_ldo10: ldo10 { regulator-min-microvolt = <1000000>; regulator-max-microvolt = <1000000>; - regulator-min-microamp = <300000>; - regulator-max-microamp = <300000>; + regulator-always-on; }; vdd_ldo11: ldo11 { regulator-min-microvolt = <2500000>; regulator-max-microvolt = <2500000>; - regulator-min-microamp = <300000>; - regulator-max-microamp = <300000>; regulator-always-on; }; }; @@ -217,7 +199,7 @@ &qspi0 { status = "okay"; flash@0 { - compatible = "issi,is25wp256", "jedec,spi-nor"; + compatible = "jedec,spi-nor"; reg = <0>; spi-max-frequency = <50000000>; m25p,fast-read; @@ -234,6 +216,7 @@ spi-max-frequency = <20000000>; voltage-ranges = <3300 3300>; disable-wp; + gpios = <&gpio 15 GPIO_ACTIVE_LOW>; }; }; @@ -256,4 +239,8 @@ &gpio { status = "okay"; + gpio-line-names = "J29.1", "PMICNTB", "PMICSHDN", "J8.1", "J8.3", + "PCIe_PWREN", "THERM", "UBRDG_RSTN", "PCIe_PERSTN", + "ULPI_RSTN", "J8.2", "UHUB_RSTN", "GEMGXL_RST", "J8.4", + "EN_VDD_SD", "SD_CD"; }; diff --git a/board/CZ.NIC/turris_atsha_otp.c b/board/CZ.NIC/turris_atsha_otp.c index aa4e29b156..a29fe36231 100644 --- a/board/CZ.NIC/turris_atsha_otp.c +++ b/board/CZ.NIC/turris_atsha_otp.c @@ -93,30 +93,57 @@ int turris_atsha_otp_init_mac_addresses(int first_idx) return 0; } -int turris_atsha_otp_get_serial_number(u32 *version_num, u32 *serial_num) +int turris_atsha_otp_init_serial_number(void) +{ + char serial[17]; + int ret; + + ret = turris_atsha_otp_get_serial_number(serial); + if (ret) + return ret; + + if (!env_get("serial#")) + return -1; + + return 0; +} + +int turris_atsha_otp_get_serial_number(char serial[17]) { struct udevice *dev = get_atsha204a_dev(); + u32 version_num, serial_num; + const char *serial_env; int ret; if (!dev) return -1; + serial_env = env_get("serial#"); + if (serial_env && strlen(serial_env) == 16) { + memcpy(serial, serial_env, 17); + return 0; + } + ret = atsha204a_wakeup(dev); if (ret) return ret; ret = atsha204a_read(dev, ATSHA204A_ZONE_OTP, false, TURRIS_ATSHA_OTP_VERSION, - (u8 *)version_num); + (u8 *)&version_num); if (ret) return ret; ret = atsha204a_read(dev, ATSHA204A_ZONE_OTP, false, TURRIS_ATSHA_OTP_SERIAL, - (u8 *)serial_num); + (u8 *)&serial_num); if (ret) return ret; atsha204a_sleep(dev); + + sprintf(serial, "%08X%08X", be32_to_cpu(version_num), be32_to_cpu(serial_num)); + env_set("serial#", serial); + return 0; } diff --git a/board/CZ.NIC/turris_atsha_otp.h b/board/CZ.NIC/turris_atsha_otp.h index bd4308fdc3..2cfe20bbc3 100644 --- a/board/CZ.NIC/turris_atsha_otp.h +++ b/board/CZ.NIC/turris_atsha_otp.h @@ -4,6 +4,7 @@ #define TURRIS_ATSHA_OTP_H int turris_atsha_otp_init_mac_addresses(int first_idx); -int turris_atsha_otp_get_serial_number(u32 *version_num, u32 *serial_num); +int turris_atsha_otp_init_serial_number(void); +int turris_atsha_otp_get_serial_number(char serial[17]); #endif diff --git a/board/CZ.NIC/turris_mox/turris_mox.c b/board/CZ.NIC/turris_mox/turris_mox.c index 3dbd68e523..ff1c4cb170 100644 --- a/board/CZ.NIC/turris_mox/turris_mox.c +++ b/board/CZ.NIC/turris_mox/turris_mox.c @@ -23,6 +23,7 @@ #include #include #include +#include #include "mox_sp.h" @@ -339,6 +340,51 @@ static int get_reset_gpio(struct gpio_desc *reset_gpio) return 0; } +/* Load default system DTB binary to $fdr_addr */ +static void load_spi_dtb(void) +{ + const char *const env_name[1] = { "fdt_addr" }; + unsigned long size, offset; + struct udevice *spi_dev; + struct spi_flash *flash; + const char *addr_str; + unsigned long addr; + void *buf; + + addr_str = env_get(env_name[0]); + if (!addr_str) { + env_set_default_vars(1, (char * const *)env_name, 0); + addr_str = env_get(env_name[0]); + } + + if (!addr_str) + return; + + addr = hextoul(addr_str, NULL); + if (!addr) + return; + + spi_flash_probe_bus_cs(CONFIG_SF_DEFAULT_BUS, CONFIG_SF_DEFAULT_CS, &spi_dev); + flash = dev_get_uclass_priv(spi_dev); + if (!flash) + return; + + /* + * SPI NOR "dtb" partition offset & size hardcoded for now because the + * mtd subsystem does not offer finding the partition yet and we do not + * want to reimplement OF partition parser here. + */ + offset = 0x7f0000; + size = 0x10000; + + buf = map_physmem(addr, size, MAP_WRBACK); + if (!buf) + return; + + spi_flash_read(flash, offset, size, buf); + unmap_physmem(buf, size); +} + int misc_init_r(void) { u8 mac[2][6]; @@ -358,6 +404,8 @@ int misc_init_r(void) eth_env_set_enetaddr_by_index("eth", i, mac[i]); } + load_spi_dtb(); + return 0; } @@ -440,8 +488,9 @@ static void handle_reset_button(void) env_set_default_vars(1, (char * const *)vars, 0); if (read_reset_button()) { - const char * const vars[2] = { + const char * const vars[3] = { "bootcmd", + "bootdelay", "distro_bootcmd", }; @@ -449,7 +498,7 @@ static void handle_reset_button(void) * Set the above envs to their default values, in case the user * managed to break them. */ - env_set_default_vars(2, (char * const *)vars, 0); + env_set_default_vars(3, (char * const *)vars, 0); /* Ensure bootcmd_rescue is used by distroboot */ env_set("boot_targets", "rescue"); diff --git a/board/CZ.NIC/turris_omnia/turris_omnia.c b/board/CZ.NIC/turris_omnia/turris_omnia.c index ab5061ef58..19c5043fcb 100644 --- a/board/CZ.NIC/turris_omnia/turris_omnia.c +++ b/board/CZ.NIC/turris_omnia/turris_omnia.c @@ -549,8 +549,9 @@ static void handle_reset_button(void) env_set_ulong("omnia_reset", reset_status); if (reset_status) { - const char * const vars[2] = { + const char * const vars[3] = { "bootcmd", + "bootdelay", "distro_bootcmd", }; @@ -558,7 +559,7 @@ static void handle_reset_button(void) * Set the above envs to their default values, in case the user * managed to break them. */ - env_set_default_vars(2, (char * const *)vars, 0); + env_set_default_vars(3, (char * const *)vars, 0); /* Ensure bootcmd_rescue is used by distroboot */ env_set("boot_targets", "rescue"); @@ -653,7 +654,7 @@ static void initialize_switch(void) ctrl[1] = EXT_CTL_nRES_LAN; err = omnia_mcu_write(CMD_EXT_CONTROL, ctrl, sizeof(ctrl)); - mdelay(10); + mdelay(50); /* Change RGMII pins back to RGMII mode */ @@ -963,19 +964,15 @@ int board_late_init(void) int show_board_info(void) { - u32 version_num, serial_num; + char serial[17]; int err; - err = turris_atsha_otp_get_serial_number(&version_num, &serial_num); + err = turris_atsha_otp_get_serial_number(serial); printf("Model: Turris Omnia\n"); printf(" MCU type: %s\n", omnia_get_mcu_type()); printf(" MCU version: %s\n", omnia_get_mcu_version()); printf(" RAM size: %i MiB\n", omnia_get_ram_size_gb() * 1024); - if (err) - printf(" Serial Number: unknown\n"); - else - printf(" Serial Number: %08X%08X\n", be32_to_cpu(version_num), - be32_to_cpu(serial_num)); + printf(" Serial Number: %s\n", !err ? serial : "unknown"); return 0; } @@ -983,6 +980,7 @@ int show_board_info(void) int misc_init_r(void) { turris_atsha_otp_init_mac_addresses(1); + turris_atsha_otp_init_serial_number(); return 0; } diff --git a/board/Marvell/mvebu_armada-37xx/board.c b/board/Marvell/mvebu_armada-37xx/board.c index 3e5e0a0b5c..c6ecc323bb 100644 --- a/board/Marvell/mvebu_armada-37xx/board.c +++ b/board/Marvell/mvebu_armada-37xx/board.c @@ -132,6 +132,8 @@ int board_late_init(void) dev = mmc_dev->dev; device_remove(dev, DM_REMOVE_NORMAL); device_unbind(dev); + if (of_live_active()) + ofnode_set_enabled(dev_ofnode(dev), false); } /* Ensure that 'env default -a' set correct value to $fdtfile */ diff --git a/board/bsh/imx6ulz_smm_m2/Kconfig b/board/bsh/imx6ulz_smm_m2/Kconfig new file mode 100644 index 0000000000..e38df7ce5c --- /dev/null +++ b/board/bsh/imx6ulz_smm_m2/Kconfig @@ -0,0 +1,12 @@ +if TARGET_MX6ULZ_SMM_M2 + +config SYS_BOARD + default "imx6ulz_smm_m2" + +config SYS_VENDOR + default "bsh" + +config SYS_CONFIG_NAME + default "imx6ulz_smm_m2" + +endif diff --git a/board/bsh/imx6ulz_smm_m2/MAINTAINERS b/board/bsh/imx6ulz_smm_m2/MAINTAINERS new file mode 100644 index 0000000000..8f3d79dbb8 --- /dev/null +++ b/board/bsh/imx6ulz_smm_m2/MAINTAINERS @@ -0,0 +1,6 @@ +MX6ULZ_SMM_M2 BOARD +M: Michael Trimarchi +S: Maintained +F: board/bsh/mx6ulz_smm_m2/ +F: include/configs/imx6ulz_smm_m2.h +F: configs/imx6ulz_smm_m2_defconfig diff --git a/board/bsh/imx6ulz_smm_m2/Makefile b/board/bsh/imx6ulz_smm_m2/Makefile new file mode 100644 index 0000000000..b761bbb2f9 --- /dev/null +++ b/board/bsh/imx6ulz_smm_m2/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0+ +# (C) Copyright 2021 Amarula Solutions B.V. + +obj-y := imx6ulz_smm_m2.o +obj-$(CONFIG_SPL_BUILD) += spl.o + diff --git a/board/bsh/imx6ulz_smm_m2/README b/board/bsh/imx6ulz_smm_m2/README new file mode 100644 index 0000000000..03d01325a9 --- /dev/null +++ b/board/bsh/imx6ulz_smm_m2/README @@ -0,0 +1,67 @@ +How to Update U-Boot on imx6ulz_smm_m2 board +-------------------------------------------- + +Required software on the host PC: + +- UUU: https://github.com/NXPmicro/mfgtools + +Build U-Boot for m2: + +$ make mrproper +$ make imx6ulz_smm_m2_defconfig +$ make + +This generates the SPL and u-boot-dtb.img binaries. + +1. Loading U-Boot via USB Serial Download Protocol + +Copy SPL and u-boot-dtb.img to the uuu folder. + +Load the U-Boot via USB: + +$ sudo uuu -v -b nand_script.lst u-boot-with-spl.imx + +where nand_script.lst contains the following: + +uuu_version 1.2.39 + +# @_flash.bin | bootloader +# @_image [_flash.bin] | image burn to nand, default is the same as bootloader + +# This command will be run when i.MX6/7 i.MX8MM, i.MX8MQ +SDP: boot -f _flash.bin + +# This command will be run when ROM support stream mode +# i.MX8QXP, i.MX8QM +SDPS: boot -f _flash.bin + +# These commands will be run when use SPL and will be skipped if no spl +# SDPU will be deprecated. please use SDPV instead of SDPU +# { +SDPU: delay 1000 +SDPU: write -f _flash.bin -offset 0x57c00 +SDPU: jump +# } + +# These commands will be run when use SPL and will be skipped if no spl +# if (SPL support SDPV) +# { +SDPV: delay 1000 +SDPV: write -f _flash.bin -offset 0x11000 +SDPV: jump +# } + +FB: ucmd setenv fastboot_buffer ${loadaddr} +FB: download -f _image +FB: ucmd if test ! -n "$fastboot_bytes"; then setenv fastboot_bytes $filesize; else true; fi +# Burn image to nandfit partition if needed +FB: ucmd if env exists nandfit_part; then nand erase.part nandfit; nand write ${fastboot_buffer} nandfit ${fastboot_bytes}; else true; fi; +FB: ucmd nandbcb init ${fastboot_buffer} nandboot ${fastboot_bytes} +FB: Done + +Then U-Boot starts and its messages appear in the console program. + +Use the default environment variables: + +=> env default -f -a +=> saveenv diff --git a/board/bsh/imx6ulz_smm_m2/imx6ulz_smm_m2.c b/board/bsh/imx6ulz_smm_m2/imx6ulz_smm_m2.c new file mode 100644 index 0000000000..c82eabbfbe --- /dev/null +++ b/board/bsh/imx6ulz_smm_m2/imx6ulz_smm_m2.c @@ -0,0 +1,53 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * + * Copyright (C) 2021 BSH Hausgeraete GmbH + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static void setup_gpmi_nand(void) +{ + setup_gpmi_io_clk((MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) | + MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) | + MXC_CCM_CS2CDR_ENFC_CLK_SEL(3))); +}; + +int dram_init(void) +{ + gd->ram_size = imx_ddr_size(); + + return 0; +} + +int board_init(void) +{ + /* Address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + + setup_gpmi_nand(); + + return 0; +} + +int board_late_init(void) +{ + if (is_boot_from_usb()) { + env_set("bootcmd", "run bootcmd_mfg"); + env_set("bootdelay", "0"); + } + + return 0; +} diff --git a/board/bsh/imx6ulz_smm_m2/spl.c b/board/bsh/imx6ulz_smm_m2/spl.c new file mode 100644 index 0000000000..5b4812e129 --- /dev/null +++ b/board/bsh/imx6ulz_smm_m2/spl.c @@ -0,0 +1,130 @@ +// SPDX-License-Identifier: GPL-2.0+ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +static const iomux_v3_cfg_t uart4_pads[] = { + MX6_PAD_UART4_TX_DATA__UART4_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_UART4_RX_DATA__UART4_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +static void setup_iomux_uart(void) +{ + imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads)); +} + +static struct mx6ul_iomux_grp_regs mx6_grp_ioregs = { + .grp_addds = 0x00000028, + .grp_ddrmode_ctl = 0x00020000, + .grp_b0ds = 0x00000028, + .grp_ctlds = 0x00000028, + .grp_b1ds = 0x00000028, + .grp_ddrpke = 0x00000000, + .grp_ddrmode = 0x00020000, + .grp_ddr_type = 0x000c0000, +}; + +static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = { + .dram_dqm0 = 0x00000028, + .dram_dqm1 = 0x00000028, + .dram_ras = 0x00000028, + .dram_cas = 0x00000028, + .dram_odt0 = 0x00000028, + .dram_odt1 = 0x00000028, + .dram_sdba2 = 0x00000000, + .dram_sdclk_0 = 0x00000028, + .dram_sdqs0 = 0x00000028, + .dram_sdqs1 = 0x00000028, + .dram_reset = 0x000c0028, +}; + +static struct mx6_mmdc_calibration mx6_mmcd_calib = { + .p0_mpwldectrl0 = 0x00000000, + .p0_mpwldectrl1 = 0x00100010, + .p0_mpdgctrl0 = 0x414c014c, + .p0_mpdgctrl1 = 0x00000000, + .p0_mprddlctl = 0x40403a42, + .p0_mpwrdlctl = 0x4040342e, +}; + +static struct mx6_ddr_sysinfo ddr_sysinfo = { + .dsize = 0, + .cs1_mirror = 0, + .cs_density = 32, + .ncs = 1, + .bi_on = 1, + .rtt_nom = 1, + .rtt_wr = 0, + .ralat = 5, + .walat = 1, + .mif3_mode = 3, + .rst_to_cke = 0x23, /* 33 cycles (JEDEC value for DDR3) - total of 500 us */ + .sde_to_rst = 0x10, /* 14 cycles (JEDEC value for DDR3) - total of 200 us */ + .refsel = 1, + .refr = 3, +}; + +static struct mx6_ddr3_cfg mem_ddr = { + .mem_speed = 1333, + .density = 2, + .width = 16, + .banks = 8, + .rowaddr = 13, + .coladdr = 10, + .pagesz = 2, + .trcd = 1350, + .trcmin = 4950, + .trasmin = 3600, +}; + +static void ccgr_init(void) +{ + struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + + writel(0xFFFFFFFF, &ccm->CCGR0); + writel(0xFFFFFFFF, &ccm->CCGR1); + writel(0xFFFFFFFF, &ccm->CCGR2); + writel(0xFFFFFFFF, &ccm->CCGR3); + writel(0xFFFFFFFF, &ccm->CCGR4); + writel(0xFFFFFFFF, &ccm->CCGR5); + writel(0xFFFFFFFF, &ccm->CCGR6); +} + +static void imx6ul_spl_dram_cfg(void) +{ + mx6ul_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs); + mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_calib, &mem_ddr); +} + +void board_init_f(ulong dummy) +{ + ccgr_init(); + arch_cpu_init(); + timer_init(); + setup_iomux_uart(); + preloader_console_init(); + imx6ul_spl_dram_cfg(); +} + +void reset_cpu(void) +{ +} diff --git a/board/data_modul/imx8mm_edm_sbc/lpddr4_timing_2G_32.c b/board/data_modul/imx8mm_edm_sbc/lpddr4_timing_2G_32.c index c2abcb5489..f40fd48fc4 100644 --- a/board/data_modul/imx8mm_edm_sbc/lpddr4_timing_2G_32.c +++ b/board/data_modul/imx8mm_edm_sbc/lpddr4_timing_2G_32.c @@ -22,7 +22,7 @@ static struct dram_cfg_param ddr_ddrc_cfg[] = { { 0x3d4000d4, 0x940000 }, { 0x3d4000dc, 0xd4002d }, { 0x3d4000e0, 0x310000 }, - { 0x3d4000e8, 0x66004d }, + { 0x3d4000e8, 0x36004d }, { 0x3d4000ec, 0x16004d }, { 0x3d400100, 0x191e1920 }, { 0x3d400104, 0x60630 }, @@ -55,6 +55,7 @@ static struct dram_cfg_param ddr_ddrc_cfg[] = { { 0x3d400204, 0x80808 }, { 0x3d400214, 0x7070707 }, { 0x3d400218, 0x7070707 }, + { 0x3d40021c, 0xf0f }, { 0x3d400250, 0x29001701 }, { 0x3d400254, 0x2c }, { 0x3d40025c, 0x4000030 }, @@ -72,7 +73,7 @@ static struct dram_cfg_param ddr_ddrc_cfg[] = { { 0x3d402064, 0xc001c }, { 0x3d4020dc, 0x840000 }, { 0x3d4020e0, 0x310000 }, - { 0x3d4020e8, 0x66004d }, + { 0x3d4020e8, 0x36004d }, { 0x3d4020ec, 0x16004d }, { 0x3d402100, 0xa040305 }, { 0x3d402104, 0x30407 }, @@ -97,7 +98,7 @@ static struct dram_cfg_param ddr_ddrc_cfg[] = { { 0x3d403064, 0x30007 }, { 0x3d4030dc, 0x840000 }, { 0x3d4030e0, 0x310000 }, - { 0x3d4030e8, 0x66004d }, + { 0x3d4030e8, 0x36004d }, { 0x3d4030ec, 0x16004d }, { 0x3d403100, 0xa010102 }, { 0x3d403104, 0x30404 }, @@ -1059,25 +1060,25 @@ static struct dram_cfg_param ddr_fsp0_cfg[] = { { 0x54012, 0x110 }, { 0x54019, 0x2dd4 }, { 0x5401a, 0x31 }, - { 0x5401b, 0x4d66 }, + { 0x5401b, 0x4d36 }, { 0x5401c, 0x4d00 }, { 0x5401e, 0x16 }, { 0x5401f, 0x2dd4 }, { 0x54020, 0x31 }, - { 0x54021, 0x4d66 }, + { 0x54021, 0x4d36 }, { 0x54022, 0x4d00 }, { 0x54024, 0x16 }, { 0x5402b, 0x1000 }, { 0x5402c, 0x1 }, { 0x54032, 0xd400 }, { 0x54033, 0x312d }, - { 0x54034, 0x6600 }, + { 0x54034, 0x3600 }, { 0x54035, 0x4d }, { 0x54036, 0x4d }, { 0x54037, 0x1600 }, { 0x54038, 0xd400 }, { 0x54039, 0x312d }, - { 0x5403a, 0x6600 }, + { 0x5403a, 0x3600 }, { 0x5403b, 0x4d }, { 0x5403c, 0x4d }, { 0x5403d, 0x1600 }, @@ -1098,25 +1099,25 @@ static struct dram_cfg_param ddr_fsp1_cfg[] = { { 0x54012, 0x110 }, { 0x54019, 0x84 }, { 0x5401a, 0x31 }, - { 0x5401b, 0x4d66 }, + { 0x5401b, 0x4d36 }, { 0x5401c, 0x4d00 }, { 0x5401e, 0x16 }, { 0x5401f, 0x84 }, { 0x54020, 0x31 }, - { 0x54021, 0x4d66 }, + { 0x54021, 0x4d36 }, { 0x54022, 0x4d00 }, { 0x54024, 0x16 }, { 0x5402b, 0x1000 }, { 0x5402c, 0x1 }, { 0x54032, 0x8400 }, { 0x54033, 0x3100 }, - { 0x54034, 0x6600 }, + { 0x54034, 0x3600 }, { 0x54035, 0x4d }, { 0x54036, 0x4d }, { 0x54037, 0x1600 }, { 0x54038, 0x8400 }, { 0x54039, 0x3100 }, - { 0x5403a, 0x6600 }, + { 0x5403a, 0x3600 }, { 0x5403b, 0x4d }, { 0x5403c, 0x4d }, { 0x5403d, 0x1600 }, @@ -1137,25 +1138,25 @@ static struct dram_cfg_param ddr_fsp2_cfg[] = { { 0x54012, 0x110 }, { 0x54019, 0x84 }, { 0x5401a, 0x31 }, - { 0x5401b, 0x4d66 }, + { 0x5401b, 0x4d36 }, { 0x5401c, 0x4d00 }, { 0x5401e, 0x16 }, { 0x5401f, 0x84 }, { 0x54020, 0x31 }, - { 0x54021, 0x4d66 }, + { 0x54021, 0x4d36 }, { 0x54022, 0x4d00 }, { 0x54024, 0x16 }, { 0x5402b, 0x1000 }, { 0x5402c, 0x1 }, { 0x54032, 0x8400 }, { 0x54033, 0x3100 }, - { 0x54034, 0x6600 }, + { 0x54034, 0x3600 }, { 0x54035, 0x4d }, { 0x54036, 0x4d }, { 0x54037, 0x1600 }, { 0x54038, 0x8400 }, { 0x54039, 0x3100 }, - { 0x5403a, 0x6600 }, + { 0x5403a, 0x3600 }, { 0x5403b, 0x4d }, { 0x5403c, 0x4d }, { 0x5403d, 0x1600 }, @@ -1177,25 +1178,25 @@ static struct dram_cfg_param ddr_fsp0_2d_cfg[] = { { 0x54012, 0x110 }, { 0x54019, 0x2dd4 }, { 0x5401a, 0x31 }, - { 0x5401b, 0x4d66 }, + { 0x5401b, 0x4d36 }, { 0x5401c, 0x4d00 }, { 0x5401e, 0x16 }, { 0x5401f, 0x2dd4 }, { 0x54020, 0x31 }, - { 0x54021, 0x4d66 }, + { 0x54021, 0x4d36 }, { 0x54022, 0x4d00 }, { 0x54024, 0x16 }, { 0x5402b, 0x1000 }, { 0x5402c, 0x1 }, { 0x54032, 0xd400 }, { 0x54033, 0x312d }, - { 0x54034, 0x6600 }, + { 0x54034, 0x3600 }, { 0x54035, 0x4d }, { 0x54036, 0x4d }, { 0x54037, 0x1600 }, { 0x54038, 0xd400 }, { 0x54039, 0x312d }, - { 0x5403a, 0x6600 }, + { 0x5403a, 0x3600 }, { 0x5403b, 0x4d }, { 0x5403c, 0x4d }, { 0x5403d, 0x1600 }, @@ -1692,15 +1693,15 @@ static struct dram_cfg_param ddr_phy_pie[] = { { 0x400d6, 0x20a }, { 0x400d7, 0x20b }, { 0x2003a, 0x2 }, - { 0x2000b, 0x5d }, + { 0x2000b, 0x34b }, { 0x2000c, 0xbb }, { 0x2000d, 0x753 }, { 0x2000e, 0x2c }, - { 0x12000b, 0xc }, + { 0x12000b, 0x70 }, { 0x12000c, 0x19 }, { 0x12000d, 0xfa }, { 0x12000e, 0x10 }, - { 0x22000b, 0x3 }, + { 0x22000b, 0x1c }, { 0x22000c, 0x6 }, { 0x22000d, 0x3e }, { 0x22000e, 0x10 }, diff --git a/board/data_modul/imx8mm_edm_sbc/lpddr4_timing_4G_32.c b/board/data_modul/imx8mm_edm_sbc/lpddr4_timing_4G_32.c index e44c1ea277..0e5be8efd0 100644 --- a/board/data_modul/imx8mm_edm_sbc/lpddr4_timing_4G_32.c +++ b/board/data_modul/imx8mm_edm_sbc/lpddr4_timing_4G_32.c @@ -22,7 +22,7 @@ static struct dram_cfg_param ddr_ddrc_cfg[] = { { 0x3d4000d4, 0x940000 }, { 0x3d4000dc, 0xd4002d }, { 0x3d4000e0, 0x310000 }, - { 0x3d4000e8, 0x66004d }, + { 0x3d4000e8, 0x36004d }, { 0x3d4000ec, 0x16004d }, { 0x3d400100, 0x191e1920 }, { 0x3d400104, 0x60630 }, @@ -55,6 +55,7 @@ static struct dram_cfg_param ddr_ddrc_cfg[] = { { 0x3d400204, 0x80808 }, { 0x3d400214, 0x7070707 }, { 0x3d400218, 0x7070707 }, + { 0x3d40021c, 0xf0f }, { 0x3d400250, 0x29001701 }, { 0x3d400254, 0x2c }, { 0x3d40025c, 0x4000030 }, @@ -72,7 +73,7 @@ static struct dram_cfg_param ddr_ddrc_cfg[] = { { 0x3d402064, 0xc001c }, { 0x3d4020dc, 0x840000 }, { 0x3d4020e0, 0x310000 }, - { 0x3d4020e8, 0x66004d }, + { 0x3d4020e8, 0x36004d }, { 0x3d4020ec, 0x16004d }, { 0x3d402100, 0xa040305 }, { 0x3d402104, 0x30407 }, @@ -1059,25 +1060,25 @@ static struct dram_cfg_param ddr_fsp0_cfg[] = { { 0x54012, 0x310 }, { 0x54019, 0x2dd4 }, { 0x5401a, 0x31 }, - { 0x5401b, 0x4d66 }, + { 0x5401b, 0x4d36 }, { 0x5401c, 0x4d00 }, { 0x5401e, 0x16 }, { 0x5401f, 0x2dd4 }, { 0x54020, 0x31 }, - { 0x54021, 0x4d66 }, + { 0x54021, 0x4d36 }, { 0x54022, 0x4d00 }, { 0x54024, 0x16 }, { 0x5402b, 0x1000 }, { 0x5402c, 0x3 }, { 0x54032, 0xd400 }, { 0x54033, 0x312d }, - { 0x54034, 0x6600 }, + { 0x54034, 0x3600 }, { 0x54035, 0x4d }, { 0x54036, 0x4d }, { 0x54037, 0x1600 }, { 0x54038, 0xd400 }, { 0x54039, 0x312d }, - { 0x5403a, 0x6600 }, + { 0x5403a, 0x3600 }, { 0x5403b, 0x4d }, { 0x5403c, 0x4d }, { 0x5403d, 0x1600 }, @@ -1098,25 +1099,25 @@ static struct dram_cfg_param ddr_fsp1_cfg[] = { { 0x54012, 0x310 }, { 0x54019, 0x84 }, { 0x5401a, 0x31 }, - { 0x5401b, 0x4d66 }, + { 0x5401b, 0x4d36 }, { 0x5401c, 0x4d00 }, { 0x5401e, 0x16 }, { 0x5401f, 0x84 }, { 0x54020, 0x31 }, - { 0x54021, 0x4d66 }, + { 0x54021, 0x4d36 }, { 0x54022, 0x4d00 }, { 0x54024, 0x16 }, { 0x5402b, 0x1000 }, { 0x5402c, 0x3 }, { 0x54032, 0x8400 }, { 0x54033, 0x3100 }, - { 0x54034, 0x6600 }, + { 0x54034, 0x3600 }, { 0x54035, 0x4d }, { 0x54036, 0x4d }, { 0x54037, 0x1600 }, { 0x54038, 0x8400 }, { 0x54039, 0x3100 }, - { 0x5403a, 0x6600 }, + { 0x5403a, 0x3600 }, { 0x5403b, 0x4d }, { 0x5403c, 0x4d }, { 0x5403d, 0x1600 }, @@ -1172,31 +1173,30 @@ static struct dram_cfg_param ddr_fsp0_2d_cfg[] = { { 0x54008, 0x61 }, { 0x54009, 0xc8 }, { 0x5400b, 0x2 }, - { 0x5400d, 0x100 }, { 0x5400f, 0x100 }, { 0x54010, 0x1f7f }, { 0x54012, 0x310 }, { 0x54019, 0x2dd4 }, { 0x5401a, 0x31 }, - { 0x5401b, 0x4d66 }, + { 0x5401b, 0x4d36 }, { 0x5401c, 0x4d00 }, { 0x5401e, 0x16 }, { 0x5401f, 0x2dd4 }, { 0x54020, 0x31 }, - { 0x54021, 0x4d66 }, + { 0x54021, 0x4d36 }, { 0x54022, 0x4d00 }, { 0x54024, 0x16 }, { 0x5402b, 0x1000 }, { 0x5402c, 0x3 }, { 0x54032, 0xd400 }, { 0x54033, 0x312d }, - { 0x54034, 0x6600 }, + { 0x54034, 0x3600 }, { 0x54035, 0x4d }, { 0x54036, 0x4d }, { 0x54037, 0x1600 }, { 0x54038, 0xd400 }, { 0x54039, 0x312d }, - { 0x5403a, 0x6600 }, + { 0x5403a, 0x3600 }, { 0x5403b, 0x4d }, { 0x5403c, 0x4d }, { 0x5403d, 0x1600 }, @@ -1693,15 +1693,15 @@ static struct dram_cfg_param ddr_phy_pie[] = { { 0x400d6, 0x20a }, { 0x400d7, 0x20b }, { 0x2003a, 0x2 }, - { 0x2000b, 0x5d }, + { 0x2000b, 0x34b }, { 0x2000c, 0xbb }, { 0x2000d, 0x753 }, { 0x2000e, 0x2c }, - { 0x12000b, 0xc }, + { 0x12000b, 0x70 }, { 0x12000c, 0x19 }, { 0x12000d, 0xfa }, { 0x12000e, 0x10 }, - { 0x22000b, 0x3 }, + { 0x22000b, 0x1c }, { 0x22000c, 0x6 }, { 0x22000d, 0x3e }, { 0x22000e, 0x10 }, @@ -1715,6 +1715,10 @@ static struct dram_cfg_param ddr_phy_pie[] = { { 0x90013, 0x6152 }, { 0x20010, 0x5a }, { 0x20011, 0x3 }, + { 0x120010, 0x5a }, + { 0x120011, 0x3 }, + { 0x220010, 0x5a }, + { 0x220011, 0x3 }, { 0x40080, 0xe0 }, { 0x40081, 0x12 }, { 0x40082, 0xe0 }, diff --git a/board/dhelectronics/dh_imx8mp/lpddr4_timing_4G_32.c b/board/dhelectronics/dh_imx8mp/lpddr4_timing_4G_32.c index 2eda4a5956..a4c1b121c2 100644 --- a/board/dhelectronics/dh_imx8mp/lpddr4_timing_4G_32.c +++ b/board/dhelectronics/dh_imx8mp/lpddr4_timing_4G_32.c @@ -1799,8 +1799,8 @@ static struct dram_cfg_param ddr_phy_pie[] = { static struct dram_fsp_msg ddr_dram_fsp_msg[] = { { - /* P0 3732mts 1D */ - .drate = 3732, + /* P0 3733mts 1D */ + .drate = 3733, .fw_type = FW_1D_IMAGE, .fsp_cfg = ddr_fsp0_cfg, .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg), @@ -1820,8 +1820,8 @@ static struct dram_fsp_msg ddr_dram_fsp_msg[] = { .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg), }, { - /* P0 3732mts 2D */ - .drate = 3732, + /* P0 3733mts 2D */ + .drate = 3733, .fw_type = FW_2D_IMAGE, .fsp_cfg = ddr_fsp0_2d_cfg, .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg), @@ -1840,5 +1840,5 @@ struct dram_timing_info dh_imx8mp_dhcom_dram_timing_32g_x32 = { .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr), .ddrphy_pie = ddr_phy_pie, .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), - .fsp_table = { 3732, 400, 100, }, + .fsp_table = { 3733, 400, 100, }, }; diff --git a/board/dhelectronics/dh_stm32mp1/board.c b/board/dhelectronics/dh_stm32mp1/board.c index 7e4f3ff157..2bc0d7b943 100644 --- a/board/dhelectronics/dh_stm32mp1/board.c +++ b/board/dhelectronics/dh_stm32mp1/board.c @@ -527,56 +527,6 @@ static void sysconf_init(void) #endif } -static void board_init_fmc2(void) -{ -#define STM32_FMC2_BCR1 0x0 -#define STM32_FMC2_BTR1 0x4 -#define STM32_FMC2_BWTR1 0x104 -#define STM32_FMC2_BCR(x) ((x) * 0x8 + STM32_FMC2_BCR1) -#define STM32_FMC2_BCRx_FMCEN BIT(31) -#define STM32_FMC2_BCRx_WREN BIT(12) -#define STM32_FMC2_BCRx_RSVD BIT(7) -#define STM32_FMC2_BCRx_FACCEN BIT(6) -#define STM32_FMC2_BCRx_MWID(n) ((n) << 4) -#define STM32_FMC2_BCRx_MTYP(n) ((n) << 2) -#define STM32_FMC2_BCRx_MUXEN BIT(1) -#define STM32_FMC2_BCRx_MBKEN BIT(0) -#define STM32_FMC2_BTR(x) ((x) * 0x8 + STM32_FMC2_BTR1) -#define STM32_FMC2_BTRx_DATAHLD(n) ((n) << 30) -#define STM32_FMC2_BTRx_BUSTURN(n) ((n) << 16) -#define STM32_FMC2_BTRx_DATAST(n) ((n) << 8) -#define STM32_FMC2_BTRx_ADDHLD(n) ((n) << 4) -#define STM32_FMC2_BTRx_ADDSET(n) ((n) << 0) - -#define RCC_MP_AHB6RSTCLRR 0x218 -#define RCC_MP_AHB6RSTCLRR_FMCRST BIT(12) -#define RCC_MP_AHB6ENSETR 0x19c -#define RCC_MP_AHB6ENSETR_FMCEN BIT(12) - - const u32 bcr = STM32_FMC2_BCRx_WREN |STM32_FMC2_BCRx_RSVD | - STM32_FMC2_BCRx_FACCEN | STM32_FMC2_BCRx_MWID(1) | - STM32_FMC2_BCRx_MTYP(2) | STM32_FMC2_BCRx_MUXEN | - STM32_FMC2_BCRx_MBKEN; - const u32 btr = STM32_FMC2_BTRx_DATAHLD(3) | - STM32_FMC2_BTRx_BUSTURN(2) | - STM32_FMC2_BTRx_DATAST(0x22) | - STM32_FMC2_BTRx_ADDHLD(2) | - STM32_FMC2_BTRx_ADDSET(2); - - /* Set up FMC2 bus for KS8851-16MLL and X11 SRAM */ - writel(RCC_MP_AHB6RSTCLRR_FMCRST, STM32_RCC_BASE + RCC_MP_AHB6RSTCLRR); - writel(RCC_MP_AHB6ENSETR_FMCEN, STM32_RCC_BASE + RCC_MP_AHB6ENSETR); - - /* KS8851-16MLL -- Muxed mode */ - writel(bcr, STM32_FMC2_BASE + STM32_FMC2_BCR(1)); - writel(btr, STM32_FMC2_BASE + STM32_FMC2_BTR(1)); - /* AS7C34098 SRAM on X11 -- Muxed mode */ - writel(bcr, STM32_FMC2_BASE + STM32_FMC2_BCR(3)); - writel(btr, STM32_FMC2_BASE + STM32_FMC2_BTR(3)); - - setbits_le32(STM32_FMC2_BASE + STM32_FMC2_BCR1, STM32_FMC2_BCRx_FMCEN); -} - #ifdef CONFIG_DM_REGULATOR #define STPMIC_NVM_BUCKS_VOUT_SHR 0xfc #define STPMIC_NVM_BUCKS_VOUT_SHR_BUCK_1V2 0 @@ -671,8 +621,6 @@ int board_init(void) sysconf_init(); - board_init_fmc2(); - return 0; } diff --git a/board/firefly/firefly-rk3308/roc_cc_rk3308.c b/board/firefly/firefly-rk3308/roc_cc_rk3308.c index 28dcc2a690..bdf3cc03dc 100644 --- a/board/firefly/firefly-rk3308/roc_cc_rk3308.c +++ b/board/firefly/firefly-rk3308/roc_cc_rk3308.c @@ -70,7 +70,7 @@ int rockchip_dnl_key_pressed(void) { unsigned int val; - if (adc_channel_single_shot("saradc", 1, &val)) { + if (adc_channel_single_shot("saradc@ff1e0000", 1, &val)) { printf("%s read adc key val failed\n", __func__); return false; } diff --git a/board/freescale/imxrt1170-evk/Kconfig b/board/freescale/imxrt1170-evk/Kconfig new file mode 100644 index 0000000000..c61fc57971 --- /dev/null +++ b/board/freescale/imxrt1170-evk/Kconfig @@ -0,0 +1,22 @@ +if TARGET_IMXRT1170_EVK + +config SYS_BOARD + string + default "imxrt1170-evk" + +config SYS_VENDOR + string + default "freescale" + +config SYS_SOC + string + default "imxrt1170" + +config SYS_CONFIG_NAME + string + default "imxrt1170-evk" + +config IMX_CONFIG + default "board/freescale/imxrt1170-evk/imximage.cfg" + +endif diff --git a/board/freescale/imxrt1170-evk/MAINTAINERS b/board/freescale/imxrt1170-evk/MAINTAINERS new file mode 100644 index 0000000000..1fc3179c00 --- /dev/null +++ b/board/freescale/imxrt1170-evk/MAINTAINERS @@ -0,0 +1,7 @@ +IMXRT1170 EVALUATION KIT +M: Giulio Benetti +M: Jesse Taube +S: Maintained +F: board/freescale/imxrt1170-evk +F: include/configs/imxrt1170-evk.h +F: configs/imxrt1170-evk_defconfig diff --git a/board/freescale/imxrt1170-evk/Makefile b/board/freescale/imxrt1170-evk/Makefile new file mode 100644 index 0000000000..857a168b09 --- /dev/null +++ b/board/freescale/imxrt1170-evk/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2019 +# Author(s): Giulio Benetti + +obj-y := imxrt1170-evk.o diff --git a/board/freescale/imxrt1170-evk/imximage.cfg b/board/freescale/imxrt1170-evk/imximage.cfg new file mode 100644 index 0000000000..57583d04ce --- /dev/null +++ b/board/freescale/imxrt1170-evk/imximage.cfg @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2022 + * Author(s): Jesse Taube + * Giulio Benetti + */ + +#include + +/* image version */ + +IMAGE_VERSION 2 + +/* + * Boot Device : one of + * spi/sd/nand/onenand, qspi/nor + */ + +BOOT_FROM sd + +/* + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ diff --git a/board/freescale/imxrt1170-evk/imxrt1170-evk.c b/board/freescale/imxrt1170-evk/imxrt1170-evk.c new file mode 100644 index 0000000000..4b82ee5e9c --- /dev/null +++ b/board/freescale/imxrt1170-evk/imxrt1170-evk.c @@ -0,0 +1,80 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2019 + * Author(s): Giulio Benetti + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +int dram_init(void) +{ +#ifndef CONFIG_SUPPORT_SPL + int rv; + struct udevice *dev; + + rv = uclass_get_device(UCLASS_RAM, 0, &dev); + if (rv) { + debug("DRAM init failed: %d\n", rv); + return rv; + } + +#endif + return fdtdec_setup_mem_size_base(); +} + +int dram_init_banksize(void) +{ + return fdtdec_setup_memory_banksize(); +} + +#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_SPL_OS_BOOT +int spl_start_uboot(void) +{ + debug("SPL: booting kernel\n"); + /* break into full u-boot on 'c' */ + return serial_tstc() && serial_getc() == 'c'; +} +#endif + +int spl_dram_init(void) +{ + struct udevice *dev; + int rv; + + rv = uclass_get_device(UCLASS_RAM, 0, &dev); + if (rv) + debug("DRAM init failed: %d\n", rv); + return rv; +} + +void spl_board_init(void) +{ + preloader_console_init(); + spl_dram_init(); + arch_cpu_init(); /* to configure mpu for sdram rw permissions */ +} + +u32 spl_boot_device(void) +{ + return BOOT_DEVICE_MMC1; +} +#endif + +int board_init(void) +{ + gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100; + + return 0; +} diff --git a/board/freescale/ls1043ardb/ddr.c b/board/freescale/ls1043ardb/ddr.c index 08b43ff5e4..4d2fce3841 100644 --- a/board/freescale/ls1043ardb/ddr.c +++ b/board/freescale/ls1043ardb/ddr.c @@ -114,7 +114,7 @@ dimm_params_t ddr_raw_timing = { .mirrored_dimm = 0, .n_row_addr = 15, .n_col_addr = 10, - .bank_addr_bits = 0, + .bank_addr_bits = 2, .bank_group_bits = 2, .edc_config = 0, .burst_lengths_bitmask = 0x0c, diff --git a/board/freescale/p1_p2_rdb_pc/README b/board/freescale/p1_p2_rdb_pc/README index 86ff04e69d..f542decec7 100644 --- a/board/freescale/p1_p2_rdb_pc/README +++ b/board/freescale/p1_p2_rdb_pc/README @@ -60,5 +60,5 @@ enabled in relative defconfig file, CONFIG_RESET_VECTOR_ADDRESS - 0xffc If device tree support is enabled in defconfig, -1. use 'u-boot-with-dtb.bin' for NOR boot. +1. use 'u-boot.bin' for NOR boot. 2. use 'u-boot-with-spl.bin' for other boot. diff --git a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c index a71952dcf3..b301491ef8 100644 --- a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c +++ b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c @@ -83,7 +83,19 @@ struct cpld_data { #define CPLD_FXS_LED 0x0F #define CPLD_SYS_RST 0x00 -void board_reset(void) +void board_reset_prepare(void) +{ + /* + * During reset preparation, turn off external watchdog. + * This ensures that external watchdog does not trigger + * another reset or possible infinite reset loop. + */ + struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE); + out_8(&cpld_data->wd_cfg, CPLD_WD_CFG); + in_8(&cpld_data->wd_cfg); /* Read back to sync write */ +} + +void board_reset_last(void) { struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE); out_8(&cpld_data->system_rst, 1); @@ -92,12 +104,46 @@ void board_reset(void) void board_cpld_init(void) { struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE); + u8 prev_wd_cfg = in_8(&cpld_data->wd_cfg); out_8(&cpld_data->wd_cfg, CPLD_WD_CFG); out_8(&cpld_data->status_led, CPLD_STATUS_LED); out_8(&cpld_data->fxo_led, CPLD_FXO_LED); out_8(&cpld_data->fxs_led, CPLD_FXS_LED); + + /* + * CPLD's system reset register on P1/P2 RDB boards is not autocleared + * after flipping it. If this register is set to one then CPLD triggers + * reset of CPU in few ms. + * + * CPLD does not trigger reset of CPU for 100ms after the last reset. + * + * This means that trying to reset board via CPLD system reset register + * cause reboot loop. To prevent this reboot loop, the only workaround + * is to try to clear CPLD's system reset register as early as possible + * and it has to be done in 100ms since the last start of reset. + */ out_8(&cpld_data->system_rst, CPLD_SYS_RST); + + /* + * If watchdog timer was already set to non-disabled value then it means + * that watchdog timer was already activated, has already expired and + * caused CPU reset. If this happened then due to CPLD firmware bug, + * writing to wd_cfg register has no effect and therefore it is not + * possible to reactivate watchdog timer again. Also if CPU was reset + * via watchdog then some peripherals like i2c do not work. Watchdog and + * i2c start working again after CPU reset via non-watchdog method. + * + * So in case watchdog timer register in CPLD was already enabled then + * disable it in CPLD and reset CPU which cause new boot. Watchdog timer + * is disabled few lines above, after reading CPLD previous value. + * This logic (disabling timer before reset) prevents reboot loop. + */ + if (prev_wd_cfg != CPLD_WD_CFG) { + eieio(); + do_reset(NULL, 0, 0, NULL); + while (1); /* do_reset() does not occur immediately */ + } } void board_gpio_init(void) @@ -368,6 +414,24 @@ int board_eth_init(struct bd_info *bis) } #endif +#if defined(CONFIG_OF_BOARD_SETUP) || defined(CONFIG_OF_BOARD_FIXUP) +static void fix_max6370_watchdog(void *blob) +{ + int off = fdt_node_offset_by_compatible(blob, -1, "maxim,max6370"); + ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR); + u32 gpioval = in_be32(&pgpio->gpdat); + + /* + * Delete watchdog max6370 node in load_default mode (detected by + * GPIO7 - LOAD_DEFAULT_N) because CPLD in load_default mode ignores + * watchdog reset signal. CPLD in load_default mode does not reset + * board when watchdog triggers reset signal. + */ + if (!(gpioval & BIT(31-7)) && off >= 0) + fdt_del_node(blob, off); +} +#endif + #ifdef CONFIG_OF_BOARD_SETUP int ft_board_setup(void *blob, struct bd_info *bd) { @@ -393,6 +457,8 @@ int ft_board_setup(void *blob, struct bd_info *bd) sizeof("okay"), 0); #endif + fix_max6370_watchdog(blob); + #if defined(CONFIG_HAS_FSL_DR_USB) fsl_fdt_fixup_dr_usb(blob, bd); #endif @@ -444,3 +510,11 @@ int ft_board_setup(void *blob, struct bd_info *bd) return 0; } #endif + +#ifdef CONFIG_OF_BOARD_FIXUP +int board_fix_fdt(void *blob) +{ + fix_max6370_watchdog(blob); + return 0; +} +#endif diff --git a/board/freescale/p1_p2_rdb_pc/spl.c b/board/freescale/p1_p2_rdb_pc/spl.c index b60027ebd9..eda84bf2b1 100644 --- a/board/freescale/p1_p2_rdb_pc/spl.c +++ b/board/freescale/p1_p2_rdb_pc/spl.c @@ -31,6 +31,12 @@ void board_init_f(ulong bootflag) u32 plat_ratio, bus_clk; ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; + /* + * Call board_early_init_f() as early as possible as it workarounds + * reboot loop due to broken CPLD state machine for reset line. + */ + board_early_init_f(); + console_init_f(); /* Set pmuxcr to allow both i2c1 and i2c2 */ diff --git a/board/freescale/p1_p2_rdb_pc/tlb.c b/board/freescale/p1_p2_rdb_pc/tlb.c index 105d9e38aa..65cedd42a0 100644 --- a/board/freescale/p1_p2_rdb_pc/tlb.c +++ b/board/freescale/p1_p2_rdb_pc/tlb.c @@ -61,11 +61,11 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 5, BOOKE_PAGESZ_1M, 1), #endif +#endif /* not SPL */ SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 6, BOOKE_PAGESZ_1M, 1), -#endif /* not SPL */ #ifdef CONFIG_SYS_NAND_BASE /* *I*G - NAND */ diff --git a/board/freescale/p2041rdb/README b/board/freescale/p2041rdb/README index 79f77e4961..96612daeeb 100644 --- a/board/freescale/p2041rdb/README +++ b/board/freescale/p2041rdb/README @@ -100,9 +100,6 @@ enabled in relative defconfig file, 3. CONFIG_MPC85XX_HAVE_RESET_VECTOR if reset vector is located at CONFIG_RESET_VECTOR_ADDRESS - 0xffc -If device tree support is enabled in defconfig, use 'u-boot-with-dtb.bin' -instead of u-boot.bin for all boot. - CPLD command ============ The CPLD is used to control the power sequence and some serdes lane diff --git a/board/freescale/t102xrdb/README b/board/freescale/t102xrdb/README index 84deb9562a..de170f52b4 100644 --- a/board/freescale/t102xrdb/README +++ b/board/freescale/t102xrdb/README @@ -267,7 +267,7 @@ enabled in relative defconfig file, config_reset_vector_address - 0xffc if device tree support is enabled in defconfig, -1. use 'u-boot-with-dtb.bin' for nor boot. +1. use 'u-boot.bin' for nor boot. 2. use 'u-boot-with-spl-pbl.bin' for other boot. 2-stage NAND/SPI/SD boot loader diff --git a/board/freescale/t104xrdb/README b/board/freescale/t104xrdb/README index 09cb98e33d..e90dca4166 100644 --- a/board/freescale/t104xrdb/README +++ b/board/freescale/t104xrdb/README @@ -382,5 +382,5 @@ enabled in relative defconfig file, CONFIG_RESET_VECTOR_ADDRESS - 0xffc If device tree support is enabled in defconfig, -1. use 'u-boot-with-dtb.bin' for NOR boot. +1. use 'u-boot.bin' for NOR boot. 2. use 'u-boot-with-spl-pbl.bin' for other boot. diff --git a/board/freescale/t208xqds/README b/board/freescale/t208xqds/README index 75d317342f..63953d6b9b 100755 --- a/board/freescale/t208xqds/README +++ b/board/freescale/t208xqds/README @@ -288,5 +288,5 @@ enabled in relative defconfig file, CONFIG_RESET_VECTOR_ADDRESS - 0xffc If device tree support is enabled in defconfig, -1. use 'u-boot-with-dtb.bin' for NOR boot. +1. use 'u-boot.bin' for NOR boot. 2. use 'u-boot-with-spl-pbl.bin' for other boot. diff --git a/board/freescale/t208xrdb/README b/board/freescale/t208xrdb/README index c4bfd3b466..60551f6723 100644 --- a/board/freescale/t208xrdb/README +++ b/board/freescale/t208xrdb/README @@ -284,5 +284,5 @@ enabled in relative defconfig file, CONFIG_RESET_VECTOR_ADDRESS - 0xffc If device tree support is enabled in defconfig, -1. use 'u-boot-with-dtb.bin' for NOR boot. +1. use 'u-boot.bin' for NOR boot. 2. use 'u-boot-with-spl-pbl.bin' for other boot. diff --git a/board/gateworks/venice/eeprom.c b/board/gateworks/venice/eeprom.c index 7a46f44828..ac52cc0a9e 100644 --- a/board/gateworks/venice/eeprom.c +++ b/board/gateworks/venice/eeprom.c @@ -20,6 +20,7 @@ struct venice_board_info som_info; struct venice_board_info base_info; char venice_model[32]; +char venice_baseboard_model[32]; u32 venice_serial; /* return a mac address from EEPROM info */ @@ -321,6 +322,7 @@ int eeprom_init(int quiet) base_info.model[3], /* baseboard */ base_info.model[4], base_info.model[5], /* subload of baseboard */ som_info.model[4], som_info.model[5]); /* last 2digits of SOM */ + strlcpy(venice_baseboard_model, base_info.model, sizeof(venice_baseboard_model)); /* baseboard revision */ rev_pcb = get_pcb_rev(base_info.model); @@ -357,6 +359,11 @@ const char *eeprom_get_model(void) return venice_model; } +const char *eeprom_get_baseboard_model(void) +{ + return venice_baseboard_model; +} + u32 eeprom_get_serial(void) { return venice_serial; diff --git a/board/gateworks/venice/eeprom.h b/board/gateworks/venice/eeprom.h index 37bfe76ad8..8ea7318d7d 100644 --- a/board/gateworks/venice/eeprom.h +++ b/board/gateworks/venice/eeprom.h @@ -26,8 +26,11 @@ struct venice_board_info { int eeprom_init(int quiet); const char *eeprom_get_model(void); +const char *eeprom_get_baseboard_model(void); const char *eeprom_get_dtb_name(int level, char *buf, int len); int eeprom_getmac(int index, uint8_t *enetaddr); uint32_t eeprom_get_serial(void); +int get_bom_rev(const char *str); +char get_pcb_rev(const char *str); #endif diff --git a/board/gateworks/venice/venice.c b/board/gateworks/venice/venice.c index f1efabb203..32b25ffd3e 100644 --- a/board/gateworks/venice/venice.c +++ b/board/gateworks/venice/venice.c @@ -3,6 +3,7 @@ * Copyright 2021 Gateworks Corporation */ +#include #include #include #include @@ -169,26 +170,54 @@ int board_mmc_get_env_dev(int devno) return devno; } -int ft_board_setup(void *blob, struct bd_info *bd) +int ft_board_setup(void *fdt, struct bd_info *bd) { + const char *base_model = eeprom_get_baseboard_model(); + char pcbrev; int off; /* set board model dt prop */ - fdt_setprop_string(blob, 0, "board", eeprom_get_model()); + fdt_setprop_string(fdt, 0, "board", eeprom_get_model()); /* update temp thresholds */ - off = fdt_path_offset(blob, "/thermal-zones/cpu-thermal/trips"); + off = fdt_path_offset(fdt, "/thermal-zones/cpu-thermal/trips"); if (off >= 0) { int minc, maxc, prop; get_cpu_temp_grade(&minc, &maxc); - fdt_for_each_subnode(prop, blob, off) { - const char *type = fdt_getprop(blob, prop, "type", NULL); + fdt_for_each_subnode(prop, fdt, off) { + const char *type = fdt_getprop(fdt, prop, "type", NULL); if (type && (!strcmp("critical", type))) - fdt_setprop_u32(blob, prop, "temperature", maxc * 1000); + fdt_setprop_u32(fdt, prop, "temperature", maxc * 1000); else if (type && (!strcmp("passive", type))) - fdt_setprop_u32(blob, prop, "temperature", (maxc - 10) * 1000); + fdt_setprop_u32(fdt, prop, "temperature", (maxc - 10) * 1000); + } + } + + if (!strncmp(base_model, "GW73", 4)) { + pcbrev = get_pcb_rev(base_model); + + if (pcbrev > 'B') { + printf("adjusting dt for %s\n", base_model); + + /* + * revC replaced PCIe 5-port switch with 4-port + * which changed ethernet1 PCIe GbE + * from: pcie@0,0/pcie@1,0/pcie@2,4/pcie@6.0 + * to: pcie@0,0/pcie@1,0/pcie@2,3/pcie@5.0 + */ + off = fdt_path_offset(fdt, "ethernet1"); + if (off > 0) { + u32 reg[5]; + + fdt_set_name(fdt, off, "pcie@5,0"); + off = fdt_parent_offset(fdt, off); + fdt_set_name(fdt, off, "pcie@2,3"); + memset(reg, 0, sizeof(reg)); + reg[0] = cpu_to_fdt32(PCI_DEVFN(3, 0)); + fdt_setprop(fdt, off, "reg", reg, sizeof(reg)); + } } } diff --git a/board/kontron/sl28/common.c b/board/kontron/sl28/common.c index 33c6843c3f..331de29bae 100644 --- a/board/kontron/sl28/common.c +++ b/board/kontron/sl28/common.c @@ -2,6 +2,9 @@ #include #include +#include + +#include "sl28.h" DECLARE_GLOBAL_DATA_PTR; @@ -9,3 +12,22 @@ u32 get_lpuart_clk(void) { return gd->bus_clk / CONFIG_SYS_FSL_LPUART_CLK_DIV; } + +enum boot_source sl28_boot_source(void) +{ + u32 rcw_src = in_le32(DCFG_BASE + DCFG_PORSR1) & DCFG_PORSR1_RCW_SRC; + + switch (rcw_src) { + case DCFG_PORSR1_RCW_SRC_SDHC1: + return BOOT_SOURCE_SDHC; + case DCFG_PORSR1_RCW_SRC_SDHC2: + return BOOT_SOURCE_MMC; + case DCFG_PORSR1_RCW_SRC_I2C: + return BOOT_SOURCE_I2C; + case DCFG_PORSR1_RCW_SRC_FSPI_NOR: + return BOOT_SOURCE_SPI; + default: + debug("unknown bootsource (%08x)\n", rcw_src); + return BOOT_SOURCE_UNKNOWN; + } +} diff --git a/board/kontron/sl28/sl28.c b/board/kontron/sl28/sl28.c index 32e9694b77..0576b3eae4 100644 --- a/board/kontron/sl28/sl28.c +++ b/board/kontron/sl28/sl28.c @@ -24,6 +24,8 @@ #include #include +#include "sl28.h" + DECLARE_GLOBAL_DATA_PTR; #if CONFIG_IS_ENABLED(EFI_HAVE_CAPSULE_SUPPORT) @@ -60,6 +62,27 @@ int board_eth_init(struct bd_info *bis) return pci_eth_init(bis); } +enum env_location env_get_location(enum env_operation op, int prio) +{ + enum boot_source src = sl28_boot_source(); + + if (prio) + return ENVL_UNKNOWN; + + if (!CONFIG_IS_ENABLED(ENV_IS_IN_SPI_FLASH)) + return ENVL_NOWHERE; + + /* write and erase always operate on the environment */ + if (op == ENVOP_SAVE || op == ENVOP_ERASE) + return ENVL_SPI_FLASH; + + /* failsafe boot will always use the compiled-in default environment */ + if (src == BOOT_SOURCE_SPI) + return ENVL_NOWHERE; + + return ENVL_SPI_FLASH; +} + static int __sl28cpld_read(uint reg) { struct udevice *dev; @@ -103,8 +126,28 @@ static void stop_recovery_watchdog(void) wdt_stop(dev); } +static void sl28_set_prompt(void) +{ + enum boot_source src = sl28_boot_source(); + + switch (src) { + case BOOT_SOURCE_SPI: + env_set("PS1", "[FAILSAFE] => "); + break; + case BOOT_SOURCE_SDHC: + env_set("PS1", "[SDHC] => "); + break; + default: + env_set("PS1", NULL); + break; + } +} + int fsl_board_late_init(void) { + if (IS_ENABLED(CONFIG_CMDLINE_PS_SUPPORT)) + sl28_set_prompt(); + /* * Usually, the after a board reset, the watchdog is enabled by * default. This is to supervise the bootloader boot-up. Therefore, diff --git a/board/kontron/sl28/sl28.h b/board/kontron/sl28/sl28.h new file mode 100644 index 0000000000..7f0105049c --- /dev/null +++ b/board/kontron/sl28/sl28.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + +#ifndef __SL28_H +#define __SL28_H + +enum boot_source { + BOOT_SOURCE_UNKNOWN, + BOOT_SOURCE_SDHC, + BOOT_SOURCE_MMC, + BOOT_SOURCE_I2C, + BOOT_SOURCE_SPI, +}; + +enum boot_source sl28_boot_source(void); + +#endif diff --git a/board/kontron/sl28/spl.c b/board/kontron/sl28/spl.c index 0e6ad5f37e..ffaf517a8b 100644 --- a/board/kontron/sl28/spl.c +++ b/board/kontron/sl28/spl.c @@ -5,6 +5,9 @@ #include #include #include +#include + +#include "sl28.h" #define DCFG_RCWSR25 0x160 #define GPINFO_HW_VARIANT_MASK 0xff @@ -58,7 +61,56 @@ int board_fit_config_name_match(const char *name) void board_boot_order(u32 *spl_boot_list) { - spl_boot_list[0] = BOOT_DEVICE_SPI; + enum boot_source src = sl28_boot_source(); + + switch (src) { + case BOOT_SOURCE_SDHC: + spl_boot_list[0] = BOOT_DEVICE_MMC2; + break; + case BOOT_SOURCE_SPI: + case BOOT_SOURCE_I2C: + spl_boot_list[0] = BOOT_DEVICE_SPI; + break; + case BOOT_SOURCE_MMC: + spl_boot_list[0] = BOOT_DEVICE_MMC1; + break; + default: + panic("unexpected bootsource (%d)\n", src); + break; + } +} + +unsigned int spl_spi_get_uboot_offs(struct spi_flash *flash) +{ + enum boot_source src = sl28_boot_source(); + + switch (src) { + case BOOT_SOURCE_SPI: + return 0x000000; + case BOOT_SOURCE_I2C: + return 0x230000; + default: + panic("unexpected bootsource (%d)\n", src); + break; + } +} + +const char *spl_board_loader_name(u32 boot_device) +{ + enum boot_source src = sl28_boot_source(); + + switch (src) { + case BOOT_SOURCE_SDHC: + return "SD card (Test mode)"; + case BOOT_SOURCE_SPI: + return "Failsafe SPI flash"; + case BOOT_SOURCE_I2C: + return "SPI flash"; + case BOOT_SOURCE_MMC: + return "eMMC"; + default: + return "(unknown)"; + } } int board_early_init_f(void) diff --git a/board/purism/librem5/Kconfig b/board/purism/librem5/Kconfig new file mode 100644 index 0000000000..cf0f303683 --- /dev/null +++ b/board/purism/librem5/Kconfig @@ -0,0 +1,15 @@ +if TARGET_LIBREM5 + +config SYS_BOARD + default "librem5" + +config SYS_VENDOR + default "purism" + +config SYS_CONFIG_NAME + default "librem5" + +config IMX_CONFIG + default "board/purism/librem5/imximage-8mq-lpddr4.cfg" + +endif diff --git a/board/purism/librem5/MAINTAINERS b/board/purism/librem5/MAINTAINERS new file mode 100644 index 0000000000..09e7f20e33 --- /dev/null +++ b/board/purism/librem5/MAINTAINERS @@ -0,0 +1,8 @@ +PURISM LIBREM5 PHONE +M: Angus Ainslie +R: kernel@puri.sm +S: Supported +F: arch/arm/dts/imx8mq-librem5* +F: board/purism/librem5/ +F: configs/librem5_defconfig +F: include/configs/librem5.h diff --git a/board/purism/librem5/Makefile b/board/purism/librem5/Makefile new file mode 100644 index 0000000000..47f25f047b --- /dev/null +++ b/board/purism/librem5/Makefile @@ -0,0 +1,13 @@ +# +# Copyright 2017 NXP +# Copyright 2019 Purism +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += librem5.o + +ifdef CONFIG_SPL_BUILD +obj-y += spl.o +obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_timing.o lpddr4_timing_b0.o +endif diff --git a/board/purism/librem5/imximage-8mq-lpddr4.cfg b/board/purism/librem5/imximage-8mq-lpddr4.cfg new file mode 100644 index 0000000000..3b5967105b --- /dev/null +++ b/board/purism/librem5/imximage-8mq-lpddr4.cfg @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2021 NXP + */ + +FIT +BOOT_FROM sd +SIGNED_HDMI signed_hdmi.bin +LOADER u-boot-spl-ddr.bin 0x7E1000 diff --git a/board/purism/librem5/librem5.c b/board/purism/librem5/librem5.c new file mode 100644 index 0000000000..caa02655fc --- /dev/null +++ b/board/purism/librem5/librem5.c @@ -0,0 +1,425 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 NXP + * Copyright 2021 Purism + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "librem5.h" + +DECLARE_GLOBAL_DATA_PTR; + +int board_early_init_f(void) +{ + return 0; +} + +#if IS_ENABLED(CONFIG_LOAD_ENV_FROM_MMC_BOOT_PARTITION) +uint board_mmc_get_env_part(struct mmc *mmc) +{ + uint part = (mmc->part_config >> 3) & PART_ACCESS_MASK; + + if (part == 7) + part = 0; + return part; +} +#endif + +int tps65982_wait_for_app(int timeout, int timeout_step) +{ + int ret; + char response[6]; + struct udevice *udev, *bus; + + log_debug("%s: starting\n", __func__); + + /* Set the i2c bus */ + ret = uclass_get_device_by_seq(UCLASS_I2C, 0, &bus); + if (ret) { + log_err("%s: No bus %d\n", __func__, 0); + return 1; + } + + ret = i2c_get_chip(bus, 0x3f, 1, &udev); + if (ret) { + log_err("%s: setting chip offset failed %d\n", __func__, ret); + return 1; + } + + while (timeout > 0) { + ret = dm_i2c_read(udev, 0x03, (u8 *)response, 5); + log_debug("tps65982 mode %s\n", response); + if (response[1] == 'A') + return 0; + mdelay(timeout_step); + timeout -= timeout_step; + log_debug("tps65982 waited %d ms %c\n", timeout_step, response[1]); + } + + return 1; +} + +int tps65982_clear_dead_battery(void) +{ + int ret; + char cmd[5] = "\04DBfg"; + struct udevice *udev, *bus; + + log_debug("%s: starting\n", __func__); + + /* Set the i2c bus */ + ret = uclass_get_device_by_seq(UCLASS_I2C, 0, &bus); + if (ret) { + log_err("%s: No bus %d\n", __func__, 0); + return 1; + } + + ret = i2c_get_chip(bus, 0x3f, 1, &udev); + if (ret) { + log_err("%s: setting chip offset failed %d\n", __func__, ret); + return 1; + } + + /* clearing the dead battery flag when not in dead battery condition + * is a no-op, so there's no need to check if it's in effect + */ + ret = dm_i2c_write(udev, 0x08, cmd, 5); + if (ret) { + log_err("%s: writing 4CC command failed %d", __func__, ret); + return 1; + } + + return 0; +} + +#define TPS_POWER_STATUS_PWROPMODE(x) FIELD_GET(GENMASK(3, 2), x) + +#define TPS_PDO_CONTRACT_TYPE(x) FIELD_GET(GENMASK(31, 30), x) +#define TPS_PDO_CONTRACT_FIXED 0 +#define TPS_PDO_CONTRACT_BATTERY 1 +#define TPS_PDO_CONTRACT_VARIABLE 2 + +#define TPS_TYPEC_PWR_MODE_USB 0 +#define TPS_TYPEC_PWR_MODE_1_5A 1 +#define TPS_TYPEC_PWR_MODE_3_0A 2 +#define TPS_TYPEC_PWR_MODE_PD 3 + +#define TPS_PDO_FIXED_CONTRACT_MAX_CURRENT(x) (FIELD_GET(GENMASK(9, 0), x) * 10) +#define TPS_PDO_VAR_CONTRACT_MAX_CURRENT(x) (FIELD_GET(GENMASK(9, 0), x) * 10) +#define TPS_PDO_BAT_CONTRACT_MAX_VOLTAGE(x) (FIELD_GET(GENMASK(29, 20), x) * 50) +#define TPS_PDO_BAT_CONTRACT_MAX_POWER(x) (FIELD_GET(GENMASK(9, 0), x) * 250) + +int tps65982_get_max_current(void) +{ + int ret; + u8 buf[7]; + u8 pwr_status; + u32 contract; + int type, mode; + struct udevice *udev, *bus; + + log_debug("%s: starting\n", __func__); + + /* Set the i2c bus */ + ret = uclass_get_device_by_seq(UCLASS_I2C, 0, &bus); + if (ret) { + log_debug("%s: No bus %d\n", __func__, 0); + return -1; + } + + ret = i2c_get_chip(bus, 0x3f, 1, &udev); + if (ret) { + log_debug("%s: setting chip offset failed %d\n", __func__, ret); + return -1; + } + + ret = dm_i2c_read(udev, 0x3f, buf, 3); + if (ret) { + log_debug("%s: reading pwr_status failed %d\n", __func__, ret); + return -1; + } + + pwr_status = buf[1]; + + if (!(pwr_status & 1)) + return 0; + + mode = TPS_POWER_STATUS_PWROPMODE(pwr_status); + switch (mode) { + case TPS_TYPEC_PWR_MODE_1_5A: + return 1500; + case TPS_TYPEC_PWR_MODE_3_0A: + return 3000; + case TPS_TYPEC_PWR_MODE_PD: + ret = dm_i2c_read(udev, 0x34, buf, 7); + if (ret) { + log_debug("%s: reading active contract failed %d\n", __func__, ret); + return -1; + } + + contract = buf[1] + (buf[2] << 8) + (buf[3] << 16) + (buf[4] << 24); + + type = TPS_PDO_CONTRACT_TYPE(contract); + + switch (type) { + case TPS_PDO_CONTRACT_FIXED: + return TPS_PDO_FIXED_CONTRACT_MAX_CURRENT(contract); + case TPS_PDO_CONTRACT_BATTERY: + return 1000 * TPS_PDO_BAT_CONTRACT_MAX_POWER(contract) + / TPS_PDO_BAT_CONTRACT_MAX_VOLTAGE(contract); + case TPS_PDO_CONTRACT_VARIABLE: + return TPS_PDO_VAR_CONTRACT_MAX_CURRENT(contract); + default: + log_debug("Unknown contract type: %d\n", type); + return -1; + } + case TPS_TYPEC_PWR_MODE_USB: + return 500; + default: + log_debug("Unknown power mode: %d\n", mode); + return -1; + } +} + +int init_tps65982(void) +{ + log_debug("%s: starting\n", __func__); + + if (tps65982_wait_for_app(500, 100)) { + log_err("tps65982 APP boot failed\n"); + return 1; + } + + log_info("tps65982 boot successful\n"); + return 0; +} + +int bq25895_set_iinlim(int current) +{ + u8 val, iinlim; + int ret; + struct udevice *udev, *bus; + + /* Set the i2c bus */ + ret = uclass_get_device_by_seq(UCLASS_I2C, 3, &bus); + if (ret) { + log_err("%s: No bus 3\n", __func__); + return ret; + } + + ret = i2c_get_chip(bus, 0x6a, 1, &udev); + if (ret) { + log_err("%s: setting chip offset failed %d\n", __func__, ret); + return ret; + } + + if (current > 3250) + current = 3250; + if (current < 100) + current = 100; + + val = dm_i2c_reg_read(udev, 0x00); + iinlim = ((current - 100) / 50) & 0x3f; + val = (val & 0xc0) | iinlim; + dm_i2c_reg_write(udev, 0x00, val); + log_debug("REG00 0x%x\n", val); + + return 0; +} + +bool bq25895_battery_present(void) +{ + u8 val; + int ret; + struct udevice *udev, *bus; + + /* Set the i2c bus */ + ret = uclass_get_device_by_seq(UCLASS_I2C, 3, &bus); + if (ret) { + log_err("%s: No bus 3\n", __func__); + return ret; + } + + ret = i2c_get_chip(bus, 0x6a, 1, &udev); + if (ret) { + log_err("%s: setting chip offset failed %d\n", __func__, ret); + return ret; + } + + /* note that this may return false negatives when there's + * no external power applied and the battery voltage is below + * Vsys. this isn't a problem when used for clearing the dead + * battery flag though, since it's certain that there's an external + * power applied in this case + */ + val = dm_i2c_reg_read(udev, 0x0e) & 0x7f; + if (val == 0x00 || val == 0x7f) + return false; + + return true; +} + +/* + * set some safe defaults for the battery charger + */ +int init_charger_bq25895(void) +{ + u8 val; + int iinlim, ret; + struct udevice *udev, *bus; + + /* Set the i2c bus */ + ret = uclass_get_device_by_seq(UCLASS_I2C, 3, &bus); + if (ret) { + log_debug("%s: No bus 3\n", __func__); + return ret; + } + + ret = i2c_get_chip(bus, 0x6a, 1, &udev); + if (ret) { + log_debug("%s: setting chip offset failed %d\n", __func__, ret); + return ret; + } + + val = dm_i2c_reg_read(udev, 0x0b); + log_debug("REG0B 0x%x\n", val); + + log_debug("VBUS_STAT 0x%x\n", val >> 5); + switch (val >> 5) { + case 0: + log_debug("VBUS not detected\n"); + break; + case 1: + log_debug("USB SDP IINLIM 500mA\n"); + break; + case 2: + log_debug("USB CDP IINLIM 1500mA\n"); + break; + case 3: + log_debug("USB DCP IINLIM 3500mA\n"); + break; + case 4: + log_debug("MAXCHARGE IINLIM 1500mA\n"); + break; + case 5: + log_debug("Unknown IINLIM 500mA\n"); + break; + case 6: + log_debug("DIVIDER IINLIM > 1000mA\n"); + break; + case 7: + log_debug("OTG\n"); + break; + }; + + log_debug("CHRG_STAT 0x%x\n", (val >> 3) & 0x3); + log_debug("PG_STAT 0x%x\n", (val >> 2) & 1); + log_debug("SDP_STAT 0x%x\n", (val >> 1) & 1); + log_debug("VSYS_STAT 0x%x\n", val & 1); + + val = dm_i2c_reg_read(udev, 0x00); + log_debug("REG00 0x%x\n", val); + iinlim = 100 + (val & 0x3f) * 50; + log_debug("IINLIM %d mA\n", iinlim); + log_debug("EN_HIZ 0x%x\n", (val >> 7) & 1); + log_debug("EN_ILIM 0x%x\n", (val >> 6) & 1); + + /* set 1.6A charge limit */ + dm_i2c_reg_write(udev, 0x04, 0x19); + + /* re-enable charger */ + val = dm_i2c_reg_read(udev, 0x03); + val = val | 0x10; + dm_i2c_reg_write(udev, 0x03, val); + + return 0; +} + +int board_init(void) +{ + struct udevice *dev; + int tps_ret; + + if (IS_ENABLED(CONFIG_USB_DWC3) || IS_ENABLED(CONFIG_USB_XHCI_IMX8M)) { + log_debug("%s: initializing USB clk\n", __func__); + + /* init_usb_clk won't enable the second clock if it's a USB boot */ + if (is_usb_boot()) { + clock_enable(CCGR_USB_CTRL2, 1); + clock_enable(CCGR_USB_PHY2, 1); + } + + printf("Enabling regulator-hub\n"); + if (!regulator_get_by_devname("regulator-hub", &dev)) { + if (regulator_set_enable(dev, true)) + pr_err("Failed to enable regulator-hub\n"); + } + } + + tps_ret = init_tps65982(); + init_charger_bq25895(); + + if (!tps_ret) { + int current = tps65982_get_max_current(); + + if (current > 500) + bq25895_set_iinlim(current); + + if (bq25895_battery_present()) + tps65982_clear_dead_battery(); + } + + return 0; +} + +int board_late_init(void) +{ + if (IS_ENABLED(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG)) { + u32 rev; + char rev_str[3]; + + env_set("board_name", "librem5"); + if (fuse_read(9, 0, &rev)) { + env_set("board_rev", BOARD_REV_ERROR); + } else if (rev == 0) { + env_set("board_rev", BOARD_REV_UNKNOWN); + } else if (rev > 0) { + sprintf(rev_str, "%u", rev); + env_set("board_rev", rev_str); + } + + printf("Board name: %s\n", env_get("board_name")); + printf("Board rev: %s\n", env_get("board_rev")); + } + + if (is_usb_boot()) { + puts("USB Boot\n"); + env_set("bootcmd", "fastboot 0"); + } + + return 0; +} diff --git a/board/purism/librem5/librem5.h b/board/purism/librem5/librem5.h new file mode 100644 index 0000000000..0d24edea9b --- /dev/null +++ b/board/purism/librem5/librem5.h @@ -0,0 +1,181 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2021 Purism + */ + +#ifndef __LIBREM5_H__ +#define __LIBREM5_H__ + +#define CAMERA_EN IMX_GPIO_NR(1, 0) +#define SD_EN IMX_GPIO_NR(1, 3) +#define AUDIO_EN IMX_GPIO_NR(1, 4) +#define DSI_EN IMX_GPIO_NR(1, 5) +#define SMC_EN IMX_GPIO_NR(1, 6) +#define TYPEC_MUX_EN IMX_GPIO_NR(1, 11) +#define HUB_NRESET IMX_GPIO_NR(1, 12) +#define HUB_EN IMX_GPIO_NR(1, 14) +#define VOL_UP IMX_GPIO_NR(1, 16) +#define VOL_DOWN IMX_GPIO_NR(1, 17) +#define DSI_BIAS_EN IMX_GPIO_NR(1, 20) +#define FLASH_EN IMX_GPIO_NR(1, 23) +#define WWAN_NRESET IMX_GPIO_NR(3, 1) +#define CHG_EN IMX_GPIO_NR(3, 2) +#define CHG_OTG_OUT_EN IMX_GPIO_NR(3, 4) +#define WIFI_EN IMX_GPIO_NR(3, 10) +#define GPS_EN IMX_GPIO_NR(3, 12) +#define BL_EN IMX_GPIO_NR(3, 14) +#define WWAN_EN IMX_GPIO_NR(3, 18) +#define NFC_EN IMX_GPIO_NR(4, 28) +#define LED_G IMX_GPIO_NR(5, 2) +#define LED_R IMX_GPIO_NR(5, 3) +#define LED_B IMX_GPIO_NR(1, 13) +#define MOTO IMX_GPIO_NR(5, 5) +#define SPI1_SCLK IMX_GPIO_NR(5, 6) +#define SPI1_MOSI IMX_GPIO_NR(5, 7) +#define SPI1_MISO IMX_GPIO_NR(5, 8) +#define SPI1_SS0 IMX_GPIO_NR(5, 9) + +#define UART1_TX IMX_GPIO_NR(5, 23) +#define UART1_RX IMX_GPIO_NR(5, 22) +#define UART2_TX IMX_GPIO_NR(5, 25) +#define UART2_RX IMX_GPIO_NR(5, 24) +#define UART3_TX IMX_GPIO_NR(5, 27) +#define UART3_RX IMX_GPIO_NR(5, 26) +#define UART4_TX IMX_GPIO_NR(5, 11) +#define UART4_RX IMX_GPIO_NR(5, 10) + +#define TPS_RESET IMX_GPIO_NR(3, 24) + +#define PURISM_VID 0x316d +#define PURISM_PID 0x4c05 + +#define BOARD_REV_ERROR "unknown" +#define BOARD_REV_BIRCH "1" +#define BOARD_REV_CHESTNUT "2" +#define BOARD_REV_DOGWOOD "3" +#define BOARD_REV_EVERGREEN "4" +/* Could be ASPEN, BIRCH or CHESTNUT. assume CHESTNUT */ +#define BOARD_REV_UNKNOWN BOARD_REV_CHESTNUT + +#ifdef CONFIG_SPL_BUILD +static const iomux_v3_cfg_t configure_pads[] = { + IMX8MQ_PAD_GPIO1_IO00__GPIO1_IO0 | MUX_PAD_CTRL(PAD_CTL_DSE6), + IMX8MQ_PAD_GPIO1_IO03__GPIO1_IO3 | MUX_PAD_CTRL(PAD_CTL_DSE6) | MUX_MODE_SION, + IMX8MQ_PAD_GPIO1_IO04__GPIO1_IO4 | MUX_PAD_CTRL(PAD_CTL_DSE6), + IMX8MQ_PAD_GPIO1_IO05__GPIO1_IO5 | MUX_PAD_CTRL(PAD_CTL_DSE6) | MUX_MODE_SION, + IMX8MQ_PAD_GPIO1_IO06__GPIO1_IO6 | MUX_PAD_CTRL(PAD_CTL_DSE6), + IMX8MQ_PAD_GPIO1_IO11__GPIO1_IO11 | MUX_PAD_CTRL(PAD_CTL_DSE6), + IMX8MQ_PAD_GPIO1_IO12__GPIO1_IO12 | MUX_PAD_CTRL(PAD_CTL_DSE6) | MUX_MODE_SION, + IMX8MQ_PAD_GPIO1_IO13__GPIO1_IO13 | MUX_PAD_CTRL(PAD_CTL_DSE6) | MUX_MODE_SION, + IMX8MQ_PAD_GPIO1_IO14__GPIO1_IO14 | MUX_PAD_CTRL(PAD_CTL_DSE6) | MUX_MODE_SION, + IMX8MQ_PAD_ENET_MDC__GPIO1_IO16 | MUX_PAD_CTRL(PAD_CTL_PUE), + IMX8MQ_PAD_ENET_MDIO__GPIO1_IO17 | MUX_PAD_CTRL(PAD_CTL_PUE), + IMX8MQ_PAD_ENET_TD1__GPIO1_IO20 | MUX_PAD_CTRL(PAD_CTL_DSE6), + IMX8MQ_PAD_ENET_TXC__GPIO1_IO23 | MUX_PAD_CTRL(PAD_CTL_DSE6), + IMX8MQ_PAD_NAND_CE0_B__GPIO3_IO1 | MUX_PAD_CTRL(PAD_CTL_DSE6), + IMX8MQ_PAD_NAND_CE1_B__GPIO3_IO2 | MUX_PAD_CTRL(PAD_CTL_DSE6), + IMX8MQ_PAD_NAND_CE3_B__GPIO3_IO4 | MUX_PAD_CTRL(PAD_CTL_DSE6), + IMX8MQ_PAD_NAND_DATA04__GPIO3_IO10 | MUX_PAD_CTRL(PAD_CTL_DSE6), + IMX8MQ_PAD_NAND_DATA06__GPIO3_IO12 | MUX_PAD_CTRL(PAD_CTL_DSE6), + IMX8MQ_PAD_NAND_DQS__GPIO3_IO14 | MUX_PAD_CTRL(PAD_CTL_DSE6), + IMX8MQ_PAD_NAND_WP_B__GPIO3_IO18 | MUX_PAD_CTRL(PAD_CTL_DSE6), + IMX8MQ_PAD_SAI3_RXFS__GPIO4_IO28 | MUX_PAD_CTRL(PAD_CTL_DSE6), + IMX8MQ_PAD_SAI3_MCLK__GPIO5_IO2 | MUX_PAD_CTRL(PAD_CTL_DSE6) | MUX_MODE_SION, + IMX8MQ_PAD_SPDIF_TX__GPIO5_IO3 | MUX_PAD_CTRL(PAD_CTL_DSE6) | MUX_MODE_SION, + IMX8MQ_PAD_SAI5_RXD3__GPIO3_IO24 | MUX_PAD_CTRL(PAD_CTL_DSE6) | MUX_MODE_SION, +}; + +static inline void init_pinmux(void) +{ + imx_iomux_v3_setup_multiple_pads(configure_pads, ARRAY_SIZE(configure_pads)); + + gpio_request(LED_R, "LED_R"); + gpio_request(LED_G, "LED_G"); + gpio_request(LED_B, "LED_B"); + gpio_request(VOL_UP, "VOL_UP"); + gpio_request(VOL_DOWN, "VOL_DOWN"); + + gpio_request(NFC_EN, "NFC_EN"); + gpio_request(CHG_EN, "CHG_EN"); + gpio_request(CHG_OTG_OUT_EN, "CHG_OTG_OUT_EN"); + + gpio_request(TYPEC_MUX_EN, "TYPEC_MUX_EN"); + + gpio_request(TPS_RESET, "TPS_RESET"); + + gpio_request(WWAN_EN, "WWAN_EN"); + gpio_request(WWAN_NRESET, "WWAN_NRESET"); + + gpio_request(HUB_EN, "HUB_EN"); + gpio_request(HUB_NRESET, "HUB_NRESET"); + gpio_request(SD_EN, "SD_EN"); + gpio_request(AUDIO_EN, "AUDIO_EN"); + gpio_request(DSI_EN, "DSI_EN"); + gpio_request(SMC_EN, "SMC_EN"); + gpio_request(CAMERA_EN, "CAMERA_EN"); + gpio_request(FLASH_EN, "FLASH_EN"); + gpio_request(DSI_BIAS_EN, "DSI_BIAS_EN"); + gpio_request(GPS_EN, "GPS_EN"); + gpio_request(BL_EN, "BL_EN"); +#ifndef CONSOLE_ON_UART4 + gpio_request(WIFI_EN, "WIFI_EN"); + gpio_direction_output(WIFI_EN, 0); +#endif /* CONSOLE_ON_UART4 */ + gpio_direction_input(VOL_UP); + gpio_direction_input(VOL_DOWN); + + /* ensure charger is in the automated mode */ + gpio_direction_output(NFC_EN, 0); + gpio_direction_output(CHG_EN, 0); + gpio_direction_output(CHG_OTG_OUT_EN, 0); + + gpio_direction_input(TYPEC_MUX_EN); + + gpio_direction_output(TPS_RESET, 0); + + gpio_direction_output(WWAN_EN, 0); + gpio_direction_output(WWAN_NRESET, 1); + + gpio_direction_output(HUB_EN, 1); + gpio_direction_output(HUB_NRESET, 1); + mdelay(10); + gpio_direction_output(SD_EN, 1); + gpio_direction_output(SMC_EN, 0); + gpio_direction_output(CAMERA_EN, 0); + gpio_direction_output(FLASH_EN, 0); + gpio_direction_output(DSI_BIAS_EN, 0); + gpio_direction_output(GPS_EN, 0); + gpio_direction_output(BL_EN, 0); + + /* turn these on for i2c busses */ + gpio_direction_output(AUDIO_EN, 1); + gpio_direction_output(DSI_EN, 1); +} +#endif /* CONFIG_SPL_BUILD */ + +#define USB1_BASE_ADDR 0x38100000 +#define USB2_BASE_ADDR 0x38200000 +#define USB1_PHY_BASE_ADDR 0x381F0000 +#define USB2_PHY_BASE_ADDR 0x382F0000 + +#define USB_PHY_CTRL0 0xF0040 +#define USB_PHY_CTRL0_REF_SSP_EN BIT(2) +#define USB_PHY_CTRL0_SSC_RANGE_MASK GENMASK(23, 21) +#define USB_PHY_CTRL0_SSC_RANGE_4003PPM (0x2 << 21) + +#define USB_PHY_CTRL1 0xF0044 +#define USB_PHY_CTRL1_RESET BIT(0) +#define USB_PHY_CTRL1_COMMONONN BIT(1) +#define USB_PHY_CTRL1_ATERESET BIT(3) +#define USB_PHY_CTRL1_VDATSRCENB0 BIT(19) +#define USB_PHY_CTRL1_VDATDETENB0 BIT(20) + +#define USB_PHY_CTRL2 0xF0048 +#define USB_PHY_CTRL2_TXENABLEN0 BIT(8) + +#define USB_PHY_CTRL6 0x18 +#define USB_PHY_CTRL6_RXTERM_OVERRIDE_SEL BIT(29) + +extern struct dram_timing_info dram_timing_b0; + +#endif diff --git a/board/purism/librem5/lpddr4_timing.c b/board/purism/librem5/lpddr4_timing.c new file mode 100644 index 0000000000..46bc7f8591 --- /dev/null +++ b/board/purism/librem5/lpddr4_timing.c @@ -0,0 +1,1324 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 NXP + */ + +#include +#include +#include +#include + +#define WR_POST_EXT_3200 /* recommened to define */ + +struct dram_cfg_param lpddr4_ddrc_cfg[] = { + /* Start to config, default 3200mbps */ + { DDRC_DBG1(0), 0x00000001 }, + { DDRC_PWRCTL(0), 0x00000001 }, + { DDRC_MSTR(0), 0xa3080020 }, + { DDRC_MSTR2(0), 0x00000000 }, + { DDRC_RFSHTMG(0), 0x006100E0 }, + { DDRC_INIT0(0), 0xC003061B }, + { DDRC_INIT1(0), 0x009D0000 }, + { DDRC_INIT3(0), 0x00D4002D }, +#ifdef WR_POST_EXT_3200 + { DDRC_INIT4(0), 0x00330008 }, +#else + { DDRC_INIT4(0), 0x00310008 }, +#endif + { DDRC_INIT6(0), 0x0066004a }, + { DDRC_INIT7(0), 0x0006004a }, + + { DDRC_DRAMTMG0(0), 0x1A201B22 }, + { DDRC_DRAMTMG1(0), 0x00060633 }, + { DDRC_DRAMTMG3(0), 0x00C0C000 }, + { DDRC_DRAMTMG4(0), 0x0F04080F }, + { DDRC_DRAMTMG5(0), 0x02040C0C }, + { DDRC_DRAMTMG6(0), 0x01010007 }, + { DDRC_DRAMTMG7(0), 0x00000401 }, + { DDRC_DRAMTMG12(0), 0x00020600 }, + { DDRC_DRAMTMG13(0), 0x0C100002 }, + { DDRC_DRAMTMG14(0), 0x000000E6 }, + { DDRC_DRAMTMG17(0), 0x00A00050 }, + + { DDRC_ZQCTL0(0), 0x03200018 }, + { DDRC_ZQCTL1(0), 0x028061A8 }, + { DDRC_ZQCTL2(0), 0x00000000 }, + + { DDRC_DFITMG0(0), 0x0497820A }, + { DDRC_DFITMG1(0), 0x00080303 }, + { DDRC_DFIUPD0(0), 0xE0400018 }, + { DDRC_DFIUPD1(0), 0x00DF00E4 }, + { DDRC_DFIUPD2(0), 0x80000000 }, + { DDRC_DFIMISC(0), 0x00000011 }, + { DDRC_DFITMG2(0), 0x0000170A }, + + { DDRC_DBICTL(0), 0x00000001 }, + { DDRC_DFIPHYMSTR(0), 0x00000001 }, + { DDRC_RANKCTL(0), 0x00000c99 }, + { DDRC_DRAMTMG2(0), 0x070E171a }, + + /* address mapping */ + { DDRC_ADDRMAP0(0), 0x00000015 }, + { DDRC_ADDRMAP3(0), 0x00000000 }, + { DDRC_ADDRMAP4(0), 0x00001F1F }, + /* bank interleave */ + { DDRC_ADDRMAP1(0), 0x00080808 }, + { DDRC_ADDRMAP5(0), 0x07070707 }, + { DDRC_ADDRMAP6(0), 0x08080707 }, + + /* performance setting */ + { DDRC_ODTCFG(0), 0x0b060908 }, + { DDRC_ODTMAP(0), 0x00000000 }, + { DDRC_SCHED(0), 0x29511505 }, + { DDRC_SCHED1(0), 0x0000002c }, + { DDRC_PERFHPR1(0), 0x5900575b }, + /* 150T starve and 0x90 max tran len */ + { DDRC_PERFLPR1(0), 0x90000096 }, + /* 300T starve and 0x10 max tran len */ + { DDRC_PERFWR1(0), 0x1000012c }, + { DDRC_DBG0(0), 0x00000016 }, + { DDRC_DBG1(0), 0x00000000 }, + { DDRC_DBGCMD(0), 0x00000000 }, + { DDRC_SWCTL(0), 0x00000001 }, + { DDRC_POISONCFG(0), 0x00000011 }, + { DDRC_PCCFG(0), 0x00000111 }, + { DDRC_PCFGR_0(0), 0x000010f3 }, + { DDRC_PCFGW_0(0), 0x000072ff }, + { DDRC_PCTRL_0(0), 0x00000001 }, + /* disable Read Qos*/ + { DDRC_PCFGQOS0_0(0), 0x00000e00 }, + { DDRC_PCFGQOS1_0(0), 0x0062ffff }, + /* disable Write Qos*/ + { DDRC_PCFGWQOS0_0(0), 0x00000e00 }, + { DDRC_PCFGWQOS1_0(0), 0x0000ffff }, + + /* Frequency 1: 400mbps */ + { DDRC_FREQ1_DRAMTMG0(0), 0x0d0b010c }, + { DDRC_FREQ1_DRAMTMG1(0), 0x00030410 }, + { DDRC_FREQ1_DRAMTMG2(0), 0x0305090c }, + { DDRC_FREQ1_DRAMTMG3(0), 0x00505006 }, + { DDRC_FREQ1_DRAMTMG4(0), 0x05040305 }, + { DDRC_FREQ1_DRAMTMG5(0), 0x0d0e0504 }, + { DDRC_FREQ1_DRAMTMG6(0), 0x0a060004 }, + { DDRC_FREQ1_DRAMTMG7(0), 0x0000090e }, + { DDRC_FREQ1_DRAMTMG14(0), 0x00000032 }, + { DDRC_FREQ1_DRAMTMG15(0), 0x00000000 }, + { DDRC_FREQ1_DRAMTMG17(0), 0x0036001b }, + { DDRC_FREQ1_DERATEINT(0), 0x7e9fbeb1 }, + { DDRC_FREQ1_DFITMG0(0), 0x03818200 }, + { DDRC_FREQ1_DFITMG2(0), 0x00000000 }, + { DDRC_FREQ1_RFSHTMG(0), 0x000C001c }, + { DDRC_FREQ1_INIT3(0), 0x00840000 }, + { DDRC_FREQ1_INIT4(0), 0x00310008 }, + { DDRC_FREQ1_INIT6(0), 0x0066004a }, + { DDRC_FREQ1_INIT7(0), 0x0006004a }, + + /* Frequency 2: 100mbps */ + { DDRC_FREQ2_DRAMTMG0(0), 0x0d0b010c }, + { DDRC_FREQ2_DRAMTMG1(0), 0x00030410 }, + { DDRC_FREQ2_DRAMTMG2(0), 0x0305090c }, + { DDRC_FREQ2_DRAMTMG3(0), 0x00505006 }, + { DDRC_FREQ2_DRAMTMG4(0), 0x05040305 }, + { DDRC_FREQ2_DRAMTMG5(0), 0x0d0e0504 }, + { DDRC_FREQ2_DRAMTMG6(0), 0x0a060004 }, + { DDRC_FREQ2_DRAMTMG7(0), 0x0000090e }, + { DDRC_FREQ2_DRAMTMG14(0), 0x00000032 }, + { DDRC_FREQ2_DRAMTMG17(0), 0x0036001b }, + { DDRC_FREQ2_DERATEINT(0), 0x7e9fbeb1 }, + { DDRC_FREQ2_DFITMG0(0), 0x03818200 }, + { DDRC_FREQ2_DFITMG2(0), 0x00000000 }, + { DDRC_FREQ2_RFSHTMG(0), 0x00030007 }, + { DDRC_FREQ2_INIT3(0), 0x00840000 }, + { DDRC_FREQ2_INIT4(0), 0x00310008 }, + { DDRC_FREQ2_INIT6(0), 0x0066004a }, + { DDRC_FREQ2_INIT7(0), 0x0006004a }, +}; + +/* PHY Initialize Configuration */ +struct dram_cfg_param lpddr4_ddrphy_cfg[] = { + { 0x20110, 0x02 }, + { 0x20111, 0x03 }, + { 0x20112, 0x04 }, + { 0x20113, 0x05 }, + { 0x20114, 0x00 }, + { 0x20115, 0x01 }, + + { 0x1005f, 0x1ff }, + { 0x1015f, 0x1ff }, + { 0x1105f, 0x1ff }, + { 0x1115f, 0x1ff }, + { 0x1205f, 0x1ff }, + { 0x1215f, 0x1ff }, + { 0x1305f, 0x1ff }, + { 0x1315f, 0x1ff }, + + { 0x11005f, 0x1ff }, + { 0x11015f, 0x1ff }, + { 0x11105f, 0x1ff }, + { 0x11115f, 0x1ff }, + { 0x11205f, 0x1ff }, + { 0x11215f, 0x1ff }, + { 0x11305f, 0x1ff }, + { 0x11315f, 0x1ff }, + + { 0x21005f, 0x1ff }, + { 0x21015f, 0x1ff }, + { 0x21105f, 0x1ff }, + { 0x21115f, 0x1ff }, + { 0x21205f, 0x1ff }, + { 0x21215f, 0x1ff }, + { 0x21305f, 0x1ff }, + { 0x21315f, 0x1ff }, + + { 0x55, 0x1ff }, + { 0x1055, 0x1ff }, + { 0x2055, 0x1ff }, + { 0x3055, 0x1ff }, + { 0x4055, 0x1ff }, + { 0x5055, 0x1ff }, + { 0x6055, 0x1ff }, + { 0x7055, 0x1ff }, + { 0x8055, 0x1ff }, + { 0x9055, 0x1ff }, + + { 0x200c5, 0x19 }, + { 0x1200c5, 0x7 }, + { 0x2200c5, 0x7 }, + + { 0x2002e, 0x2 }, + { 0x12002e, 0x2 }, + { 0x22002e, 0x2 }, + + { 0x90204, 0x0 }, + { 0x190204, 0x0 }, + { 0x290204, 0x0 }, + +#ifdef WR_POST_EXT_3200 + { 0x20024, 0xeb }, +#else + { 0x20024, 0xab }, +#endif + { 0x2003a, 0x0 }, + { 0x120024, 0xab }, + { 0x2003a, 0x0 }, + { 0x220024, 0xab }, + { 0x2003a, 0x0 }, + { 0x20056, 0x3 }, + { 0x120056, 0xa }, + { 0x220056, 0xa }, + { 0x1004d, 0xe00 }, + { 0x1014d, 0xe00 }, + { 0x1104d, 0xe00 }, + { 0x1114d, 0xe00 }, + { 0x1204d, 0xe00 }, + { 0x1214d, 0xe00 }, + { 0x1304d, 0xe00 }, + { 0x1314d, 0xe00 }, + { 0x11004d, 0xe00 }, + { 0x11014d, 0xe00 }, + { 0x11104d, 0xe00 }, + { 0x11114d, 0xe00 }, + { 0x11204d, 0xe00 }, + { 0x11214d, 0xe00 }, + { 0x11304d, 0xe00 }, + { 0x11314d, 0xe00 }, + { 0x21004d, 0xe00 }, + { 0x21014d, 0xe00 }, + { 0x21104d, 0xe00 }, + { 0x21114d, 0xe00 }, + { 0x21204d, 0xe00 }, + { 0x21214d, 0xe00 }, + { 0x21304d, 0xe00 }, + { 0x21314d, 0xe00 }, + + { 0x10049, 0xfbe }, + { 0x10149, 0xfbe }, + { 0x11049, 0xfbe }, + { 0x11149, 0xfbe }, + { 0x12049, 0xfbe }, + { 0x12149, 0xfbe }, + { 0x13049, 0xfbe }, + { 0x13149, 0xfbe }, + { 0x110049, 0xfbe }, + { 0x110149, 0xfbe }, + { 0x111049, 0xfbe }, + { 0x111149, 0xfbe }, + { 0x112049, 0xfbe }, + { 0x112149, 0xfbe }, + { 0x113049, 0xfbe }, + { 0x113149, 0xfbe }, + { 0x210049, 0xfbe }, + { 0x210149, 0xfbe }, + { 0x211049, 0xfbe }, + { 0x211149, 0xfbe }, + { 0x212049, 0xfbe }, + { 0x212149, 0xfbe }, + { 0x213049, 0xfbe }, + { 0x213149, 0xfbe }, + + { 0x43, ((LPDDR4_PHY_ADDR_RON << 5) | LPDDR4_PHY_ADDR_RON) }, + { 0x1043, ((LPDDR4_PHY_ADDR_RON << 5) | LPDDR4_PHY_ADDR_RON) }, + { 0x2043, ((LPDDR4_PHY_ADDR_RON << 5) | LPDDR4_PHY_ADDR_RON) }, + { 0x3043, ((LPDDR4_PHY_ADDR_RON << 5) | LPDDR4_PHY_ADDR_RON) }, + { 0x4043, ((LPDDR4_PHY_ADDR_RON << 5) | LPDDR4_PHY_ADDR_RON) }, + { 0x5043, ((LPDDR4_PHY_ADDR_RON << 5) | LPDDR4_PHY_ADDR_RON) }, + { 0x6043, ((LPDDR4_PHY_ADDR_RON << 5) | LPDDR4_PHY_ADDR_RON) }, + { 0x7043, ((LPDDR4_PHY_ADDR_RON << 5) | LPDDR4_PHY_ADDR_RON) }, + { 0x8043, ((LPDDR4_PHY_ADDR_RON << 5) | LPDDR4_PHY_ADDR_RON) }, + { 0x9043, ((LPDDR4_PHY_ADDR_RON << 5) | LPDDR4_PHY_ADDR_RON) }, + + { 0x20018, 0x3 }, + { 0x20075, 0x4 }, + { 0x20050, 0x0 }, + { 0x20008, 0x320 }, + { 0x120008, 0x64 }, + { 0x220008, 0x19 }, + { 0x20088, 0x9 }, + { 0x200b2, 0x104 }, + { 0x10043, 0x5a1 }, + { 0x10143, 0x5a1 }, + { 0x11043, 0x5a1 }, + { 0x11143, 0x5a1 }, + { 0x12043, 0x5a1 }, + { 0x12143, 0x5a1 }, + { 0x13043, 0x5a1 }, + { 0x13143, 0x5a1 }, + { 0x1200b2, 0x104 }, + { 0x110043, 0x5a1 }, + { 0x110143, 0x5a1 }, + { 0x111043, 0x5a1 }, + { 0x111143, 0x5a1 }, + { 0x112043, 0x5a1 }, + { 0x112143, 0x5a1 }, + { 0x113043, 0x5a1 }, + { 0x113143, 0x5a1 }, + { 0x2200b2, 0x104 }, + { 0x210043, 0x5a1 }, + { 0x210143, 0x5a1 }, + { 0x211043, 0x5a1 }, + { 0x211143, 0x5a1 }, + { 0x212043, 0x5a1 }, + { 0x212143, 0x5a1 }, + { 0x213043, 0x5a1 }, + { 0x213143, 0x5a1 }, + { 0x200fa, 0x1 }, + { 0x1200fa, 0x1 }, + { 0x2200fa, 0x1 }, + { 0x20019, 0x1 }, + { 0x120019, 0x1 }, + { 0x220019, 0x1 }, + { 0x200f0, 0x660 }, + { 0x200f1, 0x0 }, + { 0x200f2, 0x4444 }, + { 0x200f3, 0x8888 }, + { 0x200f4, 0x5665 }, + { 0x200f5, 0x0 }, + { 0x200f6, 0x0 }, + { 0x200f7, 0xf000 }, + { 0x20025, 0x0 }, + { 0x2002d, 0x0 }, + { 0x12002d, 0x0 }, + { 0x22002d, 0x0 }, + + { 0x200c7, 0x80 }, + { 0x1200c7, 0x80 }, + { 0x2200c7, 0x80 }, + { 0x200ca, 0x106 }, + { 0x1200ca, 0x106 }, + { 0x2200ca, 0x106 }, +}; + +/* P0 message block paremeter for training firmware */ +struct dram_cfg_param lpddr4_fsp0_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54000, 0x0 }, + { 0x54001, 0x0 }, + { 0x54002, 0x0 }, + { 0x54003, 0xc80 }, + { 0x54004, 0x2 }, + { 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT) }, /* PHY Ron/Rtt */ + { 0x54006, LPDDR4_PHY_VREF_VALUE }, + { 0x54007, 0x0 }, + { 0x54008, 0x131f }, + { 0x54009, LPDDR4_HDT_CTL_3200_1D }, + { 0x5400a, 0x0 }, + { 0x5400b, 0x2 }, + { 0x5400c, 0x0 }, + { 0x5400d, (LPDDR4_CATRAIN_3200_1d << 8) }, + { 0x5400e, 0x0 }, + { 0x5400f, 0x0 }, + { 0x54010, 0x0 }, + { 0x54011, 0x0 }, + { 0x54012, 0x310 }, + { 0x54013, 0x0 }, + { 0x54014, 0x0 }, + { 0x54015, 0x0 }, + { 0x54016, 0x0 }, + { 0x54017, 0x0 }, + { 0x54018, 0x0 }, + + { 0x54019, 0x2dd4 }, +#ifdef WR_POST_EXT_3200 + { 0x5401a, (((LPDDR4_RON) << 3) | 0x3) }, +#else + { 0x5401a, (((LPDDR4_RON) << 3) | 0x1) }, +#endif + { 0x5401b, ((LPDDR4_VREF_VALUE_CA << 8) | + (LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ) }, + { 0x5401c, ((LPDDR4_VREF_VALUE_DQ_RANK0 << 8) | 0x08) }, + { 0x5401d, 0x0 }, + { 0x5401e, LPDDR4_MR22_RANK0 }, + { 0x5401f, 0x2dd4 }, +#ifdef WR_POST_EXT_3200 + { 0x54020, (((LPDDR4_RON) << 3) | 0x3) }, +#else + { 0x54020, (((LPDDR4_RON) << 3) | 0x1) }, +#endif + { 0x54021, ((LPDDR4_VREF_VALUE_CA << 8) | + (LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ) }, + { 0x54022, ((LPDDR4_VREF_VALUE_DQ_RANK1 << 8) | 0x08) }, + { 0x54023, 0x0 }, + { 0x54024, LPDDR4_MR22_RANK1 }, + + { 0x54025, 0x0 }, + { 0x54026, 0x0 }, + { 0x54027, 0x0 }, + { 0x54028, 0x0 }, + { 0x54029, 0x0 }, + { 0x5402a, 0x0 }, + { 0x5402b, 0x1000 }, + { 0x5402c, 0x3 }, + { 0x5402d, 0x0 }, + { 0x5402e, 0x0 }, + { 0x5402f, 0x0 }, + { 0x54030, 0x0 }, + { 0x54031, 0x0 }, + { 0x54032, 0xd400 }, + /* MR3/MR2 */ +#ifdef WR_POST_EXT_3200 + { 0x54033, ((((LPDDR4_RON) << 3) | 0x3) << 8) | 0x2d /*0x312d*/ }, +#else + { 0x54033, ((((LPDDR4_RON) << 3) | 0x1) << 8) | 0x2d/*0x312d*/ }, +#endif + /* MR11/MR4 */ + { 0x54034, (((LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ) << 8) }, + /* self:0x284d//MR13/MR12 */ + { 0x54035, (0x0800 | LPDDR4_VREF_VALUE_CA)/*0x084d*/ }, + /* MR16/MR14*/ + { 0x54036, LPDDR4_VREF_VALUE_DQ_RANK0/*0x4d*/ }, + { 0x54037, (LPDDR4_MR22_RANK0 << 8)/*0x500*/ }, + /* MR1 */ + { 0x54038, 0xd400 }, + /* MR3/MR2 */ +#ifdef WR_POST_EXT_3200 + { 0x54039, ((((LPDDR4_RON) << 3) | 0x3) << 8) | 0x2d/*0x312d*/ }, +#else + { 0x54039, ((((LPDDR4_RON) << 3) | 0x1) << 8) | 0x2d/*0x312d*/ }, +#endif + /* MR11/MR4 */ + { 0x5403a, (((LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ) << 8) }, + /* self:0x284d//MR13/MR12 */ + { 0x5403b, (0x0800 | LPDDR4_VREF_VALUE_CA)/*0x084d*/ }, + /* MR16/MR14 */ + { 0x5403c, LPDDR4_VREF_VALUE_DQ_RANK1/*0x4d*/ }, + { 0x5403d, (LPDDR4_MR22_RANK1 << 8)/*0x500*/ }, + /* { 0x5403d, 0x500 } */ + { 0x5403d, (LPDDR4_MR22_RANK1 << 8)/*0x500*/ }, + { 0x5403e, 0x0 }, + { 0x5403f, 0x0 }, + { 0x54040, 0x0 }, + { 0x54041, 0x0 }, + { 0x54042, 0x0 }, + { 0x54043, 0x0 }, + { 0x54044, 0x0 }, + { 0xd0000, 0x1 }, +}; + +/* P1 message block paremeter for training firmware */ +struct dram_cfg_param lpddr4_fsp1_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54000, 0x0 }, + { 0x54001, 0x0 }, + { 0x54002, 0x101 }, + { 0x54003, 0x190 }, + { 0x54004, 0x2 }, + /* PHY Ron/Rtt */ + { 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT)/*0x2828*/ }, + { 0x54006, LPDDR4_PHY_VREF_VALUE }, + { 0x54007, 0x0 }, + { 0x54008, LPDDR4_TRAIN_SEQ_400 }, + { 0x54009, LPDDR4_HDT_CTL_400_1D }, + { 0x5400a, 0x0 }, + { 0x5400b, 0x2 }, + { 0x5400c, 0x0 }, + { 0x5400d, (LPDDR4_CATRAIN_400 << 8) }, + { 0x5400e, 0x0 }, + { 0x5400f, 0x0 }, + { 0x54010, 0x0 }, + { 0x54011, 0x0 }, + { 0x54012, 0x310 }, + { 0x54013, 0x0 }, + { 0x54014, 0x0 }, + { 0x54015, 0x0 }, + { 0x54016, 0x0 }, + { 0x54017, 0x0 }, + { 0x54018, 0x0 }, + { 0x54019, 0x84 }, + /* MR4/MR3 */ + { 0x5401a, (((LPDDR4_RON) << 3) | 0x1)/*0x31*/ }, + /* MR12/MR11 */ + { 0x5401b, ((LPDDR4_VREF_VALUE_CA << 8) | (LPDDR4_RTT_CA << 4) | + LPDDR4_RTT_DQ)/*0x4d46*/ }, + /* self:0x4d28//MR14/MR13 */ + { 0x5401c, ((LPDDR4_VREF_VALUE_DQ_RANK0 << 8) | 0x08)/*0x4d08*/ }, + { 0x5401d, 0x0 }, + { 0x5401e, LPDDR4_MR22_RANK0/*0x5*/ }, + { 0x5401f, 0x84 }, + { 0x54020, (((LPDDR4_RON) << 3) | 0x1)/*0x31*/ }, /* MR4/MR3 */ + { 0x54021, ((LPDDR4_VREF_VALUE_CA << 8) | (LPDDR4_RTT_CA << 4) | + LPDDR4_RTT_DQ)/*0x4d46*/ },/* MR12/MR11 */ + /* self:0x4d28//MR14/MR13 */ + { 0x54022, ((LPDDR4_VREF_VALUE_DQ_RANK1 << 8) | 0x08)/*0x4d08*/ }, + { 0x54023, 0x0 }, + { 0x54024, LPDDR4_MR22_RANK1 }, + { 0x54025, 0x0 }, + { 0x54026, 0x0 }, + { 0x54027, 0x0 }, + { 0x54028, 0x0 }, + { 0x54029, 0x0 }, + { 0x5402a, 0x0 }, + { 0x5402b, 0x1000 }, + { 0x5402c, 0x3 }, + { 0x5402d, 0x0 }, + { 0x5402e, 0x0 }, + { 0x5402f, 0x0 }, + { 0x54030, 0x0 }, + { 0x54031, 0x0 }, + { 0x54032, 0x8400 }, + { 0x54033, ((((LPDDR4_RON) << 3) | 0x1) << 8) | 0x00 }, + { 0x54034, (((LPDDR4_RTT_CA << 4) | LPDDR4_RTT_DQ) << 8) }, + { 0x54035, (0x0800 | LPDDR4_VREF_VALUE_CA) }, + { 0x54036, LPDDR4_VREF_VALUE_DQ_RANK0 }, + { 0x54037, (LPDDR4_MR22_RANK0 << 8) }, + { 0x54038, 0x8400 }, + { 0x54039, ((((LPDDR4_RON) << 3) | 0x1) << 8) | 0x00 }, + { 0x5403a, (((LPDDR4_RTT_CA << 4) | LPDDR4_RTT_DQ) << 8) }, + { 0x5403b, (0x0800 | LPDDR4_VREF_VALUE_CA) }, + { 0x5403c, LPDDR4_VREF_VALUE_DQ_RANK1 }, + { 0x5403d, (LPDDR4_MR22_RANK1 << 8) }, + { 0x5403e, 0x0 }, + { 0x5403f, 0x0 }, + { 0x54040, 0x0 }, + { 0x54041, 0x0 }, + { 0x54042, 0x0 }, + { 0x54043, 0x0 }, + { 0x54044, 0x0 }, + { 0xd0000, 0x1 }, +}; + +/* P2 message block paremeter for training firmware */ +struct dram_cfg_param lpddr4_fsp2_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54000, 0x0 }, + { 0x54001, 0x0 }, + { 0x54002, 0x102 }, + { 0x54003, 0x64 }, + { 0x54004, 0x2 }, + { 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT) }, + { 0x54006, LPDDR4_PHY_VREF_VALUE }, + { 0x54007, 0x0 }, + { 0x54008, LPDDR4_TRAIN_SEQ_100 }, + { 0x54009, LPDDR4_HDT_CTL_100_1D }, + { 0x5400a, 0x0 }, + { 0x5400b, 0x2 }, + { 0x5400c, 0x0 }, + { 0x5400d, (LPDDR4_CATRAIN_100 << 8) }, + { 0x5400e, 0x0 }, + { 0x5400f, 0x0 }, + { 0x54010, 0x0 }, + { 0x54011, 0x0 }, + { 0x54012, 0x310 }, + { 0x54013, 0x0 }, + { 0x54014, 0x0 }, + { 0x54015, 0x0 }, + { 0x54016, 0x0 }, + { 0x54017, 0x0 }, + { 0x54018, 0x0 }, + { 0x54019, 0x84 }, + { 0x5401a, (((LPDDR4_RON) << 3) | 0x1) }, + { 0x5401b, ((LPDDR4_VREF_VALUE_CA << 8) | (LPDDR4_RTT_CA << 4) | + LPDDR4_RTT_DQ) }, + { 0x5401c, ((LPDDR4_VREF_VALUE_DQ_RANK0 << 8) | 0x08) }, + { 0x5401d, 0x0 }, + { 0x5401e, LPDDR4_MR22_RANK0 }, + { 0x5401f, 0x84 }, + { 0x54020, (((LPDDR4_RON) << 3) | 0x1) }, + { 0x54021, ((LPDDR4_VREF_VALUE_CA << 8) | (LPDDR4_RTT_CA << 4) | + LPDDR4_RTT_DQ) }, + { 0x54022, ((LPDDR4_VREF_VALUE_DQ_RANK1 << 8) | 0x08) }, + { 0x54023, 0x0 }, + { 0x54024, LPDDR4_MR22_RANK1 }, + { 0x54025, 0x0 }, + { 0x54026, 0x0 }, + { 0x54027, 0x0 }, + { 0x54028, 0x0 }, + { 0x54029, 0x0 }, + { 0x5402a, 0x0 }, + { 0x5402b, 0x1000 }, + { 0x5402c, 0x3 }, + { 0x5402d, 0x0 }, + { 0x5402e, 0x0 }, + { 0x5402f, 0x0 }, + { 0x54030, 0x0 }, + { 0x54031, 0x0 }, + { 0x54032, 0x8400 }, + { 0x54033, ((((LPDDR4_RON) << 3) | 0x1) << 8) | 0x00 }, + { 0x54034, (((LPDDR4_RTT_CA << 4) | LPDDR4_RTT_DQ) << 8) }, + { 0x54035, (0x0800 | LPDDR4_VREF_VALUE_CA) }, + { 0x54036, LPDDR4_VREF_VALUE_DQ_RANK0 }, + { 0x54037, (LPDDR4_MR22_RANK0 << 8) }, + { 0x54038, 0x8400 }, + { 0x54039, ((((LPDDR4_RON) << 3) | 0x1) << 8) | 0x00 }, + { 0x5403a, (((LPDDR4_RTT_CA << 4) | LPDDR4_RTT_DQ) << 8) }, + { 0x5403b, (0x0800 | LPDDR4_VREF_VALUE_CA) }, + { 0x5403c, LPDDR4_VREF_VALUE_DQ_RANK1 }, + { 0x5403d, (LPDDR4_MR22_RANK1 << 8) }, + { 0x5403e, 0x0 }, + { 0x5403f, 0x0 }, + { 0x54040, 0x0 }, + { 0x54041, 0x0 }, + { 0x54042, 0x0 }, + { 0x54043, 0x0 }, + { 0x54044, 0x0 }, + { 0xd0000, 0x1 }, +}; + +/* P0 2D message block paremeter for training firmware */ +struct dram_cfg_param lpddr4_fsp0_2d_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54000, 0x0 }, + { 0x54001, 0x0 }, + { 0x54002, 0x0 }, + { 0x54003, 0xc80 }, + { 0x54004, 0x2 }, + { 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT) }, + { 0x54006, LPDDR4_PHY_VREF_VALUE }, + { 0x54007, 0x0 }, + { 0x54008, 0x61 }, + { 0x54009, LPDDR4_HDT_CTL_2D }, + { 0x5400a, 0x0 }, + { 0x5400b, 0x2 }, + { 0x5400c, 0x0 }, + { 0x5400d, (LPDDR4_CATRAIN_3200_2d << 8) }, + { 0x5400e, 0x0 }, + { 0x5400f, (LPDDR4_2D_SHARE << 8) | 0x00 }, + { 0x54010, LPDDR4_2D_WEIGHT }, + { 0x54011, 0x0 }, + { 0x54012, 0x310 }, + { 0x54013, 0x0 }, + { 0x54014, 0x0 }, + { 0x54015, 0x0 }, + { 0x54016, 0x0 }, + { 0x54017, 0x0 }, + { 0x54018, 0x0 }, + { 0x54019, 0x2dd4 }, +#ifdef WR_POST_EXT_3200 + { 0x5401a, (((LPDDR4_RON) << 3) | 0x3) }, +#else + { 0x5401a, (((LPDDR4_RON) << 3) | 0x1) }, +#endif + { 0x5401b, ((LPDDR4_VREF_VALUE_CA << 8) | + (LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ) }, + { 0x5401c, ((LPDDR4_VREF_VALUE_DQ_RANK0 << 8) | 0x08) }, + { 0x5401d, 0x0 }, + { 0x5401e, LPDDR4_MR22_RANK0 }, + { 0x5401f, 0x2dd4 }, +#ifdef WR_POST_EXT_3200 + { 0x54020, (((LPDDR4_RON) << 3) | 0x3) }, +#else + { 0x54020, (((LPDDR4_RON) << 3) | 0x1) }, +#endif + { 0x54021, ((LPDDR4_VREF_VALUE_CA << 8) | + (LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ) }, + { 0x54022, ((LPDDR4_VREF_VALUE_DQ_RANK1 << 8) | 0x08) }, + { 0x54023, 0x0 }, + { 0x54024, LPDDR4_MR22_RANK1 }, + { 0x54025, 0x0 }, + { 0x54026, 0x0 }, + { 0x54027, 0x0 }, + { 0x54028, 0x0 }, + { 0x54029, 0x0 }, + { 0x5402a, 0x0 }, + { 0x5402b, 0x1000 }, + { 0x5402c, 0x3 }, + { 0x5402d, 0x0 }, + { 0x5402e, 0x0 }, + { 0x5402f, 0x0 }, + { 0x54030, 0x0 }, + { 0x54031, 0x0 }, + + { 0x54032, 0xd400 }, +#ifdef WR_POST_EXT_3200 + { 0x54033, ((((LPDDR4_RON) << 3) | 0x3) << 8) | 0x2d }, +#else + { 0x54033, ((((LPDDR4_RON) << 3) | 0x1) << 8) | 0x2d }, +#endif + { 0x54034, (((LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ) << 8) }, + { 0x54035, (0x0800 | LPDDR4_VREF_VALUE_CA) }, + { 0x54036, LPDDR4_VREF_VALUE_DQ_RANK0 }, + { 0x54037, (LPDDR4_MR22_RANK0 << 8) }, + { 0x54038, 0xd400 }, +#ifdef WR_POST_EXT_3200 + { 0x54039, ((((LPDDR4_RON) << 3) | 0x3) << 8) | 0x2d }, +#else + { 0x54039, ((((LPDDR4_RON) << 3) | 0x1) << 8) | 0x2d }, +#endif + { 0x5403a, (((LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ) << 8) }, + { 0x5403b, (0x0800 | LPDDR4_VREF_VALUE_CA) }, + { 0x5403c, LPDDR4_VREF_VALUE_DQ_RANK1 }, + { 0x5403d, (LPDDR4_MR22_RANK1 << 8) }, + { 0x5403e, 0x0 }, + { 0x5403f, 0x0 }, + { 0x54040, 0x0 }, + { 0x54041, 0x0 }, + { 0x54042, 0x0 }, + { 0x54043, 0x0 }, + { 0x54044, 0x0 }, + { 0xd0000, 0x1 }, +}; + +/* DRAM PHY init engine image */ +struct dram_cfg_param lpddr4_phy_pie[] = { + { 0xd0000, 0x0 }, + { 0x90000, 0x10 }, + { 0x90001, 0x400 }, + { 0x90002, 0x10e }, + { 0x90003, 0x0 }, + { 0x90004, 0x0 }, + { 0x90005, 0x8 }, + { 0x90029, 0xb }, + { 0x9002a, 0x480 }, + { 0x9002b, 0x109 }, + { 0x9002c, 0x8 }, + { 0x9002d, 0x448 }, + { 0x9002e, 0x139 }, + { 0x9002f, 0x8 }, + { 0x90030, 0x478 }, + { 0x90031, 0x109 }, + { 0x90032, 0x0 }, + { 0x90033, 0xe8 }, + { 0x90034, 0x109 }, + { 0x90035, 0x2 }, + { 0x90036, 0x10 }, + { 0x90037, 0x139 }, + { 0x90038, 0xf }, + { 0x90039, 0x7c0 }, + { 0x9003a, 0x139 }, + { 0x9003b, 0x44 }, + { 0x9003c, 0x630 }, + { 0x9003d, 0x159 }, + { 0x9003e, 0x14f }, + { 0x9003f, 0x630 }, + { 0x90040, 0x159 }, + { 0x90041, 0x47 }, + { 0x90042, 0x630 }, + { 0x90043, 0x149 }, + { 0x90044, 0x4f }, + { 0x90045, 0x630 }, + { 0x90046, 0x179 }, + { 0x90047, 0x8 }, + { 0x90048, 0xe0 }, + { 0x90049, 0x109 }, + { 0x9004a, 0x0 }, + { 0x9004b, 0x7c8 }, + { 0x9004c, 0x109 }, + { 0x9004d, 0x0 }, + { 0x9004e, 0x1 }, + { 0x9004f, 0x8 }, + { 0x90050, 0x0 }, + { 0x90051, 0x45a }, + { 0x90052, 0x9 }, + { 0x90053, 0x0 }, + { 0x90054, 0x448 }, + { 0x90055, 0x109 }, + { 0x90056, 0x40 }, + { 0x90057, 0x630 }, + { 0x90058, 0x179 }, + { 0x90059, 0x1 }, + { 0x9005a, 0x618 }, + { 0x9005b, 0x109 }, + { 0x9005c, 0x40c0 }, + { 0x9005d, 0x630 }, + { 0x9005e, 0x149 }, + { 0x9005f, 0x8 }, + { 0x90060, 0x4 }, + { 0x90061, 0x48 }, + { 0x90062, 0x4040 }, + { 0x90063, 0x630 }, + { 0x90064, 0x149 }, + { 0x90065, 0x0 }, + { 0x90066, 0x4 }, + { 0x90067, 0x48 }, + { 0x90068, 0x40 }, + { 0x90069, 0x630 }, + { 0x9006a, 0x149 }, + { 0x9006b, 0x10 }, + { 0x9006c, 0x4 }, + { 0x9006d, 0x18 }, + { 0x9006e, 0x0 }, + { 0x9006f, 0x4 }, + { 0x90070, 0x78 }, + { 0x90071, 0x549 }, + { 0x90072, 0x630 }, + { 0x90073, 0x159 }, + { 0x90074, 0xd49 }, + { 0x90075, 0x630 }, + { 0x90076, 0x159 }, + { 0x90077, 0x94a }, + { 0x90078, 0x630 }, + { 0x90079, 0x159 }, + { 0x9007a, 0x441 }, + { 0x9007b, 0x630 }, + { 0x9007c, 0x149 }, + { 0x9007d, 0x42 }, + { 0x9007e, 0x630 }, + { 0x9007f, 0x149 }, + { 0x90080, 0x1 }, + { 0x90081, 0x630 }, + { 0x90082, 0x149 }, + { 0x90083, 0x0 }, + { 0x90084, 0xe0 }, + { 0x90085, 0x109 }, + { 0x90086, 0xa }, + { 0x90087, 0x10 }, + { 0x90088, 0x109 }, + { 0x90089, 0x9 }, + { 0x9008a, 0x3c0 }, + { 0x9008b, 0x149 }, + { 0x9008c, 0x9 }, + { 0x9008d, 0x3c0 }, + { 0x9008e, 0x159 }, + { 0x9008f, 0x18 }, + { 0x90090, 0x10 }, + { 0x90091, 0x109 }, + { 0x90092, 0x0 }, + { 0x90093, 0x3c0 }, + { 0x90094, 0x109 }, + { 0x90095, 0x18 }, + { 0x90096, 0x4 }, + { 0x90097, 0x48 }, + { 0x90098, 0x18 }, + { 0x90099, 0x4 }, + { 0x9009a, 0x58 }, + { 0x9009b, 0xa }, + { 0x9009c, 0x10 }, + { 0x9009d, 0x109 }, + { 0x9009e, 0x2 }, + { 0x9009f, 0x10 }, + { 0x900a0, 0x109 }, + { 0x900a1, 0x5 }, + { 0x900a2, 0x7c0 }, + { 0x900a3, 0x109 }, + { 0x900a4, 0x10 }, + { 0x900a5, 0x10 }, + { 0x900a6, 0x109 }, + { 0x40000, 0x811 }, + { 0x40020, 0x880 }, + { 0x40040, 0x0 }, + { 0x40060, 0x0 }, + { 0x40001, 0x4008 }, + { 0x40021, 0x83 }, + { 0x40041, 0x4f }, + { 0x40061, 0x0 }, + { 0x40002, 0x4040 }, + { 0x40022, 0x83 }, + { 0x40042, 0x51 }, + { 0x40062, 0x0 }, + { 0x40003, 0x811 }, + { 0x40023, 0x880 }, + { 0x40043, 0x0 }, + { 0x40063, 0x0 }, + { 0x40004, 0x720 }, + { 0x40024, 0xf }, + { 0x40044, 0x1740 }, + { 0x40064, 0x0 }, + { 0x40005, 0x16 }, + { 0x40025, 0x83 }, + { 0x40045, 0x4b }, + { 0x40065, 0x0 }, + { 0x40006, 0x716 }, + { 0x40026, 0xf }, + { 0x40046, 0x2001 }, + { 0x40066, 0x0 }, + { 0x40007, 0x716 }, + { 0x40027, 0xf }, + { 0x40047, 0x2800 }, + { 0x40067, 0x0 }, + { 0x40008, 0x716 }, + { 0x40028, 0xf }, + { 0x40048, 0xf00 }, + { 0x40068, 0x0 }, + { 0x40009, 0x720 }, + { 0x40029, 0xf }, + { 0x40049, 0x1400 }, + { 0x40069, 0x0 }, + { 0x4000a, 0xe08 }, + { 0x4002a, 0xc15 }, + { 0x4004a, 0x0 }, + { 0x4006a, 0x0 }, + { 0x4000b, 0x623 }, + { 0x4002b, 0x15 }, + { 0x4004b, 0x0 }, + { 0x4006b, 0x0 }, + { 0x4000c, 0x4028 }, + { 0x4002c, 0x80 }, + { 0x4004c, 0x0 }, + { 0x4006c, 0x0 }, + { 0x4000d, 0xe08 }, + { 0x4002d, 0xc1a }, + { 0x4004d, 0x0 }, + { 0x4006d, 0x0 }, + { 0x4000e, 0x623 }, + { 0x4002e, 0x1a }, + { 0x4004e, 0x0 }, + { 0x4006e, 0x0 }, + { 0x4000f, 0x4040 }, + { 0x4002f, 0x80 }, + { 0x4004f, 0x0 }, + { 0x4006f, 0x0 }, + { 0x40010, 0x2604 }, + { 0x40030, 0x15 }, + { 0x40050, 0x0 }, + { 0x40070, 0x0 }, + { 0x40011, 0x708 }, + { 0x40031, 0x5 }, + { 0x40051, 0x0 }, + { 0x40071, 0x2002 }, + { 0x40012, 0x8 }, + { 0x40032, 0x80 }, + { 0x40052, 0x0 }, + { 0x40072, 0x0 }, + { 0x40013, 0x2604 }, + { 0x40033, 0x1a }, + { 0x40053, 0x0 }, + { 0x40073, 0x0 }, + { 0x40014, 0x708 }, + { 0x40034, 0xa }, + { 0x40054, 0x0 }, + { 0x40074, 0x2002 }, + { 0x40015, 0x4040 }, + { 0x40035, 0x80 }, + { 0x40055, 0x0 }, + { 0x40075, 0x0 }, + { 0x40016, 0x60a }, + { 0x40036, 0x15 }, + { 0x40056, 0x1200 }, + { 0x40076, 0x0 }, + { 0x40017, 0x61a }, + { 0x40037, 0x15 }, + { 0x40057, 0x1300 }, + { 0x40077, 0x0 }, + { 0x40018, 0x60a }, + { 0x40038, 0x1a }, + { 0x40058, 0x1200 }, + { 0x40078, 0x0 }, + { 0x40019, 0x642 }, + { 0x40039, 0x1a }, + { 0x40059, 0x1300 }, + { 0x40079, 0x0 }, + { 0x4001a, 0x4808 }, + { 0x4003a, 0x880 }, + { 0x4005a, 0x0 }, + { 0x4007a, 0x0 }, + { 0x900a7, 0x0 }, + { 0x900a8, 0x790 }, + { 0x900a9, 0x11a }, + { 0x900aa, 0x8 }, + { 0x900ab, 0x7aa }, + { 0x900ac, 0x2a }, + { 0x900ad, 0x10 }, + { 0x900ae, 0x7b2 }, + { 0x900af, 0x2a }, + { 0x900b0, 0x0 }, + { 0x900b1, 0x7c8 }, + { 0x900b2, 0x109 }, + { 0x900b3, 0x10 }, + { 0x900b4, 0x2a8 }, + { 0x900b5, 0x129 }, + { 0x900b6, 0x8 }, + { 0x900b7, 0x370 }, + { 0x900b8, 0x129 }, + { 0x900b9, 0xa }, + { 0x900ba, 0x3c8 }, + { 0x900bb, 0x1a9 }, + { 0x900bc, 0xc }, + { 0x900bd, 0x408 }, + { 0x900be, 0x199 }, + { 0x900bf, 0x14 }, + { 0x900c0, 0x790 }, + { 0x900c1, 0x11a }, + { 0x900c2, 0x8 }, + { 0x900c3, 0x4 }, + { 0x900c4, 0x18 }, + { 0x900c5, 0xe }, + { 0x900c6, 0x408 }, + { 0x900c7, 0x199 }, + { 0x900c8, 0x8 }, + { 0x900c9, 0x8568 }, + { 0x900ca, 0x108 }, + { 0x900cb, 0x18 }, + { 0x900cc, 0x790 }, + { 0x900cd, 0x16a }, + { 0x900ce, 0x8 }, + { 0x900cf, 0x1d8 }, + { 0x900d0, 0x169 }, + { 0x900d1, 0x10 }, + { 0x900d2, 0x8558 }, + { 0x900d3, 0x168 }, + { 0x900d4, 0x70 }, + { 0x900d5, 0x788 }, + { 0x900d6, 0x16a }, + { 0x900d7, 0x1ff8 }, + { 0x900d8, 0x85a8 }, + { 0x900d9, 0x1e8 }, + { 0x900da, 0x50 }, + { 0x900db, 0x798 }, + { 0x900dc, 0x16a }, + { 0x900dd, 0x60 }, + { 0x900de, 0x7a0 }, + { 0x900df, 0x16a }, + { 0x900e0, 0x8 }, + { 0x900e1, 0x8310 }, + { 0x900e2, 0x168 }, + { 0x900e3, 0x8 }, + { 0x900e4, 0xa310 }, + { 0x900e5, 0x168 }, + { 0x900e6, 0xa }, + { 0x900e7, 0x408 }, + { 0x900e8, 0x169 }, + { 0x900e9, 0x6e }, + { 0x900ea, 0x0 }, + { 0x900eb, 0x68 }, + { 0x900ec, 0x0 }, + { 0x900ed, 0x408 }, + { 0x900ee, 0x169 }, + { 0x900ef, 0x0 }, + { 0x900f0, 0x8310 }, + { 0x900f1, 0x168 }, + { 0x900f2, 0x0 }, + { 0x900f3, 0xa310 }, + { 0x900f4, 0x168 }, + { 0x900f5, 0x1ff8 }, + { 0x900f6, 0x85a8 }, + { 0x900f7, 0x1e8 }, + { 0x900f8, 0x68 }, + { 0x900f9, 0x798 }, + { 0x900fa, 0x16a }, + { 0x900fb, 0x78 }, + { 0x900fc, 0x7a0 }, + { 0x900fd, 0x16a }, + { 0x900fe, 0x68 }, + { 0x900ff, 0x790 }, + { 0x90100, 0x16a }, + { 0x90101, 0x8 }, + { 0x90102, 0x8b10 }, + { 0x90103, 0x168 }, + { 0x90104, 0x8 }, + { 0x90105, 0xab10 }, + { 0x90106, 0x168 }, + { 0x90107, 0xa }, + { 0x90108, 0x408 }, + { 0x90109, 0x169 }, + { 0x9010a, 0x58 }, + { 0x9010b, 0x0 }, + { 0x9010c, 0x68 }, + { 0x9010d, 0x0 }, + { 0x9010e, 0x408 }, + { 0x9010f, 0x169 }, + { 0x90110, 0x0 }, + { 0x90111, 0x8b10 }, + { 0x90112, 0x168 }, + { 0x90113, 0x0 }, + { 0x90114, 0xab10 }, + { 0x90115, 0x168 }, + { 0x90116, 0x0 }, + { 0x90117, 0x1d8 }, + { 0x90118, 0x169 }, + { 0x90119, 0x80 }, + { 0x9011a, 0x790 }, + { 0x9011b, 0x16a }, + { 0x9011c, 0x18 }, + { 0x9011d, 0x7aa }, + { 0x9011e, 0x6a }, + { 0x9011f, 0xa }, + { 0x90120, 0x0 }, + { 0x90121, 0x1e9 }, + { 0x90122, 0x8 }, + { 0x90123, 0x8080 }, + { 0x90124, 0x108 }, + { 0x90125, 0xf }, + { 0x90126, 0x408 }, + { 0x90127, 0x169 }, + { 0x90128, 0xc }, + { 0x90129, 0x0 }, + { 0x9012a, 0x68 }, + { 0x9012b, 0x9 }, + { 0x9012c, 0x0 }, + { 0x9012d, 0x1a9 }, + { 0x9012e, 0x0 }, + { 0x9012f, 0x408 }, + { 0x90130, 0x169 }, + { 0x90131, 0x0 }, + { 0x90132, 0x8080 }, + { 0x90133, 0x108 }, + { 0x90134, 0x8 }, + { 0x90135, 0x7aa }, + { 0x90136, 0x6a }, + { 0x90137, 0x0 }, + { 0x90138, 0x8568 }, + { 0x90139, 0x108 }, + { 0x9013a, 0xb7 }, + { 0x9013b, 0x790 }, + { 0x9013c, 0x16a }, + { 0x9013d, 0x1f }, + { 0x9013e, 0x0 }, + { 0x9013f, 0x68 }, + { 0x90140, 0x8 }, + { 0x90141, 0x8558 }, + { 0x90142, 0x168 }, + { 0x90143, 0xf }, + { 0x90144, 0x408 }, + { 0x90145, 0x169 }, + { 0x90146, 0xc }, + { 0x90147, 0x0 }, + { 0x90148, 0x68 }, + { 0x90149, 0x0 }, + { 0x9014a, 0x408 }, + { 0x9014b, 0x169 }, + { 0x9014c, 0x0 }, + { 0x9014d, 0x8558 }, + { 0x9014e, 0x168 }, + { 0x9014f, 0x8 }, + { 0x90150, 0x3c8 }, + { 0x90151, 0x1a9 }, + { 0x90152, 0x3 }, + { 0x90153, 0x370 }, + { 0x90154, 0x129 }, + { 0x90155, 0x20 }, + { 0x90156, 0x2aa }, + { 0x90157, 0x9 }, + { 0x90158, 0x0 }, + { 0x90159, 0x400 }, + { 0x9015a, 0x10e }, + { 0x9015b, 0x8 }, + { 0x9015c, 0xe8 }, + { 0x9015d, 0x109 }, + { 0x9015e, 0x0 }, + { 0x9015f, 0x8140 }, + { 0x90160, 0x10c }, + { 0x90161, 0x10 }, + { 0x90162, 0x8138 }, + { 0x90163, 0x10c }, + { 0x90164, 0x8 }, + { 0x90165, 0x7c8 }, + { 0x90166, 0x101 }, + { 0x90167, 0x8 }, + { 0x90168, 0x0 }, + { 0x90169, 0x8 }, + { 0x9016a, 0x8 }, + { 0x9016b, 0x448 }, + { 0x9016c, 0x109 }, + { 0x9016d, 0xf }, + { 0x9016e, 0x7c0 }, + { 0x9016f, 0x109 }, + { 0x90170, 0x0 }, + { 0x90171, 0xe8 }, + { 0x90172, 0x109 }, + { 0x90173, 0x47 }, + { 0x90174, 0x630 }, + { 0x90175, 0x109 }, + { 0x90176, 0x8 }, + { 0x90177, 0x618 }, + { 0x90178, 0x109 }, + { 0x90179, 0x8 }, + { 0x9017a, 0xe0 }, + { 0x9017b, 0x109 }, + { 0x9017c, 0x0 }, + { 0x9017d, 0x7c8 }, + { 0x9017e, 0x109 }, + { 0x9017f, 0x8 }, + { 0x90180, 0x8140 }, + { 0x90181, 0x10c }, + { 0x90182, 0x0 }, + { 0x90183, 0x1 }, + { 0x90184, 0x8 }, + { 0x90185, 0x8 }, + { 0x90186, 0x4 }, + { 0x90187, 0x8 }, + { 0x90188, 0x8 }, + { 0x90189, 0x7c8 }, + { 0x9018a, 0x101 }, + { 0x90006, 0x0 }, + { 0x90007, 0x0 }, + { 0x90008, 0x8 }, + { 0x90009, 0x0 }, + { 0x9000a, 0x0 }, + { 0x9000b, 0x0 }, + { 0xd00e7, 0x400 }, + { 0x90017, 0x0 }, + { 0x9001f, 0x2a }, + { 0x90026, 0x6a }, + { 0x400d0, 0x0 }, + { 0x400d1, 0x101 }, + { 0x400d2, 0x105 }, + { 0x400d3, 0x107 }, + { 0x400d4, 0x10f }, + { 0x400d5, 0x202 }, + { 0x400d6, 0x20a }, + { 0x400d7, 0x20b }, + { 0x2003a, 0x2 }, + { 0x2000b, 0x64 }, + { 0x2000c, 0xc8 }, + { 0x2000d, 0x7d0 }, + { 0x2000e, 0x2c }, + { 0x12000b, 0xc }, + { 0x12000c, 0x19 }, + { 0x12000d, 0xfa }, + { 0x12000e, 0x10 }, + { 0x22000b, 0x3 }, + { 0x22000c, 0x6 }, + { 0x22000d, 0x3e }, + { 0x22000e, 0x10 }, + { 0x9000c, 0x0 }, + { 0x9000d, 0x173 }, + { 0x9000e, 0x60 }, + { 0x9000f, 0x6110 }, + { 0x90010, 0x2152 }, + { 0x90011, 0xdfbd }, + { 0x90012, 0x60 }, + { 0x90013, 0x6152 }, + { 0x20010, 0x5a }, + { 0x20011, 0x3 }, + { 0x40080, 0xe0 }, + { 0x40081, 0x12 }, + { 0x40082, 0xe0 }, + { 0x40083, 0x12 }, + { 0x40084, 0xe0 }, + { 0x40085, 0x12 }, + { 0x140080, 0xe0 }, + { 0x140081, 0x12 }, + { 0x140082, 0xe0 }, + { 0x140083, 0x12 }, + { 0x140084, 0xe0 }, + { 0x140085, 0x12 }, + { 0x240080, 0xe0 }, + { 0x240081, 0x12 }, + { 0x240082, 0xe0 }, + { 0x240083, 0x12 }, + { 0x240084, 0xe0 }, + { 0x240085, 0x12 }, + { 0x400fd, 0xf }, + { 0x10011, 0x1 }, + { 0x10012, 0x1 }, + { 0x10013, 0x180 }, + { 0x10018, 0x1 }, + { 0x10002, 0x6209 }, + { 0x100b2, 0x1 }, + { 0x101b4, 0x1 }, + { 0x102b4, 0x1 }, + { 0x103b4, 0x1 }, + { 0x104b4, 0x1 }, + { 0x105b4, 0x1 }, + { 0x106b4, 0x1 }, + { 0x107b4, 0x1 }, + { 0x108b4, 0x1 }, + { 0x11011, 0x1 }, + { 0x11012, 0x1 }, + { 0x11013, 0x180 }, + { 0x11018, 0x1 }, + { 0x11002, 0x6209 }, + { 0x110b2, 0x1 }, + { 0x111b4, 0x1 }, + { 0x112b4, 0x1 }, + { 0x113b4, 0x1 }, + { 0x114b4, 0x1 }, + { 0x115b4, 0x1 }, + { 0x116b4, 0x1 }, + { 0x117b4, 0x1 }, + { 0x118b4, 0x1 }, + { 0x12011, 0x1 }, + { 0x12012, 0x1 }, + { 0x12013, 0x180 }, + { 0x12018, 0x1 }, + { 0x12002, 0x6209 }, + { 0x120b2, 0x1 }, + { 0x121b4, 0x1 }, + { 0x122b4, 0x1 }, + { 0x123b4, 0x1 }, + { 0x124b4, 0x1 }, + { 0x125b4, 0x1 }, + { 0x126b4, 0x1 }, + { 0x127b4, 0x1 }, + { 0x128b4, 0x1 }, + { 0x13011, 0x1 }, + { 0x13012, 0x1 }, + { 0x13013, 0x180 }, + { 0x13018, 0x1 }, + { 0x13002, 0x6209 }, + { 0x130b2, 0x1 }, + { 0x131b4, 0x1 }, + { 0x132b4, 0x1 }, + { 0x133b4, 0x1 }, + { 0x134b4, 0x1 }, + { 0x135b4, 0x1 }, + { 0x136b4, 0x1 }, + { 0x137b4, 0x1 }, + { 0x138b4, 0x1 }, + { 0x2003a, 0x2 }, + { 0xc0080, 0x2 }, + { 0xd0000, 0x1 }, +}; + +struct dram_fsp_msg lpddr4_dram_fsp_msg[] = { + { + /* P0 3200mts 1D */ + .drate = 3200, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = lpddr4_fsp0_cfg, + .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp0_cfg), + }, + { + /* P1 400mts 1D */ + .drate = 400, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = lpddr4_fsp1_cfg, + .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp1_cfg), + }, + { + /* P1 100mts 1D */ + .drate = 100, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = lpddr4_fsp2_cfg, + .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp2_cfg), + }, + { + /* P0 3200mts 2D */ + .drate = 3200, + .fw_type = FW_2D_IMAGE, + .fsp_cfg = lpddr4_fsp0_2d_cfg, + .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp0_2d_cfg), + }, +}; + +/* lpddr4 timing config params on EVK board */ +struct dram_timing_info dram_timing = { + .ddrc_cfg = lpddr4_ddrc_cfg, + .ddrc_cfg_num = ARRAY_SIZE(lpddr4_ddrc_cfg), + .ddrphy_cfg = lpddr4_ddrphy_cfg, + .ddrphy_cfg_num = ARRAY_SIZE(lpddr4_ddrphy_cfg), + .fsp_msg = lpddr4_dram_fsp_msg, + .fsp_msg_num = ARRAY_SIZE(lpddr4_dram_fsp_msg), + .ddrphy_pie = lpddr4_phy_pie, + .ddrphy_pie_num = ARRAY_SIZE(lpddr4_phy_pie), + .fsp_table = { 3200, 400, 100, }, +}; diff --git a/board/purism/librem5/lpddr4_timing_b0.c b/board/purism/librem5/lpddr4_timing_b0.c new file mode 100644 index 0000000000..ec68edaf69 --- /dev/null +++ b/board/purism/librem5/lpddr4_timing_b0.c @@ -0,0 +1,1191 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 NXP + */ + +#include +#include +#include +#include + +#define WR_POST_EXT_3200 /* recommened to define */ + +static struct dram_cfg_param lpddr4_ddrc_cfg[] = { + /* Start to config, default 3200mbps */ + /* dis_dq=1, indicates no reads or writes are issued to SDRAM */ + { DDRC_DBG1(0), 0x00000001 }, + /* selfref_en=1, SDRAM enter self-refresh state */ + { DDRC_PWRCTL(0), 0x00000001 }, + { DDRC_MSTR(0), 0xa3080020 }, + { DDRC_MSTR2(0), 0x00000000 }, + { DDRC_RFSHTMG(0), 0x006100E0 }, + { DDRC_INIT0(0), 0xC003061B }, + { DDRC_INIT1(0), 0x009D0000 }, + { DDRC_INIT3(0), 0x00D4002D }, +#ifdef WR_POST_EXT_3200 /* recommened to define */ + { DDRC_INIT4(0), 0x00330008 }, +#else + { DDRC_INIT4(0), 0x00310008 }, +#endif + { DDRC_INIT6(0), 0x0066004a }, + { DDRC_INIT7(0), 0x0006004a }, + + { DDRC_DRAMTMG0(0), 0x1A201B22 }, + { DDRC_DRAMTMG1(0), 0x00060633 }, + { DDRC_DRAMTMG3(0), 0x00C0C000 }, + { DDRC_DRAMTMG4(0), 0x0F04080F }, + { DDRC_DRAMTMG5(0), 0x02040C0C }, + { DDRC_DRAMTMG6(0), 0x01010007 }, + { DDRC_DRAMTMG7(0), 0x00000401 }, + { DDRC_DRAMTMG12(0), 0x00020600 }, + { DDRC_DRAMTMG13(0), 0x0C100002 }, + { DDRC_DRAMTMG14(0), 0x000000E6 }, + { DDRC_DRAMTMG17(0), 0x00A00050 }, + + { DDRC_ZQCTL0(0), 0x03200018 }, + { DDRC_ZQCTL1(0), 0x028061A8 }, + { DDRC_ZQCTL2(0), 0x00000000 }, + + { DDRC_DFITMG0(0), 0x0497820A }, + { DDRC_DFITMG1(0), 0x00080303 }, + { DDRC_DFIUPD0(0), 0xE0400018 }, + { DDRC_DFIUPD1(0), 0x00DF00E4 }, + { DDRC_DFIUPD2(0), 0x80000000 }, + { DDRC_DFIMISC(0), 0x00000011 }, + { DDRC_DFITMG2(0), 0x0000170A }, + + { DDRC_DBICTL(0), 0x00000001 }, + { DDRC_DFIPHYMSTR(0), 0x00000001 }, + + /* need be refined by ddrphy trained value */ + { DDRC_RANKCTL(0), 0x00000c99 }, + { DDRC_DRAMTMG2(0), 0x070E171a }, + + /* address mapping */ + /* Address map is from MSB 29: r15, r14, cs, r13-r0, b2-b0, c9-c0 */ + { DDRC_ADDRMAP0(0), 0x00000015 }, + { DDRC_ADDRMAP3(0), 0x00000000 }, + /* addrmap_col_b10 addrmap_col_b11 set to de-activated (5-bit width) */ + { DDRC_ADDRMAP4(0), 0x00001F1F }, + /* bank interleave */ + /* addrmap_bank_b2, addrmap_bank_b1, addrmap_bank_b0 */ + { DDRC_ADDRMAP1(0), 0x00080808 }, + /* addrmap_row_b11 addrmap_row_b10_b2 addrmap_row_b1 addrmap_row_b0 */ + { DDRC_ADDRMAP5(0), 0x07070707 }, + /* addrmap_row_b15 addrmap_row_b14 addrmap_row_b13 addrmap_row_b12 */ + { DDRC_ADDRMAP6(0), 0x08080707 }, + + /* 667mts frequency setting */ + { DDRC_FREQ1_DERATEEN(0), 0x0000000 }, + { DDRC_FREQ1_DERATEINT(0), 0x0800000 }, + { DDRC_FREQ1_RFSHCTL0(0), 0x0210000 }, + { DDRC_FREQ1_RFSHTMG(0), 0x014001E }, + { DDRC_FREQ1_INIT3(0), 0x0140009 }, + { DDRC_FREQ1_INIT4(0), 0x00310008 }, + { DDRC_FREQ1_INIT6(0), 0x0066004a }, + { DDRC_FREQ1_INIT7(0), 0x0006004a }, + { DDRC_FREQ1_DRAMTMG0(0), 0xB070A07 }, + { DDRC_FREQ1_DRAMTMG1(0), 0x003040A }, + { DDRC_FREQ1_DRAMTMG2(0), 0x305080C }, + { DDRC_FREQ1_DRAMTMG3(0), 0x0505000 }, + { DDRC_FREQ1_DRAMTMG4(0), 0x3040203 }, + { DDRC_FREQ1_DRAMTMG5(0), 0x2030303 }, + { DDRC_FREQ1_DRAMTMG6(0), 0x2020004 }, + { DDRC_FREQ1_DRAMTMG7(0), 0x0000302 }, + { DDRC_FREQ1_DRAMTMG12(0), 0x0020310 }, + { DDRC_FREQ1_DRAMTMG13(0), 0xA100002 }, + { DDRC_FREQ1_DRAMTMG14(0), 0x0000020 }, + { DDRC_FREQ1_DRAMTMG17(0), 0x0220011 }, + { DDRC_FREQ1_ZQCTL0(0), 0x0A70005 }, + { DDRC_FREQ1_DFITMG0(0), 0x3858202 }, + { DDRC_FREQ1_DFITMG1(0), 0x0000404 }, + { DDRC_FREQ1_DFITMG2(0), 0x0000502 }, + + /* performance setting */ + { DDRC_ODTCFG(0), 0x0b060908 }, + { DDRC_ODTMAP(0), 0x00000000 }, + { DDRC_SCHED(0), 0x29511505 }, + { DDRC_SCHED1(0), 0x0000002c }, + { DDRC_PERFHPR1(0), 0x5900575b }, + /* 150T starve and 0x90 max tran len */ + { DDRC_PERFLPR1(0), 0x90000096 }, + /* 300T starve and 0x10 max tran len */ + { DDRC_PERFWR1(0), 0x1000012c }, + { DDRC_DBG0(0), 0x00000016 }, + { DDRC_DBG1(0), 0x00000000 }, + { DDRC_DBGCMD(0), 0x00000000 }, + { DDRC_SWCTL(0), 0x00000001 }, + { DDRC_POISONCFG(0), 0x00000011 }, + { DDRC_PCCFG(0), 0x00000111 }, + { DDRC_PCFGR_0(0), 0x000010f3 }, + { DDRC_PCFGW_0(0), 0x000072ff }, + { DDRC_PCTRL_0(0), 0x00000001 }, + /* disable Read Qos*/ + { DDRC_PCFGQOS0_0(0), 0x00000e00 }, + { DDRC_PCFGQOS1_0(0), 0x0062ffff }, + /* disable Write Qos*/ + { DDRC_PCFGWQOS0_0(0), 0x00000e00 }, + { DDRC_PCFGWQOS1_0(0), 0x0000ffff }, + { DDRC_FREQ1_DERATEEN(0), 0x00000202 }, + { DDRC_FREQ1_DERATEINT(0), 0xec78f4b5 }, + { DDRC_FREQ1_RFSHCTL0(0), 0x00618040 }, + { DDRC_FREQ1_RFSHTMG(0), 0x00610090 }, +}; + +/* PHY Initialize Configuration */ +static struct dram_cfg_param lpddr4_ddrphy_cfg[] = { + { 0x20110, 0x02 }, /* MapCAB0toDFI */ + { 0x20111, 0x03 }, /* MapCAB1toDFI */ + { 0x20112, 0x04 }, /* MapCAB2toDFI */ + { 0x20113, 0x05 }, /* MapCAB3toDFI */ + { 0x20114, 0x00 }, /* MapCAB4toDFI */ + { 0x20115, 0x01 }, /* MapCAB5toDFI */ + + /* Initialize PHY Configuration */ + { 0x1005f, 0x1ff }, + { 0x1015f, 0x1ff }, + { 0x1105f, 0x1ff }, + { 0x1115f, 0x1ff }, + { 0x1205f, 0x1ff }, + { 0x1215f, 0x1ff }, + { 0x1305f, 0x1ff }, + { 0x1315f, 0x1ff }, + + { 0x11005f, 0x1ff }, + { 0x11015f, 0x1ff }, + { 0x11105f, 0x1ff }, + { 0x11115f, 0x1ff }, + { 0x11205f, 0x1ff }, + { 0x11215f, 0x1ff }, + { 0x11305f, 0x1ff }, + { 0x11315f, 0x1ff }, + + { 0x21005f, 0x1ff }, + { 0x21015f, 0x1ff }, + { 0x21105f, 0x1ff }, + { 0x21115f, 0x1ff }, + { 0x21205f, 0x1ff }, + { 0x21215f, 0x1ff }, + { 0x21305f, 0x1ff }, + { 0x21315f, 0x1ff }, + + { 0x55, 0x1ff }, + { 0x1055, 0x1ff }, + { 0x2055, 0x1ff }, + { 0x3055, 0x1ff }, + { 0x4055, 0x1ff }, + { 0x5055, 0x1ff }, + { 0x6055, 0x1ff }, + { 0x7055, 0x1ff }, + { 0x8055, 0x1ff }, + { 0x9055, 0x1ff }, + { 0x200c5, 0x19 }, + { 0x1200c5, 0x7 }, + { 0x2200c5, 0x7 }, + { 0x2002e, 0x2 }, + { 0x12002e, 0x1 }, + { 0x22002e, 0x2 }, + { 0x90204, 0x0 }, + { 0x190204, 0x0 }, + { 0x290204, 0x0 }, + + { 0x20024, 0xe3 }, + { 0x2003a, 0x2 }, + { 0x120024, 0xa3 }, + { 0x2003a, 0x2 }, + { 0x220024, 0xa3 }, + { 0x2003a, 0x2 }, + + { 0x20056, 0x3 }, + { 0x120056, 0xa }, + { 0x220056, 0xa }, + + { 0x1004d, 0xe00 }, + { 0x1014d, 0xe00 }, + { 0x1104d, 0xe00 }, + { 0x1114d, 0xe00 }, + { 0x1204d, 0xe00 }, + { 0x1214d, 0xe00 }, + { 0x1304d, 0xe00 }, + { 0x1314d, 0xe00 }, + { 0x11004d, 0xe00 }, + { 0x11014d, 0xe00 }, + { 0x11104d, 0xe00 }, + { 0x11114d, 0xe00 }, + { 0x11204d, 0xe00 }, + { 0x11214d, 0xe00 }, + { 0x11304d, 0xe00 }, + { 0x11314d, 0xe00 }, + { 0x21004d, 0xe00 }, + { 0x21014d, 0xe00 }, + { 0x21104d, 0xe00 }, + { 0x21114d, 0xe00 }, + { 0x21204d, 0xe00 }, + { 0x21214d, 0xe00 }, + { 0x21304d, 0xe00 }, + { 0x21314d, 0xe00 }, + + { 0x10049, 0xfbe }, + { 0x10149, 0xfbe }, + { 0x11049, 0xfbe }, + { 0x11149, 0xfbe }, + { 0x12049, 0xfbe }, + { 0x12149, 0xfbe }, + { 0x13049, 0xfbe }, + { 0x13149, 0xfbe }, + + { 0x110049, 0xfbe }, + { 0x110149, 0xfbe }, + { 0x111049, 0xfbe }, + { 0x111149, 0xfbe }, + { 0x112049, 0xfbe }, + { 0x112149, 0xfbe }, + { 0x113049, 0xfbe }, + { 0x113149, 0xfbe }, + + { 0x210049, 0xfbe }, + { 0x210149, 0xfbe }, + { 0x211049, 0xfbe }, + { 0x211149, 0xfbe }, + { 0x212049, 0xfbe }, + { 0x212149, 0xfbe }, + { 0x213049, 0xfbe }, + { 0x213149, 0xfbe }, + + { 0x43, 0x63 }, + { 0x1043, 0x63 }, + { 0x2043, 0x63 }, + { 0x3043, 0x63 }, + { 0x4043, 0x63 }, + { 0x5043, 0x63 }, + { 0x6043, 0x63 }, + { 0x7043, 0x63 }, + { 0x8043, 0x63 }, + { 0x9043, 0x63 }, + + { 0x20018, 0x3 }, + { 0x20075, 0x4 }, + { 0x20050, 0x0 }, + { 0x20008, 0x320 }, + { 0x120008, 0xa7 }, + { 0x220008, 0x19 }, + { 0x20088, 0x9 }, + { 0x200b2, 0x104 }, + { 0x10043, 0x5a1 }, + { 0x10143, 0x5a1 }, + { 0x11043, 0x5a1 }, + { 0x11143, 0x5a1 }, + { 0x12043, 0x5a1 }, + { 0x12143, 0x5a1 }, + { 0x13043, 0x5a1 }, + { 0x13143, 0x5a1 }, + { 0x1200b2, 0x104 }, + { 0x110043, 0x5a1 }, + { 0x110143, 0x5a1 }, + { 0x111043, 0x5a1 }, + { 0x111143, 0x5a1 }, + { 0x112043, 0x5a1 }, + { 0x112143, 0x5a1 }, + { 0x113043, 0x5a1 }, + { 0x113143, 0x5a1 }, + { 0x2200b2, 0x104 }, + { 0x210043, 0x5a1 }, + { 0x210143, 0x5a1 }, + { 0x211043, 0x5a1 }, + { 0x211143, 0x5a1 }, + { 0x212043, 0x5a1 }, + { 0x212143, 0x5a1 }, + { 0x213043, 0x5a1 }, + { 0x213143, 0x5a1 }, + { 0x200fa, 0x1 }, + { 0x1200fa, 0x1 }, + { 0x2200fa, 0x1 }, + { 0x20019, 0x1 }, + { 0x120019, 0x1 }, + { 0x220019, 0x1 }, + { 0x200f0, 0x600 }, + { 0x200f1, 0x0 }, + { 0x200f2, 0x4444 }, + { 0x200f3, 0x8888 }, + { 0x200f4, 0x5655 }, + { 0x200f5, 0x0 }, + { 0x200f6, 0x0 }, + { 0x200f7, 0xf000 }, + { 0x20025, 0x0 }, + { 0x2002d, 0x0 }, + { 0x12002d, 0x0 }, + { 0x22002d, 0x0 }, +}; + +/* P0 message block paremeter for training firmware */ +static struct dram_cfg_param lpddr4_fsp0_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54000, 0x0 }, + { 0x54001, 0x0 }, + { 0x54002, 0x0 }, + { 0x54003, 0xc80 }, + { 0x54004, 0x2 }, + { 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT) }, + { 0x54006, LPDDR4_PHY_VREF_VALUE }, + { 0x54007, 0x0 }, + { 0x54008, 0x131f }, + { 0x54009, LPDDR4_HDT_CTL_3200_1D }, + { 0x5400a, 0x0 }, + { 0x5400b, 0x2 }, + { 0x5400c, 0x0 }, + { 0x5400d, (LPDDR4_CATRAIN_3200_1d << 8) }, + { 0x5400e, 0x0 }, + { 0x5400f, 0x0 }, + { 0x54010, 0x0 }, + { 0x54011, 0x0 }, + { 0x54012, 0x310 }, + { 0x54013, 0x0 }, + { 0x54014, 0x0 }, + { 0x54015, 0x0 }, + { 0x54016, 0x0 }, + { 0x54017, 0x0 }, + { 0x54018, 0x0 }, + { 0x54019, 0x2dd4 }, + { 0x5401a, (((LPDDR4_RON) << 3) | 0x3) }, + { 0x5401b, ((LPDDR4_VREF_VALUE_CA << 8) | + (LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ) }, + { 0x5401c, ((LPDDR4_VREF_VALUE_DQ_RANK0 << 8) | 0x08) }, + { 0x5401d, 0x0 }, + { 0x5401e, LPDDR4_MR22_RANK0 }, + { 0x5401f, 0x2dd4 }, + { 0x54020, (((LPDDR4_RON) << 3) | 0x3) }, + { 0x54021, ((LPDDR4_VREF_VALUE_CA << 8) | + (LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ) }, + { 0x54022, ((LPDDR4_VREF_VALUE_DQ_RANK1 << 8) | 0x08) }, + { 0x54023, 0x0 }, + { 0x54024, LPDDR4_MR22_RANK1 }, + { 0x54025, 0x0 }, + { 0x54026, 0x0 }, + { 0x54027, 0x0 }, + { 0x54028, 0x0 }, + { 0x54029, 0x0 }, + { 0x5402a, 0x0 }, + { 0x5402b, 0x1000 }, + { 0x5402c, 0x3 }, + { 0x5402d, 0x0 }, + { 0x5402e, 0x0 }, + { 0x5402f, 0x0 }, + { 0x54030, 0x0 }, + { 0x54031, 0x0 }, + { 0x54032, 0xd400 }, + { 0x54033, ((((LPDDR4_RON) << 3) | 0x3) << 8) | 0x2d }, + { 0x54034, (((LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ) << 8) }, + { 0x54035, (0x0800 | LPDDR4_VREF_VALUE_CA) }, + { 0x54036, LPDDR4_VREF_VALUE_DQ_RANK0 }, + { 0x54037, (LPDDR4_MR22_RANK0 << 8) }, + { 0x54038, 0xd400 }, + { 0x54039, ((((LPDDR4_RON) << 3) | 0x3) << 8) | 0x2d }, + { 0x5403a, (((LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ) << 8) }, + { 0x5403b, (0x0800 | LPDDR4_VREF_VALUE_CA) }, + { 0x5403c, LPDDR4_VREF_VALUE_DQ_RANK1 }, + { 0x5403d, (LPDDR4_MR22_RANK1 << 8) }, + { 0x5403d, (LPDDR4_MR22_RANK1 << 8) }, + { 0x5403e, 0x0 }, + { 0x5403f, 0x0 }, + { 0x54040, 0x0 }, + { 0x54041, 0x0 }, + { 0x54042, 0x0 }, + { 0x54043, 0x0 }, + { 0x54044, 0x0 }, + { 0xd0000, 0x1 }, +}; + +/* P1 message block paremeter for training firmware */ +static struct dram_cfg_param lpddr4_fsp1_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54000, 0x0 }, + { 0x54001, 0x0 }, + { 0x54002, 0x1 }, + { 0x54003, 0x29c }, + { 0x54004, 0x2 }, + { 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT) }, + { 0x54006, LPDDR4_PHY_VREF_VALUE }, + { 0x54007, 0x0 }, + { 0x54008, 0x121f }, + { 0x54009, 0xc8 }, + { 0x5400a, 0x0 }, + { 0x5400b, 0x2 }, + { 0x5400c, 0x0 }, + { 0x5400d, 0x0 }, + { 0x5400e, 0x0 }, + { 0x5400f, 0x0 }, + { 0x54010, 0x0 }, + { 0x54011, 0x0 }, + { 0x54012, 0x310 }, + { 0x54013, 0x0 }, + { 0x54014, 0x0 }, + { 0x54015, 0x0 }, + { 0x54016, 0x0 }, + { 0x54017, 0x0 }, + { 0x54018, 0x0 }, + { 0x54019, 0x914 }, + { 0x5401a, (((LPDDR4_RON) << 3) | 0x1) }, + { 0x5401b, ((LPDDR4_VREF_VALUE_CA << 8) | + (LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ) }, + { 0x5401c, ((LPDDR4_VREF_VALUE_DQ_RANK0 << 8) | 0x08) }, + { 0x5401e, 0x6 }, + { 0x5401f, 0x914 }, + { 0x54020, (((LPDDR4_RON) << 3) | 0x1) }, + { 0x54021, ((LPDDR4_VREF_VALUE_CA << 8) | + (LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ) }, + { 0x54022, ((LPDDR4_VREF_VALUE_DQ_RANK1 << 8) | 0x08) }, + { 0x54023, 0x0 }, + { 0x54024, LPDDR4_MR22_RANK1 }, + { 0x54025, 0x0 }, + { 0x54026, 0x0 }, + { 0x54027, 0x0 }, + { 0x54028, 0x0 }, + { 0x54029, 0x0 }, + { 0x5402a, 0x0 }, + { 0x5402b, 0x1000 }, + { 0x5402c, 0x3 }, + { 0x5402d, 0x0 }, + { 0x5402e, 0x0 }, + { 0x5402f, 0x0 }, + { 0x54030, 0x0 }, + { 0x54031, 0x0 }, + { 0x54032, 0x1400 }, + { 0x54033, ((((LPDDR4_RON) << 3) | 0x1) << 8) | 0x09 }, + { 0x54034, (((LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ) << 8) }, + { 0x54035, (0x0800 | LPDDR4_VREF_VALUE_CA) }, + { 0x54036, LPDDR4_VREF_VALUE_DQ_RANK0 }, + { 0x54037, 0x600 }, + { 0x54038, 0x1400 }, + { 0x54039, ((((LPDDR4_RON) << 3) | 0x1) << 8) | 0x09 }, + { 0x5403a, (((LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ) << 8) }, + { 0x5403b, (0x0800 | LPDDR4_VREF_VALUE_CA) }, + { 0x5403c, LPDDR4_VREF_VALUE_DQ_RANK1 }, + { 0x5403d, (LPDDR4_MR22_RANK1 << 8) }, + { 0x5403e, 0x0 }, + { 0x5403f, 0x0 }, + { 0x54040, 0x0 }, + { 0x54041, 0x0 }, + { 0x54042, 0x0 }, + { 0x54043, 0x0 }, + { 0xd0000, 0x1 }, + +}; + +/* P0 2D message block paremeter for training firmware */ +static struct dram_cfg_param lpddr4_fsp0_2d_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54000, 0x0 }, + { 0x54001, 0x0 }, + { 0x54002, 0x0 }, + { 0x54003, 0xc80 }, + { 0x54004, 0x2 }, + { 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT) }, + { 0x54006, LPDDR4_PHY_VREF_VALUE }, + { 0x54007, 0x0 }, + { 0x54008, 0x61 }, + { 0x54009, LPDDR4_HDT_CTL_2D }, + { 0x5400a, 0x0 }, + { 0x5400b, 0x2 }, + { 0x5400c, 0x0 }, + { 0x5400d, (LPDDR4_CATRAIN_3200_2d << 8) }, + { 0x5400e, 0x0 }, + { 0x5400f, (LPDDR4_2D_SHARE << 8) | 0x00 }, + { 0x54010, LPDDR4_2D_WEIGHT }, + { 0x54011, 0x0 }, + { 0x54012, 0x310 }, + { 0x54013, 0x0 }, + { 0x54014, 0x0 }, + { 0x54015, 0x0 }, + { 0x54016, 0x0 }, + { 0x54017, 0x0 }, + { 0x54018, 0x0 }, + { 0x54024, 0x5 }, + { 0x54019, 0x2dd4 }, + { 0x5401a, (((LPDDR4_RON) << 3) | 0x3) }, + { 0x5401b, ((LPDDR4_VREF_VALUE_CA << 8) | + (LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ) }, + { 0x5401c, ((LPDDR4_VREF_VALUE_DQ_RANK0 << 8) | 0x08) }, + { 0x5401d, 0x0 }, + { 0x5401e, LPDDR4_MR22_RANK0 }, + { 0x5401f, 0x2dd4 }, + { 0x54020, (((LPDDR4_RON) << 3) | 0x3) }, + { 0x54021, ((LPDDR4_VREF_VALUE_CA << 8) | + (LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ) }, + { 0x54022, ((LPDDR4_VREF_VALUE_DQ_RANK1 << 8) | 0x08) }, + { 0x54023, 0x0 }, + { 0x54024, LPDDR4_MR22_RANK1 }, + { 0x54025, 0x0 }, + { 0x54026, 0x0 }, + { 0x54027, 0x0 }, + { 0x54028, 0x0 }, + { 0x54029, 0x0 }, + { 0x5402a, 0x0 }, + { 0x5402b, 0x1000 }, + { 0x5402c, 0x3 }, + { 0x5402d, 0x0 }, + { 0x5402e, 0x0 }, + { 0x5402f, 0x0 }, + { 0x54030, 0x0 }, + { 0x54031, 0x0 }, + { 0x54032, 0xd400 }, + { 0x54033, ((((LPDDR4_RON) << 3) | 0x3) << 8) | 0x2d }, + { 0x54034, (((LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ) << 8) }, + { 0x54035, (0x0800 | LPDDR4_VREF_VALUE_CA) }, + { 0x54036, LPDDR4_VREF_VALUE_DQ_RANK0 }, + { 0x54037, (LPDDR4_MR22_RANK0 << 8) }, + { 0x54038, 0xd400 }, + { 0x54039, ((((LPDDR4_RON) << 3) | 0x3) << 8) | 0x2d }, + { 0x5403a, (((LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ) << 8) }, + { 0x5403b, (0x0800 | LPDDR4_VREF_VALUE_CA) }, + { 0x5403c, LPDDR4_VREF_VALUE_DQ_RANK1 }, + { 0x5403d, (LPDDR4_MR22_RANK1 << 8) }, + { 0x5403e, 0x0 }, + { 0x5403f, 0x0 }, + { 0x54040, 0x0 }, + { 0x54041, 0x0 }, + { 0x54042, 0x0 }, + { 0x54043, 0x0 }, + { 0x54044, 0x0 }, + { 0xd0000, 0x1 }, + +}; + +/* DRAM PHY init engine image */ +static struct dram_cfg_param lpddr4_phy_pie[] = { + { 0xd0000, 0x0 }, + { 0x90000, 0x10 }, + { 0x90001, 0x400 }, + { 0x90002, 0x10e }, + { 0x90003, 0x0 }, + { 0x90004, 0x0 }, + { 0x90005, 0x8 }, + { 0x90029, 0xb }, + { 0x9002a, 0x480 }, + { 0x9002b, 0x109 }, + { 0x9002c, 0x8 }, + { 0x9002d, 0x448 }, + { 0x9002e, 0x139 }, + { 0x9002f, 0x8 }, + { 0x90030, 0x478 }, + { 0x90031, 0x109 }, + { 0x90032, 0x0 }, + { 0x90033, 0xe8 }, + { 0x90034, 0x109 }, + { 0x90035, 0x2 }, + { 0x90036, 0x10 }, + { 0x90037, 0x139 }, + { 0x90038, 0xb }, + { 0x90039, 0x7c0 }, + { 0x9003a, 0x139 }, + { 0x9003b, 0x44 }, + { 0x9003c, 0x630 }, + { 0x9003d, 0x159 }, + { 0x9003e, 0x14f }, + { 0x9003f, 0x630 }, + { 0x90040, 0x159 }, + { 0x90041, 0x47 }, + { 0x90042, 0x630 }, + { 0x90043, 0x149 }, + { 0x90044, 0x4f }, + { 0x90045, 0x630 }, + { 0x90046, 0x179 }, + { 0x90047, 0x8 }, + { 0x90048, 0xe0 }, + { 0x90049, 0x109 }, + { 0x9004a, 0x0 }, + { 0x9004b, 0x7c8 }, + { 0x9004c, 0x109 }, + { 0x9004d, 0x0 }, + { 0x9004e, 0x1 }, + { 0x9004f, 0x8 }, + { 0x90050, 0x0 }, + { 0x90051, 0x45a }, + { 0x90052, 0x9 }, + { 0x90053, 0x0 }, + { 0x90054, 0x448 }, + { 0x90055, 0x109 }, + { 0x90056, 0x40 }, + { 0x90057, 0x630 }, + { 0x90058, 0x179 }, + { 0x90059, 0x1 }, + { 0x9005a, 0x618 }, + { 0x9005b, 0x109 }, + { 0x9005c, 0x40c0 }, + { 0x9005d, 0x630 }, + { 0x9005e, 0x149 }, + { 0x9005f, 0x8 }, + { 0x90060, 0x4 }, + { 0x90061, 0x48 }, + { 0x90062, 0x4040 }, + { 0x90063, 0x630 }, + { 0x90064, 0x149 }, + { 0x90065, 0x0 }, + { 0x90066, 0x4 }, + { 0x90067, 0x48 }, + { 0x90068, 0x40 }, + { 0x90069, 0x630 }, + { 0x9006a, 0x149 }, + { 0x9006b, 0x10 }, + { 0x9006c, 0x4 }, + { 0x9006d, 0x18 }, + { 0x9006e, 0x0 }, + { 0x9006f, 0x4 }, + { 0x90070, 0x78 }, + { 0x90071, 0x549 }, + { 0x90072, 0x630 }, + { 0x90073, 0x159 }, + { 0x90074, 0xd49 }, + { 0x90075, 0x630 }, + { 0x90076, 0x159 }, + { 0x90077, 0x94a }, + { 0x90078, 0x630 }, + { 0x90079, 0x159 }, + { 0x9007a, 0x441 }, + { 0x9007b, 0x630 }, + { 0x9007c, 0x149 }, + { 0x9007d, 0x42 }, + { 0x9007e, 0x630 }, + { 0x9007f, 0x149 }, + { 0x90080, 0x1 }, + { 0x90081, 0x630 }, + { 0x90082, 0x149 }, + { 0x90083, 0x0 }, + { 0x90084, 0xe0 }, + { 0x90085, 0x109 }, + { 0x90086, 0xa }, + { 0x90087, 0x10 }, + { 0x90088, 0x109 }, + { 0x90089, 0x9 }, + { 0x9008a, 0x3c0 }, + { 0x9008b, 0x149 }, + { 0x9008c, 0x9 }, + { 0x9008d, 0x3c0 }, + { 0x9008e, 0x159 }, + { 0x9008f, 0x18 }, + { 0x90090, 0x10 }, + { 0x90091, 0x109 }, + { 0x90092, 0x0 }, + { 0x90093, 0x3c0 }, + { 0x90094, 0x109 }, + { 0x90095, 0x18 }, + { 0x90096, 0x4 }, + { 0x90097, 0x48 }, + { 0x90098, 0x18 }, + { 0x90099, 0x4 }, + { 0x9009a, 0x58 }, + { 0x9009b, 0xa }, + { 0x9009c, 0x10 }, + { 0x9009d, 0x109 }, + { 0x9009e, 0x2 }, + { 0x9009f, 0x10 }, + { 0x900a0, 0x109 }, + { 0x900a1, 0x5 }, + { 0x900a2, 0x7c0 }, + { 0x900a3, 0x109 }, + { 0x900a4, 0xd }, + { 0x900a5, 0x7c0 }, + { 0x900a6, 0x109 }, + { 0x900a7, 0x4 }, + { 0x900a8, 0x7c0 }, + { 0x900a9, 0x109 }, + { 0x40000, 0x811 }, + { 0x40020, 0x880 }, + { 0x40040, 0x0 }, + { 0x40060, 0x0 }, + { 0x40001, 0x4008 }, + { 0x40021, 0x83 }, + { 0x40041, 0x4f }, + { 0x40061, 0x0 }, + { 0x40002, 0x4040 }, + { 0x40022, 0x83 }, + { 0x40042, 0x51 }, + { 0x40062, 0x0 }, + { 0x40003, 0x811 }, + { 0x40023, 0x880 }, + { 0x40043, 0x0 }, + { 0x40063, 0x0 }, + { 0x40004, 0x720 }, + { 0x40024, 0xf }, + { 0x40044, 0x1740 }, + { 0x40064, 0x0 }, + { 0x40005, 0x16 }, + { 0x40025, 0x83 }, + { 0x40045, 0x4b }, + { 0x40065, 0x0 }, + { 0x40006, 0x716 }, + { 0x40026, 0xf }, + { 0x40046, 0x2001 }, + { 0x40066, 0x0 }, + { 0x40007, 0x716 }, + { 0x40027, 0xf }, + { 0x40047, 0x2800 }, + { 0x40067, 0x0 }, + { 0x40008, 0x716 }, + { 0x40028, 0xf }, + { 0x40048, 0xf00 }, + { 0x40068, 0x0 }, + { 0x40009, 0x720 }, + { 0x40029, 0xf }, + { 0x40049, 0x1400 }, + { 0x40069, 0x0 }, + { 0x4000a, 0xe08 }, + { 0x4002a, 0xc15 }, + { 0x4004a, 0x0 }, + { 0x4006a, 0x0 }, + { 0x4000b, 0x623 }, + { 0x4002b, 0x15 }, + { 0x4004b, 0x0 }, + { 0x4006b, 0x0 }, + { 0x4000c, 0x4028 }, + { 0x4002c, 0x80 }, + { 0x4004c, 0x0 }, + { 0x4006c, 0x0 }, + { 0x4000d, 0xe08 }, + { 0x4002d, 0xc1a }, + { 0x4004d, 0x0 }, + { 0x4006d, 0x0 }, + { 0x4000e, 0x623 }, + { 0x4002e, 0x1a }, + { 0x4004e, 0x0 }, + { 0x4006e, 0x0 }, + { 0x4000f, 0x4040 }, + { 0x4002f, 0x80 }, + { 0x4004f, 0x0 }, + { 0x4006f, 0x0 }, + { 0x40010, 0x2604 }, + { 0x40030, 0x15 }, + { 0x40050, 0x0 }, + { 0x40070, 0x0 }, + { 0x40011, 0x708 }, + { 0x40031, 0x5 }, + { 0x40051, 0x0 }, + { 0x40071, 0x2002 }, + { 0x40012, 0x8 }, + { 0x40032, 0x80 }, + { 0x40052, 0x0 }, + { 0x40072, 0x0 }, + { 0x40013, 0x2604 }, + { 0x40033, 0x1a }, + { 0x40053, 0x0 }, + { 0x40073, 0x0 }, + { 0x40014, 0x708 }, + { 0x40034, 0xa }, + { 0x40054, 0x0 }, + { 0x40074, 0x2002 }, + { 0x40015, 0x4040 }, + { 0x40035, 0x80 }, + { 0x40055, 0x0 }, + { 0x40075, 0x0 }, + { 0x40016, 0x60a }, + { 0x40036, 0x15 }, + { 0x40056, 0x1200 }, + { 0x40076, 0x0 }, + { 0x40017, 0x61a }, + { 0x40037, 0x15 }, + { 0x40057, 0x1300 }, + { 0x40077, 0x0 }, + { 0x40018, 0x60a }, + { 0x40038, 0x1a }, + { 0x40058, 0x1200 }, + { 0x40078, 0x0 }, + { 0x40019, 0x642 }, + { 0x40039, 0x1a }, + { 0x40059, 0x1300 }, + { 0x40079, 0x0 }, + { 0x4001a, 0x4808 }, + { 0x4003a, 0x880 }, + { 0x4005a, 0x0 }, + { 0x4007a, 0x0 }, + { 0x900aa, 0x0 }, + { 0x900ab, 0x790 }, + { 0x900ac, 0x11a }, + { 0x900ad, 0x8 }, + { 0x900ae, 0x7aa }, + { 0x900af, 0x2a }, + { 0x900b0, 0x10 }, + { 0x900b1, 0x7b2 }, + { 0x900b2, 0x2a }, + { 0x900b3, 0x0 }, + { 0x900b4, 0x7c8 }, + { 0x900b5, 0x109 }, + { 0x900b6, 0x10 }, + { 0x900b7, 0x10 }, + { 0x900b8, 0x109 }, + { 0x900b9, 0x10 }, + { 0x900ba, 0x2a8 }, + { 0x900bb, 0x129 }, + { 0x900bc, 0x8 }, + { 0x900bd, 0x370 }, + { 0x900be, 0x129 }, + { 0x900bf, 0xa }, + { 0x900c0, 0x3c8 }, + { 0x900c1, 0x1a9 }, + { 0x900c2, 0xc }, + { 0x900c3, 0x408 }, + { 0x900c4, 0x199 }, + { 0x900c5, 0x14 }, + { 0x900c6, 0x790 }, + { 0x900c7, 0x11a }, + { 0x900c8, 0x8 }, + { 0x900c9, 0x4 }, + { 0x900ca, 0x18 }, + { 0x900cb, 0xe }, + { 0x900cc, 0x408 }, + { 0x900cd, 0x199 }, + { 0x900ce, 0x8 }, + { 0x900cf, 0x8568 }, + { 0x900d0, 0x108 }, + { 0x900d1, 0x18 }, + { 0x900d2, 0x790 }, + { 0x900d3, 0x16a }, + { 0x900d4, 0x8 }, + { 0x900d5, 0x1d8 }, + { 0x900d6, 0x169 }, + { 0x900d7, 0x10 }, + { 0x900d8, 0x8558 }, + { 0x900d9, 0x168 }, + { 0x900da, 0x70 }, + { 0x900db, 0x788 }, + { 0x900dc, 0x16a }, + { 0x900dd, 0x1ff8 }, + { 0x900de, 0x85a8 }, + { 0x900df, 0x1e8 }, + { 0x900e0, 0x50 }, + { 0x900e1, 0x798 }, + { 0x900e2, 0x16a }, + { 0x900e3, 0x60 }, + { 0x900e4, 0x7a0 }, + { 0x900e5, 0x16a }, + { 0x900e6, 0x8 }, + { 0x900e7, 0x8310 }, + { 0x900e8, 0x168 }, + { 0x900e9, 0x8 }, + { 0x900ea, 0xa310 }, + { 0x900eb, 0x168 }, + { 0x900ec, 0xa }, + { 0x900ed, 0x408 }, + { 0x900ee, 0x169 }, + { 0x900ef, 0x6e }, + { 0x900f0, 0x0 }, + { 0x900f1, 0x68 }, + { 0x900f2, 0x0 }, + { 0x900f3, 0x408 }, + { 0x900f4, 0x169 }, + { 0x900f5, 0x0 }, + { 0x900f6, 0x8310 }, + { 0x900f7, 0x168 }, + { 0x900f8, 0x0 }, + { 0x900f9, 0xa310 }, + { 0x900fa, 0x168 }, + { 0x900fb, 0x1ff8 }, + { 0x900fc, 0x85a8 }, + { 0x900fd, 0x1e8 }, + { 0x900fe, 0x68 }, + { 0x900ff, 0x798 }, + { 0x90100, 0x16a }, + { 0x90101, 0x78 }, + { 0x90102, 0x7a0 }, + { 0x90103, 0x16a }, + { 0x90104, 0x68 }, + { 0x90105, 0x790 }, + { 0x90106, 0x16a }, + { 0x90107, 0x8 }, + { 0x90108, 0x8b10 }, + { 0x90109, 0x168 }, + { 0x9010a, 0x8 }, + { 0x9010b, 0xab10 }, + { 0x9010c, 0x168 }, + { 0x9010d, 0xa }, + { 0x9010e, 0x408 }, + { 0x9010f, 0x169 }, + { 0x90110, 0x58 }, + { 0x90111, 0x0 }, + { 0x90112, 0x68 }, + { 0x90113, 0x0 }, + { 0x90114, 0x408 }, + { 0x90115, 0x169 }, + { 0x90116, 0x0 }, + { 0x90117, 0x8b10 }, + { 0x90118, 0x168 }, + { 0x90119, 0x0 }, + { 0x9011a, 0xab10 }, + { 0x9011b, 0x168 }, + { 0x9011c, 0x0 }, + { 0x9011d, 0x1d8 }, + { 0x9011e, 0x169 }, + { 0x9011f, 0x80 }, + { 0x90120, 0x790 }, + { 0x90121, 0x16a }, + { 0x90122, 0x18 }, + { 0x90123, 0x7aa }, + { 0x90124, 0x6a }, + { 0x90125, 0xa }, + { 0x90126, 0x0 }, + { 0x90127, 0x1e9 }, + { 0x90128, 0x8 }, + { 0x90129, 0x8080 }, + { 0x9012a, 0x108 }, + { 0x9012b, 0xf }, + { 0x9012c, 0x408 }, + { 0x9012d, 0x169 }, + { 0x9012e, 0xc }, + { 0x9012f, 0x0 }, + { 0x90130, 0x68 }, + { 0x90131, 0x9 }, + { 0x90132, 0x0 }, + { 0x90133, 0x1a9 }, + { 0x90134, 0x0 }, + { 0x90135, 0x408 }, + { 0x90136, 0x169 }, + { 0x90137, 0x0 }, + { 0x90138, 0x8080 }, + { 0x90139, 0x108 }, + { 0x9013a, 0x8 }, + { 0x9013b, 0x7aa }, + { 0x9013c, 0x6a }, + { 0x9013d, 0x0 }, + { 0x9013e, 0x8568 }, + { 0x9013f, 0x108 }, + { 0x90140, 0xb7 }, + { 0x90141, 0x790 }, + { 0x90142, 0x16a }, + { 0x90143, 0x1f }, + { 0x90144, 0x0 }, + { 0x90145, 0x68 }, + { 0x90146, 0x8 }, + { 0x90147, 0x8558 }, + { 0x90148, 0x168 }, + { 0x90149, 0xf }, + { 0x9014a, 0x408 }, + { 0x9014b, 0x169 }, + { 0x9014c, 0xc }, + { 0x9014d, 0x0 }, + { 0x9014e, 0x68 }, + { 0x9014f, 0x0 }, + { 0x90150, 0x408 }, + { 0x90151, 0x169 }, + { 0x90152, 0x0 }, + { 0x90153, 0x8558 }, + { 0x90154, 0x168 }, + { 0x90155, 0x8 }, + { 0x90156, 0x3c8 }, + { 0x90157, 0x1a9 }, + { 0x90158, 0x3 }, + { 0x90159, 0x370 }, + { 0x9015a, 0x129 }, + { 0x9015b, 0x20 }, + { 0x9015c, 0x2aa }, + { 0x9015d, 0x9 }, + { 0x9015e, 0x0 }, + { 0x9015f, 0x400 }, + { 0x90160, 0x10e }, + { 0x90161, 0x8 }, + { 0x90162, 0xe8 }, + { 0x90163, 0x109 }, + { 0x90164, 0x0 }, + { 0x90165, 0x8140 }, + { 0x90166, 0x10c }, + { 0x90167, 0x10 }, + { 0x90168, 0x8138 }, + { 0x90169, 0x10c }, + { 0x9016a, 0x8 }, + { 0x9016b, 0x7c8 }, + { 0x9016c, 0x101 }, + { 0x9016d, 0x8 }, + { 0x9016e, 0x0 }, + { 0x9016f, 0x8 }, + { 0x90170, 0x8 }, + { 0x90171, 0x448 }, + { 0x90172, 0x109 }, + { 0x90173, 0xf }, + { 0x90174, 0x7c0 }, + { 0x90175, 0x109 }, + { 0x90176, 0x0 }, + { 0x90177, 0xe8 }, + { 0x90178, 0x109 }, + { 0x90179, 0x47 }, + { 0x9017a, 0x630 }, + { 0x9017b, 0x109 }, + { 0x9017c, 0x8 }, + { 0x9017d, 0x618 }, + { 0x9017e, 0x109 }, + { 0x9017f, 0x8 }, + { 0x90180, 0xe0 }, + { 0x90181, 0x109 }, + { 0x90182, 0x0 }, + { 0x90183, 0x7c8 }, + { 0x90184, 0x109 }, + { 0x90185, 0x8 }, + { 0x90186, 0x8140 }, + { 0x90187, 0x10c }, + { 0x90188, 0x0 }, + { 0x90189, 0x1 }, + { 0x9018a, 0x8 }, + { 0x9018b, 0x8 }, + { 0x9018c, 0x4 }, + { 0x9018d, 0x8 }, + { 0x9018e, 0x8 }, + { 0x9018f, 0x7c8 }, + { 0x90190, 0x101 }, + { 0x90006, 0x0 }, + { 0x90007, 0x0 }, + { 0x90008, 0x8 }, + { 0x90009, 0x0 }, + { 0x9000a, 0x0 }, + { 0x9000b, 0x0 }, + { 0xd00e7, 0x400 }, + { 0x90017, 0x0 }, + { 0x9001f, 0x2b }, + { 0x90026, 0x6c }, + { 0x400d0, 0x0 }, + { 0x400d1, 0x101 }, + { 0x400d2, 0x105 }, + { 0x400d3, 0x107 }, + { 0x400d4, 0x10f }, + { 0x400d5, 0x202 }, + { 0x400d6, 0x20a }, + { 0x400d7, 0x20b }, + { 0x2003a, 0x2 }, + { 0x2000b, 0x64 }, + { 0x2000c, 0xc8 }, + { 0x2000d, 0x7d0 }, + { 0x2000e, 0x2c }, + { 0x12000b, 0x14 }, + { 0x12000c, 0x29 }, + { 0x12000d, 0x1a1 }, + { 0x12000e, 0x10 }, + { 0x22000b, 0x3 }, + { 0x22000c, 0x6 }, + { 0x22000d, 0x3e }, + { 0x22000e, 0x10 }, + { 0x9000c, 0x0 }, + { 0x9000d, 0x173 }, + { 0x9000e, 0x60 }, + { 0x9000f, 0x6110 }, + { 0x90010, 0x2152 }, + { 0x90011, 0xdfbd }, + { 0x90012, 0x60 }, + { 0x90013, 0x6152 }, + { 0x20010, 0x5a }, + { 0x20011, 0x3 }, + { 0x40080, 0xe0 }, + { 0x40081, 0x12 }, + { 0x40082, 0xe0 }, + { 0x40083, 0x12 }, + { 0x40084, 0xe0 }, + { 0x40085, 0x12 }, + { 0x140080, 0xe0 }, + { 0x140081, 0x12 }, + { 0x140082, 0xe0 }, + { 0x140083, 0x12 }, + { 0x140084, 0xe0 }, + { 0x140085, 0x12 }, + { 0x240080, 0xe0 }, + { 0x240081, 0x12 }, + { 0x240082, 0xe0 }, + { 0x240083, 0x12 }, + { 0x240084, 0xe0 }, + { 0x240085, 0x12 }, + { 0x400fd, 0xf }, + { 0x10011, 0x1 }, + { 0x10012, 0x1 }, + { 0x10013, 0x180 }, + { 0x10018, 0x1 }, + { 0x10002, 0x6209 }, + { 0x100b2, 0x1 }, + { 0x101b4, 0x1 }, + { 0x102b4, 0x1 }, + { 0x103b4, 0x1 }, + { 0x104b4, 0x1 }, + { 0x105b4, 0x1 }, + { 0x106b4, 0x1 }, + { 0x107b4, 0x1 }, + { 0x108b4, 0x1 }, + { 0x11011, 0x1 }, + { 0x11012, 0x1 }, + { 0x11013, 0x180 }, + { 0x11018, 0x1 }, + { 0x11002, 0x6209 }, + { 0x110b2, 0x1 }, + { 0x111b4, 0x1 }, + { 0x112b4, 0x1 }, + { 0x113b4, 0x1 }, + { 0x114b4, 0x1 }, + { 0x115b4, 0x1 }, + { 0x116b4, 0x1 }, + { 0x117b4, 0x1 }, + { 0x118b4, 0x1 }, + { 0x12011, 0x1 }, + { 0x12012, 0x1 }, + { 0x12013, 0x180 }, + { 0x12018, 0x1 }, + { 0x12002, 0x6209 }, + { 0x120b2, 0x1 }, + { 0x121b4, 0x1 }, + { 0x122b4, 0x1 }, + { 0x123b4, 0x1 }, + { 0x124b4, 0x1 }, + { 0x125b4, 0x1 }, + { 0x126b4, 0x1 }, + { 0x127b4, 0x1 }, + { 0x128b4, 0x1 }, + { 0x13011, 0x1 }, + { 0x13012, 0x1 }, + { 0x13013, 0x180 }, + { 0x13018, 0x1 }, + { 0x13002, 0x6209 }, + { 0x130b2, 0x1 }, + { 0x131b4, 0x1 }, + { 0x132b4, 0x1 }, + { 0x133b4, 0x1 }, + { 0x134b4, 0x1 }, + { 0x135b4, 0x1 }, + { 0x136b4, 0x1 }, + { 0x137b4, 0x1 }, + { 0x138b4, 0x1 }, + { 0x20089, 0x1 }, + { 0x20088, 0x19 }, + { 0xc0080, 0x2 }, + { 0xd0000, 0x1 }, +}; + +static struct dram_fsp_msg lpddr4_dram_fsp_msg[] = { + { + /* P0 3200mts 1D */ + .drate = 3200, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = lpddr4_fsp0_cfg, + .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp0_cfg), + }, + { + /* P1 667mts 1D */ + .drate = 667, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = lpddr4_fsp1_cfg, + .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp1_cfg), + }, + { + /* P0 3200mts 2D */ + .drate = 3200, + .fw_type = FW_2D_IMAGE, + .fsp_cfg = lpddr4_fsp0_2d_cfg, + .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp0_2d_cfg), + }, +}; + +/* lpddr4 timing config params on EVK board */ +struct dram_timing_info dram_timing_b0 = { + .ddrc_cfg = lpddr4_ddrc_cfg, + .ddrc_cfg_num = ARRAY_SIZE(lpddr4_ddrc_cfg), + .ddrphy_cfg = lpddr4_ddrphy_cfg, + .ddrphy_cfg_num = ARRAY_SIZE(lpddr4_ddrphy_cfg), + .fsp_msg = lpddr4_dram_fsp_msg, + .fsp_msg_num = ARRAY_SIZE(lpddr4_dram_fsp_msg), + .ddrphy_pie = lpddr4_phy_pie, + .ddrphy_pie_num = ARRAY_SIZE(lpddr4_phy_pie), + /* + * this table must be initialized if DDRPHY bypass mode is + * not used: all fsp drate > 666MTS. + */ + .fsp_table = { 3200, 667, }, +}; diff --git a/board/purism/librem5/spl.c b/board/purism/librem5/spl.c new file mode 100644 index 0000000000..a068f76460 --- /dev/null +++ b/board/purism/librem5/spl.c @@ -0,0 +1,592 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 NXP + * Copyright 2021 Purism + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "librem5.h" + +DECLARE_GLOBAL_DATA_PTR; + +void spl_dram_init(void) +{ + /* ddr init */ + if ((get_cpu_rev() & 0xfff) == CHIP_REV_2_1) + ddr_init(&dram_timing); + else + ddr_init(&dram_timing_b0); +} + +int spl_board_boot_device(enum boot_device boot_dev_spl) +{ + log_debug("%s : starting\n", __func__); + + switch (boot_dev_spl) { + case SD1_BOOT: + case MMC1_BOOT: + return BOOT_DEVICE_MMC1; + case USB_BOOT: + return BOOT_DEVICE_BOARD; + default: + return BOOT_DEVICE_NONE; + } +} + +#define ECSPI_PAD_CTRL (PAD_CTL_DSE2 | PAD_CTL_HYS) + +static const iomux_v3_cfg_t ecspi_pads[] = { + IMX8MQ_PAD_ECSPI1_SCLK__ECSPI1_SCLK | MUX_PAD_CTRL(ECSPI_PAD_CTRL), + IMX8MQ_PAD_ECSPI1_SS0__GPIO5_IO9 | MUX_PAD_CTRL(ECSPI_PAD_CTRL), + IMX8MQ_PAD_ECSPI1_MOSI__ECSPI1_MOSI | MUX_PAD_CTRL(ECSPI_PAD_CTRL), + IMX8MQ_PAD_ECSPI1_MISO__ECSPI1_MISO | MUX_PAD_CTRL(ECSPI_PAD_CTRL), +}; + +int board_ecspi_init(void) +{ + imx_iomux_v3_setup_multiple_pads(ecspi_pads, ARRAY_SIZE(ecspi_pads)); + + return 0; +} + +int board_spi_cs_gpio(unsigned int bus, unsigned int cs) +{ + return (bus == 0 && cs == 0) ? (SPI1_SS0) : -1; +} + +#define I2C_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_ODE | PAD_CTL_DSE7 | PAD_CTL_FSEL3) +#define PC MUX_PAD_CTRL(I2C_PAD_CTRL) +struct i2c_pads_info i2c_pad_info1 = { + .scl = { + .i2c_mode = IMX8MQ_PAD_I2C1_SCL__I2C1_SCL | PC, + .gpio_mode = IMX8MQ_PAD_I2C1_SCL__GPIO5_IO14 | PC, + .gp = IMX_GPIO_NR(5, 14), + }, + .sda = { + .i2c_mode = IMX8MQ_PAD_I2C1_SDA__I2C1_SDA | PC, + .gpio_mode = IMX8MQ_PAD_I2C1_SDA__GPIO5_IO15 | PC, + .gp = IMX_GPIO_NR(5, 15), + }, +}; + +struct i2c_pads_info i2c_pad_info2 = { + .scl = { + .i2c_mode = IMX8MQ_PAD_I2C2_SCL__I2C2_SCL | PC, + .gpio_mode = IMX8MQ_PAD_I2C2_SCL__GPIO5_IO16 | PC, + .gp = IMX_GPIO_NR(5, 16), + }, + .sda = { + .i2c_mode = IMX8MQ_PAD_I2C2_SDA__I2C2_SDA | PC, + .gpio_mode = IMX8MQ_PAD_I2C2_SDA__GPIO5_IO17 | PC, + .gp = IMX_GPIO_NR(5, 17), + }, +}; + +struct i2c_pads_info i2c_pad_info3 = { + .scl = { + .i2c_mode = IMX8MQ_PAD_I2C3_SCL__I2C3_SCL | PC, + .gpio_mode = IMX8MQ_PAD_I2C3_SCL__GPIO5_IO18 | PC, + .gp = IMX_GPIO_NR(5, 18), + }, + .sda = { + .i2c_mode = IMX8MQ_PAD_I2C3_SDA__I2C3_SDA | PC, + .gpio_mode = IMX8MQ_PAD_I2C3_SDA__GPIO5_IO19 | PC, + .gp = IMX_GPIO_NR(5, 19), + }, +}; + +struct i2c_pads_info i2c_pad_info4 = { + .scl = { + .i2c_mode = IMX8MQ_PAD_I2C4_SCL__I2C4_SCL | PC, + .gpio_mode = IMX8MQ_PAD_I2C4_SCL__GPIO5_IO20 | PC, + .gp = IMX_GPIO_NR(5, 20), + }, + .sda = { + .i2c_mode = IMX8MQ_PAD_I2C4_SDA__I2C4_SDA | PC, + .gpio_mode = IMX8MQ_PAD_I2C4_SDA__GPIO5_IO21 | PC, + .gp = IMX_GPIO_NR(5, 21), + }, +}; + +#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1) + +static const iomux_v3_cfg_t uart_pads[] = { + IMX8MQ_PAD_UART1_RXD__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL), + IMX8MQ_PAD_UART1_TXD__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL), + IMX8MQ_PAD_UART2_RXD__UART2_RX | MUX_PAD_CTRL(UART_PAD_CTRL), + IMX8MQ_PAD_UART2_TXD__UART2_TX | MUX_PAD_CTRL(UART_PAD_CTRL), + IMX8MQ_PAD_UART3_RXD__UART3_RX | MUX_PAD_CTRL(UART_PAD_CTRL), + IMX8MQ_PAD_UART3_TXD__UART3_TX | MUX_PAD_CTRL(UART_PAD_CTRL), + IMX8MQ_PAD_ECSPI2_SCLK__UART4_RX | MUX_PAD_CTRL(UART_PAD_CTRL), + IMX8MQ_PAD_ECSPI2_MOSI__UART4_TX | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +#define USDHC1_PWR_GPIO IMX_GPIO_NR(2, 10) +#define USDHC2_PWR_GPIO IMX_GPIO_NR(2, 19) + +int board_mmc_getcd(struct mmc *mmc) +{ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + int ret = 0; + + switch (cfg->esdhc_base) { + case USDHC1_BASE_ADDR: + ret = 1; + break; + case USDHC2_BASE_ADDR: + ret = 1; + break; + } + + return ret; +} + +#define USDHC_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | \ + PAD_CTL_FSEL1) +#define USDHC_GPIO_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_DSE1) + +static const iomux_v3_cfg_t usdhc1_pads[] = { + IMX8MQ_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MQ_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MQ_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MQ_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MQ_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MQ_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MQ_PAD_SD1_DATA4__USDHC1_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MQ_PAD_SD1_DATA5__USDHC1_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MQ_PAD_SD1_DATA6__USDHC1_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MQ_PAD_SD1_DATA7__USDHC1_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MQ_PAD_SD1_RESET_B__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static const iomux_v3_cfg_t usdhc2_pads[] = { + IMX8MQ_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */ + IMX8MQ_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */ + IMX8MQ_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */ + IMX8MQ_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */ + IMX8MQ_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0x16 */ + IMX8MQ_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */ + IMX8MQ_PAD_SD2_RESET_B__GPIO2_IO19 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL), +}; + +static struct fsl_esdhc_cfg usdhc_cfg[2] = { + {USDHC1_BASE_ADDR, 0, 8}, + {USDHC2_BASE_ADDR, 0, 4}, +}; + +int board_mmc_init(struct bd_info *bis) +{ + int i, ret; + /* + * According to the board_mmc_init() the following map is done: + * (U-Boot device node) (Physical Port) + * mmc0 USDHC1 + * mmc1 USDHC2 + */ + for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { + log_debug("Initializing FSL USDHC port %d\n", i); + switch (i) { + case 0: + init_clk_usdhc(0); + usdhc_cfg[0].sdhc_clk = mxc_get_clock(USDHC1_CLK_ROOT); + imx_iomux_v3_setup_multiple_pads(usdhc1_pads, + ARRAY_SIZE(usdhc1_pads)); + gpio_request(USDHC1_PWR_GPIO, "usdhc1_reset"); + gpio_direction_output(USDHC1_PWR_GPIO, 0); + udelay(500); + gpio_direction_output(USDHC1_PWR_GPIO, 1); + break; + case 1: + init_clk_usdhc(1); + usdhc_cfg[1].sdhc_clk = mxc_get_clock(USDHC2_CLK_ROOT); + imx_iomux_v3_setup_multiple_pads(usdhc2_pads, + ARRAY_SIZE(usdhc2_pads)); + gpio_request(USDHC2_PWR_GPIO, "usdhc2_reset"); + gpio_direction_output(USDHC2_PWR_GPIO, 0); + udelay(500); + gpio_direction_output(USDHC2_PWR_GPIO, 1); + break; + default: + log_err("Warning: USDHC controller(%d) not supported\n", i + 1); + return -EINVAL; + } + + ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); + if (ret) + return ret; + } + + return 0; +} + +#define LDO_VOLT_EN BIT(6) + +/* + * Disable the charger - it will be re-enabled in u-boot + */ +void disable_charger_bq25895(void) +{ + u8 val; + int timeout = 1000; // ms + + /* Set the i2c bus */ + i2c_set_bus_num(3); + + /* disable ship mode if BATFET_DLY is set */ + val = i2c_reg_read(0x6a, 0x09); + log_debug("REG09 0x%x\n", val); + if (val & 0x28) { + val = val & ~0x28; + i2c_reg_write(0x6a, 0x09, val); + } + + /* disable and trigger DPDM, ICO, HVDCP and MaxCharge */ + val = i2c_reg_read(0x6a, 0x02); + log_debug("REG02 0x%x\n", val); + val &= 0xe0; + i2c_reg_write(0x6a, 0x02, val); + + /* disable charger and enable BAT_LOADEN */ + val = i2c_reg_read(0x6a, 0x03); + log_debug("REG03 0x%x\n", val); + val = (val | 0x80) & ~0x10; + i2c_reg_write(0x6a, 0x03, val); + + mdelay(10); + + /* force ADC conversions */ + val = i2c_reg_read(0x6a, 0x02); + log_debug("REG02 0x%x\n", val); + val = (val | 0x80) & ~0x40; + i2c_reg_write(0x6a, 0x02, val); + + do { + mdelay(10); + timeout -= 10; + } while ((i2c_reg_read(0x6a, 0x02) & 0x80) && (timeout > 0)); + + /* enable STAT pin */ + val = i2c_reg_read(0x6a, 0x07); + log_debug("REG07 0x%x\n", val); + val = val & ~0x40; + i2c_reg_write(0x6a, 0x07, val); + + /* check VBUS */ + val = i2c_reg_read(0x6a, 0x11); + log_debug("VBUS good %d\n", (val >> 7) & 1); + log_debug("VBUS mV %d\n", (val & 0x7f) * 100 + 2600); + + /* check VBAT */ + val = i2c_reg_read(0x6a, 0x0e); + log_debug("VBAT mV %d\n", (val & 0x7f) * 20 + 2304); + + /* limit the VINDPM to 3.9V */ + i2c_reg_write(0x6a, 0x0d, 0x8d); + + /* set the max voltage to 4.192V */ + val = i2c_reg_read(0x6a, 0x6); + val = (val & ~0xFC) | 0x16 << 2; + i2c_reg_write(0x6a, 0x6, val); + + /* set the SYS_MIN to 3.7V */ + val = i2c_reg_read(0x6a, 0x3); + val = val | 0xE; + i2c_reg_write(0x6a, 0x3, val); + + /* disable BAT_LOADEN */ + val = i2c_reg_read(0x6a, 0x03); + log_debug("REG03 0x%x\n", val); + val = val & ~0x80; + i2c_reg_write(0x6a, 0x03, val); +} + +#define I2C_PMIC 0 + +int power_bd71837_init(unsigned char bus) +{ + static const char name[] = BD718XX_REGULATOR_DRIVER; + struct pmic *p = pmic_alloc(); + + if (!p) { + log_err("%s: POWER allocation error!\n", __func__); + return -ENOMEM; + } + + p->name = name; + p->interface = I2C_PMIC; + p->number_of_regs = BD718XX_MAX_REGISTER; + p->hw.i2c.addr = CONFIG_POWER_BD71837_I2C_ADDR; + p->hw.i2c.tx_num = 1; + p->bus = bus; + + return 0; +} + +int power_init_board(void) +{ + struct pmic *p; + int ldo[] = {BD718XX_LDO5_VOLT, BD718XX_LDO6_VOLT, + BD71837_LDO7_VOLT}; + u32 val; + int i, rv; + + /* Set the i2c bus */ + setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); + + /* + * Init PMIC + */ + rv = power_bd71837_init(CONFIG_POWER_BD71837_I2C_BUS); + if (rv) { + log_err("%s: power_bd71837_init(%d) error %d\n", __func__, + CONFIG_POWER_BD71837_I2C_BUS, rv); + goto out; + } + + p = pmic_get(BD718XX_REGULATOR_DRIVER); + if (!p) { + log_err("%s: pmic_get(%s) failed\n", __func__, BD718XX_REGULATOR_DRIVER); + rv = -ENODEV; + goto out; + } + + rv = pmic_probe(p); + if (rv) { + log_err("%s: pmic_probe() error %d\n", __func__, rv); + goto out; + } + + /* + * Unlock all regs + */ + pmic_reg_write(p, BD718XX_REGLOCK, 0); + + /* find the reset cause */ + pmic_reg_read(p, 0x29, &val); + log_debug("%s: reset cause %d\n", __func__, val); + + /* + * Reconfigure default voltages and disable: + * - BUCK3: VDD_GPU_0V9 (1.00 -> 0.90) + * - BUCK4: VDD_VPU_0V9 (1.00 -> 0.90) + */ + pmic_reg_write(p, BD71837_BUCK3_VOLT_RUN, 0x14); + pmic_reg_write(p, BD71837_BUCK4_VOLT_RUN, 0x14); + + /* + * Enable PHYs voltages: LDO5-7 + */ + for (i = 0; i < ARRAY_SIZE(ldo); i++) { + rv = pmic_reg_read(p, ldo[i], &val); + if (rv) { + log_err("%s: pmic_read(%x) error %d\n", __func__, + ldo[i], rv); + continue; + } + + pmic_reg_write(p, ldo[i], val | LDO_VOLT_EN); + } + + udelay(500); + + rv = 0; +out: + return rv; +} + +int usb_gadget_handle_interrupts(void) +{ + dwc3_uboot_handle_interrupt(0); + return 0; +} + +static void dwc3_nxp_usb_phy_init(struct dwc3_device *dwc3) +{ + u32 RegData; + + RegData = readl(dwc3->base + USB_PHY_CTRL1); + RegData &= ~(USB_PHY_CTRL1_VDATSRCENB0 | USB_PHY_CTRL1_VDATDETENB0 | + USB_PHY_CTRL1_COMMONONN); + RegData |= USB_PHY_CTRL1_RESET | USB_PHY_CTRL1_ATERESET; + writel(RegData, dwc3->base + USB_PHY_CTRL1); + + RegData = readl(dwc3->base + USB_PHY_CTRL0); + RegData |= USB_PHY_CTRL0_REF_SSP_EN; + RegData &= ~USB_PHY_CTRL0_SSC_RANGE_MASK; + RegData |= USB_PHY_CTRL0_SSC_RANGE_4003PPM; + writel(RegData, dwc3->base + USB_PHY_CTRL0); + + RegData = readl(dwc3->base + USB_PHY_CTRL2); + RegData |= USB_PHY_CTRL2_TXENABLEN0; + writel(RegData, dwc3->base + USB_PHY_CTRL2); + + RegData = readl(dwc3->base + USB_PHY_CTRL1); + RegData &= ~(USB_PHY_CTRL1_RESET | USB_PHY_CTRL1_ATERESET); + writel(RegData, dwc3->base + USB_PHY_CTRL1); + + /* Disable rx term override */ + RegData = readl(dwc3->base + USB_PHY_CTRL6); + RegData &= ~USB_PHY_CTRL6_RXTERM_OVERRIDE_SEL; + writel(RegData, dwc3->base + USB_PHY_CTRL6); +} + +static struct dwc3_device dwc3_device0_data = { + .maximum_speed = USB_SPEED_HIGH, + .base = USB1_BASE_ADDR, + .dr_mode = USB_DR_MODE_PERIPHERAL, + .index = 0, +}; + +static struct dwc3_device dwc3_device1_data = { + .maximum_speed = USB_SPEED_HIGH, + .base = USB2_BASE_ADDR, + .dr_mode = USB_DR_MODE_HOST, + .index = 1, +}; + +int board_usb_init(int index, enum usb_init_type init) +{ + int ret = 0; + + printf("%s : index %d type %d\n", __func__, index, init); + + if (index == 0 && init == USB_INIT_DEVICE) { + dwc3_nxp_usb_phy_init(&dwc3_device0_data); + ret = dwc3_uboot_init(&dwc3_device0_data); + } + if (index == 1 && init == USB_INIT_HOST) { + dwc3_nxp_usb_phy_init(&dwc3_device1_data); + ret = dwc3_uboot_init(&dwc3_device1_data); + } + + return ret; +} + +int board_usb_cleanup(int index, enum usb_init_type init) +{ + u32 RegData; + struct dwc3_device *dwc3; + + printf("%s : %d\n", __func__, index); + + if (index == 0 && init == USB_INIT_DEVICE) + dwc3 = &dwc3_device0_data; + if (index == 1 && init == USB_INIT_HOST) + dwc3 = &dwc3_device1_data; + + dwc3_uboot_exit(index); + + /* reset the phy */ + RegData = readl(dwc3->base + USB_PHY_CTRL1); + RegData &= ~(USB_PHY_CTRL1_VDATSRCENB0 | USB_PHY_CTRL1_VDATDETENB0 | + USB_PHY_CTRL1_COMMONONN); + RegData |= USB_PHY_CTRL1_RESET | USB_PHY_CTRL1_ATERESET; + writel(RegData, dwc3->base + USB_PHY_CTRL1); + + /* enable rx term override */ + RegData = readl(dwc3->base + USB_PHY_CTRL6); + RegData |= USB_PHY_CTRL6_RXTERM_OVERRIDE_SEL; + writel(RegData, dwc3->base + USB_PHY_CTRL6); + + return 0; +} + +void spl_board_init(void) +{ + if (is_usb_boot()) + puts("USB Boot\n"); + else + puts("Normal Boot\n"); +} + +void board_boot_order(u32 *spl_boot_list) +{ + if (is_usb_boot()) + spl_boot_list[0] = BOOT_DEVICE_BOARD; + else + spl_boot_list[0] = BOOT_DEVICE_MMC1; +} + +#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE) + +static const iomux_v3_cfg_t wdog_pads[] = { + IMX8MQ_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL), +}; + +void board_init_f(ulong dummy) +{ + int ret; + struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR; + + arch_cpu_init(); + + imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads)); + set_wdog_reset(wdog); + + init_uart_clk(CONSOLE_UART_CLK); + imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads)); + +#ifdef CONSOLE_ON_UART4 + gpio_request(WIFI_EN, "WIFI_EN"); + gpio_direction_output(WIFI_EN, 1); +#endif + + board_early_init_f(); + + timer_init(); + + preloader_console_init(); + + ret = spl_init(); + if (ret) { + log_err("spl_init() failed: %d\n", ret); + hang(); + } + + enable_tzc380(); + + printf("Initializing pinmux\n"); + init_pinmux(); + gpio_direction_output(LED_G, 1); + gpio_direction_output(MOTO, 1); + mdelay(50); + gpio_direction_output(MOTO, 0); + + /* Enable and configure i2c buses not used below */ + setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2); + setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info3); + setup_i2c(3, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info4); + + power_init_board(); + + disable_charger_bq25895(); + + /* initialize this for M4 even if u-boot doesn't have SF_CMD */ + printf("Initializing ECSPI\n"); + board_ecspi_init(); + + /* DDR initialization */ + printf("Initializing DRAM\n"); + spl_dram_init(); +} diff --git a/board/renesas/rcar-common/common.c b/board/renesas/rcar-common/common.c index 0352d341e7..daa1beb14f 100644 --- a/board/renesas/rcar-common/common.c +++ b/board/renesas/rcar-common/common.c @@ -9,6 +9,7 @@ #include #include +#include #include #include #include @@ -19,9 +20,11 @@ DECLARE_GLOBAL_DATA_PTR; -/* If the firmware passed a device tree use it for U-Boot DRAM setup. */ +/* If the firmware passed a device tree use it for e.g. U-Boot DRAM setup. */ extern u64 rcar_atf_boot_args[]; +#define FDT_RPC_PATH "/soc/spi@ee200000" + int fdtdec_board_setup(const void *fdt_blob) { void *atf_fdt_blob = (void *)(rcar_atf_boot_args[1]); @@ -81,7 +84,7 @@ static int is_mem_overlap(void *blob, int first_mem_node, int curr_mem_node) return 0; } -int ft_board_setup(void *blob, struct bd_info *bd) +static void scrub_duplicate_memory(void *blob) { /* * Scrub duplicate /memory@* node entries here. Some R-Car DTs might @@ -119,6 +122,45 @@ int ft_board_setup(void *blob, struct bd_info *bd) first_mem_node = 0; mem = 0; } +} + +static void update_rpc_status(void *blob) +{ + void *atf_fdt_blob = (void *)(rcar_atf_boot_args[1]); + int offset, enabled; + + /* + * Check if the DT fragment received from TF-A had its RPC-IF device node + * enabled. + */ + if (fdt_magic(atf_fdt_blob) != FDT_MAGIC) + return; + + offset = fdt_path_offset(atf_fdt_blob, FDT_RPC_PATH); + if (offset < 0) + return; + + enabled = fdtdec_get_is_enabled(atf_fdt_blob, offset); + if (!enabled) + return; + + /* + * Find the RPC-IF device node, and enable it if it has a flash subnode. + */ + offset = fdt_path_offset(blob, FDT_RPC_PATH); + if (offset < 0) + return; + + if (fdt_subnode_offset(blob, offset, "flash") < 0) + return; + + fdt_status_okay(blob, offset); +} + +int ft_board_setup(void *blob, struct bd_info *bd) +{ + scrub_duplicate_memory(blob); + update_rpc_status(blob); return 0; } diff --git a/board/st/stm32mp1/stm32mp1.c b/board/st/stm32mp1/stm32mp1.c index 6028a0b6de..581a4df1cc 100644 --- a/board/st/stm32mp1/stm32mp1.c +++ b/board/st/stm32mp1/stm32mp1.c @@ -494,7 +494,7 @@ static void sysconf_init(void) ret = uclass_get_device_by_driver(UCLASS_PMIC, DM_DRIVER_GET(stm32mp_pwr_pmic), &pwr_dev); - if (!ret && IS_ENABLED(CONFIG_DM_REGULATOR)) { + if (!ret) { ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(stm32mp_bsec), &dev); @@ -555,9 +555,6 @@ static int board_stm32mp15x_dk2_init(void) struct gpio_desc hdmi, audio; int ret = 0; - if (!IS_ENABLED(CONFIG_DM_REGULATOR)) - return -ENODEV; - /* Fix to make I2C1 usable on DK2 for touchscreen usage in kernel */ node = ofnode_path("/soc/i2c@40012000/hdmi-transmitter@39"); if (!ofnode_valid(node)) { @@ -658,8 +655,7 @@ int board_init(void) if (board_is_stm32mp15x_dk2()) board_stm32mp15x_dk2_init(); - if (IS_ENABLED(CONFIG_DM_REGULATOR)) - regulators_enable_boot_on(_DEBUG); + regulators_enable_boot_on(_DEBUG); /* * sysconf initialisation done only when U-Boot is running in secure diff --git a/board/ti/common/board_detect.c b/board/ti/common/board_detect.c index ed34991377..9fa7b7beb6 100644 --- a/board/ti/common/board_detect.c +++ b/board/ti/common/board_detect.c @@ -86,7 +86,6 @@ __weak void gpi2c_init(void) static int __maybe_unused ti_i2c_eeprom_get(int bus_addr, int dev_addr, u32 header, u32 size, uint8_t *ep) { - u32 hdr_read = 0xdeadbeef; int rc; #if CONFIG_IS_ENABLED(DM_I2C) @@ -113,10 +112,10 @@ static int __maybe_unused ti_i2c_eeprom_get(int bus_addr, int dev_addr, * We must allow for fall through to check the data if 2 byte * addressing works */ - (void)dm_i2c_read(dev, 0, (uint8_t *)&hdr_read, 4); + (void)dm_i2c_read(dev, 0, ep, size); /* Corrupted data??? */ - if (hdr_read != header) { + if (*((u32 *)ep) != header) { /* * read the eeprom header using i2c again, but use only a * 2 byte address (some newer boards need this..) @@ -125,16 +124,12 @@ static int __maybe_unused ti_i2c_eeprom_get(int bus_addr, int dev_addr, if (rc) return rc; - rc = dm_i2c_read(dev, 0, (uint8_t *)&hdr_read, 4); + rc = dm_i2c_read(dev, 0, ep, size); if (rc) return rc; } - if (hdr_read != header) + if (*((u32 *)ep) != header) return -1; - - rc = dm_i2c_read(dev, 0, ep, size); - if (rc) - return rc; #else u32 byte; @@ -154,26 +149,21 @@ static int __maybe_unused ti_i2c_eeprom_get(int bus_addr, int dev_addr, * We must allow for fall through to check the data if 2 byte * addressing works */ - (void)i2c_read(dev_addr, 0x0, byte, (uint8_t *)&hdr_read, 4); + (void)i2c_read(dev_addr, 0x0, byte, ep, size); /* Corrupted data??? */ - if (hdr_read != header) { + if (*((u32 *)ep) != header) { /* * read the eeprom header using i2c again, but use only a * 2 byte address (some newer boards need this..) */ byte = 2; - rc = i2c_read(dev_addr, 0x0, byte, (uint8_t *)&hdr_read, - 4); + rc = i2c_read(dev_addr, 0x0, byte, ep, size); if (rc) return rc; } - if (hdr_read != header) + if (*((u32 *)ep) != header) return -1; - - rc = i2c_read(dev_addr, 0x0, byte, ep, size); - if (rc) - return rc; #endif return 0; } diff --git a/board/toradex/verdin-imx8mm/spl.c b/board/toradex/verdin-imx8mm/spl.c index 243c97e0ba..fb9aae6c9c 100644 --- a/board/toradex/verdin-imx8mm/spl.c +++ b/board/toradex/verdin-imx8mm/spl.c @@ -34,14 +34,11 @@ DECLARE_GLOBAL_DATA_PTR; int spl_board_boot_device(enum boot_device boot_dev_spl) { switch (boot_dev_spl) { - case MMC1_BOOT: + case MMC1_BOOT: /* eMMC */ return BOOT_DEVICE_MMC1; - case SD2_BOOT: + case SD2_BOOT: /* SD card */ case MMC2_BOOT: return BOOT_DEVICE_MMC2; - case SD3_BOOT: - case MMC3_BOOT: - return BOOT_DEVICE_MMC1; case USB_BOOT: return BOOT_DEVICE_BOARD; default: @@ -56,6 +53,15 @@ void spl_dram_init(void) void spl_board_init(void) { + if (IS_ENABLED(CONFIG_FSL_CAAM)) { + struct udevice *dev; + int ret; + + ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(caam_jr), &dev); + if (ret) + printf("Failed to initialize %s: %d\n", dev->name, ret); + } + /* Serial download mode */ if (is_usb_boot()) { puts("Back to ROM, SDP\n"); @@ -74,7 +80,6 @@ int board_fit_config_name_match(const char *name) } #endif - __weak void board_early_init(void) { init_uart_clk(0); diff --git a/board/toradex/verdin-imx8mm/verdin-imx8mm.c b/board/toradex/verdin-imx8mm/verdin-imx8mm.c index 7597cd81f9..bad8833b22 100644 --- a/board/toradex/verdin-imx8mm/verdin-imx8mm.c +++ b/board/toradex/verdin-imx8mm/verdin-imx8mm.c @@ -102,9 +102,6 @@ static void select_dt_from_module_version(void) if (strcmp(variant, env_variant)) { printf("Setting variant to %s\n", variant); env_set("variant", variant); - - if (IS_ENABLED(CONFIG_ENV_IS_NOWHERE)) - env_save(); } } diff --git a/board/toradex/verdin-imx8mp/verdin-imx8mp.c b/board/toradex/verdin-imx8mp/verdin-imx8mp.c index e3c1a1201d..783e2bd0d2 100644 --- a/board/toradex/verdin-imx8mp/verdin-imx8mp.c +++ b/board/toradex/verdin-imx8mp/verdin-imx8mp.c @@ -108,9 +108,6 @@ static void select_dt_from_module_version(void) if (strcmp(variant, env_variant)) { printf("Setting variant to %s\n", variant); env_set("variant", variant); - - if (IS_ENABLED(CONFIG_ENV_IS_NOWHERE)) - env_save(); } } diff --git a/boot/bootm.c b/boot/bootm.c index 86dbfbcfed..e3233fdf89 100644 --- a/boot/bootm.c +++ b/boot/bootm.c @@ -305,9 +305,9 @@ int bootm_find_images(int flag, int argc, char *const argv[], ulong start, /* check if FDT overlaps OS image */ if (images.ft_addr && (((ulong)images.ft_addr >= start && - (ulong)images.ft_addr <= start + size) || + (ulong)images.ft_addr < start + size) || ((ulong)images.ft_addr + images.ft_len >= start && - (ulong)images.ft_addr + images.ft_len <= start + size))) { + (ulong)images.ft_addr + images.ft_len < start + size))) { printf("ERROR: FDT image overlaps OS image (OS=0x%lx..0x%lx)\n", start, start + size); return 1; @@ -1006,7 +1006,7 @@ static int bootm_host_load_image(const void *fit, int req_image_type, int noffset; ulong load_end, buf_size; uint8_t image_type; - uint8_t imape_comp; + uint8_t image_comp; void *load_buf; int ret; @@ -1024,20 +1024,18 @@ static int bootm_host_load_image(const void *fit, int req_image_type, return -EINVAL; } - if (fit_image_get_comp(fit, noffset, &imape_comp)) { - puts("Can't get image compression!\n"); - return -EINVAL; - } + if (fit_image_get_comp(fit, noffset, &image_comp)) + image_comp = IH_COMP_NONE; /* Allow the image to expand by a factor of 4, should be safe */ buf_size = (1 << 20) + len * 4; load_buf = malloc(buf_size); - ret = image_decomp(imape_comp, 0, data, image_type, load_buf, + ret = image_decomp(image_comp, 0, data, image_type, load_buf, (void *)data, len, buf_size, &load_end); free(load_buf); if (ret) { - ret = handle_decomp_error(imape_comp, load_end - 0, buf_size, ret); + ret = handle_decomp_error(image_comp, load_end - 0, buf_size, ret); if (ret != BOOTM_ERR_UNIMPLEMENTED) return ret; } diff --git a/boot/bootmeth_distro.c b/boot/bootmeth_distro.c index fea09b2c2f..5c6c687f0a 100644 --- a/boot/bootmeth_distro.c +++ b/boot/bootmeth_distro.c @@ -35,8 +35,8 @@ static int distro_get_state_desc(struct udevice *dev, char *buf, int maxsize) return 0; } -static int disto_getfile(struct pxe_context *ctx, const char *file_path, - char *file_addr, ulong *sizep) +static int distro_getfile(struct pxe_context *ctx, const char *file_path, + char *file_addr, ulong *sizep) { struct distro_info *info = ctx->userdata; ulong addr; @@ -113,7 +113,7 @@ static int distro_boot(struct udevice *dev, struct bootflow *bflow) addr = map_to_sysmem(bflow->buf); info.dev = dev; info.bflow = bflow; - ret = pxe_setup_ctx(&ctx, &cmdtp, disto_getfile, &info, true, + ret = pxe_setup_ctx(&ctx, &cmdtp, distro_getfile, &info, true, bflow->subdir); if (ret) return log_msg_ret("ctx", -EINVAL); diff --git a/boot/bootmeth_pxe.c b/boot/bootmeth_pxe.c index f1e2b4c776..e6992168c0 100644 --- a/boot/bootmeth_pxe.c +++ b/boot/bootmeth_pxe.c @@ -23,8 +23,8 @@ #include #include -static int disto_pxe_getfile(struct pxe_context *ctx, const char *file_path, - char *file_addr, ulong *sizep) +static int distro_pxe_getfile(struct pxe_context *ctx, const char *file_path, + char *file_addr, ulong *sizep) { struct distro_info *info = ctx->userdata; ulong addr; @@ -142,7 +142,7 @@ static int distro_pxe_boot(struct udevice *dev, struct bootflow *bflow) info.dev = dev; info.bflow = bflow; info.cmdtp = &cmdtp; - ret = pxe_setup_ctx(ctx, &cmdtp, disto_pxe_getfile, &info, false, + ret = pxe_setup_ctx(ctx, &cmdtp, distro_pxe_getfile, &info, false, bflow->subdir); if (ret) return log_msg_ret("ctx", -EINVAL); diff --git a/boot/image-fit.c b/boot/image-fit.c index df3e5df883..f16eab9df3 100644 --- a/boot/image-fit.c +++ b/boot/image-fit.c @@ -477,7 +477,7 @@ void fit_print_contents(const void *fit) void fit_image_print(const void *fit, int image_noffset, const char *p) { char *desc; - uint8_t type, arch, os, comp; + uint8_t type, arch, os, comp = IH_COMP_NONE; size_t size; ulong load, entry; const void *data; @@ -794,7 +794,6 @@ int fit_image_get_comp(const void *fit, int noffset, uint8_t *comp) data = fdt_getprop(fit, noffset, FIT_COMP_PROP, &len); if (data == NULL) { fit_get_debug(fit, noffset, FIT_COMP_PROP, len); - *comp = -1; return -1; } @@ -1917,6 +1916,43 @@ int fit_conf_get_prop_node(const void *fit, int noffset, return fit_conf_get_prop_node_index(fit, noffset, prop_name, 0); } +static int fit_get_data_tail(const void *fit, int noffset, + const void **data, size_t *size) +{ + char *desc; + + if (noffset < 0) + return noffset; + + if (!fit_image_verify(fit, noffset)) + return -EINVAL; + + if (fit_image_get_data_and_size(fit, noffset, data, size)) + return -ENOENT; + + if (!fit_get_desc(fit, noffset, &desc)) + printf("%s\n", desc); + + return 0; +} + +int fit_get_data_node(const void *fit, const char *image_uname, + const void **data, size_t *size) +{ + int noffset = fit_image_get_node(fit, image_uname); + + return fit_get_data_tail(fit, noffset, data, size); +} + +int fit_get_data_conf_prop(const void *fit, const char *prop_name, + const void **data, size_t *size) +{ + int noffset = fit_conf_get_node(fit, NULL); + + noffset = fit_conf_get_prop_node(fit, noffset, prop_name); + return fit_get_data_tail(fit, noffset, data, size); +} + static int fit_image_select(const void *fit, int rd_noffset, int verify) { fit_image_print(fit, rd_noffset, " "); diff --git a/boot/vbe.c b/boot/vbe.c index e6ee087dc2..52b3283003 100644 --- a/boot/vbe.c +++ b/boot/vbe.c @@ -40,7 +40,7 @@ int vbe_find_next_device(struct udevice **devp) int vbe_find_first_device(struct udevice **devp) { uclass_find_first_device(UCLASS_BOOTMETH, devp); - if (*devp && is_vbe(*devp)) + if (!*devp || is_vbe(*devp)) return 0; return vbe_find_next_device(devp); diff --git a/boot/vbe_simple.c b/boot/vbe_simple.c index a395bc20a6..0fc57388f3 100644 --- a/boot/vbe_simple.c +++ b/boot/vbe_simple.c @@ -225,17 +225,16 @@ static int bootmeth_vbe_simple_ft_fixup(void *ctx, struct event *event) { oftree tree = event->data.ft_fixup.tree; struct udevice *dev; - ofnode node; - int ret; /* * Ideally we would have driver model support for fixups, but that does * not exist yet. It is a step too far to try to do this before VBE is * in place. */ - for (ret = vbe_find_first_device(&dev); dev; - ret = vbe_find_next_device(&dev)) { + for (vbe_find_first_device(&dev); dev; vbe_find_next_device(&dev)) { struct simple_state state; + ofnode node; + int ret; if (strcmp("vbe_simple", dev->driver->name)) continue; diff --git a/cmd/Kconfig b/cmd/Kconfig index 6db76e9da8..bfa12ce12a 100644 --- a/cmd/Kconfig +++ b/cmd/Kconfig @@ -333,7 +333,7 @@ config BOOTM_RTEMS config CMD_VBE bool "vbe - Verified Boot for Embedded" depends on BOOTMETH_VBE - default y + default y if BOOTSTD_FULL help Provides various subcommands related to VBE, such as listing the available methods, looking at the state and changing which method @@ -1721,7 +1721,7 @@ config CMD_TFTPBOOT bool "tftpboot" default y help - tftpboot - boot image via network using TFTP protocol + tftpboot - load file via network using TFTP protocol config CMD_TFTPPUT bool "tftp put" diff --git a/cmd/dm.c b/cmd/dm.c index eb40f0865f..218be85795 100644 --- a/cmd/dm.c +++ b/cmd/dm.c @@ -87,7 +87,7 @@ static char dm_help_text[] = "dm drivers Dump list of drivers with uclass and instances\n" DM_MEM_HELP "dm static Dump list of drivers with static platform data\n" - "dn tree Dump tree of driver model devices ('*' = activated)\n" + "dm tree Dump tree of driver model devices ('*' = activated)\n" "dm uclass Dump list of instances for each uclass" ; #endif diff --git a/cmd/fpga.c b/cmd/fpga.c index c4651dd403..9cf7651d8c 100644 --- a/cmd/fpga.c +++ b/cmd/fpga.c @@ -322,7 +322,7 @@ static int do_fpga_loadmk(struct cmd_tbl *cmdtp, int flag, int argc, case IMAGE_FORMAT_FIT: { const void *fit_hdr = (const void *)fpga_data; - int noffset; + int err; const void *fit_data; if (!fit_uname) { @@ -335,23 +335,11 @@ static int do_fpga_loadmk(struct cmd_tbl *cmdtp, int flag, int argc, return CMD_RET_FAILURE; } - /* get fpga component image node offset */ - noffset = fit_image_get_node(fit_hdr, fit_uname); - if (noffset < 0) { - printf("Can't find '%s' FIT subimage\n", fit_uname); - return CMD_RET_FAILURE; - } - - /* verify integrity */ - if (!fit_image_verify(fit_hdr, noffset)) { - puts("Bad Data Hash\n"); - return CMD_RET_FAILURE; - } - - /* get fpga subimage/external data address and length */ - if (fit_image_get_data_and_size(fit_hdr, noffset, - &fit_data, &data_size)) { - puts("Fpga subimage data not found\n"); + err = fit_get_data_node(fit_hdr, fit_uname, &fit_data, + &data_size); + if (err) { + printf("Could not load '%s' subimage (err %d)\n", + fit_uname, err); return CMD_RET_FAILURE; } diff --git a/cmd/i2c.c b/cmd/i2c.c index bd04b14024..e196a73efa 100644 --- a/cmd/i2c.c +++ b/cmd/i2c.c @@ -200,10 +200,10 @@ void i2c_init_board(void) * * Returns the address length. */ -static uint get_alen(char *arg, uint default_len) +static uint get_alen(char *arg, int default_len) { - uint j; - uint alen; + int j; + int alen; alen = default_len; for (j = 0; j < 8; j++) { @@ -247,7 +247,7 @@ static int do_i2c_read(struct cmd_tbl *cmdtp, int flag, int argc, { uint chip; uint devaddr, length; - uint alen; + int alen; u_char *memaddr; int ret; #if CONFIG_IS_ENABLED(DM_I2C) @@ -301,7 +301,7 @@ static int do_i2c_write(struct cmd_tbl *cmdtp, int flag, int argc, { uint chip; uint devaddr, length; - uint alen; + int alen; u_char *memaddr; int ret; #if CONFIG_IS_ENABLED(DM_I2C) @@ -469,8 +469,9 @@ static int do_i2c_md(struct cmd_tbl *cmdtp, int flag, int argc, { uint chip; uint addr, length; - uint alen; - uint j, nbytes, linebytes; + int alen; + int j; + uint nbytes, linebytes; int ret; #if CONFIG_IS_ENABLED(DM_I2C) struct udevice *dev; @@ -589,9 +590,9 @@ static int do_i2c_mw(struct cmd_tbl *cmdtp, int flag, int argc, { uint chip; ulong addr; - uint alen; + int alen; uchar byte; - uint count; + int count; int ret; #if CONFIG_IS_ENABLED(DM_I2C) struct udevice *dev; @@ -676,8 +677,8 @@ static int do_i2c_crc(struct cmd_tbl *cmdtp, int flag, int argc, { uint chip; ulong addr; - uint alen; - uint count; + int alen; + int count; uchar byte; ulong crc; ulong err; @@ -985,7 +986,7 @@ static int do_i2c_loop(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) { uint chip; - uint alen; + int alen; uint addr; uint length; u_char bytes[16]; diff --git a/cmd/mvebu/Kconfig b/cmd/mvebu/Kconfig index 120397d6d4..9ec3aa983a 100644 --- a/cmd/mvebu/Kconfig +++ b/cmd/mvebu/Kconfig @@ -5,6 +5,7 @@ config CMD_MVEBU_BUBT bool "bubt" select SHA256 if ARMADA_3700 select SHA512 if ARMADA_3700 + select MVEBU_EFUSE if ARMADA_38X || ARMADA_3700 help bubt - Burn a u-boot image to flash For details about bubt command please see the documentation diff --git a/cmd/mvebu/bubt.c b/cmd/mvebu/bubt.c index 825d4beb89..1efbe2e607 100644 --- a/cmd/mvebu/bubt.c +++ b/cmd/mvebu/bubt.c @@ -13,6 +13,8 @@ #include #include #include +#include +#include #include #include @@ -121,6 +123,17 @@ struct a38x_main_hdr_v1 { u8 checksum; /* 0x1F */ }; +/* + * Header for the optional headers, version 1 (Armada 370/XP/375/38x/39x) + */ +struct a38x_opt_hdr_v1 { + u8 headertype; + u8 headersz_msb; + u16 headersz_lsb; + u8 data[0]; +}; +#define A38X_OPT_HDR_V1_SECURE_TYPE 0x1 + struct a38x_boot_mode { unsigned int id; const char *name; @@ -688,9 +701,25 @@ static uint8_t image_checksum8(const void *start, size_t len) return csum; } +static uint32_t image_checksum32(const void *start, size_t len) +{ + u32 csum = 0; + const u32 *p = start; + + while (len) { + csum += *p; + ++p; + len -= sizeof(u32); + } + + return csum; +} + static int check_image_header(void) { u8 checksum; + u32 checksum32, exp_checksum32; + u32 offset, size; const struct a38x_main_hdr_v1 *hdr = (struct a38x_main_hdr_v1 *)get_load_addr(); const size_t image_size = a38x_header_size(hdr); @@ -701,14 +730,74 @@ static int check_image_header(void) checksum = image_checksum8(hdr, image_size); checksum -= hdr->checksum; if (checksum != hdr->checksum) { - printf("Error: Bad A38x image checksum. 0x%x != 0x%x\n", + printf("Error: Bad A38x image header checksum. 0x%x != 0x%x\n", checksum, hdr->checksum); return -ENOEXEC; } + offset = le32_to_cpu(hdr->srcaddr); + size = le32_to_cpu(hdr->blocksize); + + if (hdr->blockid == 0x78) { /* SATA id */ + if (offset < 1) { + printf("Error: Bad A38x image srcaddr.\n"); + return -ENOEXEC; + } + offset -= 1; + offset *= 512; + } + + if (hdr->blockid == 0xAE) /* SDIO id */ + offset *= 512; + + if (offset % 4 != 0 || size < 4 || size % 4 != 0) { + printf("Error: Bad A38x image blocksize.\n"); + return -ENOEXEC; + } + + checksum32 = image_checksum32((u8 *)hdr + offset, size - 4); + exp_checksum32 = *(u32 *)((u8 *)hdr + offset + size - 4); + if (checksum32 != exp_checksum32) { + printf("Error: Bad A38x image data checksum. 0x%08x != 0x%08x\n", + checksum32, exp_checksum32); + return -ENOEXEC; + } + printf("Image checksum...OK!\n"); return 0; } + +#if defined(CONFIG_ARMADA_38X) +static int a38x_image_is_secure(const struct a38x_main_hdr_v1 *hdr) +{ + u32 image_size = a38x_header_size(hdr); + struct a38x_opt_hdr_v1 *ohdr; + u32 ohdr_size; + + if (hdr->version != 1) + return 0; + + if (!hdr->ext) + return 0; + + ohdr = (struct a38x_opt_hdr_v1 *)(hdr + 1); + do { + if (ohdr->headertype == A38X_OPT_HDR_V1_SECURE_TYPE) + return 1; + + ohdr_size = (ohdr->headersz_msb << 16) | le16_to_cpu(ohdr->headersz_lsb); + + if (!*((u8 *)ohdr + ohdr_size - 4)) + break; + + ohdr = (struct a38x_opt_hdr_v1 *)((u8 *)ohdr + ohdr_size); + if ((u8 *)ohdr >= (u8 *)hdr + image_size) + break; + } while (1); + + return 0; +} +#endif #else /* Not ARMADA? */ static int check_image_header(void) { @@ -717,20 +806,60 @@ static int check_image_header(void) } #endif +#if defined(CONFIG_ARMADA_3700) || defined(CONFIG_ARMADA_32BIT) +static u64 fuse_read_u64(u32 bank) +{ + u32 val[2]; + int ret; + + ret = fuse_read(bank, 0, &val[0]); + if (ret < 0) + return -1; + + ret = fuse_read(bank, 1, &val[1]); + if (ret < 0) + return -1; + + return ((u64)val[1] << 32) | val[0]; +} +#endif + +#if defined(CONFIG_ARMADA_3700) +static inline u8 maj3(u8 val) +{ + /* return majority vote of 3 bits */ + return ((val & 0x7) == 3 || (val & 0x7) > 4) ? 1 : 0; +} +#endif + static int bubt_check_boot_mode(const struct bubt_dev *dst) { #if defined(CONFIG_ARMADA_3700) || defined(CONFIG_ARMADA_32BIT) - int mode; + int mode, secure_mode; #if defined(CONFIG_ARMADA_3700) const struct tim_boot_flash_sign *boot_modes = tim_boot_flash_signs; const struct common_tim_data *hdr = (struct common_tim_data *)get_load_addr(); u32 id = hdr->boot_flash_sign; + int is_secure = hdr->trusted != 0; + u64 otp_secure_bits = fuse_read_u64(1); + int otp_secure_boot = ((maj3(otp_secure_bits >> 0) << 0) | + (maj3(otp_secure_bits >> 4) << 1)) == 2; + unsigned int otp_boot_device = (maj3(otp_secure_bits >> 48) << 0) | + (maj3(otp_secure_bits >> 52) << 1) | + (maj3(otp_secure_bits >> 56) << 2) | + (maj3(otp_secure_bits >> 60) << 3); #elif defined(CONFIG_ARMADA_32BIT) const struct a38x_boot_mode *boot_modes = a38x_boot_modes; const struct a38x_main_hdr_v1 *hdr = (struct a38x_main_hdr_v1 *)get_load_addr(); u32 id = hdr->blockid; +#if defined(CONFIG_ARMADA_38X) + int is_secure = a38x_image_is_secure(hdr); + u64 otp_secure_bits = fuse_read_u64(EFUSE_LINE_SECURE_BOOT); + int otp_secure_boot = otp_secure_bits & 0x1; + unsigned int otp_boot_device = (otp_secure_bits >> 8) & 0x7; +#endif #endif for (mode = 0; boot_modes[mode].name; mode++) { @@ -743,15 +872,42 @@ static int bubt_check_boot_mode(const struct bubt_dev *dst) return -ENOEXEC; } - if (strcmp(boot_modes[mode].name, dst->name) == 0) - return 0; + if (strcmp(boot_modes[mode].name, dst->name) != 0) { + printf("Error: image meant to be booted from \"%s\", not \"%s\"!\n", + boot_modes[mode].name, dst->name); + return -ENOEXEC; + } - printf("Error: image meant to be booted from \"%s\", not \"%s\"!\n", - boot_modes[mode].name, dst->name); - return -ENOEXEC; -#else - return 0; +#if defined(CONFIG_ARMADA_38X) || defined(CONFIG_ARMADA_3700) + if (otp_secure_bits == (u64)-1) { + printf("Error: cannot read OTP secure bits\n"); + return -ENOEXEC; + } else { + if (otp_secure_boot && !is_secure) { + printf("Error: secure boot is enabled in OTP but image does not have secure boot header!\n"); + return -ENOEXEC; + } else if (!otp_secure_boot && is_secure) { +#if defined(CONFIG_ARMADA_3700) + /* + * Armada 3700 BootROM rejects trusted image when secure boot is not enabled. + * Armada 385 BootROM accepts image with secure boot header also when secure boot is not enabled. + */ + printf("Error: secure boot is disabled in OTP but image has secure boot header!\n"); + return -ENOEXEC; #endif + } else if (otp_boot_device && otp_boot_device != id) { + for (secure_mode = 0; boot_modes[secure_mode].name; secure_mode++) { + if (boot_modes[secure_mode].id == otp_boot_device) + break; + } + printf("Error: boot source is set to \"%s\" in OTP but image is for \"%s\"!\n", + boot_modes[secure_mode].name ?: "unknown", dst->name); + return -ENOEXEC; + } + } +#endif +#endif + return 0; } static int bubt_verify(const struct bubt_dev *dst) diff --git a/cmd/net.c b/cmd/net.c index 3619c843d8..46f8c87b69 100644 --- a/cmd/net.c +++ b/cmd/net.c @@ -46,7 +46,7 @@ int do_tftpb(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) U_BOOT_CMD( tftpboot, 3, 1, do_tftpb, - "boot image via network using TFTP protocol", + "load file via network using TFTP protocol", "[loadAddress] [[hostIPaddr:]bootfilename]" ); #endif @@ -189,30 +189,49 @@ static void netboot_update_env(void) #endif } -static int netboot_common(enum proto_t proto, struct cmd_tbl *cmdtp, int argc, - char *const argv[]) +/** + * parse_addr_size() - parse address and size arguments for tftpput + * + * @argv: command line arguments + * Return: 0 on success + */ +static int parse_addr_size(char * const argv[]) +{ + if (strict_strtoul(argv[1], 16, &image_save_addr) < 0 || + strict_strtoul(argv[2], 16, &image_save_size) < 0) { + printf("Invalid address/size\n"); + return CMD_RET_USAGE; + } + return 0; +} + +/** + * parse_args() - parse command line arguments + * + * @proto: command prototype + * @argc: number of arguments + * @argv: command line arguments + * Return: 0 on success + */ +static int parse_args(enum proto_t proto, int argc, char *const argv[]) { - char *s; - char *end; - int rcode = 0; - int size; ulong addr; - - net_boot_file_name_explicit = false; - - /* pre-set image_load_addr */ - s = env_get("loadaddr"); - if (s != NULL) - image_load_addr = hextoul(s, NULL); + char *end; switch (argc) { case 1: + if (CONFIG_IS_ENABLED(CMD_TFTPPUT) && proto == TFTPPUT) + return 1; + /* refresh bootfile name from env */ copy_filename(net_boot_file_name, env_get("bootfile"), sizeof(net_boot_file_name)); break; - case 2: /* + case 2: + if (CONFIG_IS_ENABLED(CMD_TFTPPUT) && proto == TFTPPUT) + return 1; + /* * Only one arg - accept two forms: * Just load address, or just boot file name. The latter * form must be written in a format which can not be @@ -232,29 +251,52 @@ static int netboot_common(enum proto_t proto, struct cmd_tbl *cmdtp, int argc, break; case 3: - image_load_addr = hextoul(argv[1], NULL); - net_boot_file_name_explicit = true; - copy_filename(net_boot_file_name, argv[2], - sizeof(net_boot_file_name)); - + if (CONFIG_IS_ENABLED(CMD_TFTPPUT) && proto == TFTPPUT) { + if (parse_addr_size(argv)) + return 1; + } else { + image_load_addr = hextoul(argv[1], NULL); + net_boot_file_name_explicit = true; + copy_filename(net_boot_file_name, argv[2], + sizeof(net_boot_file_name)); + } break; #ifdef CONFIG_CMD_TFTPPUT case 4: - if (strict_strtoul(argv[1], 16, &image_save_addr) < 0 || - strict_strtoul(argv[2], 16, &image_save_size) < 0) { - printf("Invalid address/size\n"); - return CMD_RET_USAGE; - } + if (parse_addr_size(argv)) + return 1; net_boot_file_name_explicit = true; copy_filename(net_boot_file_name, argv[3], sizeof(net_boot_file_name)); break; #endif default: + return 1; + } + return 0; +} + +static int netboot_common(enum proto_t proto, struct cmd_tbl *cmdtp, int argc, + char *const argv[]) +{ + char *s; + int rcode = 0; + int size; + + net_boot_file_name_explicit = false; + *net_boot_file_name = '\0'; + + /* pre-set image_load_addr */ + s = env_get("loadaddr"); + if (s != NULL) + image_load_addr = hextoul(s, NULL); + + if (parse_args(proto, argc, argv)) { bootstage_error(BOOTSTAGE_ID_NET_START); return CMD_RET_USAGE; } + bootstage_mark(BOOTSTAGE_ID_NET_START); size = net_loop(proto); diff --git a/cmd/pci.c b/cmd/pci.c index a99e8f8ad6..6258699fec 100644 --- a/cmd/pci.c +++ b/cmd/pci.c @@ -358,6 +358,9 @@ static int pci_cfg_display(struct udevice *dev, ulong addr, if (length == 0) length = 0x40 / byte_size; /* Standard PCI config space */ + if (addr >= 4096) + return 1; + /* Print the lines. * once, and all accesses are with the specified bus width. */ @@ -378,7 +381,10 @@ static int pci_cfg_display(struct udevice *dev, ulong addr, rc = 1; break; } - } while (nbytes > 0); + } while (nbytes > 0 && addr < 4096); + + if (rc == 0 && nbytes > 0) + return 1; return (rc); } @@ -390,6 +396,9 @@ static int pci_cfg_modify(struct udevice *dev, ulong addr, ulong size, int nbytes; ulong val; + if (addr >= 4096) + return 1; + /* Print the address, followed by value. Then accept input for * the next value. A non-converted value exits. */ @@ -427,7 +436,10 @@ static int pci_cfg_modify(struct udevice *dev, ulong addr, ulong size, addr += size; } } - } while (nbytes); + } while (nbytes && addr < 4096); + + if (nbytes) + return 1; return 0; } diff --git a/cmd/riscv/sbi.c b/cmd/riscv/sbi.c index ee11e0f88e..522f502435 100644 --- a/cmd/riscv/sbi.c +++ b/cmd/riscv/sbi.c @@ -68,11 +68,21 @@ static int do_sbi(struct cmd_tbl *cmdtp, int flag, int argc, ret = sbi_get_impl_version(&vers); if (ret < 0) break; - if (impl_id == 1) + switch (impl_id) { + case 1: /* OpenSBI */ printf("%ld.%ld", vers >> 16, vers & 0xffff); - else + break; + case 3: /* KVM */ + printf("%ld.%ld.%ld", + vers >> 16, + (vers >> 8) & 0xff, + vers & 0xff); + break; + default: printf("0x%lx", vers); + break; + } break; } } diff --git a/cmd/tpm-common.c b/cmd/tpm-common.c index 47adaffd18..d0c63cadf4 100644 --- a/cmd/tpm-common.c +++ b/cmd/tpm-common.c @@ -333,6 +333,26 @@ int do_tpm_info(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) return 0; } +int do_tpm_report_state(struct cmd_tbl *cmdtp, int flag, int argc, + char *const argv[]) +{ + struct udevice *dev; + char buf[80]; + int rc; + + rc = get_tpm(&dev); + if (rc) + return rc; + rc = tpm_report_state(dev, buf, sizeof(buf)); + if (rc < 0) { + printf("Couldn't get TPM state (%d)\n", rc); + return CMD_RET_FAILURE; + } + printf("%s\n", buf); + + return 0; +} + int do_tpm_init(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) { struct udevice *dev; diff --git a/cmd/tpm-user-utils.h b/cmd/tpm-user-utils.h index 358ddff576..de4a934aab 100644 --- a/cmd/tpm-user-utils.h +++ b/cmd/tpm-user-utils.h @@ -21,6 +21,8 @@ int do_tpm_device(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]); int do_tpm_init(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]); int do_tpm_info(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]); +int do_tpm_report_state(struct cmd_tbl *cmdtp, int flag, int argc, + char *const argv[]); int do_tpm(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]); #endif /* __TPM_USER_UTILS_H */ diff --git a/cmd/tpm-v1.c b/cmd/tpm-v1.c index bf238a9f2e..0efb079b0a 100644 --- a/cmd/tpm-v1.c +++ b/cmd/tpm-v1.c @@ -131,7 +131,8 @@ static int do_tpm_extend(struct cmd_tbl *cmdtp, int flag, int argc, return CMD_RET_FAILURE; } - rc = tpm_pcr_extend(dev, index, in_digest, out_digest); + rc = tpm_pcr_extend(dev, index, in_digest, sizeof(in_digest), + out_digest, "cmd"); if (!rc) { puts("PCR value after execution of the command:\n"); print_byte_string(out_digest, sizeof(out_digest)); diff --git a/cmd/tpm-v2.c b/cmd/tpm-v2.c index 4ea5f9f094..d93b83ada9 100644 --- a/cmd/tpm-v2.c +++ b/cmd/tpm-v2.c @@ -359,6 +359,7 @@ static int do_tpm_pcr_setauthvalue(struct cmd_tbl *cmdtp, int flag, static struct cmd_tbl tpm2_commands[] = { U_BOOT_CMD_MKENT(device, 0, 1, do_tpm_device, "", ""), U_BOOT_CMD_MKENT(info, 0, 1, do_tpm_info, "", ""), + U_BOOT_CMD_MKENT(state, 0, 1, do_tpm_report_state, "", ""), U_BOOT_CMD_MKENT(init, 0, 1, do_tpm_init, "", ""), U_BOOT_CMD_MKENT(startup, 0, 1, do_tpm2_startup, "", ""), U_BOOT_CMD_MKENT(self_test, 0, 1, do_tpm2_self_test, "", ""), @@ -389,6 +390,8 @@ U_BOOT_CMD(tpm2, CONFIG_SYS_MAXARGS, 1, do_tpm, "Issue a TPMv2.x command", " Show all devices or set the specified device\n" "info\n" " Show information about the TPM.\n" +"state\n" +" Show internal state from the TPM (if available)\n" "init\n" " Initialize the software stack. Always the first command to issue.\n" "startup \n" diff --git a/cmd/tpm_test.c b/cmd/tpm_test.c index a3ccb12f53..b35eae81dc 100644 --- a/cmd/tpm_test.c +++ b/cmd/tpm_test.c @@ -91,7 +91,8 @@ static int test_early_extend(struct udevice *dev) tpm_init(dev); TPM_CHECK(tpm_startup(dev, TPM_ST_CLEAR)); TPM_CHECK(tpm_continue_self_test(dev)); - TPM_CHECK(tpm_pcr_extend(dev, 1, value_in, value_out)); + TPM_CHECK(tpm_pcr_extend(dev, 1, value_in, sizeof(value_in), value_out, + "test")); printf("done\n"); return 0; } @@ -438,7 +439,7 @@ static int test_timing(struct udevice *dev) 100); TTPM_CHECK(tpm_nv_read_value(dev, INDEX0, (uint8_t *)&x, sizeof(x)), 100); - TTPM_CHECK(tpm_pcr_extend(dev, 0, in, out), 200); + TTPM_CHECK(tpm_pcr_extend(dev, 0, in, sizeof(in), out, "test"), 200); TTPM_CHECK(tpm_set_global_lock(dev), 50); TTPM_CHECK(tpm_tsc_physical_presence(dev, PHYS_PRESENCE), 100); printf("done\n"); diff --git a/cmd/ximg.c b/cmd/ximg.c index 8533d0d238..63b200430c 100644 --- a/cmd/ximg.c +++ b/cmd/ximg.c @@ -171,11 +171,8 @@ do_imgextract(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) return 1; } - if (fit_image_get_comp(fit_hdr, noffset, &comp)) { - puts("Could not find script subimage " - "compression type\n"); - return 1; - } + if (fit_image_get_comp(fit_hdr, noffset, &comp)) + comp = IH_COMP_NONE; data = (ulong)fit_data; len = (ulong)fit_len; diff --git a/common/Kconfig b/common/Kconfig index 3e44acd2be..b776c5ca1e 100644 --- a/common/Kconfig +++ b/common/Kconfig @@ -809,6 +809,20 @@ config TPL_STACKPROTECTOR bool "Stack Protector buffer overflow detection for TPL" depends on STACKPROTECTOR && TPL +config BOARD_RNG_SEED + bool "Provide /chosen/rng-seed property to the linux kernel" + help + Selecting this option requires the board to define a + board_rng_seed() function, which should return a buffer + which will be used to populate the /chosen/rng-seed property + in the device tree for the OS being booted. + + It is up to the board code (and more generally the whole + BSP) where and how to store (or generate) such a seed, how + to ensure a given seed is only used once, how to create a + new seed for use on subsequent boots, and whether or not the + kernel should account any entropy from the given seed. + endmenu menu "Update support" diff --git a/common/console.c b/common/console.c index 66b9813b3a..e5be6ff44b 100644 --- a/common/console.c +++ b/common/console.c @@ -600,6 +600,9 @@ static void pre_console_putc(const char c) { char *buffer; + if (gd->precon_buf_idx < 0) + return; + buffer = map_sysmem(CONFIG_VAL(PRE_CON_BUF_ADDR), CONFIG_VAL(PRE_CON_BUF_SZ)); buffer[CIRC_BUF_IDX(gd->precon_buf_idx++)] = c; @@ -609,13 +612,16 @@ static void pre_console_putc(const char c) static void pre_console_puts(const char *s) { + if (gd->precon_buf_idx < 0) + return; + while (*s) pre_console_putc(*s++); } static void print_pre_console_buffer(int flushpoint) { - unsigned long in = 0, out = 0; + long in = 0, out = 0; char buf_out[CONFIG_VAL(PRE_CON_BUF_SZ) + 1]; char *buf_in; @@ -632,6 +638,7 @@ static void print_pre_console_buffer(int flushpoint) buf_out[out] = 0; + gd->precon_buf_idx = -1; switch (flushpoint) { case PRE_CONSOLE_FLUSHPOINT1_SERIAL: puts(buf_out); @@ -640,6 +647,7 @@ static void print_pre_console_buffer(int flushpoint) console_puts_select(stdout, false, buf_out); break; } + gd->precon_buf_idx = in; } #else static inline void pre_console_putc(const char c) {} diff --git a/common/fdt_support.c b/common/fdt_support.c index 8c18af2ce1..baf7fb7065 100644 --- a/common/fdt_support.c +++ b/common/fdt_support.c @@ -7,6 +7,7 @@ */ #include +#include #include #include #include @@ -279,6 +280,7 @@ __weak char *board_fdt_chosen_bootargs(void) int fdt_chosen(void *fdt) { + struct abuf buf = {}; int nodeoffset; int err; char *str; /* used to set string properties */ @@ -294,6 +296,17 @@ int fdt_chosen(void *fdt) if (nodeoffset < 0) return nodeoffset; + if (IS_ENABLED(CONFIG_BOARD_RNG_SEED) && !board_rng_seed(&buf)) { + err = fdt_setprop(fdt, nodeoffset, "rng-seed", + abuf_data(&buf), abuf_size(&buf)); + abuf_uninit(&buf); + if (err < 0) { + printf("WARNING: could not set rng-seed %s.\n", + fdt_strerror(err)); + return err; + } + } + str = board_fdt_chosen_bootargs(); if (str) { diff --git a/configs/dockstar_defconfig b/configs/dockstar_defconfig index d43423c45e..feba398912 100644 --- a/configs/dockstar_defconfig +++ b/configs/dockstar_defconfig @@ -4,6 +4,9 @@ CONFIG_SYS_DCACHE_OFF=y CONFIG_ARCH_CPU_INIT=y CONFIG_SYS_THUMB_BUILD=y CONFIG_ARCH_KIRKWOOD=y +CONFIG_SUPPORT_PASSING_ATAGS=y +CONFIG_CMDLINE_TAG=y +CONFIG_INITRD_TAG=y CONFIG_SYS_KWD_CONFIG="board/Seagate/dockstar/kwbimage.cfg" CONFIG_SYS_TEXT_BASE=0x600000 CONFIG_NR_DRAM_BANKS=2 diff --git a/configs/dreamplug_defconfig b/configs/dreamplug_defconfig index 24090c81aa..650b14620e 100644 --- a/configs/dreamplug_defconfig +++ b/configs/dreamplug_defconfig @@ -3,6 +3,9 @@ CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_SYS_DCACHE_OFF=y CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_KIRKWOOD=y +CONFIG_SUPPORT_PASSING_ATAGS=y +CONFIG_CMDLINE_TAG=y +CONFIG_INITRD_TAG=y CONFIG_SYS_KWD_CONFIG="board/Marvell/dreamplug/kwbimage.cfg" CONFIG_SYS_TEXT_BASE=0x600000 CONFIG_NR_DRAM_BANKS=2 diff --git a/configs/eDPU_defconfig b/configs/eDPU_defconfig index 7c3c9779bc..9706b648e5 100644 --- a/configs/eDPU_defconfig +++ b/configs/eDPU_defconfig @@ -3,7 +3,6 @@ CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_MVEBU=y CONFIG_SYS_TEXT_BASE=0x00000000 CONFIG_TARGET_MVEBU_ARMADA_37XX=y -CONFIG_MVEBU_EFUSE=y CONFIG_ENV_SIZE=0x10000 CONFIG_ENV_OFFSET=0x180000 CONFIG_ENV_SECT_SIZE=0x10000 diff --git a/configs/goflexhome_defconfig b/configs/goflexhome_defconfig index 0856a31c76..aeb4a7d368 100644 --- a/configs/goflexhome_defconfig +++ b/configs/goflexhome_defconfig @@ -4,6 +4,9 @@ CONFIG_SYS_DCACHE_OFF=y CONFIG_ARCH_CPU_INIT=y CONFIG_SYS_THUMB_BUILD=y CONFIG_ARCH_KIRKWOOD=y +CONFIG_SUPPORT_PASSING_ATAGS=y +CONFIG_CMDLINE_TAG=y +CONFIG_INITRD_TAG=y CONFIG_SYS_KWD_CONFIG="board/Seagate/goflexhome/kwbimage.cfg" CONFIG_SYS_TEXT_BASE=0x600000 CONFIG_NR_DRAM_BANKS=2 diff --git a/configs/iconnect_defconfig b/configs/iconnect_defconfig index 1c66b42de8..c91d58d31a 100644 --- a/configs/iconnect_defconfig +++ b/configs/iconnect_defconfig @@ -4,6 +4,9 @@ CONFIG_SYS_DCACHE_OFF=y CONFIG_ARCH_CPU_INIT=y CONFIG_SYS_THUMB_BUILD=y CONFIG_ARCH_KIRKWOOD=y +CONFIG_SUPPORT_PASSING_ATAGS=y +CONFIG_CMDLINE_TAG=y +CONFIG_INITRD_TAG=y CONFIG_SYS_KWD_CONFIG="board/iomega/iconnect/kwbimage.cfg" CONFIG_SYS_TEXT_BASE=0x600000 CONFIG_NR_DRAM_BANKS=2 diff --git a/configs/imx6ulz_smm_m2_defconfig b/configs/imx6ulz_smm_m2_defconfig new file mode 100644 index 0000000000..6b4a0cc372 --- /dev/null +++ b/configs/imx6ulz_smm_m2_defconfig @@ -0,0 +1,79 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_SYS_TEXT_BASE=0x87800000 +CONFIG_SYS_MALLOC_LEN=0x1000000 +CONFIG_SYS_MALLOC_F_LEN=0x18000 +CONFIG_SPL_GPIO=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_ENV_SIZE=0x20000 +CONFIG_ENV_OFFSET=0x400000 +CONFIG_MX6ULL=y +CONFIG_TARGET_MX6ULZ_SMM_M2=y +CONFIG_DEFAULT_DEVICE_TREE="imx6ulz-bsh-smm-m2" +CONFIG_SPL_TEXT_BASE=0x00908000 +CONFIG_SPL_SERIAL=y +CONFIG_SPL=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_FIT=y +CONFIG_FIT_SIGNATURE=y +CONFIG_FIT_VERBOSE=y +CONFIG_LEGACY_IMAGE_FORMAT=y +CONFIG_BOOTDELAY=3 +CONFIG_BOARD_LATE_INIT=y +CONFIG_SPL_BSS_START_ADDR=0x84100000 +CONFIG_SYS_SPL_MALLOC=y +CONFIG_SPL_DMA=y +CONFIG_SPL_MTD_SUPPORT=y +CONFIG_SPL_NAND_SUPPORT=y +CONFIG_SPL_USB_HOST=y +CONFIG_SPL_USB_GADGET=y +CONFIG_SPL_USB_SDP_SUPPORT=y +CONFIG_SPL_WATCHDOG=y +CONFIG_CMD_DM=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_SDP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_MTDPARTS=y +CONFIG_MTDIDS_DEFAULT="nand0=gpmi-nand" +CONFIG_MTDPARTS_DEFAULT="mtdparts=gpmi-nand:4m(nandboot),1m(env),8m(kernel),1m(nanddtb),-(rootfs)" +CONFIG_CMD_UBI=y +# CONFIG_ISO_PARTITION is not set +CONFIG_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_NAND=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +# CONFIG_NET is not set +CONFIG_BOUNCE_BUFFER=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x82000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_UUU_SUPPORT=y +CONFIG_SYS_I2C_MXC=y +# CONFIG_MMC is not set +CONFIG_MTD=y +CONFIG_MTD_RAW_NAND=y +CONFIG_SYS_NAND_USE_FLASH_BBT=y +CONFIG_NAND_MXS=y +CONFIG_NAND_MXS_DT=y +CONFIG_SYS_NAND_ONFI_DETECTION=y +CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y +CONFIG_SYS_NAND_U_BOOT_OFFS=0x111400 +CONFIG_SYS_NAND_U_BOOT_OFFS_REDUND=0x291400 +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_MXC_UART=y +CONFIG_IMX_THERMAL=y +CONFIG_USB=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="BSH" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_CI_UDC=y +CONFIG_SDP_LOADADDR=0x877fffc0 diff --git a/configs/imx8mm_venice_defconfig b/configs/imx8mm_venice_defconfig index dfe2a51722..2a44bf6910 100644 --- a/configs/imx8mm_venice_defconfig +++ b/configs/imx8mm_venice_defconfig @@ -28,7 +28,6 @@ CONFIG_SPL_LOAD_FIT=y # CONFIG_USE_SPL_FIT_GENERATOR is not set CONFIG_OF_BOARD_SETUP=y CONFIG_OF_SYSTEM_SETUP=y -# CONFIG_USE_BOOTCOMMAND is not set CONFIG_USE_PREBOOT=y CONFIG_PREBOOT="gsc wd-disable" CONFIG_BOARD_LATE_INIT=y diff --git a/configs/imx8mn_venice_defconfig b/configs/imx8mn_venice_defconfig index fa3821fc3a..1e79543b7d 100644 --- a/configs/imx8mn_venice_defconfig +++ b/configs/imx8mn_venice_defconfig @@ -29,7 +29,6 @@ CONFIG_SPL_LOAD_FIT=y # CONFIG_USE_SPL_FIT_GENERATOR is not set CONFIG_OF_BOARD_SETUP=y CONFIG_OF_SYSTEM_SETUP=y -# CONFIG_USE_BOOTCOMMAND is not set CONFIG_USE_PREBOOT=y CONFIG_PREBOOT="gsc wd-disable" CONFIG_BOARD_LATE_INIT=y diff --git a/configs/imx8mp_dhcom_pdk2_defconfig b/configs/imx8mp_dhcom_pdk2_defconfig index ff8f53d239..e78b9a1569 100644 --- a/configs/imx8mp_dhcom_pdk2_defconfig +++ b/configs/imx8mp_dhcom_pdk2_defconfig @@ -86,6 +86,7 @@ CONFIG_MD5SUM_VERIFY=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_SHA1SUM=y CONFIG_SHA1SUM_VERIFY=y +CONFIG_CMD_BIND=y CONFIG_CMD_CLK=y CONFIG_CMD_DFU=y CONFIG_CMD_FUSE=y @@ -168,6 +169,7 @@ CONFIG_FASTBOOT_BUF_SIZE=0x20000000 CONFIG_FASTBOOT_FLASH=y CONFIG_FASTBOOT_FLASH_MMC_DEV=0 CONFIG_GPIO_HOG=y +CONFIG_SPL_GPIO_HOG=y CONFIG_MXC_GPIO=y CONFIG_DM_I2C=y # CONFIG_INPUT is not set @@ -238,20 +240,23 @@ CONFIG_DM_THERMAL=y CONFIG_IMX_TMU=y CONFIG_USB=y # CONFIG_SPL_DM_USB is not set +CONFIG_DM_USB_GADGET=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_XHCI_DWC3_OF_SIMPLE=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_DWC3=y -# CONFIG_USB_DWC3_GADGET is not set CONFIG_USB_DWC3_GENERIC=y CONFIG_USB_STORAGE=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="DH electronics" CONFIG_USB_GADGET_VENDOR_NUM=0x0525 CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 -CONFIG_CI_UDC=y CONFIG_SDP_LOADADDR=0x0 CONFIG_USB_FUNCTION_ACM=y +CONFIG_USB_ETHER=y +CONFIG_USB_ETH_CDC=y CONFIG_IMX_WATCHDOG=y CONFIG_OF_LIBFDT_OVERLAY=y diff --git a/configs/imx8mp_venice_defconfig b/configs/imx8mp_venice_defconfig index ded9b7ffec..f3f98aa536 100644 --- a/configs/imx8mp_venice_defconfig +++ b/configs/imx8mp_venice_defconfig @@ -29,7 +29,6 @@ CONFIG_SPL_LOAD_FIT=y # CONFIG_USE_SPL_FIT_GENERATOR is not set CONFIG_OF_BOARD_SETUP=y CONFIG_OF_SYSTEM_SETUP=y -# CONFIG_USE_BOOTCOMMAND is not set CONFIG_USE_PREBOOT=y CONFIG_PREBOOT="gsc wd-disable" CONFIG_BOARD_LATE_INIT=y diff --git a/configs/imxrt1170-evk_defconfig b/configs/imxrt1170-evk_defconfig new file mode 100644 index 0000000000..4edda391fd --- /dev/null +++ b/configs/imxrt1170-evk_defconfig @@ -0,0 +1,70 @@ +CONFIG_ARM=y +CONFIG_SYS_DCACHE_OFF=y +# CONFIG_SPL_SYS_DCACHE_OFF is not set +CONFIG_ARCH_IMXRT=y +CONFIG_SYS_TEXT_BASE=0x20240000 +CONFIG_SYS_MALLOC_LEN=0x8000 +CONFIG_SYS_MALLOC_F_LEN=0x8000 +CONFIG_SPL_GPIO=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_ENV_OFFSET=0x80000 +CONFIG_DM_GPIO=y +CONFIG_DEFAULT_DEVICE_TREE="imxrt1170-evk" +CONFIG_SPL_TEXT_BASE=0x202C0000 +CONFIG_TARGET_IMXRT1170_EVK=y +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y +CONFIG_SPL_SIZE_LIMIT=0x20000 +CONFIG_SPL=y +CONFIG_SYS_LOAD_ADDR=0x202C0000 +CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20340000 +CONFIG_SD_BOOT=y +# CONFIG_USE_BOOTCOMMAND is not set +CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_SPL_NO_BSS_LIMIT=y +CONFIG_SPL_BOARD_INIT=y +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +CONFIG_SPL_SYS_MALLOC_SIMPLE=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x100 +# CONFIG_SPL_CRC32 is not set +# CONFIG_BOOTM_NETBSD is not set +# CONFIG_BOOTM_PLAN9 is not set +# CONFIG_BOOTM_RTEMS is not set +# CONFIG_BOOTM_VXWORKS is not set +# CONFIG_CMD_MII is not set +# CONFIG_SPL_DOS_PARTITION is not set +# CONFIG_ISO_PARTITION is not set +# CONFIG_EFI_PARTITION is not set +CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_ENV_IS_NOWHERE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_SPL_DM=y +CONFIG_SPL_DM_SEQ_ALIAS=y +# CONFIG_OF_TRANSLATE is not set +CONFIG_SPL_CLK_COMPOSITE_CCF=y +CONFIG_CLK_COMPOSITE_CCF=y +CONFIG_SPL_CLK_IMXRT1170=y +CONFIG_CLK_IMXRT1170=y +# CONFIG_SPL_DM_GPIO is not set +CONFIG_MXC_GPIO=y +# CONFIG_INPUT is not set +CONFIG_FSL_USDHC=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_IMXRT=y +CONFIG_RAM=y +CONFIG_SPL_RAM=y +CONFIG_IMXRT_SDRAM=y +CONFIG_FSL_LPUART=y +CONFIG_TIMER=y +CONFIG_SPL_TIMER=y +CONFIG_IMX_GPT_TIMER=y diff --git a/configs/kontron_sl28_defconfig b/configs/kontron_sl28_defconfig index b0b5fb11ca..9112956e07 100644 --- a/configs/kontron_sl28_defconfig +++ b/configs/kontron_sl28_defconfig @@ -12,6 +12,7 @@ CONFIG_ENV_SECT_SIZE=0x10000 CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1028a-kontron-sl28" CONFIG_SPL_TEXT_BASE=0x18010000 CONFIG_SYS_FSL_SDHC_CLK_DIV=1 +CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL_SIZE_LIMIT=0x20000 CONFIG_SPL_SIZE_LIMIT_PROVIDE_STACK=0x0 @@ -46,9 +47,11 @@ CONFIG_SPL_BOARD_INIT=y # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_STACK=0x18009ff0 CONFIG_SYS_SPL_MALLOC=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x900 CONFIG_SPL_MPC8XXX_INIT_DDR=y CONFIG_SPL_SPI_LOAD=y -CONFIG_SYS_SPI_U_BOOT_OFFS=0x230000 +CONFIG_CMDLINE_PS_SUPPORT=y CONFIG_SYS_CBSIZE=256 CONFIG_SYS_PBSIZE=276 CONFIG_SYS_BOOTM_LEN=0x800000 diff --git a/configs/librem5_defconfig b/configs/librem5_defconfig new file mode 100644 index 0000000000..b022ae3637 --- /dev/null +++ b/configs/librem5_defconfig @@ -0,0 +1,151 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8M=y +CONFIG_SYS_TEXT_BASE=0x40200000 +CONFIG_SPL_GPIO=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0x3FE000 +CONFIG_SYS_I2C_MXC_I2C1=y +CONFIG_SYS_I2C_MXC_I2C2=y +CONFIG_SYS_I2C_MXC_I2C3=y +CONFIG_SYS_I2C_MXC_I2C4=y +CONFIG_DM_GPIO=y +CONFIG_DEFAULT_DEVICE_TREE="imx8mq-librem5-r4" +CONFIG_SPL_TEXT_BASE=0x7E1000 +CONFIG_TARGET_LIBREM5=y +CONFIG_SYS_PROMPT="u-boot=> " +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y +CONFIG_SPL_DRIVERS_MISC=y +CONFIG_SPL=y +CONFIG_IMX_BOOTAUX=y +CONFIG_SYS_LOAD_ADDR=0x40480000 +CONFIG_DISTRO_DEFAULTS=y +CONFIG_REMAKE_ELF=y +CONFIG_FIT=y +CONFIG_FIT_EXTERNAL_OFFSET=0x3000 +CONFIG_SPL_LOAD_FIT=y +# CONFIG_USE_SPL_FIT_GENERATOR is not set +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_BOOTDELAY=0 +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +# CONFIG_SYS_DEVICE_NULLDEV is not set +CONFIG_ARCH_MISC_INIT=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_BOARD_LATE_INIT=y +CONFIG_SPL_MAX_SIZE=0x25000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x180000 +CONFIG_SPL_BSS_MAX_SIZE=0x2000 +CONFIG_SPL_BOARD_INIT=y +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0x187ff0 +CONFIG_SYS_SPL_MALLOC=y +CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y +CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x42200000 +CONFIG_SYS_SPL_MALLOC_SIZE=0x80000 +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300 +CONFIG_SPL_I2C=y +CONFIG_SPL_POWER=y +CONFIG_SPL_USB_GADGET=y +CONFIG_SPL_USB_SDP_SUPPORT=y +CONFIG_SPL_WATCHDOG=y +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_PBSIZE=1050 +CONFIG_CMD_MEMTEST=y +CONFIG_SYS_ALT_MEMTEST=y +CONFIG_CMD_CLK=y +CONFIG_CMD_FUSE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_SDP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_SPL_DM=y +CONFIG_DEVRES=y +# CONFIG_SPL_BLK is not set +CONFIG_BUTTON=y +CONFIG_BUTTON_GPIO=y +CONFIG_SAVED_DRAM_TIMING_BASE=0x40000000 +CONFIG_DMA=y +CONFIG_DMA_CHANNELS=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x43000000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_UUU_SUPPORT=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=0 +CONFIG_FASTBOOT_MMC_BOOT_SUPPORT=y +CONFIG_FASTBOOT_MMC_USER_SUPPORT=y +CONFIG_FASTBOOT_CMD_OEM_PARTCONF=y +CONFIG_FASTBOOT_CMD_OEM_BOOTBUS=y +# CONFIG_SPL_DM_GPIO is not set +CONFIG_GPIO_HOG=y +CONFIG_DM_GPIO_LOOKUP_LABEL=y +CONFIG_MXC_GPIO=y +CONFIG_DM_I2C=y +# CONFIG_SPL_DM_I2C is not set +CONFIG_SPL_SYS_I2C_LEGACY=y +CONFIG_SYS_I2C_EARLY_INIT=y +CONFIG_SYS_MXC_I2C1_SPEED=50000 +CONFIG_SYS_MXC_I2C2_SPEED=50000 +CONFIG_SYS_MXC_I2C3_SPEED=50000 +CONFIG_SYS_MXC_I2C4_SPEED=50000 +CONFIG_SYS_I2C_SPEED=50000 +CONFIG_LED=y +CONFIG_LED_BLINK=y +CONFIG_LED_GPIO=y +CONFIG_MISC=y +CONFIG_PWRSEQ=y +CONFIG_MMC_BROKEN_CD=y +# CONFIG_SPL_DM_MMC is not set +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_ES_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_FSL_USDHC=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_PHY=y +CONFIG_PHY_IMX8MQ_USB=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX8M=y +CONFIG_POWER_LEGACY=y +CONFIG_POWER_DOMAIN=y +CONFIG_IMX8M_POWER_DOMAIN=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_POWER_I2C=y +CONFIG_DM_RESET=y +CONFIG_MXC_UART=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_MXC_SPI=y +CONFIG_DM_THERMAL=y +CONFIG_IMX_TMU=y +CONFIG_USB=y +CONFIG_DM_USB_GADGET=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GENERIC=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="Purism" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_SDP_LOADADDR=0x40400000 +CONFIG_USB_FUNCTION_ACM=y diff --git a/configs/mvebu_db-88f3720_defconfig b/configs/mvebu_db-88f3720_defconfig index 437d438f8f..a2a1efb7f0 100644 --- a/configs/mvebu_db-88f3720_defconfig +++ b/configs/mvebu_db-88f3720_defconfig @@ -4,7 +4,6 @@ CONFIG_ARCH_MVEBU=y CONFIG_SYS_TEXT_BASE=0x00000000 CONFIG_NR_DRAM_BANKS=1 CONFIG_TARGET_MVEBU_ARMADA_37XX=y -CONFIG_MVEBU_EFUSE=y CONFIG_ENV_SIZE=0x10000 CONFIG_ENV_OFFSET=0x3f0000 CONFIG_ENV_SECT_SIZE=0x10000 diff --git a/configs/mvebu_espressobin-88f3720_defconfig b/configs/mvebu_espressobin-88f3720_defconfig index dd1f912150..c9ea42a4e7 100644 --- a/configs/mvebu_espressobin-88f3720_defconfig +++ b/configs/mvebu_espressobin-88f3720_defconfig @@ -4,7 +4,6 @@ CONFIG_ARCH_MVEBU=y CONFIG_SYS_TEXT_BASE=0x00000000 CONFIG_NR_DRAM_BANKS=1 CONFIG_TARGET_MVEBU_ARMADA_37XX=y -CONFIG_MVEBU_EFUSE=y CONFIG_ENV_SIZE=0x10000 CONFIG_ENV_OFFSET=0x3F0000 CONFIG_ENV_SECT_SIZE=0x10000 diff --git a/configs/pogo_e02_defconfig b/configs/pogo_e02_defconfig index 15b883b6b0..6adb230e29 100644 --- a/configs/pogo_e02_defconfig +++ b/configs/pogo_e02_defconfig @@ -4,6 +4,9 @@ CONFIG_SYS_DCACHE_OFF=y CONFIG_ARCH_CPU_INIT=y CONFIG_SYS_THUMB_BUILD=y CONFIG_ARCH_KIRKWOOD=y +CONFIG_SUPPORT_PASSING_ATAGS=y +CONFIG_CMDLINE_TAG=y +CONFIG_INITRD_TAG=y CONFIG_SYS_KWD_CONFIG="board/cloudengines/pogo_e02/kwbimage.cfg" CONFIG_SYS_TEXT_BASE=0x600000 CONFIG_NR_DRAM_BANKS=2 diff --git a/configs/qemu-ppce500_defconfig b/configs/qemu-ppce500_defconfig index 7756f5f4ae..f48564c3f5 100644 --- a/configs/qemu-ppce500_defconfig +++ b/configs/qemu-ppce500_defconfig @@ -61,5 +61,4 @@ CONFIG_VIRTIO_PCI=y CONFIG_VIRTIO_NET=y CONFIG_VIRTIO_BLK=y CONFIG_ADDR_MAP=y -# CONFIG_BINMAN_FDT is not set CONFIG_PANIC_HANG=y diff --git a/configs/qemu-riscv32_smode_defconfig b/configs/qemu-riscv32_smode_defconfig index 1c5a0617aa..c3d13a5b8c 100644 --- a/configs/qemu-riscv32_smode_defconfig +++ b/configs/qemu-riscv32_smode_defconfig @@ -21,4 +21,3 @@ CONFIG_CMD_NVEDIT_EFI=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM_MTD=y CONFIG_SYS_MAX_FLASH_BANKS=2 -CONFIG_SYSRESET_SBI=y diff --git a/configs/qemu-riscv32_spl_defconfig b/configs/qemu-riscv32_spl_defconfig index 2421c9a371..a3a899efc8 100644 --- a/configs/qemu-riscv32_spl_defconfig +++ b/configs/qemu-riscv32_spl_defconfig @@ -25,5 +25,4 @@ CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM_MTD=y CONFIG_SYS_MAX_FLASH_BANKS=2 -CONFIG_SYSRESET_SBI=y # CONFIG_BINMAN_FDT is not set diff --git a/configs/qemu-riscv64_smode_defconfig b/configs/qemu-riscv64_smode_defconfig index 2861d07f97..1cb06b4b2c 100644 --- a/configs/qemu-riscv64_smode_defconfig +++ b/configs/qemu-riscv64_smode_defconfig @@ -24,4 +24,3 @@ CONFIG_CMD_NVEDIT_EFI=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM_MTD=y CONFIG_SYS_MAX_FLASH_BANKS=2 -CONFIG_SYSRESET_SBI=y diff --git a/configs/qemu-riscv64_spl_defconfig b/configs/qemu-riscv64_spl_defconfig index 1ecfa27ce2..68b16f0a2c 100644 --- a/configs/qemu-riscv64_spl_defconfig +++ b/configs/qemu-riscv64_spl_defconfig @@ -25,5 +25,4 @@ CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM_MTD=y CONFIG_SYS_MAX_FLASH_BANKS=2 -CONFIG_SYSRESET_SBI=y # CONFIG_BINMAN_FDT is not set diff --git a/configs/sheevaplug_defconfig b/configs/sheevaplug_defconfig index edbc2eefa3..6d1e59ef25 100644 --- a/configs/sheevaplug_defconfig +++ b/configs/sheevaplug_defconfig @@ -4,6 +4,9 @@ CONFIG_SYS_DCACHE_OFF=y CONFIG_ARCH_CPU_INIT=y CONFIG_SYS_THUMB_BUILD=y CONFIG_ARCH_KIRKWOOD=y +CONFIG_SUPPORT_PASSING_ATAGS=y +CONFIG_CMDLINE_TAG=y +CONFIG_INITRD_TAG=y CONFIG_SYS_KWD_CONFIG="board/Marvell/sheevaplug/kwbimage.cfg" CONFIG_SYS_TEXT_BASE=0x600000 CONFIG_NR_DRAM_BANKS=2 diff --git a/configs/stm32f769-disco_defconfig b/configs/stm32f769-disco_defconfig index 1333c060d1..423af7446a 100644 --- a/configs/stm32f769-disco_defconfig +++ b/configs/stm32f769-disco_defconfig @@ -50,6 +50,7 @@ CONFIG_ETH_DESIGNWARE=y CONFIG_DW_ALTDESCRIPTOR=y CONFIG_MII=y # CONFIG_PINCTRL_FULL is not set +CONFIG_DM_REGULATOR=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_STM32_QSPI=y diff --git a/configs/stm32f769-disco_spl_defconfig b/configs/stm32f769-disco_spl_defconfig index 16763e29c3..19d2c24abb 100644 --- a/configs/stm32f769-disco_spl_defconfig +++ b/configs/stm32f769-disco_spl_defconfig @@ -72,6 +72,7 @@ CONFIG_DW_ALTDESCRIPTOR=y CONFIG_MII=y # CONFIG_PINCTRL_FULL is not set CONFIG_SPL_PINCTRL=y +CONFIG_DM_REGULATOR=y CONFIG_SPL_RAM=y CONFIG_SPECIFY_CONSOLE_INDEX=y CONFIG_SPI=y diff --git a/configs/stm32mp15_defconfig b/configs/stm32mp15_defconfig index 4bc2e8e1d8..ec8fb37110 100644 --- a/configs/stm32mp15_defconfig +++ b/configs/stm32mp15_defconfig @@ -120,6 +120,7 @@ CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y CONFIG_DM_REGULATOR_STM32_VREFBUF=y CONFIG_DM_REGULATOR_STPMIC1=y +CONFIG_DM_REGULATOR_SCMI=y CONFIG_REMOTEPROC_STM32_COPRO=y CONFIG_RESET_SCMI=y CONFIG_DM_RNG=y diff --git a/configs/stm32mp15_dhcom_basic_defconfig b/configs/stm32mp15_dhcom_basic_defconfig index e1a557ec00..f47e70be44 100644 --- a/configs/stm32mp15_dhcom_basic_defconfig +++ b/configs/stm32mp15_dhcom_basic_defconfig @@ -108,6 +108,7 @@ CONFIG_DM_I2C=y CONFIG_SYS_I2C_STM32F7=y CONFIG_LED=y CONFIG_LED_GPIO=y +CONFIG_STM32_FMC2_EBI=y CONFIG_I2C_EEPROM=y CONFIG_SYS_I2C_EEPROM_ADDR=0x50 CONFIG_SUPPORT_EMMC_BOOT=y diff --git a/configs/stm32mp15_dhcor_basic_defconfig b/configs/stm32mp15_dhcor_basic_defconfig index 81eabeb358..02cce50691 100644 --- a/configs/stm32mp15_dhcor_basic_defconfig +++ b/configs/stm32mp15_dhcor_basic_defconfig @@ -105,6 +105,7 @@ CONFIG_DM_I2C=y CONFIG_SYS_I2C_STM32F7=y CONFIG_LED=y CONFIG_LED_GPIO=y +CONFIG_STM32_FMC2_EBI=y CONFIG_I2C_EEPROM=y CONFIG_SYS_I2C_EEPROM_ADDR=0x53 CONFIG_SUPPORT_EMMC_BOOT=y diff --git a/configs/turris_mox_defconfig b/configs/turris_mox_defconfig index 1df47fe3c9..21bd1bc4b3 100644 --- a/configs/turris_mox_defconfig +++ b/configs/turris_mox_defconfig @@ -4,7 +4,6 @@ CONFIG_ARCH_MVEBU=y CONFIG_SYS_TEXT_BASE=0x00000000 CONFIG_NR_DRAM_BANKS=2 CONFIG_TARGET_TURRIS_MOX=y -CONFIG_MVEBU_EFUSE=y CONFIG_ENV_SIZE=0x10000 CONFIG_ENV_OFFSET=0x180000 CONFIG_ENV_SECT_SIZE=0x10000 diff --git a/configs/turris_omnia_defconfig b/configs/turris_omnia_defconfig index bce14cc69d..ba635feb44 100644 --- a/configs/turris_omnia_defconfig +++ b/configs/turris_omnia_defconfig @@ -33,6 +33,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_BOOTDELAY=3 CONFIG_USE_PREBOOT=y +CONFIG_CONSOLE_MUX=y CONFIG_SYS_CONSOLE_INFO_QUIET=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y @@ -103,6 +104,7 @@ CONFIG_PINCTRL_ARMADA_38X=y CONFIG_DM_RTC=y CONFIG_RTC_ARMADA38X=y CONFIG_SCSI=y +CONFIG_SERIAL_PROBE_ALL=y CONFIG_SPL_DEBUG_UART_BASE=0xd0012000 CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYS_NS16550=y diff --git a/configs/uDPU_defconfig b/configs/uDPU_defconfig index 13d1d92b7b..3b0c5273ea 100644 --- a/configs/uDPU_defconfig +++ b/configs/uDPU_defconfig @@ -3,7 +3,6 @@ CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_MVEBU=y CONFIG_SYS_TEXT_BASE=0x00000000 CONFIG_TARGET_MVEBU_ARMADA_37XX=y -CONFIG_MVEBU_EFUSE=y CONFIG_ENV_SIZE=0x10000 CONFIG_ENV_OFFSET=0x180000 CONFIG_ENV_SECT_SIZE=0x10000 diff --git a/configs/verdin-imx8mm_defconfig b/configs/verdin-imx8mm_defconfig index 59534cd512..f65b4a7f30 100644 --- a/configs/verdin-imx8mm_defconfig +++ b/configs/verdin-imx8mm_defconfig @@ -15,10 +15,14 @@ CONFIG_SYS_PROMPT="Verdin iMX8MM # " CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y +CONFIG_BOOTCOUNT_BOOTLIMIT=3 +CONFIG_SYS_BOOTCOUNT_ADDR=0x30370090 CONFIG_SPL=y -CONFIG_SYS_LOAD_ADDR=0x40480000 +CONFIG_SYS_BOOTCOUNT_SINGLEWORD=y +CONFIG_SYS_LOAD_ADDR=0x48280000 CONFIG_SYS_MEMTEST_START=0x40000000 CONFIG_SYS_MEMTEST_END=0x80000000 +CONFIG_LTO=y CONFIG_DISTRO_DEFAULTS=y CONFIG_FIT=y CONFIG_FIT_EXTERNAL_OFFSET=0x3000 @@ -26,7 +30,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_SPL_LOAD_FIT=y # CONFIG_USE_SPL_FIT_GENERATOR is not set CONFIG_OF_SYSTEM_SETUP=y -# CONFIG_USE_BOOTCOMMAND is not set +CONFIG_BOOTDELAY=1 CONFIG_USE_PREBOOT=y CONFIG_PREBOOT="test -n ${fdtfile} || setenv fdtfile imx8mm-verdin-${variant}-${fdt_board}.dtb" CONFIG_LOG=y @@ -54,20 +58,26 @@ CONFIG_SYS_PBSIZE=2081 # CONFIG_BOOTM_NETBSD is not set CONFIG_CMD_ASKENV=y # CONFIG_CMD_EXPORTENV is not set -# CONFIG_CMD_CRC32 is not set +CONFIG_CRC32_VERIFY=y +CONFIG_CMD_MD5SUM=y +CONFIG_MD5SUM_VERIFY=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_CLK=y CONFIG_CMD_FUSE=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y +CONFIG_CMD_READ=y CONFIG_CMD_USB=y +CONFIG_CMD_BOOTCOUNT=y CONFIG_CMD_CACHE=y +CONFIG_CMD_TIME=y CONFIG_CMD_UUID=y +CONFIG_CMD_PMIC=y CONFIG_CMD_REGULATOR=y CONFIG_CMD_EXT4_WRITE=y # CONFIG_ISO_PARTITION is not set -# CONFIG_EFI_PARTITION is not set +# CONFIG_SPL_EFI_PARTITION is not set CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y @@ -76,11 +86,13 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SYS_MMC_ENV_PART=1 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_USE_ETHPRIME=y -CONFIG_ETHPRIME="FEC" +CONFIG_ETHPRIME="eth0" CONFIG_VERSION_VARIABLE=y CONFIG_IP_DEFRAG=y CONFIG_TFTP_BLOCKSIZE=4096 CONFIG_SPL_DM=y +CONFIG_BOOTCOUNT_LIMIT=y +CONFIG_SYS_BOOTCOUNT_MAGIC=0xB0C40000 CONFIG_SPL_CLK_COMPOSITE_CCF=y CONFIG_CLK_COMPOSITE_CCF=y CONFIG_SPL_CLK_IMX8MM=y @@ -91,11 +103,20 @@ CONFIG_DM_I2C=y CONFIG_MISC=y CONFIG_I2C_EEPROM=y CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_SPL_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_SPL_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_ES_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_SPL_MMC_HS400_SUPPORT=y CONFIG_FSL_USDHC=y CONFIG_PHYLIB=y CONFIG_PHY_ADDR_ENABLE=y CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y +CONFIG_PHY_FIXED=y +CONFIG_DM_MDIO=y CONFIG_FEC_MXC=y CONFIG_MII=y CONFIG_PINCTRL=y @@ -105,7 +126,6 @@ CONFIG_POWER_DOMAIN=y CONFIG_IMX8M_POWER_DOMAIN=y CONFIG_DM_PMIC=y CONFIG_SPL_DM_PMIC_PCA9450=y -CONFIG_DM_PMIC_PFUZE100=y CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y @@ -116,8 +136,11 @@ CONFIG_SPL_SYSRESET=y CONFIG_SYSRESET_PSCI=y CONFIG_SYSRESET_WATCHDOG=y CONFIG_DM_THERMAL=y +CONFIG_IMX_TMU=y CONFIG_USB=y -# CONFIG_SPL_DM_USB is not set CONFIG_USB_EHCI_HCD=y +CONFIG_USB_KEYBOARD=y +CONFIG_USB_HOST_ETHER=y CONFIG_IMX_WATCHDOG=y +CONFIG_HEXDUMP=y CONFIG_OF_LIBFDT_OVERLAY=y diff --git a/configs/verdin-imx8mp_defconfig b/configs/verdin-imx8mp_defconfig index 6168ee95c1..5d0c57c52e 100644 --- a/configs/verdin-imx8mp_defconfig +++ b/configs/verdin-imx8mp_defconfig @@ -22,7 +22,7 @@ CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y CONFIG_IMX_BOOTAUX=y CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000 -CONFIG_SYS_LOAD_ADDR=0x43500000 +CONFIG_SYS_LOAD_ADDR=0x48280000 CONFIG_SYS_MEMTEST_START=0x40000000 CONFIG_SYS_MEMTEST_END=0x80000000 CONFIG_DISTRO_DEFAULTS=y diff --git a/disk/part.c b/disk/part.c index 5705c229d5..47214c0ee9 100644 --- a/disk/part.c +++ b/disk/part.c @@ -457,7 +457,7 @@ int blk_get_device_part_str(const char *ifname, const char *dev_part_str, } #endif -#ifdef CONFIG_CMD_UBIFS +#if IS_ENABLED(CONFIG_CMD_UBIFS) && !IS_ENABLED(CONFIG_SPL_BUILD) /* * Special-case ubi, ubi goes through a mtd, rather than through * a regular block device. diff --git a/doc/Makefile b/doc/Makefile index 6081858726..f5de65e927 100644 --- a/doc/Makefile +++ b/doc/Makefile @@ -58,6 +58,7 @@ quiet_cmd_sphinx = SPHINX $@ --> file://$(abspath $(BUILDDIR)/$3/$4) $(SPHINXBUILD) \ -j$(shell nproc) \ -b $2 \ + -j auto \ -c $(abspath $(srctree)/$(src)) \ -d $(abspath $(BUILDDIR)/.doctrees/$3) \ -D version=$(KERNELVERSION) -D release=$(KERNELRELEASE) \ diff --git a/doc/board/index.rst b/doc/board/index.rst index 01b99f9cf5..53edd5301f 100644 --- a/doc/board/index.rst +++ b/doc/board/index.rst @@ -28,6 +28,7 @@ Board-specific doc nokia/index nxp/index openpiton/index + purism/index qualcomm/index rockchip/index samsung/index diff --git a/doc/board/purism/index.rst b/doc/board/purism/index.rst new file mode 100644 index 0000000000..a9cdc312d4 --- /dev/null +++ b/doc/board/purism/index.rst @@ -0,0 +1,9 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +Purism SPC +========== + +.. toctree:: + :maxdepth: 2 + + librem5 diff --git a/doc/board/purism/librem5.rst b/doc/board/purism/librem5.rst new file mode 100644 index 0000000000..fb050c6302 --- /dev/null +++ b/doc/board/purism/librem5.rst @@ -0,0 +1,60 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +Librem5 +========== + +U-Boot for the Purism Librem5 phone + +Quick Start +----------- + +- Build the ARM Trusted firmware binary +- Get ddr and hdmi firmware +- Build U-Boot + +Get and Build the ARM Trusted firmware +-------------------------------------- + +Note: srctree is U-Boot source directory +Get ATF from: https://source.puri.sm/Librem5/arm-trusted-firmware +branch: librem5 + +.. code-block:: bash + + $ make PLAT=imx8mq CROSS_COMPILE=aarch64-linux-gnu- bl31 + $ cp build/imx8mq/release/bl31.bin $(builddir) + +Get the ddr and display port firmware +------------------------------------- + +.. code-block:: bash + + $ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.15.bin + $ chmod +x firmware-imx-8.15.bin + $ ./firmware-imx-8.15.bin + $ cp firmware-imx-8.15/firmware/hdmi/cadence/signed_dp_imx8m.bin $(builddir) + $ cp firmware-imx-8.15/firmware/ddr/synopsys/lpddr4*.bin $(builddir) + +Build U-Boot +------------ + +.. code-block:: bash + + $ export CROSS_COMPILE=aarch64-linux-gnu- + $ make librem5_defconfig + $ make ARCH=arm + +Burn the flash.bin +------------------ + +Use uuu to burn flash.bin. Power on the phone while holding vol+ to get it +into uuu mode. + +.. code-block:: bash + + $ git clone https://source.puri.sm/Librem5/librem5-devkit-tools.git + $ cd librem5-devkit-tools + $ cp $(builddir)/flash.bin files/u-boot-librem5.imx + $ uuu uuu_scripts/u-boot_flash_librem5.lst + +Reboot the phone. diff --git a/doc/develop/bootstd.rst b/doc/develop/bootstd.rst index f7fc725707..1ccc49424e 100644 --- a/doc/develop/bootstd.rst +++ b/doc/develop/bootstd.rst @@ -322,7 +322,7 @@ look like this:: The `sf-bootdev` driver can implement a way to read from the SPI flash, using the offset and size provided, and return that bootflow file back to the caller. -When distro boot wants to read the kernel it calls disto_getfile() which must +When distro boot wants to read the kernel it calls distro_getfile() which must provide a way to read from the SPI flash. See `distro_boot()` at distro_boot_ for more details. diff --git a/doc/develop/index.rst b/doc/develop/index.rst index ce6b38e576..5934d9ffb1 100644 --- a/doc/develop/index.rst +++ b/doc/develop/index.rst @@ -11,6 +11,7 @@ General codingstyle designprinciples + patman process release_cycle system_configuration diff --git a/doc/develop/process.rst b/doc/develop/process.rst index 388945cf9b..0fa0143bf3 100644 --- a/doc/develop/process.rst +++ b/doc/develop/process.rst @@ -108,6 +108,8 @@ Differences to the Linux Development Process In U-Boot, ``"-rc1"`` will only be released after all (or at least most of the) patches that were submitted during the merge window have been applied. +.. _custodians: + Custodians ---------- @@ -127,31 +129,88 @@ patch, these should leave no doubt if they were just comments and the patch will be accepted anyway, or if the patch should be reworked/resubmitted, or if it was rejected. +Review Process, Git Tags +------------------------ + +There are a number of *git tags* that are used to document the origin and the +processing of patches on their way into the mainline U-Boot code. The following +is an attempt to document how these are usually handled in the U-Boot project. + +In general, we try to follow the established procedures from other projects, +especially the Linux kernel, but there may be smaller differences. For +reference, see the Linux kernel's `Submitting patches +`_ +document. + +.. _dco: + +* Signed-off-by: the *Signed-off-by:* is a line at the end of the commit + message by which the signer certifies that they were involved in the development + of the patch and that they accept the `Developer Certificate of Origin + `_. Following this and adding a + ``Signed-off-by:`` line that contains the developer's name and email address + is required. + + * Please note that in U-Boot, we do not add a ``Signed-off-by`` tag if we + just pass on a patch without any changes. + + * Please note that when importing code from other projects you must say + where it comes from, and what revision you are importing. You must not + however copy ``Signed-off-by`` or other tags. + +* Everybody who can is invited to review and test the changes. Typically, we + follow the same guidelines as the Linux kernel for `Acked-by + `_ + as well as `Reviewed-by + `_ + and similar additional tags. + +* Reviewed-by: The patch has been reviewed and found acceptible according to + the `Reveiwer's statement of oversight + `_. + A *Reviewed-by:* tag is a statement of opinion that the patch is an + appropriate modification of the code without any remaining serious technical + issues. Any interested reviewer (who has done the work) can offer a + *Reviewed-by:* tag for a patch. + +* Acked-by: If a person was not directly involved in the preparation or + handling of a patch but wishes to signify and record their approval of it + then they can arrange to have an *Acked-by:* line added to the patch's + changelog. + +* Tested-by: A *Tested-by:* tag indicates that the patch has been successfully + tested (in some environment) by the person named. Andrew Morton: "I think + it's very useful information to have. For a start, it tells you who has the + hardware and knows how to build a kernel. So if you're making a change to a + driver and want it tested, you can troll the file's changelog looking for + people who might be able to help." + +* Reported-by: If this patch fixes a problem reported by somebody else, + consider adding a *Reported-by:* tag to credit the reporter for their + contribution. Please note that this tag should not be added without the + reporter's permission, especially if the problem was not reported in a public + forum. + +* Cc: If a person should have the opportunity to comment on a patch, you may + optionally add a *Cc:* tag to the patch. Git tools (git send-email) will then + automatically arrange that they receives a copy of the patch when you submit it + to the mainling list. This is the only tag which might be added without an + explicit action by the person it names. This tag documents that potentially + interested parties have been included in the discussion. + For example, when your change affects a specific board or driver, then makes + a lot of sense to put the respective maintainer of this code on Cc: + Work flow of a Custodian ------------------------ The normal flow of work in the U-Boot development process will look like this: -#. A developer submits a patch via e-mail to the u-boot mailing list. In - U-Boot, we make use of the `Developer Certificate of Origin - `_ that is common in other projects such - as the Linux kernel. Following this and adding a ``Signed-off-by:`` line - that contains the developer's name and email address is required. - - * Please note that when importing code from other projects you must say - where it comes from, and what revision you are importing. You must not - however copy ``Signed-off-by`` or other tags. - -#. Everybody who can is invited to review and test the changes. Typically, we - follow the same guidelines as the Linux kernel for `Acked-by - `_ - as well as `Reviewed-by - `_ - and similar additional tags. - #. The responsible custodian inspects this patch, especially for: + #. The commit message is useful, descriptive and makes correct and + appropraite usage of required *git tags*. + #. :doc:`codingstyle` #. Basic logic: diff --git a/doc/develop/release_cycle.rst b/doc/develop/release_cycle.rst index b75576cb57..7d8a610779 100644 --- a/doc/develop/release_cycle.rst +++ b/doc/develop/release_cycle.rst @@ -68,9 +68,9 @@ For the next scheduled release, release candidates were made on:: * U-Boot v2022.10-rc3 was released on Mon 22 August 2022. -.. * U-Boot v2022.10-rc4 was released on Mon 05 September 2022. +* U-Boot v2022.10-rc4 was released on Mon 05 September 2022. -.. * U-Boot v2022.10-rc5 was released on Mon 19 September 2022. +* U-Boot v2022.10-rc5 was released on Mon 19 September 2022. Please note that the following dates are planned only and may be deviated from as needed. diff --git a/doc/develop/sending_patches.rst b/doc/develop/sending_patches.rst index 0542adeaed..173075687e 100644 --- a/doc/develop/sending_patches.rst +++ b/doc/develop/sending_patches.rst @@ -3,14 +3,452 @@ Sending patches =============== -.. toctree:: - :maxdepth: 2 +*Before you begin* to implement any new ideas or concepts it is always a good +idea to present your plans on the `U-Boot mailing list +`_. U-Boot supports a huge amount of +very different systems, and it is often impossible for the individual developer +to oversee the consequences of a specific change to all architectures. +Discussing concepts early can help you to avoid spending effort on code which, +when submitted as a patch, might be rejected and/or will need lots of rework +because it does not fit for some reason. Early peer review is an important +resource - use it. Being familiar with the :doc:`process` is also important. - patman +A good introduction how to prepare for submitting patches can be found in the +LWN article `How to Get Your Change Into the Linux Kernel +`_ as the same rules apply to U-Boot, too. +Using patman +------------ You can use a tool called patman to prepare, check and sent patches. It creates change logs, cover letters and patch notes. It also simplified the process of sending multiple versions of a series. See more details at :doc:`patman`. + +General Patch Submission Rules +------------------------------ + +* All patches must be sent to the `u-boot@lists.denx.de + `_ mailing list. + +* If your patch affects the code maintained by one of the :ref:`custodians`, CC + them when emailing your patch. The easiest way to make sure you don't forget + this even when you resubmit the patch later is to add a ``Cc: name +
`` line after your ``Signed-off-by:`` line (see the example below). + +* Take a look at the commit logs of the files you are modifying. Authors of + past commits might have input to your change, so also CC them if you think + they may have feedback. + +* Patches should always contain exactly one complete logical change, i. e. + + * Changes that contain different, unrelated modifications shall be submitted + as *separate* patches, one patch per changeset. + + * If one logical set of modifications affects or creates several files, all + these changes shall be submitted in a *single* patch. + +* Non-functional changes, i.e. whitespace and reformatting changes, should be + done in separate patches marked as ``cosmetic``. This separation of functional + and cosmetic changes greatly facilitates the review process. + +* Some comments on running :doc:`checkpatch.pl `: + + * Checkpatch is a tool that can help you find some style problems, but is + imperfect, and the things it complains about are of varying importance. + So use common sense in interpreting the results. + + * Warnings that clearly only make sense in the Linux kernel can be ignored. + This includes ``Use #include instead of `` for + example. + + * If you encounter warnings for existing code, not modified by your patch, + consider submitting a separate, cosmetic-only patch -- clearly described + as such -- that *precedes* your substantive patch. + + * For minor modifications (e.g. changed arguments of a function call), + adhere to the present codingstyle of the module. Relating checkpatch + warnings can be ignored in this case. A respective note in the commit or + cover letter why they are ignored is desired. + +* Send your patches as plain text messages: no HTML, no MIME, no links, no + compression, no attachments. Just plain text. The best way the generate + patches is by using the ``git format-patch`` command. Please use the + ``master`` branch of the mainline U-Boot git repository + (``https://source.denx.de/u-boot/u-boot.git``) as reference, unless (usually + late in a release cycle) there has been an announcement to use the ``next`` + branch of this repository instead. + +* Make sure that your mailer does not mangle the patch by automatic changes + like wrapping of longer lines etc. + The best way to send patches is by not using your regular mail tool, but by + using either ``git send-email`` or the ``git imap-send`` command instead. + If you believe you need to use a mailing list for testing (instead of any + regular mail address you own), we have a special test list for such purposes. + It would be best to subscribe to the list for the duration of your tests to + avoid repeated moderation - see https://lists.denx.de/listinfo/test + +* Choose a meaningful Subject: - keep in mind that the Subject will also be + visible as headline of your commit message. Make sure the subject does not + exceed 60 characters or so. + +* The start of the subject should be a meaningfull tag (arm:, ppc:, tegra:, + net:, ext2:, etc) + +* Include the string "PATCH" in the Subject: line of your message, e. g. + "[PATCH] Add support for feature X". ``git format-patch`` should automatically + do this. + +* If you are sending a patch series composed of multiple patches, make sure + their titles clearly state the patch order and total number of patches (``git + format-patch -n``). Also, often times an introductory email describing what + the patchset does is useful (``git format-patch -n --cover-letter``). As an + example:: + + [PATCH 0/3] Add support for new SuperCPU2000 + (This email does not contain a patch, just a description) + [PATCH 1/3] Add core support for SuperCPU2000 + [PATCH 2/3] Add support for SuperCPU2000's on-chip I2C controller + [PATCH 3/3] Add support for SuperCPU2000's on-chip UART + +* In the message body, include a description of your changes. + + * For bug fixes: a description of the bug and how your patch fixes this bug. + Please try to include a way of demonstrating that the patch actually fixes + something. + + * For new features: a description of the feature and your implementation. + +* Additional comments which you don't want included in U-Boot's history can be + included below the first "---" in the message body. + +* If your description gets too long, that's a strong indication that you should + split up your patch. + +* Remember that there is a size limit of 100 kB on the mailing list. In most + cases, you did something wrong if your patch exceeds this limit. Think again + if you should not split it into separate logical parts. + +Attributing Code, Copyrights, Signing +------------------------------------- + +* Sign your changes, i. e. add a *Signed-off-by:* line to the message body. + This can be automated by using ``git commit -s``. Please see the + :ref:`Developer Certificate of Origin ` section for more details here. + +* If you change or add *significant* parts to a file, then please make sure to + add your copyright to that file, for example like this:: + + (C) Copyright 2010 Joe Hacker + + Please do *not* include a detailed description of your + changes. We use the *git* commit messages for this purpose. + +* If you add new files, please always make sure that these contain your + copyright note and a GPLv2+ SPDX-License-Identifier, for example like this:: + + (C) Copyright 2010 Joe Hacker + + SPDX-License-Identifier:GPL-2.0+ + +* If you are copying or adapting code from other projects, like the Linux + kernel, or BusyBox, or similar, please make sure to state clearly where you + copied the code from, and provide terse but precise information which exact + version or even commit ID was used. Follow the ideas of this note from the + Linux "SubmittingPatches" document:: + + Special note to back-porters: It seems to be a common and useful practice + to insert an indication of the origin of a patch at the top of the commit + message (just after the subject line) to facilitate tracking. For instance, + here's what we see in 2.6-stable : + + Date: Tue May 13 19:10:30 2008 +0000 + + SCSI: libiscsi regression in 2.6.25: fix nop timer handling + + commit 4cf1043593db6a337f10e006c23c69e5fc93e722 upstream + + And here's what appears in 2.4 : + + Date: Tue May 13 22:12:27 2008 +0200 + + wireless, airo: waitbusy() won't delay + + [backport of 2.6 commit b7acbdfbd1f277c1eb23f344f899cfa4cd0bf36a] + +Whatever the format, this information provides a valuable help to people +tracking your trees, and to people trying to trouble-shoot bugs in your +tree. + +Commit message conventions +-------------------------- + +Please adhere to the following conventions when writing your commit +log messages. + +* The first line of the log message is the summary line. Keep this less than 70 + characters long. + +* Don't use periods to end the summary line (e.g., don't do "Add support for + X.") + +* Use the present tense in your summary line (e.g., "Add support for X" rather + than "Added support for X"). Furthermore, use the present tense in your log + message to describe what the patch is doing. This isn't a strict rule -- it's + OK to use the past tense for describing things that were happening in the old + code for example. + +* Use the imperative tense in your summary line (e.g., "Add support for X" + rather than "Adds support for X"). In general, you can think of the summary + line as "this commit is meant to 'Add support for X'" + +* If applicable, prefix the summary line with a word describing what area of + code is being affected followed by a colon. This is a standard adopted by + both U-Boot and Linux. For example, if your change affects all mpc85xx + boards, prefix your summary line with "mpc85xx:". If your change affects the + PCI common code, prefix your summary line with "pci:". The best thing to do + is look at the "git log " output to see what others have done so you + don't break conventions. + +* Insert a blank line after the summary line + +* For bug fixes, it's good practice to briefly describe how things behaved + before this commit + +* Put a detailed description after the summary and blank line. If the summary + line is sufficient to describe the change (e.g. it is a trivial spelling + correction or whitespace update), you can omit the blank line and detailed + description. + +* End your log message with S.O.B. (Signed-off-by) line. This is done + automatically when you use ``git commit -s``. Please see the + :ref:`Developer Certificate of Origin ` section for more details here. + +* Keep EVERY line under 72 characters. That is, your message should be + line-wrapped with line-feeds. However, don't get carried away and wrap it too + short either since this also looks funny. + +* Detail level: The audience of the commit log message that you should cater to + is those familiar with the underlying source code you are modifying, but who + are _not_ familiar with the patch you are submitting. They should be able to + determine what is being changed and why. Avoid excessive low-level detail. + Before submitting, re-read your commit log message with this audience in mind + and adjust as needed. + +Sending updated patch versions +------------------------------ + +It is pretty normal that the first version of a patch you are submitting does +not get accepted as is, and that you are asked to submit another, improved +version. + +When re-posting such a new version of your patch(es), please always make sure +to observe the following rules. + +* Make an appropriate note that this is a re-submission in the subject line, + eg. "[PATCH v2] Add support for feature X". ``git format-patch + --subject-prefix="PATCH v2"`` can be used in this case (see the example + below). + +* Please make sure to keep a "change log", i. e. a description of what you have + changed compared to previous versions of this patch. This change log should + be added below the "---" line in the patch, which starts the "comment + section", i. e. which contains text that does not get included into the + actual commit message. + Note: it is *not* sufficient to provide a change log in some cover letter + that gets sent as a separate message with the patch series. The reason is + that such cover letters are not as easily reviewed in our `patchwork queue + `_ so they are not helpful + to any reviewers using this tool. Example:: + + From: Joe Hacker + Date: Thu, 1 Jan 2222 12:21:22 +0200 + Subject: [PATCH 1/2 v3] FOO: add timewarp-support + + This patch adds timewarp-support for the FOO family of processors. + + adapted for the current kernel structures. + + Signed-off-by: Joe Hacker + Cc: Tom Maintainer + --- + Changes for v2: + - Coding Style cleanup + - fixed miscalculation of time-space discontinuities + Changes for v3: + - fixed compiler warnings observed with GCC-17.3.5 + - worked around integer overflow in warp driver + + arch/foo/cpu/spacetime.c | 8 + + drivers/warp/Kconfig | 7 + + drivers/warp/Makefile | 42 +++ + drivers/warp/warp-core.c | 255 +++++++++++++++++++++++++ + +* Make sure that your mailer adds or keeps correct ``In-reply-to:`` and + ``References:`` headers, so threading of messages is working and everybody + can see that the new message refers to some older posting of the same topic. + +Uncommented and un-threaded repostings are extremely annoying and +time-consuming, as we have to try to remember if anything similar has been +posted before, look up the old threads, and then manually compare if anything +has been changed, or what. + +If you have problems with your e-mail client, for example because it mangles +white space or wraps long lines, then please read this article about `Email +Clients and Patches `_. + +Notes +----- + +1. U-Boot is Free Software that can redistributed and/or modified under the + terms of the `GNU General Public License + `_ (GPL). Currently (August + 2022) version 2 of the GPL applies. Please see :download:`Licensing + <../../Licenses/README>` for details. To allow that later versions of U-Boot + may be released under a later version of the GPL, all new code that gets + added to U-Boot shall use a "GPL-2.0+" SPDX-License-Identifier. + +2. All code must follow the :doc:`codingstyle` requirements. + +3. Before sending the patch, you *must* run some form of local testing. + Submitting a patch that does not build or function correct is a mistake. For + non-trivial patches, either building a number of platforms locally or making + use of :doc:`ci_testing` is strongly encouraged in order to avoid problems + that can be found when attempting to merge the patch. + +4. If you modify existing code, make sure that your new code does not add to + the memory footprint of the code. Remember: Small is beautiful! When adding + new features follow the guidelines laid out in :doc:`system_configuration`. + +Patch Tracking +-------------- + +Like some other projects, U-Boot uses `Patchwork `_ +to track the state of patches. This is one of the reasons why it is mandatory +to submit all patches to the U-Boot mailing list - only then they will be +picked up by patchwork. + +At http://patchwork.ozlabs.org/project/uboot/list/ you can find the list of +open U-Boot patches. By using the "Filters" link (Note: requires JavaScript) +you can also select other views, for example, to include old patches that have, +for example, already been applied or rejected. + +Note that Patchwork automatically tracks and collects a number of git tags from +follow-up mails, so it is usually better to apply a patch through the Patchwork +commandline interface than just manually applying it from a posting on the +mailing list (in which case you have to do all the tracking and adding of git +tags yourself). This also obviates the need of a developer to resubmit a patch +only in order to collect these tags. + +A Custodian has additional privileges and can: + +* **Delegate** a patch + +* **Change the state** of a patch. The following states exist: + + * New + + * Under Review + + * Accepted + + * Rejected + + * RFC + + * Not Applicable + + * Changes Requested + + * Awaiting Upstream + + * Superseeded + + * Deferred + + * Archived + +Patchwork work-flow +^^^^^^^^^^^^^^^^^^^ + +The following are a "rule of thumb" as to how the states are used in patchwork +today. Not all states are used by all custodians. + +* New: Patch has been submitted to the list, and none of the maintainers has + changed it's state since. + +* Under Review: A custodian is reviewing the patch currently. + +* Accepted: When a patch has been applied to a custodian repository that gets + used for pulling from into upstream, they are put into "accepted" state. + +* Rejected: Rejected means we just don't want to do what the patch does. + +* RFC: The patch is not intended to be applied to any of the mainline + repositories, but merely for discussing or testing some idea or new feature. + +* Not Applicable: The patch either was not intended to be applied, as it was + a debugging or discussion aide that patchwork picked up, or was cross-posted + to our list but intended for another project entirely. + +* Changes Requested: The patch looks mostly OK, but requires some rework before + it will be accepted for mainline. + +* Awaiting Upstream: A custodian may have applied this to the ``next`` branch + and has not merged yet to master, or has queued the patch up to be submitted + to be merged, but has not yet. + +* Superseeded: Patches are marked as 'superseeded' when the poster submits a + new version of these patches. + +* Deferred: Deferred usually means the patch depends on something else that + isn't upstream, such as patches that only apply against some specific other + repository. This is also used when a patch has been in patchwork for over a + year and it is unlikely to be applied as-is. + +* Archived: Archiving puts the patch away somewhere where it doesn't appear in + the normal pages and needs extra effort to get to. + +Apply patches +^^^^^^^^^^^^^ + +To apply a patch from the `patchwork queue +`_ using ``git``, download the +mbox file and apply it using:: + + git am file + +The `openembedded wiki `_ also provides a script +named `pw-am.sh +`_ +which can be used to fetch an 'mbox' patch from patchwork and git am it:: + + usage: pw-am.sh + example: 'pw-am.sh 71002' will get and apply the patch from http://patchwork.ozlabs.org/patch/71002/ + +Update the state of patches +^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +You have to register to be able to update the state of patches. You can use the +Web interface, `pwclient`, or `pwparser`. + +pwclient +^^^^^^^^ + +The `pwclient` command line tool can be used for example to retrieve patches, +search the queue or update the state. + +All necessary information for `pwclient` is linked from the bottom of +http://patchwork.ozlabs.org/project/uboot/ + +Use:: + + pwclient help + +for an overview on how to use it. + +pwparser +^^^^^^^^ + +See http://www.mail-archive.com/patchwork@lists.ozlabs.org/msg00057.html diff --git a/doc/device-tree-bindings/firmware/fwu-mdata-mtd.yaml b/doc/device-tree-bindings/firmware/fwu-mdata-mtd.yaml new file mode 100644 index 0000000000..4f5404f999 --- /dev/null +++ b/doc/device-tree-bindings/firmware/fwu-mdata-mtd.yaml @@ -0,0 +1,38 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/firmware/u-boot,fwu-mdata-sf.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: FWU metadata on MTD device without GPT + +maintainers: + - Masami Hiramatsu + +properties: + compatible: + items: + - const: u-boot,fwu-mdata-mtd + + fwu-mdata-store: + maxItems: 1 + description: Phandle of the MTD device which contains the FWU medatata. + + mdata-offsets: + minItems: 2 + description: Offsets of the primary and secondary FWU metadata in the NOR flash. + +required: + - compatible + - fwu-mdata-store + - mdata-offsets + +additionalProperties: false + +examples: + - | + fwu-mdata { + compatible = "u-boot,fwu-mdata-mtd"; + fwu-mdata-store = <&spi-flash>; + mdata-offsets = <0x500000 0x530000>; + }; diff --git a/doc/imx/habv4/csf_examples/mx8m/csf.sh b/doc/imx/habv4/csf_examples/mx8m/csf.sh new file mode 100644 index 0000000000..6898513be5 --- /dev/null +++ b/doc/imx/habv4/csf_examples/mx8m/csf.sh @@ -0,0 +1,77 @@ +#!/bin/sh + +# 0) Generate keys +# +# WARNING: ECDSA keys are only supported by HAB 4.5 and newer (i.e. i.MX8M Plus) +# +# cd /path/to/cst-3.3.1/keys/ +# ./hab4_pki_tree.sh -existing-ca n -use-ecc n -kl 4096 -duration 10 -num-srk 4 -srk-ca y +# cd /path/to/cst-3.3.1/crts/ +# ../linux64/bin/srktool -h 4 -t SRK_1_2_3_4_table.bin -e SRK_1_2_3_4_fuse.bin -d sha256 -c ./SRK1_sha256_4096_65537_v3_ca_crt.pem,./SRK2_sha256_4096_65537_v3_ca_crt.pem,./SRK3_sha256_4096_65537_v3_ca_crt.pem,./SRK4_sha256_4096_65537_v3_ca_crt.pem -f 1 + +# 1) Build U-Boot (e.g. for i.MX8MM) +# +# export ATF_LOAD_ADDR=0x920000 +# cp -Lv /path/to/arm-trusted-firmware/build/imx8mm/release/bl31.bin . +# cp -Lv /path/to/firmware-imx-8.14/firmware/ddr/synopsys/ddr3* . +# make -j imx8mm_board_defconfig +# make -j`nproc` flash.bin + +# 2) Sign SPL and DRAM blobs + +cp doc/imx/habv4/csf_examples/mx8m/csf_spl.txt csf_spl.tmp +cp doc/imx/habv4/csf_examples/mx8m/csf_fit.txt csf_fit.tmp + +spl_block_base=$(printf "0x%x" $(( $(sed -n "/CONFIG_SPL_TEXT_BASE=/ s@.*=@@p" .config) - 0x40)) ) +spl_block_size=$(printf "0x%x" $(stat -tc %s u-boot-spl-ddr.bin)) +sed -i "/Blocks = / s@.*@ Blocks = $spl_block_base 0x0 $spl_block_size \"flash.bin\"@" csf_spl.tmp + +# Generate CSF blob +cst -i csf_spl.tmp -o csf_spl.bin + +# Patch CSF blob into flash.bin +spl_csf_offset=$(xxd -s 24 -l 4 -e flash.bin | cut -d " " -f 2 | sed "s@^@0x@") +spl_bin_offset=$(xxd -s 4 -l 4 -e flash.bin | cut -d " " -f 2 | sed "s@^@0x@") +spl_dd_offset=$((${spl_csf_offset} - ${spl_bin_offset} + 0x40)) +dd if=csf_spl.bin of=flash.bin bs=1 seek=${spl_dd_offset} conv=notrunc + +# 3) Sign u-boot.itb + +# fitImage tree +fit_block_base=$(printf "0x%x" $(( $(sed -n "/CONFIG_SYS_TEXT_BASE=/ s@.*=@@p" .config) - $(sed -n "/CONFIG_FIT_EXTERNAL_OFFSET=/ s@.*=@@p" .config) - 0x200 - 0x40)) ) +fit_block_offset=$(printf "0x%s" $(fdtget -t x u-boot.dtb /binman/imx-boot/uboot offset)) +fit_block_size=$(printf "0x%x" $(( ( $(fdtdump u-boot.itb 2>/dev/null | sed -n "/^...totalsize:/ s@.*\(0x[0-9a-f]\+\).*@\1@p") + 0x1000 - 0x1 ) & ~(0x1000 - 0x1) + 0x20 )) ) +sed -i "/Blocks = / s@.*@ Blocks = $fit_block_base $fit_block_offset $fit_block_size \"flash.bin\", \\\\@" csf_fit.tmp + +# U-Boot +uboot_block_base=$(printf "0x%s" $(fdtget -t x u-boot.itb /images/uboot load)) +uboot_block_offset=$(printf "0x%x" $(( $(printf "0x%s" $(fdtget -t x u-boot.itb /images/uboot data-position)) + ${fit_block_offset} ))) +uboot_block_size=$(printf "0x%s" $(fdtget -t x u-boot.itb /images/uboot data-size)) +sed -i "/0xuuuu/ s@.*@ $uboot_block_base $uboot_block_offset $uboot_block_size \"flash.bin\", \\\\@" csf_fit.tmp + +# ATF +atf_block_base=$(printf "0x%s" $(fdtget -t x u-boot.itb /images/atf load)) +atf_block_offset=$(printf "0x%x" $(( $(printf "0x%s" $(fdtget -t x u-boot.itb /images/atf data-position)) + ${fit_block_offset} ))) +atf_block_size=$(printf "0x%s" $(fdtget -t x u-boot.itb /images/atf data-size)) +sed -i "/0xaaaa/ s@.*@ $atf_block_base $atf_block_offset $atf_block_size \"flash.bin\", \\\\@" csf_fit.tmp + +# DTB +dtb_block_base=$(printf "0x%x" $(( ${uboot_block_base} + ${uboot_block_size} ))) +dtb_block_offset=$(printf "0x%x" $(( $(printf "0x%s" $(fdtget -t x u-boot.itb /images/fdt-1 data-position)) + ${fit_block_offset} ))) +dtb_block_size=$(printf "0x%s" $(fdtget -t x u-boot.itb /images/fdt-1 data-size)) +sed -i "/0xdddd/ s@.*@ $dtb_block_base $dtb_block_offset $dtb_block_size \"flash.bin\"@" csf_fit.tmp + +# IVT +ivt_ptr_base=$(printf "%08x" ${fit_block_base} | sed "s@\(..\)\(..\)\(..\)\(..\)@0x\4\3\2\1@") +ivt_block_base=$(printf "%08x" $(( ${fit_block_base} + ${fit_block_size} - 0x20 )) | sed "s@\(..\)\(..\)\(..\)\(..\)@0x\4\3\2\1@") +csf_block_base=$(printf "%08x" $(( ${fit_block_base} + ${fit_block_size} )) | sed "s@\(..\)\(..\)\(..\)\(..\)@0x\4\3\2\1@") +ivt_block_offset=$((${fit_block_offset} + ${fit_block_size} - 0x20)) +csf_block_offset=$((${ivt_block_offset} + 0x20)) + +echo "0xd1002041 ${ivt_ptr_base} 0x00000000 0x00000000 0x00000000 ${ivt_block_base} ${csf_block_base} 0x00000000" | xxd -r -p > ivt.bin +dd if=ivt.bin of=flash.bin bs=1 seek=${ivt_block_offset} conv=notrunc + +# Generate CSF blob +cst -i csf_fit.tmp -o csf_fit.bin +# Patch CSF blob into flash.bin +dd if=csf_fit.bin of=flash.bin bs=1 seek=${csf_block_offset} conv=notrunc diff --git a/doc/imx/habv4/csf_examples/mx8m/csf_fit.txt b/doc/imx/habv4/csf_examples/mx8m/csf_fit.txt new file mode 100644 index 0000000000..cd1d4070a5 --- /dev/null +++ b/doc/imx/habv4/csf_examples/mx8m/csf_fit.txt @@ -0,0 +1,36 @@ +[Header] + Version = 4.3 + Hash Algorithm = sha256 + Engine = CAAM + Engine Configuration = 0 + Certificate Format = X509 + Signature Format = CMS + +[Install SRK] + # FIXME: Adjust path here + File = "/path/to/cst-3.3.1/crts/SRK_1_2_3_4_table.bin" + Source index = 0 + +[Install CSFK] + # FIXME: Adjust path here + File = "/path/to/cst-3.3.1/crts/CSF1_1_sha256_4096_65537_v3_usr_crt.pem" + +[Authenticate CSF] + +[Install Key] + Verification index = 0 + Target Index = 2 + # FIXME: Adjust path here + File = "/path/to/cst-3.3.1/crts/IMG1_1_sha256_4096_65537_v3_usr_crt.pem" + +[Authenticate Data] + Verification index = 2 + # FIXME: + # Line 1 -- fitImage tree + # Line 2 -- U-Boot u-boot-nodtb.bin blob + # Line 3 -- ATF BL31 blob + # Line 4 -- DT blob + Blocks = 0x401fcdc0 0x57c00 0xffff "flash.bin", \ + 0x40200000 0x62c00 0xuuuu "flash.bin", \ + 0x920000 0x00000 0xaaaa "flash.bin", \ + 0x40200000 0x00000 0xdddd "flash.bin" diff --git a/doc/imx/habv4/csf_examples/mx8m/csf_spl.txt b/doc/imx/habv4/csf_examples/mx8m/csf_spl.txt new file mode 100644 index 0000000000..00e34f6b1b --- /dev/null +++ b/doc/imx/habv4/csf_examples/mx8m/csf_spl.txt @@ -0,0 +1,33 @@ +[Header] + Version = 4.3 + Hash Algorithm = sha256 + Engine = CAAM + Engine Configuration = 0 + Certificate Format = X509 + Signature Format = CMS + +[Install SRK] + # FIXME: Adjust path here + File = "/path/to/cst-3.3.1/crts/SRK_1_2_3_4_table.bin" + Source index = 0 + +[Install CSFK] + # FIXME: Adjust path here + File = "/path/to/cst-3.3.1/crts/CSF1_1_sha256_4096_65537_v3_usr_crt.pem" + +[Authenticate CSF] + +[Unlock] + Engine = CAAM + Features = MID + +[Install Key] + Verification index = 0 + Target Index = 2 + # FIXME: Adjust path here + File = "/path/to/cst-3.3.1/crts/IMG1_1_sha256_4096_65537_v3_usr_crt.pem" + +[Authenticate Data] + Verification index = 2 + # FIXME: Adjust start (first column) and size (third column) here + Blocks = 0x7e0fc0 0x0 0x306f0 "flash.bin" diff --git a/doc/imx/habv4/guides/mx8m_spl_secure_boot.txt b/doc/imx/habv4/guides/mx8m_spl_secure_boot.txt new file mode 100644 index 0000000000..747f7cd260 --- /dev/null +++ b/doc/imx/habv4/guides/mx8m_spl_secure_boot.txt @@ -0,0 +1,265 @@ + +=========================================================+ + + i.MX8M U-Boot HABv4 Secure Boot guide for SPL targets + + +=========================================================+ + +1. HABv4 secure boot process +----------------------------- + +This document is an addendum of mx6_mx7_spl_secure_boot.txt guide describing +a step-by-step procedure on how to sign and securely boot an U-Boot image for +SPL targets on i.MX8M, i.MX8M Mini, i.MX8M Nano, i.MX8M Plus. + +Details about HAB can be found in the application note AN4581[1] and in the +introduction_habv4.txt document. + +1.1 Building a SPL target supporting secure boot +------------------------------------------------- + +The U-Boot build for i.MX8M SoC makes use of Second Program Loader (SPL) +support, fitImage support and custom i.MX8M specific flash.bin container. +This leads to a generation of multiple intermediate build artifacts, the +U-Boot SPL, U-Boot binary, DT blob. These later two artifacts are bundled +with external ATF BL31 blob to form a fitImage. The fitImage is bundled +with SPL and external DDR and optional HDMI PHY initialization blobs to +form the final flash.bin container. The HABv4 can be used to authenticate +all of the input binaries separately. + +Out of reset the ROM code authenticates the SPL and PHY initialization +blobs, combination of which is responsible for initializing essential +features such as DDR, UART, PMIC and clock enablement. Once the DDR is +available, the SPL code loads the secondary fitImage to its specific +address and call the HAB APIs to extend the root of trust on its +components. + +The U-Boot SPL provides support to secure boot configuration and also +provide access to the HAB APIs exposed by the ROM vector table, the +U-Boot provides access to HAB APIs via SMC calls to ATF. The support +is enabled by selecting the CONFIG_IMX_HAB option. + +When built with this configuration the U-Boot correctly pads combined +SPL and PHY initialization blob image, called u-boot-spl-ddr.bin, by +aligning to the next 0xC00 address, so the CSF signature data generated +by CST can be concatenated to the image. + +The U-Boot also reserves space in the fitImage binary (u-boot.itb) between +the fitImage tree and external blobs included in it, so it can be used to +inject IVT and CST signatures used by SPL HAB calls to authenticate the +fitImage components. + +The diagram below illustrate a signed SPL combined with DDR PHY +initialization firmware blobs part of flash.bin container layout. +This part is loaded to memory address ( CONFIG_SPL_TEXT_BASE - 0x40 ) and +authenticated the BootROM. The reason for the offset is so that the *entry +would be at memory address CONFIG_SPL_TEXT_BASE when BootROM executes the +code within it: + + ------- +-----------------------------+ <-- *start + ^ | Image Vector Table | + | | (0x20 bytes) | + | +-----------------------------+ <-- *boot_data + | | Boot Data | + | +-----------------------------+ + | | Padding | + Signed | | to 0x40 bytes from *start | + Data | +-----------------------------+ <-- *entry + | | | + | | SPL combined with DDR PHY | + | | initialization blobs | + | | (u-boot-spl-ddr.bin) | + | | | + | +-----------------------------+ + v | Padding | + ------- +-----------------------------+ <-- *csf + | | + | Command Sequence File (CSF) | + | | + +-----------------------------+ + | Padding (optional) | + +-----------------------------+ + +The diagram below illustrate a signed U-Boot binary, DT blob and external +ATF BL31 blob combined to form fitImage part of flash.bin container layout. +The *load_address is derived from CONFIG_SYS_TEXT_BASE such that the U-Boot +binary *start is placed exactly at CONFIG_SPL_TEXT_BASE in DRAM, however the +SPL moves the fitImage tree further to location: + *load_address = CONFIG_SPL_TEXT_BASE - CONFIG_FIT_EXTERNAL_OFFSET (=12kiB) - + 512 Byte sector - sizeof(mkimage header) + + ------- +-----------------------------+ <-- *load_address + ^ | | + | | fitImage tree | + | | with external data at | + | | offset 12 kiB from tree | + | | (cca. 1 kiB) | + Signed | | | + .----- Tree | +-----------------------------+ + | Data | | Padding to next 4k aligned | + | | | from *load_address | + | | +-----------------------------+ <-- *ivt + | | | Image Vector Table | + | v | (0x20 bytes) | + | ------- +-----------------------------+ <-- *csf + | | Command Sequence File (CSF) | + | | for all signed entries in | + >--------------->| the fitImage, tree and data | + | | (cca 6-7 kiB) | + | +-----------------------------+ + | | Padding to 12 kiB offset | + | | from *load_address | + | ------- +-----------------------------+ <-- *start + | ^ | | + | Signed | | | + |---- Payload | | U-Boot external data blob | + | Data | | | + | v | | + | ------- +-----------------------------+ + | | Padding to 4 Bytes | + | ------- +-----------------------------+ + | ^ | | + | Signed | | | + |---- Payload | | ATF external data blob | + | Data | | | + | v | | + | ------- +-----------------------------+ + | | Padding to 4 Bytes | + | ------- +-----------------------------+ + | ^ | | + | Signed | | | + '---- Payload | | DTB external data blob | + Data | | | + v | | + ------- +-----------------------------+ + +The diagram below illustrate a combined flash.bin container layout: + + +-----------------------------+ + | Signed SPL part | + +-----------------------------+ + | Signed fitImage part | + +-----------------------------+ + +1.2 Enabling the secure boot support +------------------------------------- + +The first step is to generate an U-Boot image supporting the HAB features +mentioned above, this can be achieved by adding CONFIG_IMX_HAB to the +build configuration: + +- Defconfig: + + CONFIG_IMX_HAB=y + +- Kconfig: + + ARM architecture -> Support i.MX HAB features + +1.3 Signing the images +----------------------- + +The CSF contains all the commands that the HAB executes during the secure +boot. These commands instruct the HAB code on which memory areas of the image +to authenticate, which keys to install, use and etc. + +CSF examples are available under doc/imx/habv4/csf_examples/ directory. + +CSF "Blocks" line for csf_spl.txt can be generated as follows: + +``` +spl_block_base=$(printf "0x%x" $(( $(sed -n "/CONFIG_SPL_TEXT_BASE=/ s@.*=@@p" .config) - 0x40)) ) +spl_block_size=$(printf "0x%x" $(stat -tc %s u-boot-spl-ddr.bin)) +sed -i "/Blocks = / s@.*@ Blocks = $spl_block_base 0x0 $spl_block_size \"flash.bin\"@" csf_spl.txt +``` + +The resulting line looks as follows: +``` + Blocks = 0x7e0fc0 0x0 0x306f0 "flash.bin" +``` + +The columns mean: + - CONFIG_SPL_TEXT_BASE - 0x40 -- Start address of signed data, in DRAM + - 0x0 -- Start address of signed data, in "flash.bin" + - 0x306f0 -- Length of signed data, in "flash.bin" + - Filename -- "flash.bin" + +To generate signature for the SPL part of flash.bin container, use CST: +``` +cst -i csf_spl.tmp -o csf_spl.bin +``` + +The newly generated CST blob has to be patched into existing flash.bin +container. Conveniently, flash.bin IVT contains physical address of the +CSF blob. Remember, the SPL part of flash.bin container is loaded by the +BootROM at CONFIG_SPL_TEXT_BASE - 0x40 , so the offset of CSF blob in +the fitImage can be calculated and inserted into the flash.bin in the +correct location as follows: +``` +# offset = IVT_HEADER[6 = CSF address] - CONFIG_SPL_TEXT_BASE - 0x40 +spl_csf_offset=$(xxd -s 24 -l 4 -e flash.bin | cut -d " " -f 2 | sed "s@^@0x@") +spl_bin_offset=$(xxd -s 4 -l 4 -e flash.bin | cut -d " " -f 2 | sed "s@^@0x@") +spl_dd_offset=$((${spl_csf_offset} - ${spl_bin_offset} + 0x40)) +dd if=csf_spl.bin of=flash.bin bs=1 seek=${spl_dd_offset} conv=notrunc +``` + +CSF "Blocks" line for csf_fit.txt can be generated as follows: +``` +# fitImage tree +fit_block_base=$(printf "0x%x" $(( $(sed -n "/CONFIG_SYS_TEXT_BASE=/ s@.*=@@p" .config) - $(sed -n "/CONFIG_FIT_EXTERNAL_OFFSET=/ s@.*=@@p" .config) - 0x200 - 0x40)) ) +fit_block_offset=$(printf "0x%s" $(fdtget -t x u-boot.dtb /binman/imx-boot/uboot offset)) +fit_block_size=$(printf "0x%x" $(( ( $(fdtdump u-boot.itb 2>/dev/null | sed -n "/^...totalsize:/ s@.*\(0x[0-9a-f]\+\).*@\1@p") + 0x1000 - 0x1 ) & ~(0x1000 - 0x1) + 0x20 )) ) +sed -i "/Blocks = / s@.*@ Blocks = $fit_block_base $fit_block_offset $fit_block_size \"flash.bin\", \\\\@" csf_fit.tmp + +# U-Boot +uboot_block_base=$(printf "0x%s" $(fdtget -t x u-boot.itb /images/uboot load)) +uboot_block_offset=$(printf "0x%x" $(( $(printf "0x%s" $(fdtget -t x u-boot.itb /images/uboot data-position)) + ${fit_block_offset} ))) +uboot_block_size=$(printf "0x%s" $(fdtget -t x u-boot.itb /images/uboot data-size)) +sed -i "/0xuuuu/ s@.*@ $uboot_block_base $uboot_block_offset $uboot_block_size \"flash.bin\", \\\\@" csf_fit.tmp + +# ATF +atf_block_base=$(printf "0x%s" $(fdtget -t x u-boot.itb /images/atf load)) +atf_block_offset=$(printf "0x%x" $(( $(printf "0x%s" $(fdtget -t x u-boot.itb /images/atf data-position)) + ${fit_block_offset} ))) +atf_block_size=$(printf "0x%s" $(fdtget -t x u-boot.itb /images/atf data-size)) +sed -i "/0xaaaa/ s@.*@ $atf_block_base $atf_block_offset $atf_block_size \"flash.bin\", \\\\@" csf_fit.tmp + +# DTB +dtb_block_base=$(printf "0x%x" $(( ${uboot_block_base} + ${uboot_block_size} ))) +dtb_block_offset=$(printf "0x%x" $(( $(printf "0x%s" $(fdtget -t x u-boot.itb /images/fdt-1 data-position)) + ${fit_block_offset} ))) +dtb_block_size=$(printf "0x%s" $(fdtget -t x u-boot.itb /images/fdt-1 data-size)) +sed -i "/0xdddd/ s@.*@ $dtb_block_base $dtb_block_offset $dtb_block_size \"flash.bin\"@" csf_fit.tmp +``` + +The fitImage part of flash.bin requires separate IVT. Generate the IVT and +patch it into the correct aligned location of flash.bin as follows: +``` +# IVT +ivt_ptr_base=$(printf "%08x" ${fit_block_base} | sed "s@\(..\)\(..\)\(..\)\(..\)@0x\4\3\2\1@") +ivt_block_base=$(printf "%08x" $(( ${fit_block_base} + ${fit_block_size} - 0x20 )) | sed "s@\(..\)\(..\)\(..\)\(..\)@0x\4\3\2\1@") +csf_block_base=$(printf "%08x" $(( ${fit_block_base} + ${fit_block_size} )) | sed "s@\(..\)\(..\)\(..\)\(..\)@0x\4\3\2\1@") +ivt_block_offset=$((${fit_block_offset} + ${fit_block_size} - 0x20)) +csf_block_offset=$((${ivt_block_offset} + 0x20)) + +echo "0xd1002041 ${ivt_ptr_base} 0x00000000 0x00000000 0x00000000 ${ivt_block_base} ${csf_block_base} 0x00000000" | xxd -r -p > ivt.bin +dd if=ivt.bin of=flash.bin bs=1 seek=${ivt_block_offset} conv=notrunc + +To generate CSF signature for the fitImage part of flash.bin container, use CST: +``` +cst -i csf_fit.tmp -o csf_fit.bin +``` + +Finally, patch the CSF signature into the fitImage right past the IVT: +``` +dd if=csf_fit.bin of=flash.bin bs=1 seek=${csf_block_offset} conv=notrunc +``` + +The entire script is available in doc/imx/habv4/csf_examples/mx8m/csf.sh + +1.4 Closing the device +----------------------- + +The procedure for closing the device is similar as in Non-SPL targets, for a +complete procedure please refer to section "1.5 Programming SRK Hash" in +mx6_mx7_secure_boot.txt document available under doc/imx/habv4/guides/ +directory. + +References: +[1] AN4581: "Secure Boot on i.MX 50, i.MX 53, i.MX 6 and i.MX 7 Series using + HABv4" - Rev 2. diff --git a/doc/usage/cmd/gpio.rst b/doc/usage/cmd/gpio.rst index f6a5668388..ee902138f1 100644 --- a/doc/usage/cmd/gpio.rst +++ b/doc/usage/cmd/gpio.rst @@ -45,6 +45,31 @@ gpio status Display the status of one or multiple GPIOs. By default only claimed GPIOs are displayed. +gpio status command output fields are:: + + : : [x]