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Add multi chip support to the FSL-UPM driver

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This patch adds support for multi-chip NAND devices to the FSL-UPM
driver. The "dev_ready" callback of the "struct fsl_upm_nand" is now
called with the argument "chip_nr" to allow testing the proper chip
select line. The NAND support of the MPC8360ERDK is updated as well.
No other boards are currently using the FSL UPM driver.

Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
This commit is contained in:
Wolfgang Grandegger 2009-02-11 18:38:21 +01:00 committed by Scott Wood
parent 672ed2aee9
commit e93c1c169d
3 changed files with 40 additions and 10 deletions
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2
board/freescale/mpc8360erdk/nand.c
View File

@ -57,7 +57,7 @@ static void upm_setup(struct fsl_upm *upm)
eieio();
}
static int dev_ready(void)
static int dev_ready(int chip_nr)
{
if (in_be32(&im->qepio.ioport[4].pdat) & 0x00002000) {
debug("nand ready\n");

44
drivers/mtd/nand/fsl_upm.c
View File

@ -31,26 +31,45 @@ static void fsl_upm_end_pattern(struct fsl_upm *upm)
eieio();
}
static void fsl_upm_run_pattern(struct fsl_upm *upm, int width, u32 cmd)
static void fsl_upm_run_pattern(struct fsl_upm *upm, int width,
void __iomem *io_addr, u32 mar)
{
out_be32(upm->mar, cmd << (32 - width));
out_be32(upm->mar, mar);
switch (width) {
case 8:
out_8(upm->io_addr, 0x0);
out_8(io_addr, 0x0);
break;
case 16:
out_be16(upm->io_addr, 0x0);
out_be16(io_addr, 0x0);
break;
case 32:
out_be32(upm->io_addr, 0x0);
out_be32(io_addr, 0x0);
break;
}
}
#if CONFIG_SYS_NAND_MAX_CHIPS > 1
static void fun_select_chip(struct mtd_info *mtd, int chip_nr)
{
struct nand_chip *chip = mtd->priv;
struct fsl_upm_nand *fun = chip->priv;
if (chip_nr >= 0) {
fun->chip_nr = chip_nr;
chip->IO_ADDR_R = chip->IO_ADDR_W =
fun->upm.io_addr + fun->chip_offset * chip_nr;
} else if (chip_nr == -1) {
chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE);
}
}
#endif
static void fun_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
{
struct nand_chip *chip = mtd->priv;
struct fsl_upm_nand *fun = chip->priv;
void __iomem *io_addr;
u32 mar;
if (!(ctrl & fun->last_ctrl)) {
fsl_upm_end_pattern(&fun->upm);
@ -68,7 +87,13 @@ static void fun_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
fsl_upm_start_pattern(&fun->upm, fun->upm_cmd_offset);
}
fsl_upm_run_pattern(&fun->upm, fun->width, cmd);
mar = cmd << (32 - fun->width);
io_addr = fun->upm.io_addr;
#if CONFIG_SYS_NAND_MAX_CHIPS > 1
if (fun->chip_nr > 0)
io_addr += fun->chip_offset * fun->chip_nr;
#endif
fsl_upm_run_pattern(&fun->upm, fun->width, io_addr, mar);
/*
* Some boards/chips needs this. At least on MPC8360E-RDK we
@ -77,7 +102,7 @@ static void fun_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
* 0-2 unexpected busy states per block read.
*/
if (fun->wait_pattern) {
while (!fun->dev_ready())
while (!fun->dev_ready(fun->chip_nr))
debug("unexpected busy state\n");
}
}
@ -125,7 +150,7 @@ static int nand_dev_ready(struct mtd_info *mtd)
struct nand_chip *chip = mtd->priv;
struct fsl_upm_nand *fun = chip->priv;
return fun->dev_ready();
return fun->dev_ready(fun->chip_nr);
}
int fsl_upm_nand_init(struct nand_chip *chip, struct fsl_upm_nand *fun)
@ -139,6 +164,9 @@ int fsl_upm_nand_init(struct nand_chip *chip, struct fsl_upm_nand *fun)
chip->chip_delay = fun->chip_delay;
chip->ecc.mode = NAND_ECC_SOFT;
chip->cmd_ctrl = fun_cmd_ctrl;
#if CONFIG_SYS_NAND_MAX_CHIPS > 1
chip->select_chip = fun_select_chip;
#endif
chip->read_byte = nand_read_byte;
chip->read_buf = nand_read_buf;
chip->write_buf = nand_write_buf;

4
include/linux/mtd/fsl_upm.h
View File

@ -29,8 +29,10 @@ struct fsl_upm_nand {
int upm_cmd_offset;
int upm_addr_offset;
int wait_pattern;
int (*dev_ready)(void);
int (*dev_ready)(int chip_nr);
int chip_delay;
int chip_offset;
int chip_nr;
/* no need to fill */
int last_ctrl;