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Merge git://git.denx.de/u-boot-marvell

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- Sync Armada-38x dts with Linux 4.20 from Chris
- Misc changes and enhancements to Turris Mox (v4) from Marek
- Reserve PSCI area for Armada 8k from Heinrich
- New Allied Telesis x530 board (Armada-385) from Chris
- Misc minor changes (defconfig etc)
This commit is contained in:
Tom Rini
2019-01-21 11:59:21 -05:00
parent 27fb313dd6 0e31666dfa
commit e8ddbefccd
40 changed files with 1929 additions and 411 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
arch/arm/dts/Makefile
View File

@@ -109,7 +109,9 @@ dtb-$(CONFIG_ARCH_MVEBU) += \
armada-xp-maxbcm.dtb \
armada-xp-synology-ds414.dtb \
armada-xp-theadorable.dtb \
armada-38x-controlcenterdc.dtb
armada-38x-controlcenterdc.dtb \
armada-385-atl-x530.dtb \
armada-385-atl-x530DP.dtb
dtb-$(CONFIG_ARCH_UNIPHIER_LD11) += \
uniphier-ld11-global.dtb \

23
arch/arm/dts/armada-3720-turris-mox.dts
View File

@@ -24,6 +24,7 @@
aliases {
ethernet0 = &eth0;
ethernet1 = &eth1;
i2c0 = &i2c0;
spi0 = &spi0;
};
@@ -38,12 +39,16 @@
regulator-name = "usb3-vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
startup-delay-us = <2000000>;
shutdown-delay-us = <1000000>;
gpio = <&gpiosb 0 GPIO_ACTIVE_HIGH>;
regulator-boot-on;
};
mdio {
#address-cells = <1>;
#size-cells = <0>;
eth_phy1: ethernet-phy@1 {
reg = <1>;
};
@@ -59,7 +64,7 @@
phy1 {
phy-type = <PHY_TYPE_PEX0>;
phy-speed = <PHY_SPEED_2_5G>;
phy-speed = <PHY_SPEED_5G>;
};
phy2 {
@@ -80,6 +85,11 @@
pinctrl-names = "default";
pinctrl-0 = <&i2c1_pins>;
status = "okay";
rtc@6f {
compatible = "microchip,mcp7941x";
reg = <0x6f>;
};
};
&sdhci1 {
@@ -110,6 +120,17 @@
spi-max-frequency = <20000000>;
m25p,fast-read;
};
moxtet@1 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "cznic,moxtet";
reg = <1>;
reset-gpios = <&gpiosb 2 GPIO_ACTIVE_LOW>;
spi-max-frequency = <1000000>;
spi-cpol;
spi-cpha;
};
};
&uart0 {

44
arch/arm/dts/armada-380.dtsi
View File

@@ -1,3 +1,4 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Device Tree Include file for Marvell Armada 380 SoC.
*
@@ -6,44 +7,6 @@
* Lior Amsalem <alior@marvell.com>
* Gregory CLEMENT <gregory.clement@free-electrons.com>
* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#include "armada-38x.dtsi"
@@ -71,7 +34,7 @@
};
};
pcie-controller {
pcie {
compatible = "marvell,armada-370-pcie";
status = "disabled";
device_type = "pci";
@@ -104,6 +67,7 @@
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
0x81000000 0 0 0x81000000 0x1 0 1 0>;
bus-range = <0x00 0xff>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
marvell,pcie-port = <0>;
@@ -122,6 +86,7 @@
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
0x81000000 0 0 0x81000000 0x2 0 1 0>;
bus-range = <0x00 0xff>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
marvell,pcie-port = <1>;
@@ -140,6 +105,7 @@
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
0x81000000 0 0 0x81000000 0x3 0 1 0>;
bus-range = <0x00 0xff>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
marvell,pcie-port = <2>;

13
arch/arm/dts/armada-385-atl-x530-u-boot.dtsi Normal file
View File

@@ -0,0 +1,13 @@
// SPDX-License-Identifier: GPL-2.0
&spi1 {
u-boot,dm-pre-reloc;
spi-flash@0 {
u-boot,dm-pre-reloc;
};
};
&uart0 {
u-boot,dm-pre-reloc;
};

50
arch/arm/dts/armada-385-atl-x530.dts Normal file
View File

@@ -0,0 +1,50 @@
// SPDX-License-Identifier: GPL-2.0
/dts-v1/;
#include "armada-385-atl-x530.dtsi"
#include "armada-385-atl-x530-u-boot.dtsi"
/ {
model = "Allied Telesis x530";
compatible = "alliedtelesis,x530", "marvell,armada385", "marvell,armada380";
nand-protect {
compatible = "atl,nand-protect";
protect-gpio = <&gpio1 11 GPIO_ACTIVE_HIGH>;
};
usb-enable {
compatible = "atl,usb-enable";
enable-gpio = <&gpio0 19 GPIO_ACTIVE_HIGH>;
};
boot-board {
compatible = "atl,boot-board";
present-gpio = <&gpio0 24 GPIO_ACTIVE_HIGH>;
override-gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>;
};
phy-reset {
compatible = "atl,phy-reset";
reset-gpio = <&gpio0 12 GPIO_ACTIVE_HIGH>,
<&gpio1 21 GPIO_ACTIVE_HIGH>;
};
led-enable {
compatible = "atl,led-enable";
enable-gpio = <&gpio1 17 GPIO_ACTIVE_HIGH>;
};
led_7seg {
compatible = "atl,of-led-7seg";
segment-gpios = <
&led_7seg_gpio 0 0
&led_7seg_gpio 1 0
&led_7seg_gpio 2 0
&led_7seg_gpio 3 0
&led_7seg_gpio 4 0
&led_7seg_gpio 5 0
&led_7seg_gpio 6 0
&led_7seg_gpio 7 0>;
};
};

266
arch/arm/dts/armada-385-atl-x530.dtsi Normal file
View File

@@ -0,0 +1,266 @@
// SPDX-License-Identifier: GPL-2.0
#include <dt-bindings/gpio/gpio.h>
#include "armada-385.dtsi"
/ {
model = "Allied Telesis x530";
compatible = "alliedtelesis,x530", "marvell,armada385", "marvell,armada380";
chosen {
stdout-path = "serial0:115200n8";
bootargs = "console=ttyS0,115200 earlyprintk";
};
aliases {
spi1 = &spi1;
i2c0 = &i2c0;
};
memory {
device_type = "memory";
reg = <0 0x00000000 0 0x40000000>; /* 1 GB */
};
soc {
ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
MBUS_ID(0x01, 0x3d) 0 0xf4800000 0x80000
MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000>;
pcie-mem-aperture = <0xa0000000 0x40000000>;
};
eco-button-interrupt {
compatible = "atl,eco-button-interrupt";
eco-button-gpio = <&gpio0 14 GPIO_ACTIVE_LOW>;
};
board-reset {
compatible = "atl,phy_reset";
/* Physical board layout of reset pin is active-low but for the
* current driver we have to set it to active-high here.
*/
phy-reset-gpio = <&gpio0 12 GPIO_ACTIVE_HIGH>,
<&gpio1 21 GPIO_ACTIVE_HIGH>;
};
phy-int {
compatible = "linux,uio-pdrv-genirq";
interrupt-parent = <&gpio0>;
interrupts = <6 IRQ_TYPE_EDGE_BOTH>;
};
led-enable {
compatible = "atl,led-enable";
led-enable-gpios = <&gpio1 17 GPIO_ACTIVE_LOW>;
};
led_7seg {
compatible = "atl,of-led-7seg";
segment-gpios = <
&led_7seg_gpio 0 0
&led_7seg_gpio 1 0
&led_7seg_gpio 2 0
&led_7seg_gpio 3 0
&led_7seg_gpio 4 0
&led_7seg_gpio 5 0
&led_7seg_gpio 6 0
&led_7seg_gpio 7 0>;
};
poe {
compatible = "atl,periph-poe";
poe-reset-gpio = <&gpio0 15 GPIO_ACTIVE_HIGH>;
interrupt-parent = <&gpio0>;
interrupts = <20 IRQ_TYPE_EDGE_BOTH>;
};
};
&pciec {
status = "okay";
};
&pcie1 {
status = "okay";
};
&devbus_cs1 {
compatible = "marvell,mvebu-devbus";
status = "okay";
devbus,bus-width = <8>;
devbus,turn-off-ps = <60000>;
devbus,badr-skew-ps = <0>;
devbus,acc-first-ps = <124000>;
devbus,acc-next-ps = <248000>;
devbus,rd-setup-ps = <0>;
devbus,rd-hold-ps = <0>;
/* Write parameters */
devbus,sync-enable = <0>;
devbus,wr-high-ps = <60000>;
devbus,wr-low-ps = <60000>;
devbus,ale-wr-ps = <60000>;
nvs@0 {
status = "okay";
compatible = "mtd-ram";
reg = <0 0x00080000>;
bank-width = <1>;
label = "nvs";
};
};
&gpio0 {
poe-disable {
gpio-hog;
gpios = <16 GPIO_ACTIVE_HIGH>;
output-high;
line-name = "poe-disable";
};
};
&gpio1 {
poe-mezz-reset {
gpio-hog;
gpios = <15 GPIO_ACTIVE_HIGH>;
output-high;
line-name = "poe-mezz-reset";
};
};
&i2c0 {
clock-frequency = <100000>;
status = "okay";
mux@71 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "nxp,pca9544";
reg = <0x71>;
i2c-mux-idle-disconnect;
i2c@0 { /* POE devices MUX */
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
};
i2c@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
rng@3b {
compatible = "maxim,ds2476";
reg = <0x3b>;
};
hwmon@2e {
compatible = "adi,adt7476";
reg = <0x2e>;
};
hwmon@2d {
compatible = "adi,adt7476";
reg = <0x2d>;
};
};
i2c@2 {
#address-cells = <1>;
#size-cells = <0>;
reg = <2>;
rtc@68 {
compatible = "dallas,ds1340";
reg = <0x68>;
};
};
i2c@3 {
#address-cells = <1>;
#size-cells = <0>;
reg = <3>;
led_7seg_gpio: gpio@20 {
compatible = "nxp,pca9554";
gpio-controller;
#gpio-cells = <2>;
reg = <0x20>;
};
sfpgpio: gpio@27 { /* I2C to GPIO */
compatible = "nxp,pca9555";
gpio-controller;
#gpio-cells = <2>;
reg = <0x27>;
interrupt-parent = <&gpio0>;
interrupts = <13 IRQ_TYPE_LEVEL_LOW>;
};
sfpmux: mux@77 { /* SFP I2C MUX */
#address-cells = <1>;
#size-cells = <0>;
compatible = "nxp,pca9544";
reg = <0x77>;
i2c-mux-idle-disconnect;
};
};
};
};
&spi1 {
status = "okay";
spi-flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
reg = <0>; /* Chip select 0 */
spi-max-frequency = <50000000>;
m25p,fast-read;
partition@u-boot {
reg = <0x00000000 0x00100000>;
label = "u-boot";
};
partition@u-boot-env {
reg = <0x00100000 0x00040000>;
label = "u-boot-env";
};
partition@unused {
reg = <0x00140000 0x00e80000>;
label = "unused";
};
partition@idprom {
reg = <0x00fc0000 0x00040000>;
label = "idprom";
};
};
};
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins>;
status = "okay";
};
&usb0 {
status = "okay";
};
&refclk {
clock-frequency = <25000000>;
};
&nand_controller { /* 256 MB */
status = "okay";
num-cs = <1>;
nand-ecc-strength = <4>;
nand-ecc-step-size = <512>;
marvell,nand-enable-arbiter;
nand-on-flash-bbt;
};

51
arch/arm/dts/armada-385-atl-x530DP.dts Normal file
View File

@@ -0,0 +1,51 @@
// SPDX-License-Identifier: GPL-2.0
/dts-v1/;
#include "armada-385-atl-x530.dtsi"
#include "armada-385-atl-x530-u-boot.dtsi"
#include "armada-385-atl-x530DP.dtsi"
/ {
model = "Allied Telesis x530DP";
compatible = "alliedtelesis,x530DP", "alliedtelesis,x530", "marvell,armada385", "marvell,armada380";
nand-protect {
compatible = "atl,nand-protect";
protect-gpio = <&gpio1 11 GPIO_ACTIVE_HIGH>;
};
usb-enable {
compatible = "atl,usb-enable";
enable-gpio = <&gpio0 19 GPIO_ACTIVE_HIGH>;
};
boot-board {
compatible = "atl,boot-board";
present-gpio = <&gpio0 24 GPIO_ACTIVE_HIGH>;
override-gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>;
};
phy-reset {
compatible = "atl,phy-reset";
reset-gpio = <&gpio0 12 GPIO_ACTIVE_HIGH>,
<&gpio1 21 GPIO_ACTIVE_HIGH>;
};
led-enable {
compatible = "atl,led-enable";
enable-gpio = <&gpio1 17 GPIO_ACTIVE_HIGH>;
};
led_7seg {
compatible = "atl,of-led-7seg";
segment-gpios = <
&led_7seg_gpio 0 0
&led_7seg_gpio 1 0
&led_7seg_gpio 2 0
&led_7seg_gpio 3 0
&led_7seg_gpio 4 0
&led_7seg_gpio 5 0
&led_7seg_gpio 6 0
&led_7seg_gpio 7 0>;
};
};

149
arch/arm/dts/armada-385-atl-x530DP.dtsi Normal file
View File

@@ -0,0 +1,149 @@
// SPDX-License-Identifier: GPL-2.0
&i2c0 {
mux@71 {
compatible = "nxp,pca9548";
i2c@1 {
hwmon@2c {
compatible = "ti,lm87";
reg = <0x2c>;
};
hwmon@2d {
compatible = "ti,lm87";
reg = <0x2d>;
};
hwmon@2e {
pwm-polarity = <1>;
};
};
psu_a_adapter: i2c@4 {
#address-cells = <1>;
#size-cells = <0>;
reg = <4>;
};
psu_b_adapter: i2c@5 {
#address-cells = <1>;
#size-cells = <0>;
reg = <5>;
};
i2c@6 {
#address-cells = <1>;
#size-cells = <0>;
reg = <6>;
misc_gpio: gpio@26 {
compatible = "nxp,pca9555";
gpio-controller;
#gpio-cells = <2>;
reg = <0x26>;
interrupt-parent = <&gpio0>;
interrupts = <5 IRQ_TYPE_LEVEL_LOW>;
status = "okay";
interrupt-controller;
#interrupt-cells = <2>;
psu_bank2 {
gpio-hog;
gpios = <0 GPIO_ACTIVE_HIGH>;
output-high;
line-name = "psu-bank2";
};
};
};
};
};
/ {
psu_slot_a {
compatible = "atl,dts-overlay-gpio-psu-slot";
slot-name = "PSU Bay A";
board-index = <1>;
present-gpio = <&misc_gpio 1 GPIO_ACTIVE_LOW>;
output-ok-gpio = <&gpio1 16 GPIO_ACTIVE_HIGH>;
interrupt-parent = <&misc_gpio>;
interrupts = <1 IRQ_TYPE_EDGE_BOTH>;
overlay = <&psu_a_overlay>;
};
psu_slot_b {
compatible = "atl,dts-overlay-gpio-psu-slot";
slot-name = "PSU Bay B";
board-index = <2>;
present-gpio = <&misc_gpio 2 GPIO_ACTIVE_LOW>;
output-ok-gpio = <&gpio1 22 GPIO_ACTIVE_HIGH>;
interrupt-parent = <&misc_gpio>;
interrupts = <2 IRQ_TYPE_EDGE_BOTH>;
overlay = <&psu_b_overlay>;
};
fan_slot_a {
compatible = "atl,fan05-slot";
slot-name = "Fan Bay A";
board-index = <3>;
present-gpio = <&misc_gpio 3 GPIO_ACTIVE_LOW>;
fault-gpio = <&misc_gpio 11 GPIO_ACTIVE_LOW>;
interrupt-parent = <&misc_gpio>;
interrupts = <3 IRQ_TYPE_EDGE_BOTH>;
overlay = <&fan_a_overlay>;
};
};
/ {
psu_a_overlay: psu_a {
fragment@0 {
target = <&psu_a_adapter>;
__overlay__ {
#address-cells = <1>;
#size-cells = <0>;
psu@51 {
compatible = "atl,atl-pwr-gen2";
reg = <0x51>;
board-index = <1>;
};
};
};
};
};
/ {
psu_b_overlay: psu_b {
fragment@0 {
target = <&psu_b_adapter>;
__overlay__ {
#address-cells = <1>;
#size-cells = <0>;
psu@51 {
compatible = "atl,atl-pwr-gen2";
reg = <0x51>;
board-index = <2>;
};
};
};
};
};
/ {
fan_a_overlay:fan_a {
fragment@1 {
target-path = "/";
__overlay__ {
fan@1 {
compatible = "atl,fan05";
board-index = <3>;
module-id-gpios =
<&misc_gpio 4 GPIO_ACTIVE_HIGH>,
<&misc_gpio 5 GPIO_ACTIVE_HIGH>,
<&misc_gpio 6 GPIO_ACTIVE_HIGH>;
};
};
};
};
};

63
arch/arm/dts/armada-385.dtsi
View File

@@ -1,3 +1,4 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Device Tree Include file for Marvell Armada 385 SoC.
*
@@ -6,44 +7,6 @@
* Lior Amsalem <alior@marvell.com>
* Gregory CLEMENT <gregory.clement@free-electrons.com>
* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#include "armada-38x.dtsi"
@@ -70,13 +33,7 @@
};
soc {
internal-regs {
pinctrl@18000 {
compatible = "marvell,mv88f6820-pinctrl";
};
};
pcie-controller {
pciec: pcie {
compatible = "marvell,armada-370-pcie";
status = "disabled";
device_type = "pci";
@@ -106,7 +63,7 @@
* configured in x4 by the bootloader, then
* pcie@4,0 is not available.
*/
pcie@1,0 {
pcie1: pcie@1,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0x80000 0 0x2000>;
reg = <0x0800 0 0 0 0>;
@@ -115,6 +72,7 @@
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
0x81000000 0 0 0x81000000 0x1 0 1 0>;
bus-range = <0x00 0xff>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
marvell,pcie-port = <0>;
@@ -124,7 +82,7 @@
};
/* x1 port */
pcie@2,0 {
pcie2: pcie@2,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
reg = <0x1000 0 0 0 0>;
@@ -133,6 +91,7 @@
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
0x81000000 0 0 0x81000000 0x2 0 1 0>;
bus-range = <0x00 0xff>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
marvell,pcie-port = <1>;
@@ -142,7 +101,7 @@
};
/* x1 port */
pcie@3,0 {
pcie3: pcie@3,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
reg = <0x1800 0 0 0 0>;
@@ -151,6 +110,7 @@
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
0x81000000 0 0 0x81000000 0x3 0 1 0>;
bus-range = <0x00 0xff>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
marvell,pcie-port = <2>;
@@ -163,7 +123,7 @@
* x1 port only available when pcie@1,0 is
* configured as a x1 port
*/
pcie@4,0 {
pcie4: pcie@4,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0x48000 0 0x2000>;
reg = <0x2000 0 0 0 0>;
@@ -172,6 +132,7 @@
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
0x81000000 0 0 0x81000000 0x4 0 1 0>;
bus-range = <0x00 0xff>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
marvell,pcie-port = <3>;
@@ -182,3 +143,7 @@
};
};
};
&pinctrl {
compatible = "marvell,mv88f6820-pinctrl";
};

25
arch/arm/dts/armada-388-clearfog.dts
View File

@@ -118,18 +118,7 @@
status = "okay";
};
spi1: spi@10680 {
/*
* CS0: W25Q32
* CS1:
* CS2: mikrobus
*/
pinctrl-0 = <&spi1_pins &clearfog_spi1_cs_pins &mikro_spi_pins>;
pinctrl-names = "default";
status = "okay";
};
usb0: usb3@f8000 {
usb3@f8000 {
/* CON7, USB-A port on back of device */
status = "okay";
};
@@ -322,6 +311,18 @@
};
};
&spi1 {
/*
* Add SPI CS pins for clearfog:
* CS0: W25Q32
* CS1:
* CS2: mikrobus
*/
pinctrl-0 = <&spi1_pins &mikro_spi_pins>;
pinctrl-names = "default";
status = "okay";
};
/*
+#define A38x_CUSTOMER_BOARD_1_MPP16_23 0x00400011
MPP18: gpio ? (pca9655 int?)

43
arch/arm/dts/armada-388.dtsi
View File

@@ -1,3 +1,4 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Device Tree Include file for Marvell Armada 388 SoC.
*
@@ -5,39 +6,6 @@
*
* Gregory CLEMENT <gregory.clement@free-electrons.com>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without
* any warranty of any kind, whether express or implied.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
*
* The main difference with the Armada 385 is that the 388 can handle two more
* SATA ports. So we can reuse the dtsi of the Armada 385, override the pinctrl
* property and the name of the SoC, and add the second SATA host which control
@@ -50,13 +18,8 @@
model = "Marvell Armada 388 family SoC";
compatible = "marvell,armada388", "marvell,armada385",
"marvell,armada380";
soc {
internal-regs {
pinctrl@18000 {
compatible = "marvell,mv88f6828-pinctrl";
};
sata@e0000 {
compatible = "marvell,armada-380-ahci";
reg = <0xe0000 0x2000>;
@@ -68,3 +31,7 @@
};
};
};
&pinctrl {
compatible = "marvell,mv88f6828-pinctrl";
};

68
arch/arm/dts/armada-38x-controlcenterdc.dts
View File

@@ -72,40 +72,6 @@
MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000>;
internal-regs {
spi0: spi@10600 {
status = "okay";
sc16is741: sc16is741@0 {
compatible = "nxp,sc16is741";
reg = <0>;
clocks = <&sc16isclk>;
spi-max-frequency = <4000000>;
interrupt-parent = <&gpio0>;
interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
gpio-controller;
#gpio-cells = <2>;
};
};
spi1: spi@10680 {
status = "okay";
u-boot,dm-pre-reloc;
spi-flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "n25q016a", "spi-flash";
reg = <0>; /* Chip select 0 */
spi-max-frequency = <108000000>;
};
spi-flash@1 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "n25q128a11", "spi-flash";
reg = <1>; /* Chip select 1 */
spi-max-frequency = <108000000>;
u-boot,dm-pre-reloc;
};
};
I2C0: i2c@11000 {
status = "okay";
clock-frequency = <1000000>;
@@ -586,3 +552,37 @@
};
};
};
&spi0 {
status = "okay";
sc16is741: sc16is741@0 {
compatible = "nxp,sc16is741";
reg = <0>;
clocks = <&sc16isclk>;
spi-max-frequency = <4000000>;
interrupt-parent = <&gpio0>;
interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
gpio-controller;
#gpio-cells = <2>;
};
};
&spi1 {
status = "okay";
u-boot,dm-pre-reloc;
spi-flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "n25q016a", "spi-flash";
reg = <0>; /* Chip select 0 */
spi-max-frequency = <108000000>;
};
spi-flash@1 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "n25q128a11", "spi-flash";
reg = <1>; /* Chip select 1 */
spi-max-frequency = <108000000>;
u-boot,dm-pre-reloc;
};
};

283
arch/arm/dts/armada-38x.dtsi
View File

@@ -1,3 +1,4 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Device Tree Include file for Marvell Armada 38x family of SoCs.
*
@@ -6,44 +7,6 @@
* Lior Amsalem <alior@marvell.com>
* Gregory CLEMENT <gregory.clement@free-electrons.com>
* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#include "skeleton.dtsi"
@@ -83,7 +46,7 @@
reg = <MBUS_ID(0x01, 0x1d) 0 0x200000>;
};
devbus-bootcs {
devbus_bootcs: devbus-bootcs {
compatible = "marvell,mvebu-devbus";
reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>;
ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>;
@@ -93,7 +56,7 @@
status = "disabled";
};
devbus-cs0 {
devbus_cs0: devbus-cs0 {
compatible = "marvell,mvebu-devbus";
reg = <MBUS_ID(0xf0, 0x01) 0x10408 0x8>;
ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>;
@@ -103,7 +66,7 @@
status = "disabled";
};
devbus-cs1 {
devbus_cs1: devbus-cs1 {
compatible = "marvell,mvebu-devbus";
reg = <MBUS_ID(0xf0, 0x01) 0x10410 0x8>;
ranges = <0 MBUS_ID(0x01, 0x3d) 0 0xffffffff>;
@@ -113,7 +76,7 @@
status = "disabled";
};
devbus-cs2 {
devbus_cs2: devbus-cs2 {
compatible = "marvell,mvebu-devbus";
reg = <MBUS_ID(0xf0, 0x01) 0x10418 0x8>;
ranges = <0 MBUS_ID(0x01, 0x3b) 0 0xffffffff>;
@@ -123,7 +86,7 @@
status = "disabled";
};
devbus-cs3 {
devbus_cs3: devbus-cs3 {
compatible = "marvell,mvebu-devbus";
reg = <MBUS_ID(0xf0, 0x01) 0x10420 0x8>;
ranges = <0 MBUS_ID(0x01, 0x37) 0 0xffffffff>;
@@ -145,6 +108,10 @@
reg = <0x8000 0x1000>;
cache-unified;
cache-level = <2>;
arm,double-linefill-incr = <0>;
arm,double-linefill-wrap = <0>;
arm,double-linefill = <0>;
prefetch-data = <1>;
};
scu@c000 {
@@ -152,6 +119,13 @@
reg = <0xc000 0x58>;
};
timer@c200 {
compatible = "arm,cortex-a9-global-timer";
reg = <0xc200 0x20>;
interrupts = <GIC_PPI 11 (IRQ_TYPE_EDGE_RISING | GIC_CPU_MASK_SIMPLE(2))>;
clocks = <&coreclk 2>;
};
timer@c600 {
compatible = "arm,cortex-a9-twd-timer";
reg = <0xc600 0x20>;
@@ -168,32 +142,8 @@
<0xc100 0x100>;
};
spi0: spi@10600 {
compatible = "marvell,armada-380-spi",
"marvell,orion-spi";
reg = <0x10600 0x50>;
#address-cells = <1>;
#size-cells = <0>;
cell-index = <0>;
interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&coreclk 0>;
status = "disabled";
};
spi1: spi@10680 {
compatible = "marvell,armada-380-spi",
"marvell,orion-spi";
reg = <0x10680 0x50>;
#address-cells = <1>;
#size-cells = <0>;
cell-index = <1>;
interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&coreclk 0>;
status = "disabled";
};
i2c0: i2c@11000 {
compatible = "marvell,mv64xxx-i2c";
compatible = "marvell,mv78230-a0-i2c", "marvell,mv64xxx-i2c";
reg = <0x11000 0x20>;
#address-cells = <1>;
#size-cells = <0>;
@@ -204,7 +154,7 @@
};
i2c1: i2c@11100 {
compatible = "marvell,mv64xxx-i2c";
compatible = "marvell,mv78230-a0-i2c", "marvell,mv64xxx-i2c";
reg = <0x11100 0x20>;
#address-cells = <1>;
#size-cells = <0>;
@@ -258,19 +208,6 @@
marvell,function = "i2c0";
};
nand_pins: nand-pins {
marvell,pins = "mpp22", "mpp34", "mpp23", "mpp33",
"mpp38", "mpp28", "mpp40", "mpp42",
"mpp35", "mpp36", "mpp25", "mpp30",
"mpp32";
marvell,function = "dev";
};
nand_rb: nand-rb {
marvell,pins = "mpp41";
marvell,function = "nand";
};
mdio_pins: mdio-pins {
marvell,pins = "mpp4", "mpp5";
marvell,function = "ge";
@@ -298,6 +235,20 @@
marvell,function = "spi1";
};
nand_pins: nand-pins {
marvell,pins = "mpp22", "mpp34", "mpp23",
"mpp33", "mpp38", "mpp28",
"mpp40", "mpp42", "mpp35",
"mpp36", "mpp25", "mpp30",
"mpp32";
marvell,function = "dev";
};
nand_rb: nand-rb {
marvell,pins = "mpp41";
marvell,function = "nand";
};
uart0_pins: uart-pins-0 {
marvell,pins = "mpp0", "mpp1";
marvell,function = "ua0";
@@ -338,34 +289,42 @@
};
gpio0: gpio@18100 {
compatible = "marvell,orion-gpio";
reg = <0x18100 0x40>;
compatible = "marvell,armada-370-gpio",
"marvell,orion-gpio";
reg = <0x18100 0x40>, <0x181c0 0x08>;
reg-names = "gpio", "pwm";
ngpios = <32>;
gpio-controller;
#gpio-cells = <2>;
#pwm-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&coreclk 0>;
};
gpio1: gpio@18140 {
compatible = "marvell,orion-gpio";
reg = <0x18140 0x40>;
compatible = "marvell,armada-370-gpio",
"marvell,orion-gpio";
reg = <0x18140 0x40>, <0x181c8 0x08>;
reg-names = "gpio", "pwm";
ngpios = <28>;
gpio-controller;
#gpio-cells = <2>;
#pwm-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&coreclk 0>;
};
system-controller@18200 {
systemc: system-controller@18200 {
compatible = "marvell,armada-380-system-controller",
"marvell,armada-370-xp-system-controller";
reg = <0x18200 0x100>;
@@ -386,7 +345,8 @@
mbusc: mbus-controller@20000 {
compatible = "marvell,mbus-controller";
reg = <0x20000 0x100>, <0x20180 0x20>;
reg = <0x20000 0x100>, <0x20180 0x20>,
<0x20250 0x8>;
};
mpic: interrupt-controller@20a00 {
@@ -399,7 +359,7 @@
interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
};
timer@20300 {
timer: timer@20300 {
compatible = "marvell,armada-380-timer",
"marvell,armada-xp-timer";
reg = <0x20300 0x30>, <0x21040 0x30>;
@@ -413,14 +373,14 @@
clock-names = "nbclk", "fixed";
};
watchdog@20300 {
watchdog: watchdog@20300 {
compatible = "marvell,armada-380-wdt";
reg = <0x20300 0x34>, <0x20704 0x4>, <0x18260 0x4>;
clocks = <&coreclk 2>, <&refclk>;
clock-names = "nbclk", "fixed";
};
cpurst@20800 {
cpurst: cpurst@20800 {
compatible = "marvell,armada-370-cpu-reset";
reg = <0x20800 0x10>;
};
@@ -430,16 +390,37 @@
reg = <0x20d20 0x6c>;
};
coherency-fabric@21010 {
coherencyfab: coherency-fabric@21010 {
compatible = "marvell,armada-380-coherency-fabric";
reg = <0x21010 0x1c>;
};
pmsu@22000 {
pmsu: pmsu@22000 {
compatible = "marvell,armada-380-pmsu";
reg = <0x22000 0x1000>;
};
/*
* As a special exception to the "order by
* register address" rule, the eth0 node is
* placed here to ensure that it gets
* registered as the first interface, since
* the network subsystem doesn't allow naming
* interfaces using DT aliases. Without this,
* the ordering of interfaces is different
* from the one used in U-Boot and the
* labeling of interfaces on the boards, which
* is very confusing for users.
*/
eth0: ethernet@70000 {
compatible = "marvell,armada-370-neta";
reg = <0x70000 0x4000>;
interrupts-extended = <&mpic 8>;
clocks = <&gateclk 4>;
tx-csum-limit = <9800>;
status = "disabled";
};
eth1: ethernet@30000 {
compatible = "marvell,armada-370-neta";
reg = <0x30000 0x4000>;
@@ -456,7 +437,7 @@
status = "disabled";
};
usb@58000 {
usb0: usb@58000 {
compatible = "marvell,orion-ehci";
reg = <0x58000 0x500>;
interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
@@ -464,8 +445,8 @@
status = "disabled";
};
xor@60800 {
compatible = "marvell,orion-xor";
xor0: xor@60800 {
compatible = "marvell,armada-380-xor", "marvell,orion-xor";
reg = <0x60800 0x100
0x60a00 0x100>;
clocks = <&gateclk 22>;
@@ -484,8 +465,8 @@
};
};
xor@60900 {
compatible = "marvell,orion-xor";
xor1: xor@60900 {
compatible = "marvell,armada-380-xor", "marvell,orion-xor";
reg = <0x60900 0x100
0x60b00 0x100>;
clocks = <&gateclk 28>;
@@ -504,14 +485,6 @@
};
};
eth0: ethernet@70000 {
compatible = "marvell,armada-370-neta";
reg = <0x70000 0x4000>;
interrupts-extended = <&mpic 8>;
clocks = <&gateclk 4>;
status = "disabled";
};
mdio: mdio@72004 {
#address-cells = <1>;
#size-cells = <0>;
@@ -520,14 +493,29 @@
clocks = <&gateclk 4>;
};
rtc@a3800 {
cesa: crypto@90000 {
compatible = "marvell,armada-38x-crypto";
reg = <0x90000 0x10000>;
reg-names = "regs";
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gateclk 23>, <&gateclk 21>,
<&gateclk 14>, <&gateclk 16>;
clock-names = "cesa0", "cesa1",
"cesaz0", "cesaz1";
marvell,crypto-srams = <&crypto_sram0>,
<&crypto_sram1>;
marvell,crypto-sram-size = <0x800>;
};
rtc: rtc@a3800 {
compatible = "marvell,armada-380-rtc";
reg = <0xa3800 0x20>, <0x184a0 0x0c>;
reg-names = "rtc", "rtc-soc";
interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
};
sata@a8000 {
ahci0: sata@a8000 {
compatible = "marvell,armada-380-ahci";
reg = <0xa8000 0x2000>;
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
@@ -535,7 +523,15 @@
status = "disabled";
};
sata@e0000 {
bm: bm@c8000 {
compatible = "marvell,armada-380-neta-bm";
reg = <0xc8000 0xac>;
clocks = <&gateclk 13>;
internal-mem = <&bm_bppi>;
status = "disabled";
};
ahci1: sata@e0000 {
compatible = "marvell,armada-380-ahci";
reg = <0xe0000 0x2000>;
interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
@@ -551,23 +547,23 @@
clock-output-names = "nand";
};
thermal@e8078 {
thermal: thermal@e8078 {
compatible = "marvell,armada380-thermal";
reg = <0xe4078 0x4>, <0xe4074 0x4>;
reg = <0xe4078 0x4>, <0xe4070 0x8>;
status = "okay";
};
flash@d0000 {
nand_controller: nand-controller@d0000 {
compatible = "marvell,armada370-nand","marvell,mvebu-pxa3xx-nand";
reg = <0xd0000 0x54>;
#address-cells = <1>;
#size-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&coredivclk 0>;
status = "disabled";
};
sdhci@d8000 {
sdhci: sdhci@d8000 {
compatible = "marvell,armada-380-sdhci";
reg-names = "sdhci", "mbus", "conf-sdio3";
reg = <0xd8000 0x1000>,
@@ -579,7 +575,7 @@
status = "disabled";
};
usb3@f0000 {
usb3_0: usb3@f0000 {
compatible = "marvell,armada-380-xhci";
reg = <0xf0000 0x4000>,<0xf4000 0x4000>;
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
@@ -587,7 +583,7 @@
status = "disabled";
};
usb3@f8000 {
usb3_1: usb3@f8000 {
compatible = "marvell,armada-380-xhci";
reg = <0xf8000 0x4000>,<0xfc000 0x4000>;
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
@@ -595,10 +591,63 @@
status = "disabled";
};
};
crypto_sram0: sa-sram0 {
compatible = "mmio-sram";
reg = <MBUS_ID(0x09, 0x19) 0 0x800>;
clocks = <&gateclk 23>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 MBUS_ID(0x09, 0x19) 0 0x800>;
};
crypto_sram1: sa-sram1 {
compatible = "mmio-sram";
reg = <MBUS_ID(0x09, 0x15) 0 0x800>;
clocks = <&gateclk 21>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 MBUS_ID(0x09, 0x15) 0 0x800>;
};
bm_bppi: bm-bppi {
compatible = "mmio-sram";
reg = <MBUS_ID(0x0c, 0x04) 0 0x100000>;
ranges = <0 MBUS_ID(0x0c, 0x04) 0 0x100000>;
#address-cells = <1>;
#size-cells = <1>;
clocks = <&gateclk 13>;
no-memory-wc;
status = "disabled";
};
spi0: spi@10600 {
compatible = "marvell,armada-380-spi",
"marvell,orion-spi";
reg = <MBUS_ID(0xf0, 0x01) 0x10600 0x50>;
#address-cells = <1>;
#size-cells = <0>;
cell-index = <0>;
interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&coreclk 0>;
status = "disabled";
};
spi1: spi@10680 {
compatible = "marvell,armada-380-spi",
"marvell,orion-spi";
reg = <MBUS_ID(0xf0, 0x01) 0x10680 0x50>;
#address-cells = <1>;
#size-cells = <0>;
cell-index = <1>;
interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&coreclk 0>;
status = "disabled";
};
};
clocks {
/* 2 GHz fixed main PLL */
/* 1 GHz fixed main PLL */
mainpll: mainpll {
compatible = "fixed-clock";
#clock-cells = <0>;

11
arch/arm/dts/armada-ap806.dtsi
View File

@@ -64,6 +64,17 @@
method = "smc";
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
psci-area@4000000 {
reg = <0x0 0x4000000 0x0 0x200000>;
no-map;
};
};
ap806 {
#address-cells = <2>;
#size-cells = <2>;

7
arch/arm/mach-mvebu/Kconfig
View File

@@ -132,6 +132,10 @@ config TARGET_CONTROLCENTERDC
bool "Support CONTROLCENTERDC"
select 88F6820
config TARGET_X530
bool "Support Allied Telesis x530"
select 88F6820
endchoice
config SYS_BOARD
@@ -149,6 +153,7 @@ config SYS_BOARD
default "maxbcm" if TARGET_MAXBCM
default "theadorable" if TARGET_THEADORABLE
default "a38x" if TARGET_CONTROLCENTERDC
default "x530" if TARGET_X530
config SYS_CONFIG_NAME
default "clearfog" if TARGET_CLEARFOG
@@ -165,6 +170,7 @@ config SYS_CONFIG_NAME
default "turris_omnia" if TARGET_TURRIS_OMNIA
default "turris_mox" if TARGET_TURRIS_MOX
default "controlcenterdc" if TARGET_CONTROLCENTERDC
default "x530" if TARGET_X530
config SYS_VENDOR
default "Marvell" if TARGET_DB_MV784MP_GP
@@ -179,6 +185,7 @@ config SYS_VENDOR
default "CZ.NIC" if TARGET_TURRIS_OMNIA
default "CZ.NIC" if TARGET_TURRIS_MOX
default "gdsys" if TARGET_CONTROLCENTERDC
default "alliedtelesis" if TARGET_X530
config SYS_SOC
default "mvebu"

4
arch/arm/mach-mvebu/arm64-common.c
View File

@@ -84,7 +84,7 @@ static void a8k_dram_init_banksize(void)
}
}
int dram_init_banksize(void)
__weak int dram_init_banksize(void)
{
if (CONFIG_IS_ENABLED(ARMADA_8K))
a8k_dram_init_banksize();
@@ -94,7 +94,7 @@ int dram_init_banksize(void)
return 0;
}
int dram_init(void)
__weak int dram_init(void)
{
if (CONFIG_IS_ENABLED(ARMADA_8K)) {
gd->ram_size = a8k_dram_scan_ap_sz();