stm32mp: regulator: add SoC pwr regulator support
This driver binds and manages the following regulator of SoC's PWR block : - reg11 - reg18 - usb33 Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
This commit is contained in:
Patrick Delaunay
Tom Rini
parent
cb61c9ec64
commit
e8b85e810a
@ -9,3 +9,4 @@ obj-y += syscon.o
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obj-$(CONFIG_SPL_BUILD) += spl.o
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obj-$(CONFIG_ARMV7_PSCI) += psci.o
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obj-$(CONFIG_$(SPL_)DM_REGULATOR) += pwr_regulator.o
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@ -28,6 +28,7 @@
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enum {
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STM32MP_SYSCON_UNKNOWN,
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STM32MP_SYSCON_STGEN,
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STM32MP_SYSCON_PWR,
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};
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/*
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274
arch/arm/mach-stm32mp/pwr_regulator.c
Normal file
274
arch/arm/mach-stm32mp/pwr_regulator.c
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@ -0,0 +1,274 @@
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// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
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/*
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* Copyright (C) 2018, STMicroelectronics - All Rights Reserved
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*/
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#include <common.h>
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#include <dm.h>
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#include <errno.h>
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#include <regmap.h>
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#include <syscon.h>
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#include <power/pmic.h>
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#include <power/regulator.h>
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#define STM32MP_PWR_CR3 0xc
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#define STM32MP_PWR_CR3_USB33DEN BIT(24)
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#define STM32MP_PWR_CR3_USB33RDY BIT(26)
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#define STM32MP_PWR_CR3_REG18DEN BIT(28)
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#define STM32MP_PWR_CR3_REG18RDY BIT(29)
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#define STM32MP_PWR_CR3_REG11DEN BIT(30)
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#define STM32MP_PWR_CR3_REG11RDY BIT(31)
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struct stm32mp_pwr_reg_info {
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u32 enable;
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u32 ready;
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char *name;
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};
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struct stm32mp_pwr_priv {
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struct regmap *regmap;
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};
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static int stm32mp_pwr_write(struct udevice *dev, uint reg,
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const uint8_t *buff, int len)
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{
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struct stm32mp_pwr_priv *priv = dev_get_priv(dev);
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u32 val = *(u32 *)buff;
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if (len != 4)
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return -EINVAL;
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return regmap_write(priv->regmap, STM32MP_PWR_CR3, val);
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}
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static int stm32mp_pwr_read(struct udevice *dev, uint reg, uint8_t *buff,
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int len)
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{
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struct stm32mp_pwr_priv *priv = dev_get_priv(dev);
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if (len != 4)
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return -EINVAL;
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return regmap_read(priv->regmap, STM32MP_PWR_CR3, (u32 *)buff);
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}
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static int stm32mp_pwr_ofdata_to_platdata(struct udevice *dev)
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{
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struct stm32mp_pwr_priv *priv = dev_get_priv(dev);
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struct regmap *regmap;
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regmap = syscon_get_regmap_by_driver_data(STM32MP_SYSCON_PWR);
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if (IS_ERR(regmap)) {
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pr_err("%s: unable to find regmap (%ld)\n", __func__,
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PTR_ERR(regmap));
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return PTR_ERR(regmap);
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}
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priv->regmap = regmap;
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return 0;
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}
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static const struct pmic_child_info pwr_children_info[] = {
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{ .prefix = "reg", .driver = "stm32mp_pwr_regulator"},
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{ .prefix = "usb", .driver = "stm32mp_pwr_regulator"},
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{ },
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};
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static int stm32mp_pwr_bind(struct udevice *dev)
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{
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int children;
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children = pmic_bind_children(dev, dev->node, pwr_children_info);
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if (!children)
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dev_dbg(dev, "no child found\n");
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return 0;
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}
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static struct dm_pmic_ops stm32mp_pwr_ops = {
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.read = stm32mp_pwr_read,
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.write = stm32mp_pwr_write,
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};
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static const struct udevice_id stm32mp_pwr_ids[] = {
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{ .compatible = "st,stm32mp1,pwr-reg" },
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{ }
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};
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U_BOOT_DRIVER(stm32mp_pwr_pmic) = {
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.name = "stm32mp_pwr_pmic",
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.id = UCLASS_PMIC,
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.of_match = stm32mp_pwr_ids,
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.bind = stm32mp_pwr_bind,
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.ops = &stm32mp_pwr_ops,
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.ofdata_to_platdata = stm32mp_pwr_ofdata_to_platdata,
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.priv_auto_alloc_size = sizeof(struct stm32mp_pwr_priv),
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};
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static const struct stm32mp_pwr_reg_info stm32mp_pwr_reg11 = {
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.enable = STM32MP_PWR_CR3_REG11DEN,
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.ready = STM32MP_PWR_CR3_REG11RDY,
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.name = "reg11"
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};
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static const struct stm32mp_pwr_reg_info stm32mp_pwr_reg18 = {
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.enable = STM32MP_PWR_CR3_REG18DEN,
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.ready = STM32MP_PWR_CR3_REG18RDY,
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.name = "reg18"
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};
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static const struct stm32mp_pwr_reg_info stm32mp_pwr_usb33 = {
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.enable = STM32MP_PWR_CR3_USB33DEN,
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.ready = STM32MP_PWR_CR3_USB33RDY,
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.name = "usb33"
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};
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static const struct stm32mp_pwr_reg_info *stm32mp_pwr_reg_infos[] = {
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&stm32mp_pwr_reg11,
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&stm32mp_pwr_reg18,
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&stm32mp_pwr_usb33,
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NULL
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};
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static int stm32mp_pwr_regulator_probe(struct udevice *dev)
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{
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const struct stm32mp_pwr_reg_info **p = stm32mp_pwr_reg_infos;
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struct dm_regulator_uclass_platdata *uc_pdata;
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uc_pdata = dev_get_uclass_platdata(dev);
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while (*p) {
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int rc;
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rc = dev_read_stringlist_search(dev, "regulator-name",
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(*p)->name);
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if (rc >= 0) {
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dev_dbg(dev, "found regulator %s\n", (*p)->name);
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break;
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} else if (rc != -ENODATA) {
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return rc;
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}
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p++;
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}
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if (!*p) {
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int i = 0;
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const char *s;
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dev_dbg(dev, "regulator ");
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while (dev_read_string_index(dev, "regulator-name",
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i++, &s) >= 0)
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dev_dbg(dev, "%s'%s' ", (i > 1) ? ", " : "", s);
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dev_dbg(dev, "%s not supported\n", (i > 2) ? "are" : "is");
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return -EINVAL;
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}
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uc_pdata->type = REGULATOR_TYPE_FIXED;
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dev->priv = (void *)*p;
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return 0;
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}
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static int stm32mp_pwr_regulator_set_value(struct udevice *dev, int uV)
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{
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struct dm_regulator_uclass_platdata *uc_pdata;
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uc_pdata = dev_get_uclass_platdata(dev);
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if (!uc_pdata)
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return -ENXIO;
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if (uc_pdata->min_uV != uV) {
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dev_dbg(dev, "Invalid uV=%d for: %s\n", uV, uc_pdata->name);
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return -EINVAL;
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}
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return 0;
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}
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static int stm32mp_pwr_regulator_get_value(struct udevice *dev)
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{
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struct dm_regulator_uclass_platdata *uc_pdata;
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uc_pdata = dev_get_uclass_platdata(dev);
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if (!uc_pdata)
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return -ENXIO;
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if (uc_pdata->min_uV != uc_pdata->max_uV) {
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dev_dbg(dev, "Invalid constraints for: %s\n", uc_pdata->name);
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return -EINVAL;
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}
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return uc_pdata->min_uV;
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}
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static int stm32mp_pwr_regulator_get_enable(struct udevice *dev)
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{
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const struct stm32mp_pwr_reg_info *p = dev_get_priv(dev);
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int rc;
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u32 reg;
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rc = pmic_read(dev->parent, 0, (uint8_t *)®, sizeof(reg));
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if (rc)
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return rc;
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dev_dbg(dev, "%s id %s\n", p->name, (reg & p->enable) ? "on" : "off");
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return (reg & p->enable) != 0;
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}
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static int stm32mp_pwr_regulator_set_enable(struct udevice *dev, bool enable)
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{
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const struct stm32mp_pwr_reg_info *p = dev_get_priv(dev);
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int rc;
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u32 reg;
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u32 time_start;
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dev_dbg(dev, "Turning %s %s\n", enable ? "on" : "off", p->name);
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rc = pmic_read(dev->parent, 0, (uint8_t *)®, sizeof(reg));
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if (rc)
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return rc;
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/* if regulator is already in the wanted state, nothing to do */
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if (!!(reg & p->enable) == enable)
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return 0;
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reg &= ~p->enable;
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if (enable)
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reg |= p->enable;
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rc = pmic_write(dev->parent, 0, (uint8_t *)®, sizeof(reg));
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if (rc)
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return rc;
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if (!enable)
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return 0;
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/* waiting ready for enable */
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time_start = get_timer(0);
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while (1) {
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rc = pmic_read(dev->parent, 0, (uint8_t *)®, sizeof(reg));
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if (rc)
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return rc;
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if (reg & p->ready)
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break;
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if (get_timer(time_start) > CONFIG_SYS_HZ) {
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dev_dbg(dev, "%s: timeout\n", p->name);
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return -ETIMEDOUT;
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}
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}
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return 0;
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}
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static const struct dm_regulator_ops stm32mp_pwr_regulator_ops = {
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.set_value = stm32mp_pwr_regulator_set_value,
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.get_value = stm32mp_pwr_regulator_get_value,
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.get_enable = stm32mp_pwr_regulator_get_enable,
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.set_enable = stm32mp_pwr_regulator_set_enable,
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};
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U_BOOT_DRIVER(stm32mp_pwr_regulator) = {
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.name = "stm32mp_pwr_regulator",
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.id = UCLASS_REGULATOR,
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.ops = &stm32mp_pwr_regulator_ops,
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.probe = stm32mp_pwr_regulator_probe,
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};
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@ -11,6 +11,8 @@
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static const struct udevice_id stm32mp_syscon_ids[] = {
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{ .compatible = "st,stm32-stgen",
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.data = STM32MP_SYSCON_STGEN },
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{ .compatible = "st,stm32mp1-pwr",
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.data = STM32MP_SYSCON_PWR },
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{ }
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};
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