fix: phy: marvell: cp110: fix comphy lane 4 selection options
The comphy configuration is incorrect. Set the correct values for SGMII. In addition, remove xaui from the comment as it is not supported. Signed-off-by: Yoav Gvili <ygvili@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de> Signed-off-by: Igal Liberman <igall@marvell.com> Reviewed-by: Stefan Roese <sr@denx.de>
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@ -34,7 +34,7 @@ struct utmi_phy_data {
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* PIPE selector include USB and PCIe options.
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* PHY selector include the Ethernet and SATA options, every Ethernet
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* option has different options, for example: serdes lane2 had option
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* Eth_port_0 that include (SGMII0, XAUI0, RXAUI0, SFI)
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* Eth_port_0 that include (SGMII0, RXAUI0, SFI)
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*/
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struct comphy_mux_data cp110_comphy_phy_mux_data[] = {
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{4, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII1, 0x1}, /* Lane 0 */
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@ -46,9 +46,9 @@ struct comphy_mux_data cp110_comphy_phy_mux_data[] = {
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{PHY_TYPE_SATA0, 0x4} } },
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{8, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_RXAUI1, 0x1}, /* Lane 3 */
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{PHY_TYPE_SGMII1, 0x2}, {PHY_TYPE_SATA1, 0x4} } },
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{7, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII2, 0x1}, /* Lane 4 */
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{7, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII0, 0x2}, /* Lane 4 */
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{PHY_TYPE_RXAUI0, 0x2}, {PHY_TYPE_SFI, 0x2},
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{PHY_TYPE_SGMII1, 0x2} } },
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{PHY_TYPE_SGMII1, 0x1} } },
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{6, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII2, 0x1}, /* Lane 5 */
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{PHY_TYPE_RXAUI1, 0x2}, {PHY_TYPE_SATA1, 0x4} } },
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};
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