imx: mx6slevk: add SPL support
Add SPL boot support for mx6slevk board. 1. Introduce a configuration file mx6slevk_spl_defconfig. 2. i.MX6SL has same DRAM space with i.MX6SX, need to change SPL DRAM SPACE. 3. Include imx6_spl.h and related SPL macro in mx6slevk.h. 4. select SUPPORT_SPL for TARGET_MX6SLEVK. 5. Add SPL board code to do related initialization. Boot Log: U-Boot SPL 2015.07-00544-g1594a76 (Aug 17 2015 - 01:56:59) reading u-boot.img reading u-boot.img U-Boot 2015.07-00544-g1594a76 (Aug 17 2015 - 01:56:59 +0000) CPU: Freescale i.MX6SL rev1.2 996 MHz (running at 396 MHz) CPU: Commercial temperature grade (0C to 95C) at 50C Reset cause: POR Board: MX6SLEVK I2C: ready DRAM: 1 GiB PMIC: PFUZE100 ID=0x10 MMC: FSL_SDHC: 0, FSL_SDHC: 1, FSL_SDHC: 2 *** Warning - bad CRC, using default environment In: serial Out: serial Err: serial Net: FEC [PRIME] Hit any key to stop autoboot: 0 Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com>
This commit is contained in:
Peng Fan
Stefano Babic
parent
eb796cbb69
commit
e7d3b21bb7
@ -91,6 +91,7 @@ config TARGET_MX6SABRESD
|
||||
config TARGET_MX6SLEVK
|
||||
bool "mx6slevk"
|
||||
select CPU_V7
|
||||
select SUPPORT_SPL
|
||||
|
||||
config TARGET_MX6SXSABRESD
|
||||
bool "mx6sxsabresd"
|
||||
|
||||
@ -8,7 +8,9 @@
|
||||
|
||||
#include <asm/arch/clock.h>
|
||||
#include <asm/arch/iomux.h>
|
||||
#include <asm/arch/crm_regs.h>
|
||||
#include <asm/arch/imx-regs.h>
|
||||
#include <asm/arch/mx6-ddr.h>
|
||||
#include <asm/arch/mx6-pins.h>
|
||||
#include <asm/arch/sys_proto.h>
|
||||
#include <asm/gpio.h>
|
||||
@ -190,6 +192,7 @@ int board_mmc_getcd(struct mmc *mmc)
|
||||
|
||||
int board_mmc_init(bd_t *bis)
|
||||
{
|
||||
#ifndef CONFIG_SPL_BUILD
|
||||
int i, ret;
|
||||
|
||||
/*
|
||||
@ -234,6 +237,44 @@ int board_mmc_init(bd_t *bis)
|
||||
}
|
||||
|
||||
return 0;
|
||||
#else
|
||||
struct src *src_regs = (struct src *)SRC_BASE_ADDR;
|
||||
u32 val;
|
||||
u32 port;
|
||||
|
||||
val = readl(&src_regs->sbmr1);
|
||||
|
||||
/* Boot from USDHC */
|
||||
port = (val >> 11) & 0x3;
|
||||
switch (port) {
|
||||
case 0:
|
||||
imx_iomux_v3_setup_multiple_pads(usdhc1_pads,
|
||||
ARRAY_SIZE(usdhc1_pads));
|
||||
gpio_direction_input(USDHC1_CD_GPIO);
|
||||
usdhc_cfg[0].esdhc_base = USDHC1_BASE_ADDR;
|
||||
usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
|
||||
break;
|
||||
case 1:
|
||||
imx_iomux_v3_setup_multiple_pads(usdhc2_pads,
|
||||
ARRAY_SIZE(usdhc2_pads));
|
||||
gpio_direction_input(USDHC2_CD_GPIO);
|
||||
usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR;
|
||||
usdhc_cfg[0].max_bus_width = 4;
|
||||
usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
|
||||
break;
|
||||
case 2:
|
||||
imx_iomux_v3_setup_multiple_pads(usdhc3_pads,
|
||||
ARRAY_SIZE(usdhc3_pads));
|
||||
gpio_direction_input(USDHC3_CD_GPIO);
|
||||
usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR;
|
||||
usdhc_cfg[0].max_bus_width = 4;
|
||||
usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
|
||||
break;
|
||||
}
|
||||
|
||||
gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
|
||||
return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
|
||||
#endif
|
||||
}
|
||||
|
||||
#ifdef CONFIG_SYS_I2C_MXC
|
||||
@ -361,3 +402,126 @@ int checkboard(void)
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_SPL_BUILD
|
||||
#include <spl.h>
|
||||
#include <libfdt.h>
|
||||
|
||||
const struct mx6sl_iomux_ddr_regs mx6_ddr_ioregs = {
|
||||
.dram_sdqs0 = 0x00003030,
|
||||
.dram_sdqs1 = 0x00003030,
|
||||
.dram_sdqs2 = 0x00003030,
|
||||
.dram_sdqs3 = 0x00003030,
|
||||
.dram_dqm0 = 0x00000030,
|
||||
.dram_dqm1 = 0x00000030,
|
||||
.dram_dqm2 = 0x00000030,
|
||||
.dram_dqm3 = 0x00000030,
|
||||
.dram_cas = 0x00000030,
|
||||
.dram_ras = 0x00000030,
|
||||
.dram_sdclk_0 = 0x00000028,
|
||||
.dram_reset = 0x00000030,
|
||||
.dram_sdba2 = 0x00000000,
|
||||
.dram_odt0 = 0x00000008,
|
||||
.dram_odt1 = 0x00000008,
|
||||
};
|
||||
|
||||
const struct mx6sl_iomux_grp_regs mx6_grp_ioregs = {
|
||||
.grp_b0ds = 0x00000030,
|
||||
.grp_b1ds = 0x00000030,
|
||||
.grp_b2ds = 0x00000030,
|
||||
.grp_b3ds = 0x00000030,
|
||||
.grp_addds = 0x00000030,
|
||||
.grp_ctlds = 0x00000030,
|
||||
.grp_ddrmode_ctl = 0x00020000,
|
||||
.grp_ddrpke = 0x00000000,
|
||||
.grp_ddrmode = 0x00020000,
|
||||
.grp_ddr_type = 0x00080000,
|
||||
};
|
||||
|
||||
const struct mx6_mmdc_calibration mx6_mmcd_calib = {
|
||||
.p0_mpdgctrl0 = 0x20000000,
|
||||
.p0_mpdgctrl1 = 0x00000000,
|
||||
.p0_mprddlctl = 0x4241444a,
|
||||
.p0_mpwrdlctl = 0x3030312b,
|
||||
.mpzqlp2ctl = 0x1b4700c7,
|
||||
};
|
||||
|
||||
static struct mx6_lpddr2_cfg mem_ddr = {
|
||||
.mem_speed = 800,
|
||||
.density = 4,
|
||||
.width = 32,
|
||||
.banks = 8,
|
||||
.rowaddr = 14,
|
||||
.coladdr = 10,
|
||||
.trcd_lp = 2000,
|
||||
.trppb_lp = 2000,
|
||||
.trpab_lp = 2250,
|
||||
.trasmin = 4200,
|
||||
};
|
||||
|
||||
static void ccgr_init(void)
|
||||
{
|
||||
struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
|
||||
|
||||
writel(0xFFFFFFFF, &ccm->CCGR0);
|
||||
writel(0xFFFFFFFF, &ccm->CCGR1);
|
||||
writel(0xFFFFFFFF, &ccm->CCGR2);
|
||||
writel(0xFFFFFFFF, &ccm->CCGR3);
|
||||
writel(0xFFFFFFFF, &ccm->CCGR4);
|
||||
writel(0xFFFFFFFF, &ccm->CCGR5);
|
||||
writel(0xFFFFFFFF, &ccm->CCGR6);
|
||||
|
||||
writel(0x00260324, &ccm->cbcmr);
|
||||
}
|
||||
|
||||
static void spl_dram_init(void)
|
||||
{
|
||||
struct mx6_ddr_sysinfo sysinfo = {
|
||||
.dsize = mem_ddr.width / 32,
|
||||
.cs_density = 20,
|
||||
.ncs = 2,
|
||||
.cs1_mirror = 0,
|
||||
.walat = 0,
|
||||
.ralat = 2,
|
||||
.mif3_mode = 3,
|
||||
.bi_on = 1,
|
||||
.rtt_wr = 0, /* LPDDR2 does not need rtt_wr rtt_nom */
|
||||
.rtt_nom = 0,
|
||||
.sde_to_rst = 0, /* LPDDR2 does not need this field */
|
||||
.rst_to_cke = 0x10, /* JEDEC value for LPDDR2: 200us */
|
||||
.ddr_type = DDR_TYPE_LPDDR2,
|
||||
};
|
||||
mx6sl_dram_iocfg(32, &mx6_ddr_ioregs, &mx6_grp_ioregs);
|
||||
mx6_dram_cfg(&sysinfo, &mx6_mmcd_calib, &mem_ddr);
|
||||
}
|
||||
|
||||
void board_init_f(ulong dummy)
|
||||
{
|
||||
/* setup AIPS and disable watchdog */
|
||||
arch_cpu_init();
|
||||
|
||||
ccgr_init();
|
||||
|
||||
/* iomux and setup of i2c */
|
||||
board_early_init_f();
|
||||
|
||||
/* setup GP timer */
|
||||
timer_init();
|
||||
|
||||
/* UART clocks enabled and gd valid - init serial console */
|
||||
preloader_console_init();
|
||||
|
||||
/* DDR initialization */
|
||||
spl_dram_init();
|
||||
|
||||
/* Clear the BSS. */
|
||||
memset(__bss_start, 0, __bss_end - __bss_start);
|
||||
|
||||
/* load/boot image from boot device */
|
||||
board_init_r(NULL, 0);
|
||||
}
|
||||
|
||||
void reset_cpu(ulong addr)
|
||||
{
|
||||
}
|
||||
#endif
|
||||
|
||||
8
configs/mx6slevk_spl_defconfig
Normal file
8
configs/mx6slevk_spl_defconfig
Normal file
@ -0,0 +1,8 @@
|
||||
CONFIG_ARM=y
|
||||
CONFIG_ARCH_MX6=y
|
||||
CONFIG_TARGET_MX6SLEVK=y
|
||||
CONFIG_SPL=y
|
||||
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,SPL,MX6SL"
|
||||
CONFIG_DM=y
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_DM_THERMAL=y
|
||||
@ -61,7 +61,7 @@
|
||||
#define CONFIG_SPL_LIBDISK_SUPPORT
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL)
|
||||
#if defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL) || defined(CONFIG_MX6SL)
|
||||
#define CONFIG_SPL_BSS_START_ADDR 0x88200000
|
||||
#define CONFIG_SPL_BSS_MAX_SIZE 0x100000 /* 1 MB */
|
||||
#define CONFIG_SYS_SPL_MALLOC_START 0x88300000
|
||||
|
||||
@ -11,6 +11,13 @@
|
||||
|
||||
#include "mx6_common.h"
|
||||
|
||||
#ifdef CONFIG_SPL
|
||||
#define CONFIG_SPL_LIBCOMMON_SUPPORT
|
||||
#define CONFIG_SPL_MMC_SUPPORT
|
||||
#define CONFIG_SPL_FAT_SUPPORT
|
||||
#include "imx6_spl.h"
|
||||
#endif
|
||||
|
||||
#define MACH_TYPE_MX6SLEVK 4307
|
||||
#define CONFIG_MACH_TYPE MACH_TYPE_MX6SLEVK
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user