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Added support for TQM834x boards.

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This commit is contained in:
Marian Balakowicz 2005-10-11 19:09:42 +02:00
parent 3df5bea0b0
commit e6f2e90233
25 changed files with 1282 additions and 140 deletions
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2
MAKEALL
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@ -114,7 +114,7 @@ LIST_8260=" \
######################################################################### #########################################################################
LIST_83xx=" \ LIST_83xx=" \
MPC8349ADS \ MPC8349ADS TQM834x\
" "

3
Makefile
View File

@ -1241,6 +1241,9 @@ TASREG_config : unconfig
MPC8349ADS_config: unconfig MPC8349ADS_config: unconfig
@./mkconfig $(@:_config=) ppc mpc83xx mpc8349ads @./mkconfig $(@:_config=) ppc mpc83xx mpc8349ads
TQM834x_config: unconfig
@./mkconfig $(@:_config=) ppc mpc83xx tqm834x
######################################################################### #########################################################################
## MPC85xx Systems ## MPC85xx Systems
######################################################################### #########################################################################

45
board/tqm834x/Makefile Normal file
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@ -0,0 +1,45 @@
#
# Copyright 2004 Freescale Semiconductor, Inc.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = lib$(BOARD).a
OBJS := $(BOARD).o
$(LIB): $(OBJS) $(SOBJS)
$(AR) crv $@ $(OBJS)
clean:
rm -f $(SOBJS) $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak .depend
#########################################################################
.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
-include .depend
#########################################################################

24
board/tqm834x/config.mk Normal file
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@ -0,0 +1,24 @@
#
# Copyright 2004 Freescale Semiconductor, Inc.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
TEXT_BASE = 0x80000000

416
board/tqm834x/tqm834x.c Normal file
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@ -0,0 +1,416 @@
/*
* (C) Copyright 2005
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
*/
#include <common.h>
#include <ioports.h>
#include <mpc83xx.h>
#include <asm/mpc8349_pci.h>
#include <i2c.h>
#include <spd.h>
#include <miiphy.h>
#include <asm-ppc/mmu.h>
#if defined(CONFIG_PCI)
#include <pci.h>
#endif
#define IOSYNC asm("eieio")
#define ISYNC asm("isync")
#define SYNC asm("sync")
#define FPW FLASH_PORT_WIDTH
#define FPWV FLASH_PORT_WIDTHV
#define DDR_MAX_SIZE_PER_CS 0x20000000
#if defined(DDR_CASLAT_20)
#define TIMING_CASLAT TIMING_CFG1_CASLAT_20
#define MODE_CASLAT DDR_MODE_CASLAT_20
#else
#define TIMING_CASLAT TIMING_CFG1_CASLAT_25
#define MODE_CASLAT DDR_MODE_CASLAT_25
#endif
#define INITIAL_CS_CONFIG (CSCONFIG_EN | CSCONFIG_ROW_BIT_12 | \
CSCONFIG_COL_BIT_9)
/* Global variable used to store detected number of banks */
int tqm834x_num_flash_banks;
/* External definitions */
ulong flash_get_size (ulong base, int banknum);
extern flash_info_t flash_info[];
extern long spd_sdram (void);
/* Local functions */
static int detect_num_flash_banks(void);
static long int get_ddr_bank_size(short cs, volatile long *base);
static void set_cs_bounds(short cs, long base, long size);
static void set_cs_config(short cs, long config);
static void set_ddr_config(void);
/* Local variable */
static volatile immap_t *im = (immap_t *)CFG_IMMRBAR;
/**************************************************************************
* Board initialzation after relocation to RAM. Used to detect the number
* of Flash banks on TQM834x.
*/
int board_early_init_r (void) {
/* sanity check, IMMARBAR should be mirrored at offset zero of IMMR */
if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
return 0;
/* detect the number of Flash banks */
return detect_num_flash_banks();
}
/**************************************************************************
* DRAM initalization and size detection
*/
long int initdram (int board_type)
{
long bank_size;
long size;
int cs;
/* during size detection, set up the max DDRLAW size */
im->sysconf.ddrlaw[0].bar = CFG_DDR_BASE;
im->sysconf.ddrlaw[0].ar = (LAWAR_EN | LAWAR_SIZE_2G);
/* set CS bounds to maximum size */
for(cs = 0; cs < 4; ++cs) {
set_cs_bounds(cs,
CFG_DDR_BASE + (cs * DDR_MAX_SIZE_PER_CS),
DDR_MAX_SIZE_PER_CS);
set_cs_config(cs, INITIAL_CS_CONFIG);
}
/* configure ddr controller */
set_ddr_config();
udelay(200);
/* enable DDR controller */
im->ddr.sdram_cfg = (SDRAM_CFG_MEM_EN |
SDRAM_CFG_SREN |
SDRAM_CFG_SDRAM_TYPE_DDR);
SYNC;
/* size detection */
debug("\n");
size = 0;
for(cs = 0; cs < 4; ++cs) {
debug("\nDetecting Bank%d\n", cs);
bank_size = get_ddr_bank_size(cs,
(volatile long*)(CFG_DDR_BASE + size));
size += bank_size;
debug("DDR Bank%d size: %d MiB\n\n", cs, bank_size >> 20);
/* exit if less than one bank */
if(size < DDR_MAX_SIZE_PER_CS) break;
}
return size;
}
/**************************************************************************
* checkboard()
*/
int checkboard (void)
{
puts("Board: TQM834x\n");
#ifdef CONFIG_PCI
printf("PCI1: 32 bit, %d MHz (compiled)\n",
CONFIG_SYS_CLK_FREQ / 1000000);
#else
printf("PCI1: disabled\n");
#endif
return 0;
}
#if defined(CONFIG_PCI)
/*
* Initialize PCI Devices, report devices found
*/
/* FIXME: No PCI support */
#endif /* CONFIG_PCI */
/**************************************************************************
* pci_init_board()
*/
void
pci_init_board(void)
{
#ifdef CONFIG_PCI
extern void pci_mpc83xx_init(volatile struct pci_controller *hose);
pci_mpc83xx_init(hose);
#endif /* CONFIG_PCI */
}
/**************************************************************************
*
* Local functions
*
*************************************************************************/
/**************************************************************************
* Detect the number of flash banks (1 or 2). Store it in
* a global variable tqm834x_num_flash_banks.
* Bank detection code based on the Monitor code.
*/
static int detect_num_flash_banks(void)
{
typedef unsigned long FLASH_PORT_WIDTH;
typedef volatile unsigned long FLASH_PORT_WIDTHV;
FPWV *bank1_base;
FPWV *bank2_base;
FPW bank1_read;
FPW bank2_read;
ulong bank1_size;
ulong bank2_size;
ulong total_size;
tqm834x_num_flash_banks = 2; /* assume two banks */
/* Get bank 1 and 2 information */
bank1_size = flash_get_size(CFG_FLASH_BASE, 0);
debug("Bank1 size: %lu\n", bank1_size);
bank2_size = flash_get_size(CFG_FLASH_BASE + bank1_size, 1);
debug("Bank2 size: %lu\n", bank2_size);
total_size = bank1_size + bank2_size;
if (bank2_size > 0) {
/* Seems like we've got bank 2, but maybe it's mirrored 1 */
/* Set the base addresses */
bank1_base = (FPWV *) (CFG_FLASH_BASE);
bank2_base = (FPWV *) (CFG_FLASH_BASE + bank1_size);
/* Put bank 2 into CFI command mode and read */
bank2_base[0x55] = 0x00980098;
IOSYNC;
ISYNC;
bank2_read = bank2_base[0x10];
/* Read from bank 1 (it's in read mode) */
bank1_read = bank1_base[0x10];
/* Reset Flash */
bank1_base[0] = 0x00F000F0;
bank2_base[0] = 0x00F000F0;
if (bank2_read == bank1_read) {
/*
* Looks like just one bank, but not sure yet. Let's
* read from bank 2 in autosoelect mode.
*/
bank2_base[0x0555] = 0x00AA00AA;
bank2_base[0x02AA] = 0x00550055;
bank2_base[0x0555] = 0x00900090;
IOSYNC;
ISYNC;
bank2_read = bank2_base[0x10];
/* Read from bank 1 (it's in read mode) */
bank1_read = bank1_base[0x10];
/* Reset Flash */
bank1_base[0] = 0x00F000F0;
bank2_base[0] = 0x00F000F0;
if (bank2_read == bank1_read) {
/*
* In both CFI command and autoselect modes,
* we got the some data reading from Flash.
* There is only one mirrored bank.
*/
tqm834x_num_flash_banks = 1;
total_size = bank1_size;
}
}
}
debug("Number of flash banks detected: %d\n", tqm834x_num_flash_banks);
/* set OR0 and BR0 */
im->lbus.bank[0].or = CFG_OR_TIMING_FLASH |
(-(total_size) & OR_GPCM_AM);
im->lbus.bank[0].br = (CFG_FLASH_BASE & BR_BA) |
(BR_MS_GPCM | BR_PS_32 | BR_V);
return (0);
}
/*************************************************************************
* Detect the size of a ddr bank. Sets CS bounds and CS config accordingly.
*/
static long int get_ddr_bank_size(short cs, volatile long *base)
{
/* This array lists all valid DDR SDRAM configurations, with
* Bank sizes in bytes. (Refer to Table 9-27 in the MPC8349E RM).
* The last entry has to to have size equal 0 and is igonred during
* autodection. Bank sizes must be in increasing order of size
*/
struct {
long row;
long col;
long size;
} conf[] = {
{CSCONFIG_ROW_BIT_12, CSCONFIG_COL_BIT_8, 32 << 20},
{CSCONFIG_ROW_BIT_12, CSCONFIG_COL_BIT_9, 64 << 20},
{CSCONFIG_ROW_BIT_12, CSCONFIG_COL_BIT_10, 128 << 20},
{CSCONFIG_ROW_BIT_13, CSCONFIG_COL_BIT_9, 128 << 20},
{CSCONFIG_ROW_BIT_13, CSCONFIG_COL_BIT_10, 256 << 20},
{CSCONFIG_ROW_BIT_13, CSCONFIG_COL_BIT_11, 512 << 20},
{CSCONFIG_ROW_BIT_14, CSCONFIG_COL_BIT_10, 512 << 20},
{CSCONFIG_ROW_BIT_14, CSCONFIG_COL_BIT_11, 1024 << 20},
{0, 0, 0}
};
int i;
int detected;
long size;
detected = -1;
for(i = 0; conf[i].size != 0; ++i) {
/* set sdram bank configuration */
set_cs_config(cs, CSCONFIG_EN | conf[i].col | conf[i].row);
debug("Getting RAM size...\n");
size = get_ram_size(base, DDR_MAX_SIZE_PER_CS);
if((size == conf[i].size) && (i == detected + 1))
detected = i;
debug("Trying %ld x %ld (%ld MiB) at addr %p, detected: %ld MiB\n",
conf[i].row,
conf[i].col,
conf[i].size >> 20,
base,
size >> 20);
}
if(detected == -1){
/* disable empty cs */
debug("\nNo valid configurations for CS%d, disabling...\n", cs);
set_cs_config(cs, 0);
return 0;
}
debug("\nDetected configuration %ld x %ld (%ld MiB) at addr %p\n",
conf[detected].row, conf[detected].col, conf[detected].size >> 20, base);
/* configure cs ro detected params */
set_cs_config(cs, CSCONFIG_EN | conf[detected].row |
conf[detected].col);
set_cs_bounds(cs, (long)base, conf[detected].size);
return(conf[detected].size);
}
/**************************************************************************
* Sets DDR bank CS bounds.
*/
static void set_cs_bounds(short cs, long base, long size)
{
debug("Setting bounds %08x, %08x for cs %d\n", base, size, cs);
if(size == 0){
im->ddr.csbnds[cs].csbnds = 0x00000000;
} else {
im->ddr.csbnds[cs].csbnds =
((base >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
(((base + size - 1) >> CSBNDS_EA_SHIFT) &
CSBNDS_EA);
}
SYNC;
}
/**************************************************************************
* Sets DDR banks CS configuration.
* config == 0x00000000 disables the CS.
*/
static void set_cs_config(short cs, long config)
{
debug("Setting config %08x for cs %d\n", config, cs);
im->ddr.cs_config[cs] = config;
SYNC;
}
/**************************************************************************
* Sets DDR clocks, timings and configuration.
*/
static void set_ddr_config(void) {
/* clock control */
im->ddr.sdram_clk_cntl = DDR_SDRAM_CLK_CNTL_SS_EN |
DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05;
SYNC;
/* timing configuration */
im->ddr.timing_cfg_1 =
(4 << TIMING_CFG1_PRETOACT_SHIFT) |
(7 << TIMING_CFG1_ACTTOPRE_SHIFT) |
(4 << TIMING_CFG1_ACTTORW_SHIFT) |
(5 << TIMING_CFG1_REFREC_SHIFT) |
(3 << TIMING_CFG1_WRREC_SHIFT) |
(3 << TIMING_CFG1_ACTTOACT_SHIFT) |
(1 << TIMING_CFG1_WRTORD_SHIFT) |
(TIMING_CFG1_CASLAT & TIMING_CASLAT);
im->ddr.timing_cfg_2 =
TIMING_CFG2_CPO_DEF |
(2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT);
SYNC;
/* don't enable DDR controller yet */
im->ddr.sdram_cfg =
SDRAM_CFG_SREN |
SDRAM_CFG_SDRAM_TYPE_DDR;
SYNC;
/* Set SDRAM mode */
im->ddr.sdram_mode =
((DDR_MODE_EXT_MODEREG | DDR_MODE_WEAK) <<
SDRAM_MODE_ESD_SHIFT) |
((DDR_MODE_MODEREG | DDR_MODE_BLEN_4) <<
SDRAM_MODE_SD_SHIFT) |
((DDR_MODE_CASLAT << SDRAM_MODE_SD_SHIFT) &
MODE_CASLAT);
SYNC;
/* Set fast SDRAM refresh rate */
im->ddr.sdram_interval =
(DDR_REFINT_166MHZ_7US << SDRAM_INTERVAL_REFINT_SHIFT) |
(DDR_BSTOPRE << SDRAM_INTERVAL_BSTOPRE_SHIFT);
SYNC;
}

121
board/tqm834x/u-boot.lds Normal file
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@ -0,0 +1,121 @@
/*
* Copyright 2004 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
OUTPUT_ARCH(powerpc)
SECTIONS
{
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
.interp : { *(.interp) }
.hash : { *(.hash) }
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rel.text : { *(.rel.text) }
.rela.text : { *(.rela.text) }
.rel.data : { *(.rel.data) }
.rela.data : { *(.rela.data) }
.rel.rodata : { *(.rel.rodata) }
.rela.rodata : { *(.rela.rodata) }
.rel.got : { *(.rel.got) }
.rela.got : { *(.rela.got) }
.rel.ctors : { *(.rel.ctors) }
.rela.ctors : { *(.rela.ctors) }
.rel.dtors : { *(.rel.dtors) }
.rela.dtors : { *(.rela.dtors) }
.rel.bss : { *(.rel.bss) }
.rela.bss : { *(.rela.bss) }
.rel.plt : { *(.rel.plt) }
.rela.plt : { *(.rela.plt) }
.init : { *(.init) }
.plt : { *(.plt) }
.text :
{
cpu/mpc83xx/start.o (.text)
*(.text)
*(.fixup)
*(.got1)
. = ALIGN(16);
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
.dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x0FFF) & 0xFFFFF000;
_erotext = .;
PROVIDE (erotext = .);
.reloc :
{
*(.got)
_GOT2_TABLE_ = .;
*(.got2)
_FIXUP_TABLE_ = .;
*(.fixup)
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
__fixup_entries = (. - _FIXUP_TABLE_) >> 2;
.data :
{
*(.data)
*(.data1)
*(.sdata)
*(.sdata2)
*(.dynamic)
CONSTRUCTORS
}
_edata = .;
PROVIDE (edata = .);
. = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
. = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
. = ALIGN(4096);
__init_begin = .;
.text.init : { *(.text.init) }
.data.init : { *(.data.init) }
. = ALIGN(4096);
__init_end = .;
__bss_start = .;
.bss :
{
*(.sbss) *(.scommon)
*(.dynbss)
*(.bss)
*(COMMON)
}
_end = . ;
PROVIDE (end = .);
}
ENTRY(_start)

4
common/cmd_bootm.c
View File

@ -84,7 +84,7 @@ static int image_info (unsigned long addr);
#if (CONFIG_COMMANDS & CFG_CMD_IMLS) #if (CONFIG_COMMANDS & CFG_CMD_IMLS)
#include <flash.h> #include <flash.h>
extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ extern flash_info_t flash_info[]; /* info for FLASH chips */
static int do_imls (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); static int do_imls (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
#endif #endif
@ -1082,7 +1082,7 @@ int do_imls (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
for (i=0, info=&flash_info[0]; i<CFG_MAX_FLASH_BANKS; ++i, ++info) { for (i=0, info=&flash_info[0]; i<CFG_MAX_FLASH_BANKS; ++i, ++info) {
if (info->flash_id == FLASH_UNKNOWN) if (info->flash_id == FLASH_UNKNOWN)
goto next_bank; goto next_bank;
for (j=0; j<CFG_MAX_FLASH_SECT; ++j) { for (j=0; j<info->sector_count; ++j) {
if (!(hdr=(image_header_t *)info->start[j]) || if (!(hdr=(image_header_t *)info->start[j]) ||
(ntohl(hdr->ih_magic) != IH_MAGIC)) (ntohl(hdr->ih_magic) != IH_MAGIC))

8
common/cmd_flash.c
View File

@ -404,7 +404,11 @@ int flash_sect_erase (ulong addr_first, ulong addr_last)
{ {
flash_info_t *info; flash_info_t *info;
ulong bank; ulong bank;
#ifdef CFG_MAX_FLASH_BANKS_DETECT
int s_first[CFG_MAX_FLASH_BANKS_DETECT], s_last[CFG_MAX_FLASH_BANKS_DETECT];
#else
int s_first[CFG_MAX_FLASH_BANKS], s_last[CFG_MAX_FLASH_BANKS]; int s_first[CFG_MAX_FLASH_BANKS], s_last[CFG_MAX_FLASH_BANKS];
#endif
int erased = 0; int erased = 0;
int planned; int planned;
int rcode = 0; int rcode = 0;
@ -617,7 +621,11 @@ int flash_sect_protect (int p, ulong addr_first, ulong addr_last)
{ {
flash_info_t *info; flash_info_t *info;
ulong bank; ulong bank;
#ifdef CFG_MAX_FLASH_BANKS_DETECT
int s_first[CFG_MAX_FLASH_BANKS_DETECT], s_last[CFG_MAX_FLASH_BANKS_DETECT];
#else
int s_first[CFG_MAX_FLASH_BANKS], s_last[CFG_MAX_FLASH_BANKS]; int s_first[CFG_MAX_FLASH_BANKS], s_last[CFG_MAX_FLASH_BANKS];
#endif
int protected, i; int protected, i;
int planned; int planned;
int rcode; int rcode;

4
common/cmd_jffs2.c
View File

@ -316,7 +316,7 @@ static int part_validate_nor(struct mtdids *id, struct part_info *part)
{ {
#if (CONFIG_COMMANDS & CFG_CMD_FLASH) #if (CONFIG_COMMANDS & CFG_CMD_FLASH)
/* info for FLASH chips */ /* info for FLASH chips */
extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; extern flash_info_t flash_info[];
flash_info_t *flash; flash_info_t *flash;
int offset_aligned; int offset_aligned;
u32 end_offset; u32 end_offset;
@ -711,7 +711,7 @@ static int device_validate(u8 type, u8 num, u32 *size)
if (type == MTD_DEV_TYPE_NOR) { if (type == MTD_DEV_TYPE_NOR) {
#if (CONFIG_COMMANDS & CFG_CMD_FLASH) #if (CONFIG_COMMANDS & CFG_CMD_FLASH)
if (num < CFG_MAX_FLASH_BANKS) { if (num < CFG_MAX_FLASH_BANKS) {
extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; extern flash_info_t flash_info[];
*size = flash_info[num].size; *size = flash_info[num].size;
return 0; return 0;
} }

2
common/cmd_mii.c
View File

@ -91,7 +91,7 @@ int do_mii (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
* Look for any and all PHYs. Valid addresses are 0..31. * Look for any and all PHYs. Valid addresses are 0..31.
*/ */
if (argc >= 3) { if (argc >= 3) {
start = addr; end = addr + 1; start = addrlo; end = addrhi + 1;
} else { } else {
start = 0; end = 32; start = 0; end = 32;
} }

2
common/flash.c
View File

@ -28,7 +28,7 @@
#if !defined(CFG_NO_FLASH) #if !defined(CFG_NO_FLASH)
extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ extern flash_info_t flash_info[]; /* info for FLASH chips */
/*----------------------------------------------------------------------- /*-----------------------------------------------------------------------
* Functions * Functions

2
cpu/mpc83xx/cpu.c
View File

@ -50,7 +50,7 @@ int checkcpu(void)
return -1; return -1;
} }
puts("CPU: MPC83xx, "); puts("CPU: MPC83xx, ");
switch(pvr) { switch(pvr) {
case PVR_8349_REV10: case PVR_8349_REV10:
break; break;

4
cpu/mpc83xx/i2c.c
View File

@ -41,7 +41,7 @@
#include <i2c.h> #include <i2c.h>
#include <asm/i2c.h> #include <asm/i2c.h>
#ifdef CONFIG_MPC8349ADS #if defined(CONFIG_MPC8349ADS) || defined(CONFIG_TQM834X)
i2c_t * mpc8349_i2c = (i2c_t*)(CFG_IMMRBAR + CFG_I2C_OFFSET); i2c_t * mpc8349_i2c = (i2c_t*)(CFG_IMMRBAR + CFG_I2C_OFFSET);
#endif #endif
@ -109,7 +109,9 @@ i2c_wait (int write)
return 0; return 0;
} while (get_timer (timeval) < I2C_TIMEOUT); } while (get_timer (timeval) < I2C_TIMEOUT);
debug("i2c_wait: timed out\n"); debug("i2c_wait: timed out\n");
return -1;
} }
static __inline__ int static __inline__ int

4
cpu/mpc83xx/pci.c
View File

@ -35,7 +35,7 @@
#include <common.h> #include <common.h>
#include <pci.h> #include <pci.h>
#ifdef CONFIG_MPC8349ADS #if defined(CONFIG_MPC8349ADS) || defined(CONFIG_TQM834X)
#include <asm/i2c.h> #include <asm/i2c.h>
#endif #endif
@ -114,7 +114,7 @@ pci_mpc83xx_init(volatile struct pci_controller *hose)
/* /*
* Assign PIB PMC slot to desired PCI bus * Assign PIB PMC slot to desired PCI bus
*/ */
#ifdef CONFIG_MPC8349ADS #if defined(CONFIG_MPC8349ADS) || defined(CONFIG_TQM834X)
mpc8349_i2c = (i2c_t*)(CFG_IMMRBAR + CFG_I2C2_OFFSET); mpc8349_i2c = (i2c_t*)(CFG_IMMRBAR + CFG_I2C2_OFFSET);
i2c_init(CFG_I2C_SPEED,CFG_I2C_SLAVE); i2c_init(CFG_I2C_SPEED,CFG_I2C_SLAVE);
#endif #endif

112
cpu/mpc83xx/speed.c
View File

@ -118,41 +118,50 @@ int get_clocks (void)
return -1; return -1;
#ifndef CFG_HRCW_HIGH #ifndef CFG_HRCW_HIGH
# error "CFG_HRCW_HIGH must be defined in include/configs/MCP83XXADS.h" # error "CFG_HRCW_HIGH must be defined in board config file"
#endif /* CFG_HCWD_HIGH */ #endif /* CFG_HCWD_HIGH */
#if (CFG_HRCW_HIGH & HRCWH_PCI_HOST) #if (CFG_HRCW_HIGH & HRCWH_PCI_HOST)
# ifndef CONFIG_83XX_CLKIN # ifndef CONFIG_83XX_CLKIN
# error "In PCI Host Mode, CONFIG_83XX_CLKIN must be defined in include/configs/MCP83XXADS.h" # error "In PCI Host Mode, CONFIG_83XX_CLKIN must be defined in board config file"
# endif /* CONFIG_83XX_CLKIN */ # endif /* CONFIG_83XX_CLKIN */
# ifdef CONFIG_83XX_PCICLK # ifdef CONFIG_83XX_PCICLK
# warning "In PCI Host Mode, CONFIG_83XX_PCICLK in include/configs/MCP83XXADS.h is igonred." # warning "In PCI Host Mode, CONFIG_83XX_PCICLK in board config file is igonred"
# endif /* CONFIG_83XX_PCICLK */ # endif /* CONFIG_83XX_PCICLK */
/* PCI Host Mode */
/* PCI Host Mode */
if (!(im->reset.rcwh & RCWH_PCIHOST)) { if (!(im->reset.rcwh & RCWH_PCIHOST)) {
/* though RCWH_PCIHOST is defined in CFG_HRCW_HIGH the im->reset.rcwhr PCI Host Mode is disabled */ /* though RCWH_PCIHOST is defined in CFG_HRCW_HIGH
/* FIXME: findout if there is a way to issue some warning */ * the im->reset.rcwhr PCI Host Mode is disabled
* FIXME: findout if there is a way to issue some warning */
return -2; return -2;
} }
if (im->clk.spmr & SPMR_CKID) { if (im->clk.spmr & SPMR_CKID) {
pci_sync_in = CONFIG_83XX_CLKIN / 2; /* PCI Clock is half CONFIG_83XX_CLKIN */ /* PCI Clock is half CONFIG_83XX_CLKIN */
pci_sync_in = CONFIG_83XX_CLKIN / 2;
} }
else { else {
pci_sync_in = CONFIG_83XX_CLKIN; pci_sync_in = CONFIG_83XX_CLKIN;
} }
#else
#else /* (CFG_HRCW_HIGH & HRCWH_PCI_HOST) */
# ifdef CONFIG_83XX_CLKIN # ifdef CONFIG_83XX_CLKIN
# warning "In PCI Agent Mode, CONFIG_83XX_CLKIN in include/configs/MCP83XXADS.h is igonred." # warning "In PCI Agent Mode, CONFIG_83XX_CLKIN in board config file is igonred"
# endif /* CONFIG_83XX_CLKIN */ # endif /* CONFIG_83XX_CLKIN */
# ifndef CONFIG_83XX_PCICLK # ifndef CONFIG_83XX_PCICLK
# error "In PCI Agent Mode, CONFIG_83XX_PCICLK must be defined in include/configs/MCP83XXADS.h" # error "In PCI Agent Mode, CONFIG_83XX_PCICLK must be defined in board config file"
# endif /* CONFIG_83XX_PCICLK */ # endif /* CONFIG_83XX_PCICLK */
/* PCI Agent Mode */
/* PCI Agent Mode */
if (im->reset.rcwh & RCWH_PCIHOST) { if (im->reset.rcwh & RCWH_PCIHOST) {
/* though RCWH_PCIHOST is not defined in CFG_HRCW_HIGH the im->reset.rcwhr PCI Host Mode is enabled */ /* though RCWH_PCIHOST is not defined in CFG_HRCW_HIGH
* the im->reset.rcwhr PCI Host Mode is enabled */
return -3; return -3;
} }
pci_sync_in = CONFIG_83XX_PCICLK; pci_sync_in = CONFIG_83XX_PCICLK;
#endif /* (CFG_HRCW_HIGH | RCWH_PCIHOST) */ #endif /* (CFG_HRCW_HIGH | RCWH_PCIHOST) */
/* we have up to date pci_sync_in */ /* we have up to date pci_sync_in */
@ -343,79 +352,14 @@ int print_clock_conf (void)
printf("Clock configuration:\n"); printf("Clock configuration:\n");
printf(" Coherent System Bus: %4d MHz\n",gd->csb_clk/1000000); printf(" Coherent System Bus: %4d MHz\n",gd->csb_clk/1000000);
printf(" Core: %4d MHz\n",gd->core_clk/1000000); printf(" Core: %4d MHz\n",gd->core_clk/1000000);
printf(" Local Bus Controller:%4d MHz\n",gd->lbiu_clk/1000000); debug(" Local Bus Controller:%4d MHz\n",gd->lbiu_clk/1000000);
printf(" Local Bus: %4d MHz\n",gd->lclk_clk/1000000); printf(" Local Bus: %4d MHz\n",gd->lclk_clk/1000000);
printf(" DDR: %4d MHz\n",gd->ddr_clk/1000000); debug(" DDR: %4d MHz\n",gd->ddr_clk/1000000);
printf(" I2C: %4d MHz\n",gd->i2c_clk/1000000); debug(" I2C: %4d MHz\n",gd->i2c_clk/1000000);
printf(" TSEC1: %4d MHz\n",gd->tsec1_clk/1000000); debug(" TSEC1: %4d MHz\n",gd->tsec1_clk/1000000);
printf(" TSEC2: %4d MHz\n",gd->tsec2_clk/1000000); debug(" TSEC2: %4d MHz\n",gd->tsec2_clk/1000000);
printf(" USB MPH: %4d MHz\n",gd->usbmph_clk/1000000); debug(" USB MPH: %4d MHz\n",gd->usbmph_clk/1000000);
printf(" USB DR: %4d MHz\n",gd->usbdr_clk/1000000); debug(" USB DR: %4d MHz\n",gd->usbdr_clk/1000000);
#if 0
DECLARE_GLOBAL_DATA_PTR;
volatile immap_t *immap = (immap_t *) CFG_IMMR;
ulong sccr, dfbrg;
ulong scmr, corecnf, busdf, cpmdf, plldf, pllmf;
corecnf_t *cp;
sccr = immap->im_clkrst.car_sccr;
dfbrg = (sccr & SCCR_DFBRG_MSK) >> SCCR_DFBRG_SHIFT;
scmr = immap->im_clkrst.car_scmr;
corecnf = (scmr & SCMR_CORECNF_MSK) >> SCMR_CORECNF_SHIFT;
busdf = (scmr & SCMR_BUSDF_MSK) >> SCMR_BUSDF_SHIFT;
cpmdf = (scmr & SCMR_CPMDF_MSK) >> SCMR_CPMDF_SHIFT;
plldf = (scmr & SCMR_PLLDF) ? 1 : 0;
pllmf = (scmr & SCMR_PLLMF_MSK) >> SCMR_PLLMF_SHIFT;
cp = &corecnf_tab[corecnf];
puts (CPU_ID_STR " Clock Configuration\n - Bus-to-Core Mult ");
switch (cp->b2c_mult) {
case _byp:
puts ("BYPASS");
break;
case _off:
puts ("OFF");
break;
case _unk:
puts ("UNKNOWN");
break;
default:
printf ("%d%sx",
cp->b2c_mult / 2,
(cp->b2c_mult % 2) ? ".5" : "");
break;
}
printf (", VCO Div %d, 60x Bus Freq %s, Core Freq %s\n",
cp->vco_div, cp->freq_60x, cp->freq_core);
printf (" - dfbrg %ld, corecnf 0x%02lx, busdf %ld, cpmdf %ld, "
"plldf %ld, pllmf %ld\n", dfbrg, corecnf, busdf, cpmdf, plldf,
pllmf);
printf (" - vco_out %10ld, scc_clk %10ld, brg_clk %10ld\n",
gd->vco_out, gd->scc_clk, gd->brg_clk);
printf (" - cpu_clk %10ld, cpm_clk %10ld, bus_clk %10ld\n",
gd->cpu_clk, gd->cpm_clk, gd->bus_clk);
if (sccr & SCCR_PCI_MODE) {
uint pci_div;
pci_div = ( (sccr & SCCR_PCI_MODCK) ? 2 : 1) *
( ( (sccr & SCCR_PCIDF_MSK) >> SCCR_PCIDF_SHIFT) + 1);
printf (" - pci_clk %10ld\n", (gd->cpm_clk * 2) / pci_div);
}
putc ('\n');
#endif
return 0; return 0;
} }

14
drivers/cfi_flash.c
View File

@ -166,9 +166,15 @@ typedef union {
#define NUM_ERASE_REGIONS 4 #define NUM_ERASE_REGIONS 4
/* use CFG_MAX_FLASH_BANKS_DETECT if defined */
#ifdef CFG_MAX_FLASH_BANKS_DETECT
static ulong bank_base[CFG_MAX_FLASH_BANKS_DETECT] = CFG_FLASH_BANKS_LIST;
flash_info_t flash_info[CFG_MAX_FLASH_BANKS_DETECT]; /* FLASH chips info */
#else
static ulong bank_base[CFG_MAX_FLASH_BANKS] = CFG_FLASH_BANKS_LIST; static ulong bank_base[CFG_MAX_FLASH_BANKS] = CFG_FLASH_BANKS_LIST;
flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* FLASH chips info */
#endif
flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
/*----------------------------------------------------------------------- /*-----------------------------------------------------------------------
* Functions * Functions
@ -184,7 +190,7 @@ static int flash_isequal (flash_info_t * info, flash_sect_t sect, uint offset, u
static int flash_isset (flash_info_t * info, flash_sect_t sect, uint offset, uchar cmd); static int flash_isset (flash_info_t * info, flash_sect_t sect, uint offset, uchar cmd);
static int flash_toggle (flash_info_t * info, flash_sect_t sect, uint offset, uchar cmd); static int flash_toggle (flash_info_t * info, flash_sect_t sect, uint offset, uchar cmd);
static int flash_detect_cfi (flash_info_t * info); static int flash_detect_cfi (flash_info_t * info);
static ulong flash_get_size (ulong base, int banknum); ulong flash_get_size (ulong base, int banknum);
static int flash_write_cfiword (flash_info_t * info, ulong dest, cfiword_t cword); static int flash_write_cfiword (flash_info_t * info, ulong dest, cfiword_t cword);
static int flash_full_status_check (flash_info_t * info, flash_sect_t sector, static int flash_full_status_check (flash_info_t * info, flash_sect_t sector,
ulong tout, char *prompt); ulong tout, char *prompt);
@ -371,7 +377,7 @@ unsigned long flash_init (void)
static flash_info_t *flash_get_info(ulong base) static flash_info_t *flash_get_info(ulong base)
{ {
int i; int i;
flash_info_t * info; flash_info_t * info = 0;
for (i = 0; i < CFG_MAX_FLASH_BANKS; i ++) { for (i = 0; i < CFG_MAX_FLASH_BANKS; i ++) {
info = & flash_info[i]; info = & flash_info[i];
@ -1007,7 +1013,7 @@ static int flash_detect_cfi (flash_info_t * info)
* The following code cannot be run from FLASH! * The following code cannot be run from FLASH!
* *
*/ */
static ulong flash_get_size (ulong base, int banknum) ulong flash_get_size (ulong base, int banknum)
{ {
flash_info_t *info = &flash_info[banknum]; flash_info_t *info = &flash_info[banknum];
int i, j; int i, j;

2
fs/cramfs/cramfs.c
View File

@ -44,7 +44,7 @@ struct cramfs_super super;
/* CPU address space offset calculation macro, struct part_info offset is /* CPU address space offset calculation macro, struct part_info offset is
* device address space offset, so we need to shift it by a device start address. */ * device address space offset, so we need to shift it by a device start address. */
extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; extern flash_info_t flash_info[];
#define PART_OFFSET(x) (x->offset + flash_info[x->dev->id->num].start[0]) #define PART_OFFSET(x) (x->offset + flash_info[x->dev->id->num].start[0])
static int cramfs_read_super (struct part_info *info) static int cramfs_read_super (struct part_info *info)

2
fs/jffs2/jffs2_1pass.c
View File

@ -263,7 +263,7 @@ static inline void *get_fl_mem_nor(u32 off)
u32 addr = off; u32 addr = off;
struct mtdids *id = current_part->dev->id; struct mtdids *id = current_part->dev->id;
extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; extern flash_info_t flash_info[];
flash_info_t *flash = &flash_info[id->num]; flash_info_t *flash = &flash_info[id->num];
addr += flash->start[0]; addr += flash->start[0];

2
include/asm-ppc/i2c.h
View File

@ -87,7 +87,7 @@ typedef struct i2c
#error CFG_I2C_OFFSET is not defined in /include/configs/${BOARD}.h #error CFG_I2C_OFFSET is not defined in /include/configs/${BOARD}.h
#endif #endif
#ifdef CONFIG_MPC8349ADS #if defined(CONFIG_MPC8349ADS) || defined(CONFIG_TQM834X)
/* /*
* MPC8349 have two i2c bus * MPC8349 have two i2c bus
*/ */

30
include/asm-ppc/immap_83xx.h
View File

@ -613,9 +613,9 @@ typedef struct gpio8349 {
typedef struct ddr_cs_bnds{ typedef struct ddr_cs_bnds{
u32 csbnds; u32 csbnds;
#define CSBNDS_SA 0x00FF0000 #define CSBNDS_SA 0x00FF0000
#define CSBNDS_SA_SHIFT 16 #define CSBNDS_SA_SHIFT 8
#define CSBNDS_EA 0x000000FF #define CSBNDS_EA 0x000000FF
#define CSBNDS_EA_SHIFT 0 #define CSBNDS_EA_SHIFT 24
u8 res0[4]; u8 res0[4];
} ddr_cs_bnds_t; } ddr_cs_bnds_t;
@ -652,6 +652,8 @@ typedef struct ddr8349{
#define TIMING_CFG1_ACTTOACT_SHIFT 4 #define TIMING_CFG1_ACTTOACT_SHIFT 4
#define TIMING_CFG1_WRTORD 0x00000007 #define TIMING_CFG1_WRTORD 0x00000007
#define TIMING_CFG1_WRTORD_SHIFT 0 #define TIMING_CFG1_WRTORD_SHIFT 0
#define TIMING_CFG1_CASLAT_20 0x00030000 /* CAS latency = 2.0 */
#define TIMING_CFG1_CASLAT_25 0x00040000 /* CAS latency = 2.5 */
u32 timing_cfg_2; /**< SDRAM Timing Configuration 2 */ u32 timing_cfg_2; /**< SDRAM Timing Configuration 2 */
#define TIMING_CFG2_CPO 0x0F000000 #define TIMING_CFG2_CPO 0x0F000000
@ -659,6 +661,7 @@ typedef struct ddr8349{
#define TIMING_CFG2_ACSM 0x00080000 #define TIMING_CFG2_ACSM 0x00080000
#define TIMING_CFG2_WR_DATA_DELAY 0x00001C00 #define TIMING_CFG2_WR_DATA_DELAY 0x00001C00
#define TIMING_CFG2_WR_DATA_DELAY_SHIFT 10 #define TIMING_CFG2_WR_DATA_DELAY_SHIFT 10
#define TIMING_CFG2_CPO_DEF 0x00000000 /* default (= CASLAT + 1) */
u32 sdram_cfg; /**< SDRAM Control Configuration */ u32 sdram_cfg; /**< SDRAM Control Configuration */
#define SDRAM_CFG_MEM_EN 0x80000000 #define SDRAM_CFG_MEM_EN 0x80000000
@ -672,6 +675,7 @@ typedef struct ddr8349{
#define SDRAM_CFG_8_BE 0x00040000 #define SDRAM_CFG_8_BE 0x00040000
#define SDRAM_CFG_NCAP 0x00020000 #define SDRAM_CFG_NCAP 0x00020000
#define SDRAM_CFG_2T_EN 0x00008000 #define SDRAM_CFG_2T_EN 0x00008000
#define SDRAM_CFG_SDRAM_TYPE_DDR 0x02000000
u8 res2[4]; u8 res2[4];
u32 sdram_mode; /**< SDRAM Mode Configuration */ u32 sdram_mode; /**< SDRAM Mode Configuration */
@ -679,6 +683,25 @@ typedef struct ddr8349{
#define SDRAM_MODE_ESD_SHIFT 16 #define SDRAM_MODE_ESD_SHIFT 16
#define SDRAM_MODE_SD 0x0000FFFF #define SDRAM_MODE_SD 0x0000FFFF
#define SDRAM_MODE_SD_SHIFT 0 #define SDRAM_MODE_SD_SHIFT 0
#define DDR_MODE_EXT_MODEREG 0x4000 /* select extended mode reg */
#define DDR_MODE_EXT_OPMODE 0x3FF8 /* operating mode, mask */
#define DDR_MODE_EXT_OP_NORMAL 0x0000 /* normal operation */
#define DDR_MODE_QFC 0x0004 /* QFC / compatibility, mask */
#define DDR_MODE_QFC_COMP 0x0000 /* compatible to older SDRAMs */
#define DDR_MODE_WEAK 0x0002 /* weak drivers */
#define DDR_MODE_DLL_DIS 0x0001 /* disable DLL */
#define DDR_MODE_CASLAT 0x0070 /* CAS latency, mask */
#define DDR_MODE_CASLAT_15 0x0010 /* CAS latency 1.5 */
#define DDR_MODE_CASLAT_20 0x0020 /* CAS latency 2 */
#define DDR_MODE_CASLAT_25 0x0060 /* CAS latency 2.5 */
#define DDR_MODE_CASLAT_30 0x0030 /* CAS latency 3 */
#define DDR_MODE_BTYPE_SEQ 0x0000 /* sequential burst */
#define DDR_MODE_BTYPE_ILVD 0x0008 /* interleaved burst */
#define DDR_MODE_BLEN_2 0x0001 /* burst length 2 */
#define DDR_MODE_BLEN_4 0x0002 /* burst length 4 */
#define DDR_REFINT_166MHZ_7US 1302 /* exact value for 7.8125 µs */
#define DDR_BSTOPRE 256 /* use 256 cycles as a starting point */
#define DDR_MODE_MODEREG 0x0000 /* select mode register */
u8 res3[8]; u8 res3[8];
u32 sdram_interval; /**< SDRAM Interval Configuration */ u32 sdram_interval; /**< SDRAM Interval Configuration */
@ -688,6 +711,9 @@ typedef struct ddr8349{
#define SDRAM_INTERVAL_BSTOPRE_SHIFT 0 #define SDRAM_INTERVAL_BSTOPRE_SHIFT 0
u8 res9[8]; u8 res9[8];
u32 sdram_clk_cntl; u32 sdram_clk_cntl;
#define DDR_SDRAM_CLK_CNTL_SS_EN 0x80000000
#define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 0x02000000
u8 res4[0xCCC]; u8 res4[0xCCC];
u32 data_err_inject_hi; /**< Memory Data Path Error Injection Mask High */ u32 data_err_inject_hi; /**< Memory Data Path Error Injection Mask High */
u32 data_err_inject_lo; /**< Memory Data Path Error Injection Mask Low */ u32 data_err_inject_lo; /**< Memory Data Path Error Injection Mask Low */

522
include/configs/TQM834x.h Normal file
View File

@ -0,0 +1,522 @@
/*
* (C) Copyright 2005
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* TQM8349 board configuration file
*/
#ifndef __CONFIG_H
#define __CONFIG_H
#define DEBUG
#undef DEBUG
/*
* High Level Configuration Options
*/
#define CONFIG_E300 1 /* E300 Family */
#define CONFIG_MPC83XX 1 /* MPC83XX family */
#define CONFIG_MPC834X 1 /* MPC834X specific */
#define CONFIG_TQM834X 1 /* TQM834X board specific */
/* IMMR Base Addres Register, use Freescale default: 0xff400000 */
#define CFG_IMMRBAR IMMRBAR_BASE_ADDR
/* System clock. Primary input clock when in PCI host mode */
#define CONFIG_83XX_CLKIN 66666000 /* 66,666 MHz */
/*
* Local Bus LCRR
* LCRR: DLL bypass, Clock divider is 8
*
* for CSB = 266 MHz it gives LCB clock frequency = 33 MHz
*
* External Local Bus rate is
* CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
*/
#define CFG_LCRR (LCRR_DBYP | LCRR_CLKDIV_8)
/* board pre init: do not call, nothing to do */
#undef CONFIG_BOARD_EARLY_INIT_F
/* detect the number of flash banks */
#define CONFIG_BOARD_EARLY_INIT_R
/*
* DDR Setup
*/
#define CFG_DDR_BASE 0x00000000 /* DDR is system memory*/
#define CFG_SDRAM_BASE CFG_DDR_BASE
#define CFG_DDR_SDRAM_BASE CFG_DDR_BASE
#define DDR_CASLAT_25 /* CASLAT set to 2.5 */
#undef CONFIG_DDR_ECC /* only for ECC DDR module */
#undef CONFIG_SPD_EEPROM /* do not use SPD EEPROM for DDR setup */
#undef CFG_DRAM_TEST /* memory test, takes time */
#define CFG_MEMTEST_START 0x00000000 /* memtest region */
#define CFG_MEMTEST_END 0x00100000
/*
* FLASH on the Local Bus
*/
#define CFG_FLASH_CFI /* use the Common Flash Interface */
#define CFG_FLASH_CFI_DRIVER /* use the CFI driver */
#undef CFG_FLASH_CHECKSUM
#define CFG_FLASH_BASE 0x80000000 /* start of FLASH */
/* buffered writes in the AMD chip set is not supported yet */
#undef CFG_FLASH_USE_BUFFER_WRITE
/*
* FLASH bank number detection
*/
/*
* When CFG_MAX_FLASH_BANKS_DETECT is defined, the actual number of Flash
* banks has to be determined at runtime and stored in a gloabl variable
* tqm834x_num_flash_banks. The value of CFG_MAX_FLASH_BANKS_DETECT is only
* used insted of CFG_MAX_FLASH_BANKS to allocate the array flash_info, and
* should be made sufficiently large to accomodate the number of banks that
* might acutally be detected. Since most (all?) Flash related functions use
* CFG_MAX_FLASH_BANKS as the number of actual banks on the board, it is
* defined as tqm834x_num_flash_banks.
*/
#define CFG_MAX_FLASH_BANKS_DETECT 2
#ifndef __ASSEMBLY__
extern int tqm834x_num_flash_banks;
#endif
#define CFG_MAX_FLASH_BANKS (tqm834x_num_flash_banks)
#define CFG_MAX_FLASH_SECT 512 /* max sectors per device */
/* 32 bit device at 0x80000000 via GPCM (0x8000_1801) */
#define CFG_BR0_PRELIM ((CFG_FLASH_BASE & BR_BA) | \
BR_MS_GPCM | BR_PS_32 | BR_V)
/* FLASH timing (0x0000_0c54) */
#define CFG_OR_TIMING_FLASH (OR_GPCM_CSNT | OR_GPCM_ACS_0b10 | \
OR_GPCM_SCY_5 | OR_GPCM_TRLX)
#define CFG_PRELIM_OR_AM 0xc0000000 /* OR addr mask: 1 GiB */
#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
#define CFG_LBLAWAR0_PRELIM 0x8000001D /* 1 GiB window size (2^(size + 1)) */
#define CFG_LBLAWBAR0_PRELIM CFG_FLASH_BASE /* Window base at flash base */
/* disable remaining mappings */
#define CFG_BR1_PRELIM 0x00000000
#define CFG_OR1_PRELIM 0x00000000
#define CFG_LBLAWBAR1_PRELIM 0x00000000
#define CFG_LBLAWAR1_PRELIM 0x00000000
#define CFG_BR2_PRELIM 0x00000000
#define CFG_OR2_PRELIM 0x00000000
#define CFG_LBLAWBAR2_PRELIM 0x00000000
#define CFG_LBLAWAR2_PRELIM 0x00000000
#define CFG_BR3_PRELIM 0x00000000
#define CFG_OR3_PRELIM 0x00000000
#define CFG_LBLAWBAR3_PRELIM 0x00000000
#define CFG_LBLAWAR3_PRELIM 0x00000000
#define CFG_BR4_PRELIM 0x00000000
#define CFG_OR4_PRELIM 0x00000000
#define CFG_LBLAWBAR4_PRELIM 0x00000000
#define CFG_LBLAWAR4_PRELIM 0x00000000
#define CFG_BR5_PRELIM 0x00000000
#define CFG_OR5_PRELIM 0x00000000
#define CFG_LBLAWBAR5_PRELIM 0x00000000
#define CFG_LBLAWAR5_PRELIM 0x00000000
#define CFG_BR6_PRELIM 0x00000000
#define CFG_OR6_PRELIM 0x00000000
#define CFG_LBLAWBAR6_PRELIM 0x00000000
#define CFG_LBLAWAR6_PRELIM 0x00000000
#define CFG_BR7_PRELIM 0x00000000
#define CFG_OR7_PRELIM 0x00000000
#define CFG_LBLAWBAR7_PRELIM 0x00000000
#define CFG_LBLAWAR7_PRELIM 0x00000000
/*
* Monitor config
*/
#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
#define CFG_RAMBOOT
#else
#undef CFG_RAMBOOT
#endif
#define CONFIG_L1_INIT_RAM
#define CFG_INIT_RAM_LOCK 1
#define CFG_INIT_RAM_ADDR 0x20000000 /* Initial RAM address */
#define CFG_INIT_RAM_END 0x1000 /* End of used area in RAM*/
#define CFG_GBL_DATA_SIZE 0x100 /* num bytes initial data */
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
/*
* Serial Port
*/
#define CONFIG_CONS_INDEX 1
#undef CONFIG_SERIAL_SOFTWARE_FIFO
#define CFG_NS16550
#define CFG_NS16550_SERIAL
#define CFG_NS16550_REG_SIZE 1
#define CFG_NS16550_CLK get_bus_freq(0)
#define CFG_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
#define CFG_NS16550_COM1 (CFG_IMMRBAR + 0x4500)
#define CFG_NS16550_COM2 (CFG_IMMRBAR + 0x4600)
/*
* I2C
*/
#define CONFIG_HARD_I2C /* I2C with hardware support */
#undef CONFIG_SOFT_I2C /* I2C bit-banged */
#define CFG_I2C_SPEED 400000 /* I2C speed: 400KHz */
#define CFG_I2C_SLAVE 0x7F /* slave address */
#define CFG_I2C_OFFSET 0x3000
/* I2C EEPROM, configuration for onboard EEPROMs 24C256 and 24C32 */
#define CFG_I2C_EEPROM_ADDR 0x50 /* 1010000x */
#define CFG_I2C_EEPROM_ADDR_LEN 2 /* 16 bit */
#define CFG_EEPROM_PAGE_WRITE_BITS 5 /* 32 bytes per write */
#define CFG_EEPROM_PAGE_WRITE_ENABLE
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 12 /* 10ms +/- 20% */
#define CFG_I2C_MULTI_EEPROMS 1 /* more than one eeprom */
/* I2C RTC */
#define CONFIG_RTC_DS1337 /* use ds1337 rtc via i2c */
#define CFG_I2C_RTC_ADDR 0x68 /* at address 0x68 */
/* I2C SYSMON (LM75) */
#define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */
#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */
#define CFG_DTT_MAX_TEMP 70
#define CFG_DTT_LOW_TEMP -30
#define CFG_DTT_HYSTERESIS 3
/*
* TSEC
*/
#define CONFIG_TSEC_ENET /* tsec ethernet support */
#define CONFIG_MII
#define CFG_TSEC1_OFFSET 0x24000
#define CFG_TSEC1 (CFG_IMMRBAR + CFG_TSEC1_OFFSET)
#define CFG_TSEC2_OFFSET 0x25000
#define CFG_TSEC2 (CFG_IMMRBAR + CFG_TSEC2_OFFSET)
#if defined(CONFIG_TSEC_ENET)
#ifndef CONFIG_NET_MULTI
#define CONFIG_NET_MULTI 1
#endif
#define CONFIG_MPC83XX_TSEC1 1
#define CONFIG_MPC83XX_TSEC1_NAME "TSEC0"
#define CONFIG_MPC83XX_TSEC2 1
#define CONFIG_MPC83XX_TSEC2_NAME "TSEC1"
#define TSEC1_PHY_ADDR 0
#define TSEC2_PHY_ADDR 1
#define TSEC1_PHYIDX 0
#define TSEC2_PHYIDX 0
/* Options are: TSEC[0-1] */
#define CONFIG_ETHPRIME "TSEC0"
#endif /* CONFIG_TSEC_ENET */
/*
* General PCI
* Addresses are mapped 1-1.
*/
/* FIXME: Real PCI support will come in a follow-up update. */
#undef CONFIG_PCI
#define CFG_PCI1_MEM_BASE 0x80000000
#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE
#define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */
#define CFG_PCI1_IO_BASE 0x00000000
#define CFG_PCI1_IO_PHYS 0xe2000000
#define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */
#define CFG_PCI2_MEM_BASE 0xA0000000
#define CFG_PCI2_MEM_PHYS CFG_PCI2_MEM_BASE
#define CFG_PCI2_MEM_SIZE 0x20000000 /* 512M */
#define CFG_PCI2_IO_BASE 0x00000000
#define CFG_PCI2_IO_PHYS 0xe3000000
#define CFG_PCI2_IO_SIZE 0x1000000 /* 16M */
#if defined(CONFIG_PCI)
#define PCI_ALL_PCI1
#if defined(PCI_64BIT)
#undef PCI_ALL_PCI1
#undef PCI_TWO_PCI1
#undef PCI_ONE_PCI1
#endif
#define CONFIG_NET_MULTI
#define CONFIG_PCI_PNP /* do pci plug-and-play */
#undef CONFIG_EEPRO100
#undef CONFIG_TULIP
#if !defined(CONFIG_PCI_PNP)
#define PCI_ENET0_IOADDR 0xFIXME
#define PCI_ENET0_MEMADDR 0xFIXME
#define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */
#endif
#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
#define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
#endif /* CONFIG_PCI */
/*
* Environment
*/
#define CONFIG_ENV_OVERWRITE
#ifndef CFG_RAMBOOT
#define CFG_ENV_IS_IN_FLASH 1
#define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000)
#define CFG_ENV_SECT_SIZE 0x20000 /* 256K(one sector) for env */
#define CFG_ENV_SIZE 0x2000
#else
#define CFG_NO_FLASH 1 /* Flash is not usable now */
#define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
#define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000)
#define CFG_ENV_SIZE 0x2000
#endif
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
/* Common commands */
#define CFG_CMD_TQM8349_COMMON CFG_CMD_DATE | CFG_CMD_I2C | CFG_CMD_DTT\
| CFG_CMD_PING | CFG_CMD_EEPROM \
| CFG_CMD_MII | CFG_CMD_JFFS2
#if defined(CFG_RAMBOOT)
#if defined(CONFIG_PCI)
#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_PCI \
| CFG_CMD_TQM8349_COMMON) \
& \
~(CFG_CMD_ENV | CFG_CMD_LOADS))
#else
#define CONFIG_COMMANDS ((CONFIG_CMD_DFL \
| CFG_CMD_TQM8349_COMMON) \
& \
~(CFG_CMD_ENV | CFG_CMD_LOADS))
#endif
#else /* CFG_RAMBOOT */
#if defined(CONFIG_PCI)
#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_PCI \
| CFG_CMD_TQM8349_COMMON)
#else
#define CONFIG_COMMANDS (CONFIG_CMD_DFL \
| CFG_CMD_TQM8349_COMMON)
#endif
#endif /* CFG_RAMBOOT */
#include <cmd_confdefs.h>
/*
* Miscellaneous configurable options
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_LOAD_ADDR 0x2000000 /* default load address */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
#endif
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define CFG_MAXARGS 16 /* max number of command args */
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */
#undef CONFIG_WATCHDOG /* watchdog disabled */
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
/*
* Cache Configuration
*/
#define CFG_DCACHE_SIZE 32768
#define CFG_CACHELINE_SIZE 32
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/
#endif
#define CFG_HRCW_LOW (\
HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
HRCWL_DDR_TO_SCB_CLK_1X1 |\
HRCWL_CSB_TO_CLKIN_4X1 |\
HRCWL_VCO_1X2 |\
HRCWL_CORE_TO_CSB_2X1)
#if defined(PCI_64BIT)
#define CFG_HRCW_HIGH (\
HRCWH_PCI_HOST |\
HRCWH_64_BIT_PCI |\
HRCWH_PCI1_ARBITER_ENABLE |\
HRCWH_PCI2_ARBITER_DISABLE |\
HRCWH_CORE_ENABLE |\
HRCWH_FROM_0X00000100 |\
HRCWH_BOOTSEQ_DISABLE |\
HRCWH_SW_WATCHDOG_DISABLE |\
HRCWH_ROM_LOC_LOCAL_16BIT |\
HRCWH_TSEC1M_IN_GMII |\
HRCWH_TSEC2M_IN_GMII )
#else
#define CFG_HRCW_HIGH (\
HRCWH_PCI_HOST |\
HRCWH_32_BIT_PCI |\
HRCWH_PCI1_ARBITER_ENABLE |\
HRCWH_PCI2_ARBITER_ENABLE |\
HRCWH_CORE_ENABLE |\
HRCWH_FROM_0X00000100 |\
HRCWH_BOOTSEQ_DISABLE |\
HRCWH_SW_WATCHDOG_DISABLE |\
HRCWH_ROM_LOC_LOCAL_16BIT |\
HRCWH_TSEC1M_IN_GMII |\
HRCWH_TSEC2M_IN_GMII )
#endif
/* i-cache and d-cache disabled */
#define CFG_HID0_INIT 0x000000000
#define CFG_HID0_FINAL CFG_HID0_INIT
#define CFG_HID2 0x000000000
/*
* Internal Definitions
*
* Boot Flags
*/
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
/*
* Environment Configuration
*/
#if defined(CONFIG_TSEC_ENET)
#define CONFIG_ETHADDR D2:DA:5E:44:BC:29
#define CONFIG_HAS_ETH1
#define CONFIG_ETH1ADDR 1E:F3:40:21:92:53
#endif
#define CONFIG_IPADDR 192.168.205.1
#define CONFIG_HOSTNAME tqm8349
#define CONFIG_ROOTPATH /opt/eldk/ppc_6xx
#define CONFIG_BOOTFILE /tftpboot/tqm83xx/uImage
#define CONFIG_SERVERIP 192.168.1.1
#define CONFIG_GATEWAYIP 192.168.1.1
#define CONFIG_NETMASK 255.255.255.0
#define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */
#define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */
#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
#define CONFIG_BAUDRATE 115200
#define CONFIG_PREBOOT "echo;" \
"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
"echo"
#undef CONFIG_BOOTARGS
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"hostname=tqm83xx\0" \
"nfsargs=setenv bootargs root=/dev/nfs rw " \
"nfsroot=$(serverip):$(rootpath)\0" \
"ramargs=setenv bootargs root=/dev/ram rw\0" \
"addip=setenv bootargs $(bootargs) " \
"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
":$(hostname):$(netdev):off panic=1\0" \
"addtty=setenv bootargs $(bootargs) console=ttyS0,$(baudrate)\0"\
"flash_nfs=run nfsargs addip addtty;" \
"bootm $(kernel_addr)\0" \
"flash_self=run ramargs addip addtty;" \
"bootm $(kernel_addr) $(ramdisk_addr)\0" \
"net_nfs=tftp 200000 $(bootfile);run nfsargs addip addtty;" \
"bootm\0" \
"rootpath=/opt/eldk/ppc_6xx\0" \
"bootfile=/tftpboot/tqm83xx/uImage\0" \
"kernel_addr=80060000\0" \
"ramdisk_addr=80160000\0" \
"load=tftp 100000 /tftpboot/tqm83xx/u-boot.bin\0" \
"update=protect off 80000000 8003ffff; " \
"era 80000000 8003ffff; cp.b 100000 80000000 40000\0" \
"upd=run load;run update\0" \
""
#define CONFIG_BOOTCOMMAND "run flash_self"
/*
* JFFS2 partitions
*/
/* mtdparts command line support */
#define CONFIG_JFFS2_CMDLINE
#define MTDIDS_DEFAULT "nor0=TQM834x-0"
/* default mtd partition table */
#define MTDPARTS_DEFAULT "mtdparts=TQM834x-0:256k(u-boot),128k(env),"\
"1m(kernel),2m(initrd),"\
"-(user);"\
#endif /* __CONFIG_H */

91
include/mpc83xx.h
View File

@ -98,19 +98,27 @@
#define BR6 0x5030 #define BR6 0x5030
#define BR7 0x5038 #define BR7 0x5038
#define BR_BA 0xFFFF8000 #define BR_BA 0xFFFF8000
#define BR_BA_SHIFT 15 #define BR_BA_SHIFT 15
#define BR_PS 0x00001800 #define BR_PS 0x00001800
#define BR_PS_SHIFT 11 #define BR_PS_SHIFT 11
#define BR_DECC 0x00000600 #define BR_PS_8 0x00000800 /* Port Size 8 bit */
#define BR_DECC_SHIFT 9 #define BR_PS_16 0x00001000 /* Port Size 16 bit */
#define BR_WP 0x00000100 #define BR_PS_32 0x00001800 /* Port Size 32 bit */
#define BR_WP_SHIFT 8 #define BR_DECC 0x00000600
#define BR_MSEL 0x000000E0 #define BR_DECC_SHIFT 9
#define BR_MSEL_SHIFT 5 #define BR_WP 0x00000100
#define BR_V 0x00000001 #define BR_WP_SHIFT 8
#define BR_V_SHIFT 0 #define BR_MSEL 0x000000E0
#define BR_RES ~(BR_BA|BR_PS|BR_DECC|BR_WP|BR_MSEL|BR_V) #define BR_MSEL_SHIFT 5
#define BR_MS_GPCM 0x00000000 /* GPCM */
#define BR_MS_SDRAM 0x00000060 /* SDRAM */
#define BR_MS_UPMA 0x00000080 /* UPMA */
#define BR_MS_UPMB 0x000000A0 /* UPMB */
#define BR_MS_UPMC 0x000000C0 /* UPMC */
#define BR_V 0x00000001
#define BR_V_SHIFT 0
#define BR_RES ~(BR_BA|BR_PS|BR_DECC|BR_WP|BR_MSEL|BR_V)
#define OR0 0x5004 #define OR0 0x5004
#define OR1 0x500C #define OR1 0x500C
@ -121,26 +129,43 @@
#define OR6 0x5034 #define OR6 0x5034
#define OR7 0x503C #define OR7 0x503C
#define OR_GPCM_AM 0xFFFF8000 #define OR_GPCM_AM 0xFFFF8000
#define OR_GPCM_AM_SHIFT 15 #define OR_GPCM_AM_SHIFT 15
#define OR_GPCM_BCTLD 0x00001000 #define OR_GPCM_BCTLD 0x00001000
#define OR_GPCM_BCTLD_SHIFT 12 #define OR_GPCM_BCTLD_SHIFT 12
#define OR_GPCM_CSNT 0x00000800 #define OR_GPCM_CSNT 0x00000800
#define OR_GPCM_CSNT_SHIFT 11 #define OR_GPCM_CSNT_SHIFT 11
#define OR_GPCM_ACS 0x00000600 #define OR_GPCM_ACS 0x00000600
#define OR_GPCM_ACS_SHIFT 9 #define OR_GPCM_ACS_SHIFT 9
#define OR_GPCM_XACS 0x00000100 #define OR_GPCM_ACS_0b10 0x00000400
#define OR_GPCM_XACS_SHIFT 8 #define OR_GPCM_ACS_0b11 0x00000600
#define OR_GPCM_SCY 0x000000F0 #define OR_GPCM_XACS 0x00000100
#define OR_GPCM_SCY_SHIFT 4 #define OR_GPCM_XACS_SHIFT 8
#define OR_GPCM_SETA 0x00000008 #define OR_GPCM_SCY 0x000000F0
#define OR_GPCM_SETA_SHIFT 3 #define OR_GPCM_SCY_SHIFT 4
#define OR_GPCM_TRLX 0x00000004 #define OR_GPCM_SCY_1 0x00000010
#define OR_GPCM_TRLX_SHIFT 2 #define OR_GPCM_SCY_2 0x00000020
#define OR_GPCM_EHTR 0x00000002 #define OR_GPCM_SCY_3 0x00000030
#define OR_GPCM_EHTR_SHIFT 1 #define OR_GPCM_SCY_4 0x00000040
#define OR_GPCM_EAD 0x00000001 #define OR_GPCM_SCY_5 0x00000050
#define OR_GPCM_EAD_SHIFT 0 #define OR_GPCM_SCY_6 0x00000060
#define OR_GPCM_SCY_7 0x00000070
#define OR_GPCM_SCY_8 0x00000080
#define OR_GPCM_SCY_9 0x00000090
#define OR_GPCM_SCY_10 0x000000a0
#define OR_GPCM_SCY_11 0x000000b0
#define OR_GPCM_SCY_12 0x000000c0
#define OR_GPCM_SCY_13 0x000000d0
#define OR_GPCM_SCY_14 0x000000e0
#define OR_GPCM_SCY_15 0x000000f0
#define OR_GPCM_SETA 0x00000008
#define OR_GPCM_SETA_SHIFT 3
#define OR_GPCM_TRLX 0x00000004
#define OR_GPCM_TRLX_SHIFT 2
#define OR_GPCM_EHTR 0x00000002
#define OR_GPCM_EHTR_SHIFT 1
#define OR_GPCM_EAD 0x00000001
#define OR_GPCM_EAD_SHIFT 0
#define OR_UPM_AM 0xFFFF8000 #define OR_UPM_AM 0xFFFF8000
#define OR_UPM_AM_SHIFT 15 #define OR_UPM_AM_SHIFT 15

2
net/tftp.c
View File

@ -58,7 +58,7 @@ static char default_filename[DEFAULT_NAME_LEN];
static char *tftp_filename; static char *tftp_filename;
#ifdef CFG_DIRECT_FLASH_TFTP #ifdef CFG_DIRECT_FLASH_TFTP
extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; extern flash_info_t flash_info[];
#endif #endif
static __inline__ void static __inline__ void

2
tools/updater/flash.c
View File

@ -24,7 +24,7 @@
#include <common.h> #include <common.h>
#include <flash.h> #include <flash.h>
extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ extern flash_info_t flash_info[]; /* info for FLASH chips */
/*----------------------------------------------------------------------- /*-----------------------------------------------------------------------
* Functions * Functions

2
tools/updater/flash_hw.c
View File

@ -39,7 +39,7 @@
#endif #endif
/*---------------------------------------------------------------------*/ /*---------------------------------------------------------------------*/
flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; flash_info_t flash_info[];
static ulong flash_get_size (ulong addr, flash_info_t *info); static ulong flash_get_size (ulong addr, flash_info_t *info);
static int flash_get_offsets (ulong base, flash_info_t *info); static int flash_get_offsets (ulong base, flash_info_t *info);