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Merge branch 'u-boot-ti/master' into 'u-boot-arm/master'

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This commit is contained in:
Albert ARIBAUD
2013-09-04 14:06:56 +02:00
parent 4eef93da26 901ce27c6f
commit e62d5fb0da
56 changed files with 4387 additions and 114 deletions
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6
arch/arm/cpu/armv7/omap3/clock.c
View File

@@ -183,8 +183,7 @@ static void dpll3_init_34xx(u32 sil_index, u32 clk_index)
* if running from flash, jump to small relocated code
* area in SRAM.
*/
f_lock_pll = (void *) ((u32) &_end_vect - (u32) &_start +
SRAM_VECT_CODE);
f_lock_pll = (void *) (SRAM_CLK_CODE);
p0 = readl(&prcm_base->clken_pll);
sr32(&p0, 0, 3, PLL_FAST_RELOCK_BYPASS);
@@ -401,8 +400,7 @@ static void dpll3_init_36xx(u32 sil_index, u32 clk_index)
* if running from flash, jump to small relocated code
* area in SRAM.
*/
f_lock_pll = (void *) ((u32) &_end_vect - (u32) &_start +
SRAM_VECT_CODE);
f_lock_pll = (void *) (SRAM_CLK_CODE);
p0 = readl(&prcm_base->clken_pll);
sr32(&p0, 0, 3, PLL_FAST_RELOCK_BYPASS);

8
arch/arm/cpu/armv7/omap3/lowlevel_init.S
View File

@@ -69,15 +69,13 @@ ENDPROC(do_omap3_emu_romcode_call)
*************************************************************************/
ENTRY(cpy_clk_code)
/* Copy DPLL code into SRAM */
adr r0, go_to_speed /* get addr of clock setting code */
mov r2, #384 /* r2 size to copy (div by 32 bytes) */
mov r1, r1 /* r1 <- dest address (passed in) */
add r2, r2, r0 /* r2 <- source end address */
adr r0, go_to_speed /* copy from start of go_to_speed... */
adr r2, lowlevel_init /* ... up to start of low_level_init */
next2:
ldmia r0!, {r3 - r10} /* copy from source address [r0] */
stmia r1!, {r3 - r10} /* copy to target address [r1] */
cmp r0, r2 /* until source end address [r2] */
bne next2
blo next2
mov pc, lr /* back to caller */
ENDPROC(cpy_clk_code)

36
arch/arm/cpu/armv7/omap4/hw_data.c
View File

@@ -50,6 +50,7 @@ static const struct dpll_params mpu_dpll_params_1400mhz[NUM_SYS_CLKS] = {
/*
* dpll locked at 1600 MHz - MPU clk at 800 MHz(OPP Turbo 4430)
* OMAP4430 OPP_TURBO frequency
* OMAP4470 OPP_NOM frequency
*/
static const struct dpll_params mpu_dpll_params_1600mhz[NUM_SYS_CLKS] = {
{200, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
@@ -76,6 +77,7 @@ static const struct dpll_params mpu_dpll_params_1200mhz[NUM_SYS_CLKS] = {
};
/* OMAP4460 OPP_NOM frequency */
/* OMAP4470 OPP_NOM (Low Power) frequency */
static const struct dpll_params core_dpll_params_1600mhz[NUM_SYS_CLKS] = {
{200, 2, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 12 MHz */
{800, 12, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 13 MHz */
@@ -198,6 +200,20 @@ struct dplls omap4460_dplls = {
.ddr = NULL
};
struct dplls omap4470_dplls = {
.mpu = mpu_dpll_params_1600mhz,
.core = core_dpll_params_1600mhz,
.per = per_dpll_params_1536mhz,
.iva = iva_dpll_params_1862mhz,
#ifdef CONFIG_SYS_OMAP_ABE_SYSCK
.abe = abe_dpll_params_sysclk_196608khz,
#else
.abe = &abe_dpll_params_32k_196608khz,
#endif
.usb = usb_dpll_params_1920mhz,
.ddr = NULL
};
struct pmic_data twl6030_4430es1 = {
.base_offset = PHOENIX_SMPS_BASE_VOLT_STD_MODE_UV,
.step = 12660, /* 12.66 mV represented in uV */
@@ -208,6 +224,7 @@ struct pmic_data twl6030_4430es1 = {
.pmic_write = omap_vc_bypass_send_value,
};
/* twl6030 struct is used for TWL6030 and TWL6032 PMIC */
struct pmic_data twl6030 = {
.base_offset = PHOENIX_SMPS_BASE_VOLT_STD_MODE_WITH_OFFSET_UV,
.step = 12660, /* 12.66 mV represented in uV */
@@ -271,6 +288,20 @@ struct vcores_data omap4460_volts = {
.mm.pmic = &twl6030,
};
struct vcores_data omap4470_volts = {
.mpu.value = 1200,
.mpu.addr = SMPS_REG_ADDR_SMPS1,
.mpu.pmic = &twl6030,
.core.value = 1126,
.core.addr = SMPS_REG_ADDR_SMPS1,
.core.pmic = &twl6030,
.mm.value = 1137,
.mm.addr = SMPS_REG_ADDR_SMPS1,
.mm.pmic = &twl6030,
};
/*
* Enable essential clock domains, modules and
* do some additional special settings needed
@@ -476,6 +507,11 @@ void hw_data_init(void)
*omap_vcores = &omap4460_volts;
break;
case OMAP4470_ES1_0:
*dplls_data = &omap4470_dplls;
*omap_vcores = &omap4470_volts;
break;
default:
printf("\n INVALID OMAP REVISION ");
}

3
arch/arm/cpu/armv7/omap4/hwinit.c
View File

@@ -138,6 +138,9 @@ void init_omap_revision(void)
break;
case MIDR_CORTEX_A9_R2P10:
switch (readl(CONTROL_ID_CODE)) {
case OMAP4470_CONTROL_ID_CODE_ES1_0:
*omap_si_rev = OMAP4470_ES1_0;
break;
case OMAP4460_CONTROL_ID_CODE_ES1_1:
*omap_si_rev = OMAP4460_ES1_1;
break;

41
arch/arm/cpu/armv7/omap4/sdram_elpida.c
View File

@@ -60,6 +60,20 @@ static const struct emif_regs emif_regs_elpida_380_mhz_1cs = {
.emif_ddr_phy_ctlr_1 = 0x049ff418
};
const struct emif_regs emif_regs_elpida_400_mhz_1cs = {
.sdram_config_init = 0x80800eb2,
.sdram_config = 0x80801ab2,
.ref_ctrl = 0x00000618,
.sdram_tim1 = 0x10eb0662,
.sdram_tim2 = 0x20370dd2,
.sdram_tim3 = 0x00b1c33f,
.read_idle_ctrl = 0x000501ff,
.zq_config = 0x500b3215,
.temp_alert_config = 0x58016893,
.emif_ddr_phy_ctlr_1_init = 0x049ffff5,
.emif_ddr_phy_ctlr_1 = 0x049ff418
};
const struct emif_regs emif_regs_elpida_400_mhz_2cs = {
.sdram_config_init = 0x80000eb9,
.sdram_config = 0x80001ab9,
@@ -107,8 +121,10 @@ static void emif_get_reg_dump_sdp(u32 emif_nr, const struct emif_regs **regs)
*regs = &emif_regs_elpida_380_mhz_1cs;
else if (omap4_rev == OMAP4430_ES2_0)
*regs = &emif_regs_elpida_200_mhz_2cs;
else
else if (omap4_rev < OMAP4470_ES1_0)
*regs = &emif_regs_elpida_400_mhz_2cs;
else
*regs = &emif_regs_elpida_400_mhz_1cs;
}
void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
__attribute__((weak, alias("emif_get_reg_dump_sdp")));
@@ -138,20 +154,31 @@ static const struct lpddr2_device_details elpida_2G_S4_details = {
.manufacturer = LPDDR2_MANUFACTURER_ELPIDA
};
static const struct lpddr2_device_details elpida_4G_S4_details = {
.type = LPDDR2_TYPE_S4,
.density = LPDDR2_DENSITY_4Gb,
.io_width = LPDDR2_IO_WIDTH_32,
.manufacturer = LPDDR2_MANUFACTURER_ELPIDA
};
struct lpddr2_device_details *emif_get_device_details_sdp(u32 emif_nr, u8 cs,
struct lpddr2_device_details *lpddr2_dev_details)
{
u32 omap_rev = omap_revision();
/* EMIF1 & EMIF2 have identical configuration */
if ((omap_rev == OMAP4430_ES1_0) && (cs == CS1)) {
/* Nothing connected on CS1 for ES1.0 */
if (((omap_rev == OMAP4430_ES1_0) || (omap_rev == OMAP4470_ES1_0))
&& (cs == CS1)) {
/* Nothing connected on CS1 for 4430/4470 ES1.0 */
return NULL;
} else {
/* In all other cases Elpida 2G device */
} else if (omap_rev < OMAP4470_ES1_0) {
/* In all other 4430/4460 cases Elpida 2G device */
*lpddr2_dev_details = elpida_2G_S4_details;
return lpddr2_dev_details;
} else {
/* 4470: 4G device */
*lpddr2_dev_details = elpida_4G_S4_details;
}
return lpddr2_dev_details;
}
struct lpddr2_device_details *emif_get_device_details(u32 emif_nr, u8 cs,
@@ -265,7 +292,7 @@ void emif_get_device_timings_sdp(u32 emif_nr,
/* Identical devices on EMIF1 & EMIF2 */
*cs0_device_timings = &elpida_2G_S4_timings;
if (omap_rev == OMAP4430_ES1_0)
if ((omap_rev == OMAP4430_ES1_0) || (omap_rev == OMAP4470_ES1_0))
*cs1_device_timings = NULL;
else
*cs1_device_timings = &elpida_2G_S4_timings;

74
arch/arm/include/asm/arch-am33xx/cpu.h
View File

@@ -46,6 +46,26 @@
#define PRM_RSTCTRL_RESET 0x01
#define PRM_RSTST_WARM_RESET_MASK 0x232
/*
* Watchdog:
* Using the prescaler, the OMAP watchdog could go for many
* months before firing. These limits work without scaling,
* with the 60 second default assumed by most tools and docs.
*/
#define TIMER_MARGIN_MAX (24 * 60 * 60) /* 1 day */
#define TIMER_MARGIN_DEFAULT 60 /* 60 secs */
#define TIMER_MARGIN_MIN 1
#define PTV 0 /* prescale */
#define GET_WLDR_VAL(secs) (0xffffffff - ((secs) * (32768/(1<<PTV))) + 1)
#define WDT_WWPS_PEND_WCLR BIT(0)
#define WDT_WWPS_PEND_WLDR BIT(2)
#define WDT_WWPS_PEND_WTGR BIT(3)
#define WDT_WWPS_PEND_WSPR BIT(4)
#define WDT_WCLR_PRE BIT(5)
#define WDT_WCLR_PTV_OFF 2
#ifndef __KERNEL_STRICT_NAMES
#ifndef __ASSEMBLY__
struct gpmc_cs {
@@ -193,7 +213,8 @@ struct cm_perpll {
unsigned int dcan1clkctrl; /* offset 0xC4 */
unsigned int resv6[2];
unsigned int emiffwclkctrl; /* offset 0xD0 */
unsigned int resv7[2];
unsigned int epwmss0clkctrl; /* offset 0xD4 */
unsigned int epwmss2clkctrl; /* offset 0xD8 */
unsigned int l3instrclkctrl; /* offset 0xDC */
unsigned int l3clkctrl; /* Offset 0xE0 */
unsigned int resv8[4];
@@ -204,6 +225,7 @@ struct cm_perpll {
unsigned int l4hsclkctrl; /* offset 0x120 */
unsigned int resv10[8];
unsigned int cpswclkstctrl; /* offset 0x144 */
unsigned int lcdcclkstctrl; /* offset 0x148 */
};
#else
/* Encapsulating core pll registers */
@@ -366,6 +388,8 @@ struct cm_perpll {
struct cm_dpll {
unsigned int resv1[2];
unsigned int clktimer2clk; /* offset 0x08 */
unsigned int resv2[10];
unsigned int clklcdcpixelclk; /* offset 0x34 */
};
/* Control Module RTC registers */
@@ -486,6 +510,54 @@ struct ctrl_dev {
unsigned int resv4[4];
unsigned int miisel; /* offset 0x50 */
};
/* gmii_sel register defines */
#define GMII1_SEL_MII 0x0
#define GMII1_SEL_RMII 0x1
#define GMII1_SEL_RGMII 0x2
#define GMII2_SEL_MII 0x0
#define GMII2_SEL_RMII 0x4
#define GMII2_SEL_RGMII 0x8
#define RGMII1_IDMODE BIT(4)
#define RGMII2_IDMODE BIT(5)
#define RMII1_IO_CLK_EN BIT(6)
#define RMII2_IO_CLK_EN BIT(7)
#define MII_MODE_ENABLE (GMII1_SEL_MII | GMII2_SEL_MII)
#define RMII_MODE_ENABLE (GMII1_SEL_RMII | GMII2_SEL_RMII)
#define RGMII_MODE_ENABLE (GMII1_SEL_RGMII | GMII2_SEL_RGMII)
#define RGMII_INT_DELAY (RGMII1_IDMODE | RGMII2_IDMODE)
#define RMII_CHIPCKL_ENABLE (RMII1_IO_CLK_EN | RMII2_IO_CLK_EN)
/* PWMSS */
struct pwmss_regs {
unsigned int idver;
unsigned int sysconfig;
unsigned int clkconfig;
unsigned int clkstatus;
};
#define ECAP_CLK_EN BIT(0)
#define ECAP_CLK_STOP_REQ BIT(1)
struct pwmss_ecap_regs {
unsigned int tsctr;
unsigned int ctrphs;
unsigned int cap1;
unsigned int cap2;
unsigned int cap3;
unsigned int cap4;
unsigned int resv1[4];
unsigned short ecctl1;
unsigned short ecctl2;
};
/* Capture Control register 2 */
#define ECTRL2_SYNCOSEL_MASK (0x03 << 6)
#define ECTRL2_MDSL_ECAP BIT(9)
#define ECTRL2_CTRSTP_FREERUN BIT(4)
#define ECTRL2_PLSL_LOW BIT(10)
#define ECTRL2_SYNC_EN BIT(5)
#endif /* __ASSEMBLY__ */
#endif /* __KERNEL_STRICT_NAMES */

7
arch/arm/include/asm/arch-am33xx/hardware_am33xx.h
View File

@@ -58,4 +58,11 @@
#define USB0_OTG_BASE 0x47401000
#define USB1_OTG_BASE 0x47401800
/* LCD Controller */
#define LCD_CNTL_BASE 0x4830E000
/* PWMSS */
#define PWMSS0_BASE 0x48300000
#define AM33XX_ECAP0_BASE 0x48300100
#endif /* __AM33XX_HARDWARE_AM33XX_H */

2
arch/arm/include/asm/arch-am33xx/omap.h
View File

@@ -18,7 +18,7 @@
#ifdef CONFIG_AM33XX
#define NON_SECURE_SRAM_START 0x402F0400
#define NON_SECURE_SRAM_END 0x40310000
#define SRAM_SCRATCH_SPACE_ADDR 0x4030C000
#define SRAM_SCRATCH_SPACE_ADDR 0x4030B800
#elif defined(CONFIG_TI81XX)
#define NON_SECURE_SRAM_START 0x40300000
#define NON_SECURE_SRAM_END 0x40320000

2
arch/arm/include/asm/arch-omap3/clock.h
View File

@@ -63,6 +63,4 @@ extern dpll_param *get_36x_core_dpll_param(void);
extern dpll_param *get_36x_per_dpll_param(void);
extern dpll_param *get_36x_per2_dpll_param(void);
extern void *_end_vect, *_start;
#endif

7
arch/arm/include/asm/arch-omap4/clock.h
View File

@@ -149,11 +149,16 @@
/* PRM_VC_VAL_BYPASS */
#define PRM_VC_I2C_CHANNEL_FREQ_KHZ 400
/* SMPS */
/* PMIC */
#define SMPS_I2C_SLAVE_ADDR 0x12
/* TWL6030 SMPS */
#define SMPS_REG_ADDR_VCORE1 0x55
#define SMPS_REG_ADDR_VCORE2 0x5B
#define SMPS_REG_ADDR_VCORE3 0x61
/* TWL6032 SMPS */
#define SMPS_REG_ADDR_SMPS1 0x55
#define SMPS_REG_ADDR_SMPS2 0x5B
#define SMPS_REG_ADDR_SMPS5 0x49
#define PHOENIX_SMPS_BASE_VOLT_STD_MODE_UV 607700
#define PHOENIX_SMPS_BASE_VOLT_STD_MODE_WITH_OFFSET_UV 709000

1
arch/arm/include/asm/arch-omap4/omap.h
View File

@@ -41,6 +41,7 @@
#define OMAP4_CONTROL_ID_CODE_ES2_3 0x6B95C02F
#define OMAP4460_CONTROL_ID_CODE_ES1_0 0x0B94E02F
#define OMAP4460_CONTROL_ID_CODE_ES1_1 0x2B94E02F
#define OMAP4470_CONTROL_ID_CODE_ES1_0 0x0B97502F
/* UART */
#define UART1_BASE (OMAP44XX_L4_PER_BASE + 0x6a000)

11
arch/arm/include/asm/arch-omap5/omap.h
View File

@@ -153,6 +153,15 @@ struct s32ktimer {
#define EFUSE_4 0x45145100
#endif /* __ASSEMBLY__ */
/*
* In all cases, the TRM defines the RAM Memory Map for the processor
* and indicates the area for the downloaded image. We use all of that
* space for download and once up and running may use other parts of the
* map for our needs. We set a scratch space that is at the end of the
* OMAP5 download area, but within the DRA7xx download area (as it is
* much larger) and do not, at this time, make use of the additional
* space.
*/
#ifdef CONFIG_DRA7XX
#define NON_SECURE_SRAM_START 0x40300000
#define NON_SECURE_SRAM_END 0x40380000 /* Not inclusive */
@@ -160,7 +169,7 @@ struct s32ktimer {
#define NON_SECURE_SRAM_START 0x40300000
#define NON_SECURE_SRAM_END 0x40320000 /* Not inclusive */
#endif
#define SRAM_SCRATCH_SPACE_ADDR NON_SECURE_SRAM_START
#define SRAM_SCRATCH_SPACE_ADDR 0x4031E000
/* base address for indirect vectors (internal boot mode) */
#define SRAM_ROM_VECT_BASE 0x4031F000

1
arch/arm/include/asm/omap_common.h
View File

@@ -622,6 +622,7 @@ static inline u8 is_omap54xx(void)
#define OMAP4430_ES2_3 0x44300230
#define OMAP4460_ES1_0 0x44600100
#define OMAP4460_ES1_1 0x44600110
#define OMAP4470_ES1_0 0x44700100
/* omap5 */
#define OMAP5430_SILICON_ID_INVALID 0