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armv8: Move secure_ram variable out of generic global data

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Secure_ram variable was put in generic global data. But only ARMv8
uses this variable. Move it to ARM specific data structure.

Signed-off-by: York Sun <york.sun@nxp.com>
This commit is contained in:
York Sun 2016-06-24 16:46:18 -07:00
parent 3a592a1349
commit e61a7534e3
11 changed files with 69 additions and 63 deletions
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3
README
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@ -3766,10 +3766,11 @@ Configuration Settings:
You only need to set this if address zero isn't writeable You only need to set this if address zero isn't writeable
- CONFIG_SYS_MEM_RESERVE_SECURE - CONFIG_SYS_MEM_RESERVE_SECURE
Only implemented for ARMv8 for now.
If defined, the size of CONFIG_SYS_MEM_RESERVE_SECURE memory If defined, the size of CONFIG_SYS_MEM_RESERVE_SECURE memory
is substracted from total RAM and won't be reported to OS. is substracted from total RAM and won't be reported to OS.
This memory can be used as secure memory. A variable This memory can be used as secure memory. A variable
gd->secure_ram is used to track the location. In systems gd->arch.secure_ram is used to track the location. In systems
the RAM base is not zero, or RAM is divided into banks, the RAM base is not zero, or RAM is divided into banks,
this variable needs to be recalcuated to get the address. this variable needs to be recalcuated to get the address.

20
arch/arm/cpu/armv8/fsl-layerscape/cpu.c
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@ -289,8 +289,8 @@ static inline int final_secure_ddr(u64 *level0_table,
* These tables are in DRAM. Sub tables are added to enable cache for * These tables are in DRAM. Sub tables are added to enable cache for
* QBMan and OCRAM. * QBMan and OCRAM.
* *
* Put the MMU table in secure memory if gd->secure_ram is valid. * Put the MMU table in secure memory if gd->arch.secure_ram is valid.
* OCRAM will be not used for this purpose so gd->secure_ram can't be 0. * OCRAM will be not used for this purpose so gd->arch.secure_ram can't be 0.
* *
* Level 1 table 0 contains 512 entries for each 1GB from 0 to 512GB. * Level 1 table 0 contains 512 entries for each 1GB from 0 to 512GB.
* Level 1 table 1 contains 512 entries for each 1GB from 512GB to 1TB. * Level 1 table 1 contains 512 entries for each 1GB from 512GB to 1TB.
@ -321,13 +321,13 @@ static inline void final_mmu_setup(void)
if (el == 3) { if (el == 3) {
/* /*
* Only use gd->secure_ram if the address is recalculated * Only use gd->arch.secure_ram if the address is recalculated
* Align to 4KB for MMU table * Align to 4KB for MMU table
*/ */
if (gd->secure_ram & MEM_RESERVE_SECURE_MAINTAINED) if (gd->arch.secure_ram & MEM_RESERVE_SECURE_MAINTAINED)
level0_table = (u64 *)(gd->secure_ram & ~0xfff); level0_table = (u64 *)(gd->arch.secure_ram & ~0xfff);
else else
printf("MMU warning: gd->secure_ram is not maintained, disabled.\n"); printf("MMU warning: gd->arch.secure_ram is not maintained, disabled.\n");
} }
#endif #endif
level1_table0 = level0_table + 512; level1_table0 = level0_table + 512;
@ -374,7 +374,7 @@ static inline void final_mmu_setup(void)
} }
/* Set the secure memory to secure in MMU */ /* Set the secure memory to secure in MMU */
#ifdef CONFIG_SYS_MEM_RESERVE_SECURE #ifdef CONFIG_SYS_MEM_RESERVE_SECURE
if (el == 3 && gd->secure_ram & MEM_RESERVE_SECURE_MAINTAINED) { if (el == 3 && gd->arch.secure_ram & MEM_RESERVE_SECURE_MAINTAINED) {
#ifdef CONFIG_FSL_LSCH3 #ifdef CONFIG_FSL_LSCH3
level2_table_secure = level2_table1 + 512; level2_table_secure = level2_table1 + 512;
#elif defined(CONFIG_FSL_LSCH2) #elif defined(CONFIG_FSL_LSCH2)
@ -382,10 +382,10 @@ static inline void final_mmu_setup(void)
#endif #endif
if (!final_secure_ddr(level0_table, if (!final_secure_ddr(level0_table,
level2_table_secure, level2_table_secure,
gd->secure_ram & ~0x3)) { gd->arch.secure_ram & ~0x3)) {
gd->secure_ram |= MEM_RESERVE_SECURE_SECURED; gd->arch.secure_ram |= MEM_RESERVE_SECURE_SECURED;
debug("Now MMU table is in secured memory at 0x%llx\n", debug("Now MMU table is in secured memory at 0x%llx\n",
gd->secure_ram & ~0x3); gd->arch.secure_ram & ~0x3);
} else { } else {
printf("MMU warning: Failed to secure DDR\n"); printf("MMU warning: Failed to secure DDR\n");
} }

14
arch/arm/include/asm/global_data.h
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@ -44,6 +44,20 @@ struct arch_global_data {
unsigned long tlb_emerg; unsigned long tlb_emerg;
#endif #endif
#endif #endif
#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
#define MEM_RESERVE_SECURE_SECURED 0x1
#define MEM_RESERVE_SECURE_MAINTAINED 0x2
#define MEM_RESERVE_SECURE_ADDR_MASK (~0x3)
/*
* Secure memory addr
* This variable needs maintenance if the RAM base is not zero,
* or if RAM splits into non-consecutive banks. It also has a
* flag indicating the secure memory is marked as secure by MMU.
* Flags used: 0x1 secured
* 0x2 maintained
*/
phys_addr_t secure_ram;
#endif
#ifdef CONFIG_OMAP_COMMON #ifdef CONFIG_OMAP_COMMON
u32 omap_boot_device; u32 omap_boot_device;

15
board/freescale/ls1043aqds/ddr.c
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@ -128,7 +128,7 @@ phys_size_t initdram(int board_type)
void dram_init_banksize(void) void dram_init_banksize(void)
{ {
/* /*
* gd->secure_ram tracks the location of secure memory. * gd->arch.secure_ram tracks the location of secure memory.
* It was set as if the memory starts from 0. * It was set as if the memory starts from 0.
* The address needs to add the offset of its bank. * The address needs to add the offset of its bank.
*/ */
@ -139,16 +139,17 @@ void dram_init_banksize(void)
gd->bd->bi_dram[1].size = gd->ram_size - gd->bd->bi_dram[1].size = gd->ram_size -
CONFIG_SYS_DDR_BLOCK1_SIZE; CONFIG_SYS_DDR_BLOCK1_SIZE;
#ifdef CONFIG_SYS_MEM_RESERVE_SECURE #ifdef CONFIG_SYS_MEM_RESERVE_SECURE
gd->secure_ram = gd->bd->bi_dram[1].start + gd->arch.secure_ram = gd->bd->bi_dram[1].start +
gd->secure_ram - gd->arch.secure_ram -
CONFIG_SYS_DDR_BLOCK1_SIZE; CONFIG_SYS_DDR_BLOCK1_SIZE;
gd->secure_ram |= MEM_RESERVE_SECURE_MAINTAINED; gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
#endif #endif
} else { } else {
gd->bd->bi_dram[0].size = gd->ram_size; gd->bd->bi_dram[0].size = gd->ram_size;
#ifdef CONFIG_SYS_MEM_RESERVE_SECURE #ifdef CONFIG_SYS_MEM_RESERVE_SECURE
gd->secure_ram = gd->bd->bi_dram[0].start + gd->secure_ram; gd->arch.secure_ram = gd->bd->bi_dram[0].start +
gd->secure_ram |= MEM_RESERVE_SECURE_MAINTAINED; gd->arch.secure_ram;
gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
#endif #endif
} }
} }

15
board/freescale/ls1043ardb/ddr.c
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@ -189,7 +189,7 @@ phys_size_t initdram(int board_type)
void dram_init_banksize(void) void dram_init_banksize(void)
{ {
/* /*
* gd->secure_ram tracks the location of secure memory. * gd->arch.secure_ram tracks the location of secure memory.
* It was set as if the memory starts from 0. * It was set as if the memory starts from 0.
* The address needs to add the offset of its bank. * The address needs to add the offset of its bank.
*/ */
@ -200,16 +200,17 @@ void dram_init_banksize(void)
gd->bd->bi_dram[1].size = gd->ram_size - gd->bd->bi_dram[1].size = gd->ram_size -
CONFIG_SYS_DDR_BLOCK1_SIZE; CONFIG_SYS_DDR_BLOCK1_SIZE;
#ifdef CONFIG_SYS_MEM_RESERVE_SECURE #ifdef CONFIG_SYS_MEM_RESERVE_SECURE
gd->secure_ram = gd->bd->bi_dram[1].start + gd->arch.secure_ram = gd->bd->bi_dram[1].start +
gd->secure_ram - gd->arch.secure_ram -
CONFIG_SYS_DDR_BLOCK1_SIZE; CONFIG_SYS_DDR_BLOCK1_SIZE;
gd->secure_ram |= MEM_RESERVE_SECURE_MAINTAINED; gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
#endif #endif
} else { } else {
gd->bd->bi_dram[0].size = gd->ram_size; gd->bd->bi_dram[0].size = gd->ram_size;
#ifdef CONFIG_SYS_MEM_RESERVE_SECURE #ifdef CONFIG_SYS_MEM_RESERVE_SECURE
gd->secure_ram = gd->bd->bi_dram[0].start + gd->secure_ram; gd->arch.secure_ram = gd->bd->bi_dram[0].start +
gd->secure_ram |= MEM_RESERVE_SECURE_MAINTAINED; gd->arch.secure_ram;
gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
#endif #endif
} }
} }

15
board/freescale/ls2080a/ddr.c
View File

@ -177,7 +177,7 @@ void dram_init_banksize(void)
#endif #endif
/* /*
* gd->secure_ram tracks the location of secure memory. * gd->arch.secure_ram tracks the location of secure memory.
* It was set as if the memory starts from 0. * It was set as if the memory starts from 0.
* The address needs to add the offset of its bank. * The address needs to add the offset of its bank.
*/ */
@ -188,16 +188,17 @@ void dram_init_banksize(void)
gd->bd->bi_dram[1].size = gd->ram_size - gd->bd->bi_dram[1].size = gd->ram_size -
CONFIG_SYS_LS2_DDR_BLOCK1_SIZE; CONFIG_SYS_LS2_DDR_BLOCK1_SIZE;
#ifdef CONFIG_SYS_MEM_RESERVE_SECURE #ifdef CONFIG_SYS_MEM_RESERVE_SECURE
gd->secure_ram = gd->bd->bi_dram[1].start + gd->arch.secure_ram = gd->bd->bi_dram[1].start +
gd->secure_ram - gd->arch.secure_ram -
CONFIG_SYS_LS2_DDR_BLOCK1_SIZE; CONFIG_SYS_LS2_DDR_BLOCK1_SIZE;
gd->secure_ram |= MEM_RESERVE_SECURE_MAINTAINED; gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
#endif #endif
} else { } else {
gd->bd->bi_dram[0].size = gd->ram_size; gd->bd->bi_dram[0].size = gd->ram_size;
#ifdef CONFIG_SYS_MEM_RESERVE_SECURE #ifdef CONFIG_SYS_MEM_RESERVE_SECURE
gd->secure_ram = gd->bd->bi_dram[0].start + gd->secure_ram; gd->arch.secure_ram = gd->bd->bi_dram[0].start +
gd->secure_ram |= MEM_RESERVE_SECURE_MAINTAINED; gd->arch.secure_ram;
gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
#endif #endif
} }

15
board/freescale/ls2080aqds/ddr.c
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@ -177,7 +177,7 @@ void dram_init_banksize(void)
#endif #endif
/* /*
* gd->secure_ram tracks the location of secure memory. * gd->arch.secure_ram tracks the location of secure memory.
* It was set as if the memory starts from 0. * It was set as if the memory starts from 0.
* The address needs to add the offset of its bank. * The address needs to add the offset of its bank.
*/ */
@ -188,16 +188,17 @@ void dram_init_banksize(void)
gd->bd->bi_dram[1].size = gd->ram_size - gd->bd->bi_dram[1].size = gd->ram_size -
CONFIG_SYS_LS2_DDR_BLOCK1_SIZE; CONFIG_SYS_LS2_DDR_BLOCK1_SIZE;
#ifdef CONFIG_SYS_MEM_RESERVE_SECURE #ifdef CONFIG_SYS_MEM_RESERVE_SECURE
gd->secure_ram = gd->bd->bi_dram[1].start + gd->arch.secure_ram = gd->bd->bi_dram[1].start +
gd->secure_ram - gd->arch.secure_ram -
CONFIG_SYS_LS2_DDR_BLOCK1_SIZE; CONFIG_SYS_LS2_DDR_BLOCK1_SIZE;
gd->secure_ram |= MEM_RESERVE_SECURE_MAINTAINED; gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
#endif #endif
} else { } else {
gd->bd->bi_dram[0].size = gd->ram_size; gd->bd->bi_dram[0].size = gd->ram_size;
#ifdef CONFIG_SYS_MEM_RESERVE_SECURE #ifdef CONFIG_SYS_MEM_RESERVE_SECURE
gd->secure_ram = gd->bd->bi_dram[0].start + gd->secure_ram; gd->arch.secure_ram = gd->bd->bi_dram[0].start +
gd->secure_ram |= MEM_RESERVE_SECURE_MAINTAINED; gd->arch.secure_ram;
gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
#endif #endif
} }

15
board/freescale/ls2080ardb/ddr.c
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@ -177,7 +177,7 @@ void dram_init_banksize(void)
#endif #endif
/* /*
* gd->secure_ram tracks the location of secure memory. * gd->arch.secure_ram tracks the location of secure memory.
* It was set as if the memory starts from 0. * It was set as if the memory starts from 0.
* The address needs to add the offset of its bank. * The address needs to add the offset of its bank.
*/ */
@ -188,16 +188,17 @@ void dram_init_banksize(void)
gd->bd->bi_dram[1].size = gd->ram_size - gd->bd->bi_dram[1].size = gd->ram_size -
CONFIG_SYS_LS2_DDR_BLOCK1_SIZE; CONFIG_SYS_LS2_DDR_BLOCK1_SIZE;
#ifdef CONFIG_SYS_MEM_RESERVE_SECURE #ifdef CONFIG_SYS_MEM_RESERVE_SECURE
gd->secure_ram = gd->bd->bi_dram[1].start + gd->arch.secure_ram = gd->bd->bi_dram[1].start +
gd->secure_ram - gd->arch.secure_ram -
CONFIG_SYS_LS2_DDR_BLOCK1_SIZE; CONFIG_SYS_LS2_DDR_BLOCK1_SIZE;
gd->secure_ram |= MEM_RESERVE_SECURE_MAINTAINED; gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
#endif #endif
} else { } else {
gd->bd->bi_dram[0].size = gd->ram_size; gd->bd->bi_dram[0].size = gd->ram_size;
#ifdef CONFIG_SYS_MEM_RESERVE_SECURE #ifdef CONFIG_SYS_MEM_RESERVE_SECURE
gd->secure_ram = gd->bd->bi_dram[0].start + gd->secure_ram; gd->arch.secure_ram = gd->bd->bi_dram[0].start +
gd->secure_ram |= MEM_RESERVE_SECURE_MAINTAINED; gd->arch.secure_ram;
gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
#endif #endif
} }

4
cmd/bdinfo.c
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@ -385,9 +385,9 @@ static int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc,
} }
#ifdef CONFIG_SYS_MEM_RESERVE_SECURE #ifdef CONFIG_SYS_MEM_RESERVE_SECURE
if (gd->secure_ram & MEM_RESERVE_SECURE_SECURED) { if (gd->arch.secure_ram & MEM_RESERVE_SECURE_SECURED) {
print_num("Secure ram", print_num("Secure ram",
gd->secure_ram & MEM_RESERVE_SECURE_ADDR_MASK); gd->arch.secure_ram & MEM_RESERVE_SECURE_ADDR_MASK);
} }
#endif #endif
#if defined(CONFIG_CMD_NET) && !defined(CONFIG_DM_ETH) #if defined(CONFIG_CMD_NET) && !defined(CONFIG_DM_ETH)

2
common/board_f.c
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@ -339,7 +339,7 @@ static int setup_dest_addr(void)
* Record secure memory location. Need recalcuate if memory splits * Record secure memory location. Need recalcuate if memory splits
* into banks, or the ram base is not zero. * into banks, or the ram base is not zero.
*/ */
gd->secure_ram = gd->ram_size; gd->arch.secure_ram = gd->ram_size;
#endif #endif
/* /*
* Subtract specified amount of memory to hide so that it won't * Subtract specified amount of memory to hide so that it won't

14
include/asm-generic/global_data.h
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@ -55,20 +55,6 @@ typedef struct global_data {
unsigned long relocaddr; /* Start address of U-Boot in RAM */ unsigned long relocaddr; /* Start address of U-Boot in RAM */
phys_size_t ram_size; /* RAM size */ phys_size_t ram_size; /* RAM size */
#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
#define MEM_RESERVE_SECURE_SECURED 0x1
#define MEM_RESERVE_SECURE_MAINTAINED 0x2
#define MEM_RESERVE_SECURE_ADDR_MASK (~0x3)
/*
* Secure memory addr
* This variable needs maintenance if the RAM base is not zero,
* or if RAM splits into non-consecutive banks. It also has a
* flag indicating the secure memory is marked as secure by MMU.
* Flags used: 0x1 secured
* 0x2 maintained
*/
phys_addr_t secure_ram;
#endif
unsigned long mon_len; /* monitor len */ unsigned long mon_len; /* monitor len */
unsigned long irq_sp; /* irq stack pointer */ unsigned long irq_sp; /* irq stack pointer */
unsigned long start_addr_sp; /* start_addr_stackpointer */ unsigned long start_addr_sp; /* start_addr_stackpointer */