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Merge branch 'master' of /home/wd/git/u-boot/work

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This commit is contained in:
Wolfgang Denk 2007-11-02 15:09:22 +01:00
commit e60adeac2d
36 changed files with 180 additions and 116 deletions
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4
Makefile
View File

@ -1733,9 +1733,13 @@ M54455EVB_i66_config : unconfig
>include/config.h ; \ >include/config.h ; \
if [ "$${FLASH}" == "INTEL" ] ; then \ if [ "$${FLASH}" == "INTEL" ] ; then \
echo "#undef CFG_ATMEL_BOOT" >> $(obj)include/config.h ; \ echo "#undef CFG_ATMEL_BOOT" >> $(obj)include/config.h ; \
echo "TEXT_BASE = 0x00000000" > $(obj)board/freescale/m54455evb/config.tmp ; \
cp $(obj)board/freescale/m54455evb/u-boot.int $(obj)board/freescale/m54455evb/u-boot.lds ; \
echo "... with INTEL boot..." ; \ echo "... with INTEL boot..." ; \
else \ else \
echo "#define CFG_ATMEL_BOOT" >> $(obj)include/config.h ; \ echo "#define CFG_ATMEL_BOOT" >> $(obj)include/config.h ; \
echo "TEXT_BASE = 0x04000000" > $(obj)board/freescale/m54455evb/config.tmp ; \
cp $(obj)board/freescale/m54455evb/u-boot.atm $(obj)board/freescale/m54455evb/u-boot.lds ; \
echo "... with ATMEL boot..." ; \ echo "... with ATMEL boot..." ; \
fi; \ fi; \
echo "#define CFG_INPUT_CLKSRC $${FREQ}" >> $(obj)include/config.h ; \ echo "#define CFG_INPUT_CLKSRC $${FREQ}" >> $(obj)include/config.h ; \

7
board/cds/common/ft_board.c
View File

@ -37,6 +37,10 @@ static void cds_pci_fixup(void *blob)
map = ft_get_prop(blob, "/" OF_SOC "/pci@8000/interrupt-map", &len); map = ft_get_prop(blob, "/" OF_SOC "/pci@8000/interrupt-map", &len);
if (!map)
map = ft_get_prop(blob, "/" OF_PCI "/interrupt-map", &len);
if (map) {
len /= sizeof(u32); len /= sizeof(u32);
slot = get_pci_slot(); slot = get_pci_slot();
@ -49,6 +53,9 @@ static void cds_pci_fixup(void *blob)
map+=7; map+=7;
} }
} else {
printf("*** Warning - No PCI node found\n");
}
} }
#endif #endif

10
board/dbau1x00/u-boot.lds
View File

@ -43,14 +43,14 @@ SECTIONS
. = ALIGN(4); . = ALIGN(4);
.data : { *(.data) } .data : { *(.data) }
. = ALIGN(4); . = .;
.sdata : { *(.sdata) } _gp = ALIGN(16) + 0x7ff0;
_gp = ALIGN(16);
.got : {
__got_start = .; __got_start = .;
.got : { *(.got) } *(.got)
__got_end = .; __got_end = .;
}
.sdata : { *(.sdata) } .sdata : { *(.sdata) }

4
board/freescale/m54455evb/config.mk
View File

@ -22,4 +22,6 @@
# MA 02111-1307 USA # MA 02111-1307 USA
# #
TEXT_BASE = 0 sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE)

10
board/gth2/u-boot.lds
View File

@ -43,14 +43,14 @@ SECTIONS
. = ALIGN(4); . = ALIGN(4);
.data : { *(.data) } .data : { *(.data) }
. = ALIGN(4); . = .;
.sdata : { *(.sdata) } _gp = ALIGN(16) + 0x7ff0;
_gp = ALIGN(16);
.got : {
__got_start = .; __got_start = .;
.got : { *(.got) } *(.got)
__got_end = .; __got_end = .;
}
.sdata : { *(.sdata) } .sdata : { *(.sdata) }

10
board/incaip/u-boot.lds
View File

@ -43,14 +43,14 @@ SECTIONS
. = ALIGN(4); . = ALIGN(4);
.data : { *(.data) } .data : { *(.data) }
. = ALIGN(4); . = .;
.sdata : { *(.sdata) } _gp = ALIGN(16) + 0x7ff0;
_gp = ALIGN(16);
.got : {
__got_start = .; __got_start = .;
.got : { *(.got) } *(.got)
__got_end = .; __got_end = .;
}
.sdata : { *(.sdata) } .sdata : { *(.sdata) }

1
board/m5282evb/m5282evb.c
View File

@ -89,4 +89,5 @@ long int initdram (int board_type)
/* Write to the SDRAM Mode Register */ /* Write to the SDRAM Mode Register */
*(u32 *)(CFG_SDRAM_BASE + 0x400) = 0xA5A59696; *(u32 *)(CFG_SDRAM_BASE + 0x400) = 0xA5A59696;
} }
return dramsize;
} }

10
board/pb1x00/u-boot.lds
View File

@ -43,14 +43,14 @@ SECTIONS
. = ALIGN(4); . = ALIGN(4);
.data : { *(.data) } .data : { *(.data) }
. = ALIGN(4); . = .;
.sdata : { *(.sdata) } _gp = ALIGN(16) + 0x7ff0;
_gp = ALIGN(16);
.got : {
__got_start = .; __got_start = .;
.got : { *(.got) } *(.got)
__got_end = .; __got_end = .;
}
.sdata : { *(.sdata) } .sdata : { *(.sdata) }

10
board/purple/u-boot.lds
View File

@ -53,14 +53,14 @@ SECTIONS
. = ALIGN(4); . = ALIGN(4);
.data : { *(.data) } .data : { *(.data) }
. = ALIGN(4); . = .;
.sdata : { *(.sdata) } _gp = ALIGN(16) + 0x7ff0;
_gp = ALIGN(16);
.got : {
__got_start = .; __got_start = .;
.got : { *(.got) } *(.got)
__got_end = .; __got_end = .;
}
.sdata : { *(.sdata) } .sdata : { *(.sdata) }

10
board/tb0229/u-boot.lds
View File

@ -43,14 +43,14 @@ SECTIONS
. = ALIGN(4); . = ALIGN(4);
.data : { *(.data) } .data : { *(.data) }
. = ALIGN(4); . = .;
.sdata : { *(.sdata) } _gp = ALIGN(16) + 0x7ff0;
_gp = ALIGN(16);
.got : {
__got_start = .; __got_start = .;
.got : { *(.got) } *(.got)
__got_end = .; __got_end = .;
}
.sdata : { *(.sdata) } .sdata : { *(.sdata) }

6
cpu/mcf52x2/start.S
View File

@ -58,7 +58,7 @@ _vectors:
.long 0x00000000 /* Flash offset is 0 until we setup CS0 */ .long 0x00000000 /* Flash offset is 0 until we setup CS0 */
#if defined(CONFIG_R5200) #if defined(CONFIG_R5200)
.long 0x400 .long 0x400
#elif defined(CONFIG_M5282) #elif defined(CONFIG_M5282) && (TEXT_BASE == CFG_INT_FLASH_BASE)
.long _start - TEXT_BASE .long _start - TEXT_BASE
#else #else
.long _START .long _START
@ -177,7 +177,11 @@ _after_flashbar_copy:
* therefore no VBR to set * therefore no VBR to set
*/ */
#if !defined(CONFIG_MONITOR_IS_IN_RAM) #if !defined(CONFIG_MONITOR_IS_IN_RAM)
#if defined(CONFIG_M5282) && (TEXT_BASE == CFG_INT_FLASH_BASE)
move.l #CFG_INT_FLASH_BASE, %d0
#else
move.l #CFG_FLASH_BASE, %d0 move.l #CFG_FLASH_BASE, %d0
#endif
movec %d0, %VBR movec %d0, %VBR
#endif #endif

4
cpu/mcf532x/start.S
View File

@ -131,7 +131,7 @@ _start:
movec %d0, %VBR movec %d0, %VBR
move.l #(CFG_INIT_RAM_ADDR + CFG_INIT_RAM_CTRL), %d0 move.l #(CFG_INIT_RAM_ADDR + CFG_INIT_RAM_CTRL), %d0
movec %d0, %RAMBAR0 movec %d0, %RAMBAR1
/* invalidate and disable cache */ /* invalidate and disable cache */
move.l #0x01000000, %d0 /* Invalidate cache cmd */ move.l #0x01000000, %d0 /* Invalidate cache cmd */
@ -268,7 +268,7 @@ _int_handler:
icache_enable: icache_enable:
move.l #0x01000000, %d0 /* Invalidate cache cmd */ move.l #0x01000000, %d0 /* Invalidate cache cmd */
movec %d0, %CACR /* Invalidate cache */ movec %d0, %CACR /* Invalidate cache */
move.l #(CFG_SDRAM_BASE + 0xc000 + ((CFG_SDRAM_SIZE & 0x1fe0) << 11)), %d0 move.l #(CFG_SDRAM_BASE + 0x1c000), %d0
movec %d0, %ACR0 /* Enable cache */ movec %d0, %ACR0 /* Enable cache */
move.l #0x80000200, %d0 /* Setup cache mask */ move.l #0x80000200, %d0 /* Setup cache mask */

2
cpu/mips/config.mk
View File

@ -35,6 +35,6 @@ else
ENDIANNESS = -EB ENDIANNESS = -EB
endif endif
MIPSFLAGS += $(ENDIANNESS) -mabicalls MIPSFLAGS += $(ENDIANNESS)
PLATFORM_CPPFLAGS += $(MIPSFLAGS) PLATFORM_CPPFLAGS += $(MIPSFLAGS)

19
cpu/mips/start.S
View File

@ -234,11 +234,11 @@ reset:
li t0, CONF_CM_UNCACHED li t0, CONF_CM_UNCACHED
mtc0 t0, CP0_CONFIG mtc0 t0, CP0_CONFIG
/* Initialize GOT pointer. /* Initialize $gp.
*/ */
bal 1f bal 1f
nop nop
.word _GLOBAL_OFFSET_TABLE_ .word _gp
1: 1:
move gp, ra move gp, ra
lw t1, 0(ra) lw t1, 0(ra)
@ -306,9 +306,9 @@ relocate_code:
move t1, a2 move t1, a2
/* /*
* Fix GOT pointer: * Fix $gp:
* *
* New GOT-PTR = (old GOT-PTR - CFG_MONITOR_BASE) + Destination Address * New $gp = (Old $gp - CFG_MONITOR_BASE) + Destination Address
*/ */
move t6, gp move t6, gp
sub gp, CFG_MONITOR_BASE sub gp, CFG_MONITOR_BASE
@ -341,15 +341,22 @@ relocate_code:
j t0 j t0
nop nop
.gpword _GLOBAL_OFFSET_TABLE_ /* _GLOBAL_OFFSET_TABLE_ - _gp */
.word uboot_end_data .word uboot_end_data
.word uboot_end .word uboot_end
.word num_got_entries .word num_got_entries
in_ram: in_ram:
/* Now we want to update GOT. /*
* Now we want to update GOT.
*
* GOT[0] is reserved. GOT[1] is also reserved for the dynamic object
* generated by GNU ld. Skip these reserved entries from relocation.
*/ */
lw t3, -4(t0) /* t3 <-- num_got_entries */ lw t3, -4(t0) /* t3 <-- num_got_entries */
addi t4, gp, 8 /* Skipping first two entries. */ lw t4, -16(t0) /* t4 <-- (_GLOBAL_OFFSET_TABLE_ - _gp) */
add t4, t4, gp /* t4 now holds _GLOBAL_OFFSET_TABLE_ */
addi t4, t4, 8 /* Skipping first two entries. */
li t2, 2 li t2, 2
1: 1:
lw t1, 0(t4) lw t1, 0(t4)

7
cpu/mpc85xx/cpu.c
View File

@ -163,7 +163,12 @@ int do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
* Initiate hard reset in debug control register DBCR0 * Initiate hard reset in debug control register DBCR0
* Make sure MSR[DE] = 1 * Make sure MSR[DE] = 1
*/ */
unsigned long val; unsigned long val, msr;
msr = mfmsr ();
msr |= MSR_DE;
mtmsr (msr);
val = mfspr(DBCR0); val = mfspr(DBCR0);
val |= 0x70000000; val |= 0x70000000;
mtspr(DBCR0,val); mtspr(DBCR0,val);

24
cpu/mpc85xx/start.S
View File

@ -218,6 +218,8 @@ _start_e500:
bdnz 0b bdnz 0b
/* Clear and set up some registers. */ /* Clear and set up some registers. */
li r0,0
mtmsr r0
li r0,0x0000 li r0,0x0000
lis r1,0xffff lis r1,0xffff
mtspr DEC,r0 /* prevent dec exceptions */ mtspr DEC,r0 /* prevent dec exceptions */
@ -266,18 +268,17 @@ _start_e500:
*/ */
lis r3,CFG_INIT_RAM_ADDR@h lis r3,CFG_INIT_RAM_ADDR@h
ori r3,r3,CFG_INIT_RAM_ADDR@l ori r3,r3,CFG_INIT_RAM_ADDR@l
li r2,512 /* 512*32=16K */ li r2,(CFG_DCACHE_SIZE / (2 * CFG_CACHELINE_SIZE))
mtctr r2 mtctr r2
li r0,0 li r0,0
1: 1:
dcbz r0,r3 dcbz r0,r3
dcbtls 0,r0,r3 dcbtls 0,r0,r3
addi r3,r3,32 addi r3,r3,CFG_CACHELINE_SIZE
bdnz 1b bdnz 1b
/* Jump out the last 4K page and continue to 'normal' start */ /* Jump out the last 4K page and continue to 'normal' start */
#ifdef CFG_RAMBOOT #ifdef CFG_RAMBOOT
bl 3f
b _start_cont b _start_cont
#else #else
/* Calculate absolute address in FLASH and jump there */ /* Calculate absolute address in FLASH and jump there */
@ -286,15 +287,9 @@ _start_e500:
ori r3,r3,CFG_MONITOR_BASE@l ori r3,r3,CFG_MONITOR_BASE@l
addi r3,r3,_start_cont - _start + _START_OFFSET addi r3,r3,_start_cont - _start + _START_OFFSET
mtlr r3 mtlr r3
blr
#endif #endif
3: li r0,0
mtspr SRR1,r0 /* Keep things disabled for now */
mflr r1
mtspr SRR0,r1
rfi
isync
.text .text
.globl _start .globl _start
_start: _start:
@ -701,6 +696,7 @@ in8:
.globl out8 .globl out8
out8: out8:
stb r4,0x0000(r3) stb r4,0x0000(r3)
sync
blr blr
/*------------------------------------------------------------------------------- */ /*------------------------------------------------------------------------------- */
@ -710,6 +706,7 @@ out8:
.globl out16 .globl out16
out16: out16:
sth r4,0x0000(r3) sth r4,0x0000(r3)
sync
blr blr
/*------------------------------------------------------------------------------- */ /*------------------------------------------------------------------------------- */
@ -719,6 +716,7 @@ out16:
.globl out16r .globl out16r
out16r: out16r:
sthbrx r4,r0,r3 sthbrx r4,r0,r3
sync
blr blr
/*------------------------------------------------------------------------------- */ /*------------------------------------------------------------------------------- */
@ -728,6 +726,7 @@ out16r:
.globl out32 .globl out32
out32: out32:
stw r4,0x0000(r3) stw r4,0x0000(r3)
sync
blr blr
/*------------------------------------------------------------------------------- */ /*------------------------------------------------------------------------------- */
@ -737,6 +736,7 @@ out32:
.globl out32r .globl out32r
out32r: out32r:
stwbrx r4,r0,r3 stwbrx r4,r0,r3
sync
blr blr
/*------------------------------------------------------------------------------- */ /*------------------------------------------------------------------------------- */
@ -1061,11 +1061,11 @@ unlock_ram_in_cache:
/* invalidate the INIT_RAM section */ /* invalidate the INIT_RAM section */
lis r3,(CFG_INIT_RAM_ADDR & ~31)@h lis r3,(CFG_INIT_RAM_ADDR & ~31)@h
ori r3,r3,(CFG_INIT_RAM_ADDR & ~31)@l ori r3,r3,(CFG_INIT_RAM_ADDR & ~31)@l
li r4,512 li r4,(CFG_DCACHE_SIZE / (2 * CFG_CACHELINE_SIZE))
mtctr r4 mtctr r4
1: icbi r0,r3 1: icbi r0,r3
dcbi r0,r3 dcbi r0,r3
addi r3,r3,32 addi r3,r3,CFG_CACHELINE_SIZE
bdnz 1b bdnz 1b
sync /* Wait for all icbi to complete on bus */ sync /* Wait for all icbi to complete on bus */
isync isync

2
drivers/Makefile
View File

@ -45,7 +45,7 @@ COBJS = 3c589.o 5701rls.o ali512x.o at45.o ata_piix.o \
s3c4510b_eth.o s3c4510b_uart.o \ s3c4510b_eth.o s3c4510b_uart.o \
sed13806.o sed156x.o \ sed13806.o sed156x.o \
serial.o serial_max3100.o \ serial.o serial_max3100.o \
serial_pl010.o serial_pl011.o serial_xuartlite.o \ serial_xuartlite.o \
sil680.o sl811_usb.o sm501.o smc91111.o smiLynxEM.o \ sil680.o sl811_usb.o sm501.o smc91111.o smiLynxEM.o \
status_led.o sym53c8xx.o systemace.o ahci.o \ status_led.o sym53c8xx.o systemace.o ahci.o \
ti_pci1410a.o tigon3.o tqm8xx_pcmcia.o tsec.o \ ti_pci1410a.o tigon3.o tqm8xx_pcmcia.o tsec.o \

2
drivers/serial/Makefile
View File

@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
LIB := $(obj)libserial.a LIB := $(obj)libserial.a
COBJS := mcfuart.o COBJS := mcfuart.o serial_pl010.o serial_pl011.o
SRCS := $(COBJS:.o=.c) SRCS := $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS)) OBJS := $(addprefix $(obj),$(COBJS))

0
drivers/serial_pl010.c → drivers/serial/serial_pl010.c
View File

0
drivers/serial_pl011.c → drivers/serial/serial_pl011.c
View File

0
drivers/serial_pl011.h → drivers/serial/serial_pl011.h
View File

1
drivers/tsec.c
View File

@ -803,6 +803,7 @@ static void startup_tsec(struct eth_device *dev)
/* Tell the DMA it is clear to go */ /* Tell the DMA it is clear to go */
regs->dmactrl |= DMACTRL_INIT_SETTINGS; regs->dmactrl |= DMACTRL_INIT_SETTINGS;
regs->tstat = TSTAT_CLEAR_THALT; regs->tstat = TSTAT_CLEAR_THALT;
regs->rstat = RSTAT_CLEAR_RHALT;
regs->dmactrl &= ~(DMACTRL_GRS | DMACTRL_GTS); regs->dmactrl &= ~(DMACTRL_GRS | DMACTRL_GTS);
} }

10
examples/mips.lds
View File

@ -39,14 +39,14 @@ SECTIONS
. = ALIGN(4); . = ALIGN(4);
.data : { *(.data) } .data : { *(.data) }
. = ALIGN(4); . = .;
.sdata : { *(.sdata) } _gp = ALIGN(16) + 0x7ff0;
_gp = ALIGN(16);
.got : {
__got_start = .; __got_start = .;
.got : { *(.got) } *(.got)
__got_end = .; __got_end = .;
}
.sdata : { *(.sdata) } .sdata : { *(.sdata) }

2
include/asm-mips/addrspace.h
View File

@ -49,7 +49,7 @@
cannot access physical memory directly from core */ cannot access physical memory directly from core */
#define UNCACHED_SDRAM(a) (((unsigned long)(a)) | 0x20000000) #define UNCACHED_SDRAM(a) (((unsigned long)(a)) | 0x20000000)
#else /* !CONFIG_AU1X00 */ #else /* !CONFIG_AU1X00 */
#define UNCACHED_SDRAM(a) PHYSADDR(a) #define UNCACHED_SDRAM(a) KSEG1ADDR(a)
#endif /* CONFIG_AU1X00 */ #endif /* CONFIG_AU1X00 */
#endif /* __ASSEMBLY__ */ #endif /* __ASSEMBLY__ */
/* /*

2
include/configs/M5253EVBE.h
View File

@ -146,7 +146,7 @@
* Please note that CFG_SDRAM_BASE _must_ start at 0 * Please note that CFG_SDRAM_BASE _must_ start at 0
*/ */
#define CFG_SDRAM_BASE 0x00000000 #define CFG_SDRAM_BASE 0x00000000
#define CFG_SDRAM_SIZE 16 /* SDRAM size in MB */ #define CFG_SDRAM_SIZE 8 /* SDRAM size in MB */
#ifdef CONFIG_MONITOR_IS_IN_RAM #ifdef CONFIG_MONITOR_IS_IN_RAM
#define CFG_MONITOR_BASE 0x20000 #define CFG_MONITOR_BASE 0x20000

2
include/configs/M5282EVB.h
View File

@ -163,7 +163,7 @@
* Please note that CFG_SDRAM_BASE _must_ start at 0 * Please note that CFG_SDRAM_BASE _must_ start at 0
*/ */
#define CFG_SDRAM_BASE 0x00000000 #define CFG_SDRAM_BASE 0x00000000
#define CFG_SDRAM_SIZE 8 /* SDRAM size in MB */ #define CFG_SDRAM_SIZE 16 /* SDRAM size in MB */
#define CFG_FLASH_BASE 0xffe00000 #define CFG_FLASH_BASE 0xffe00000
#define CFG_INT_FLASH_BASE 0xf0000000 #define CFG_INT_FLASH_BASE 0xf0000000
#define CFG_INT_FLASH_ENABLE 0x21 #define CFG_INT_FLASH_ENABLE 0x21

2
include/configs/M5329EVB.h
View File

@ -175,7 +175,7 @@
* Please note that CFG_SDRAM_BASE _must_ start at 0 * Please note that CFG_SDRAM_BASE _must_ start at 0
*/ */
#define CFG_SDRAM_BASE 0x40000000 #define CFG_SDRAM_BASE 0x40000000
#define CFG_SDRAM_SIZE 16 /* SDRAM size in MB */ #define CFG_SDRAM_SIZE 32 /* SDRAM size in MB */
#define CFG_SDRAM_CFG1 0x53722730 #define CFG_SDRAM_CFG1 0x53722730
#define CFG_SDRAM_CFG2 0x56670000 #define CFG_SDRAM_CFG2 0x56670000
#define CFG_SDRAM_CTRL 0xE1092000 #define CFG_SDRAM_CTRL 0xE1092000

36
include/configs/M54455EVB.h
View File

@ -27,8 +27,8 @@
* board/config.h - configuration options, board specific * board/config.h - configuration options, board specific
*/ */
#ifndef _JAMICA54455_H #ifndef _M54455EVB_H
#define _JAMICA54455_H #define _M54455EVB_H
/* /*
* High Level Configuration Options * High Level Configuration Options
@ -75,7 +75,7 @@
#define CONFIG_CMD_MISC #define CONFIG_CMD_MISC
#define CONFIG_CMD_MII #define CONFIG_CMD_MII
#define CONFIG_CMD_NET #define CONFIG_CMD_NET
#define CONFIG_CMD_PCI #undef CONFIG_CMD_PCI
#define CONFIG_CMD_PING #define CONFIG_CMD_PING
#define CONFIG_CMD_REGINFO #define CONFIG_CMD_REGINFO
@ -129,8 +129,8 @@
"u-boot=u-boot.bin\0" \ "u-boot=u-boot.bin\0" \
"load=tftp ${loadaddr) ${u-boot}\0" \ "load=tftp ${loadaddr) ${u-boot}\0" \
"upd=run load; run prog\0" \ "upd=run load; run prog\0" \
"prog=prot off 0 2ffff;" \ "prog=prot off 4000000 402ffff;" \
"era 0 2ffff;" \ "era 4000000 402ffff;" \
"cp.b ${loadaddr} 0 ${filesize};" \ "cp.b ${loadaddr} 0 ${filesize};" \
"save\0" \ "save\0" \
"" ""
@ -174,6 +174,7 @@
#define CFG_IMMR CFG_MBAR #define CFG_IMMR CFG_MBAR
/* PCI */ /* PCI */
#ifdef CONFIG_CMD_PCI
#define CONFIG_PCI 1 #define CONFIG_PCI 1
#define CFG_PCI_MEM_BUS 0xA0000000 #define CFG_PCI_MEM_BUS 0xA0000000
@ -187,6 +188,7 @@
#define CFG_PCI_CFG_BUS 0xB0000000 #define CFG_PCI_CFG_BUS 0xB0000000
#define CFG_PCI_CFG_PHYS CFG_PCI_CFG_BUS #define CFG_PCI_CFG_PHYS CFG_PCI_CFG_BUS
#define CFG_PCI_CFG_SIZE 0x01000000 #define CFG_PCI_CFG_SIZE 0x01000000
#endif
/* FPGA - Spartan 2 */ /* FPGA - Spartan 2 */
/* experiment /* experiment
@ -268,8 +270,6 @@
/* Configuration for environment /* Configuration for environment
* Environment is embedded in u-boot in the second sector of the flash * Environment is embedded in u-boot in the second sector of the flash
*/ */
#define CFG_ENV_OFFSET 0x4000
#define CFG_ENV_SECT_SIZE 0x2000
#define CFG_ENV_IS_IN_FLASH 1 #define CFG_ENV_IS_IN_FLASH 1
#define CONFIG_ENV_OVERWRITE 1 #define CONFIG_ENV_OVERWRITE 1
#undef CFG_ENV_IS_EMBEDDED #undef CFG_ENV_IS_EMBEDDED
@ -278,13 +278,17 @@
* FLASH organization * FLASH organization
*/ */
#ifdef CFG_ATMEL_BOOT #ifdef CFG_ATMEL_BOOT
# define CFG_FLASH_BASE 0 # define CFG_FLASH_BASE CFG_CS0_BASE
# define CFG_FLASH0_BASE CFG_CS0_BASE # define CFG_FLASH0_BASE CFG_CS0_BASE
# define CFG_FLASH1_BASE CFG_CS1_BASE # define CFG_FLASH1_BASE CFG_CS1_BASE
# define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x4000)
# define CFG_ENV_SECT_SIZE 0x2000
#else #else
# define CFG_FLASH_BASE CFG_FLASH0_BASE # define CFG_FLASH_BASE CFG_FLASH0_BASE
# define CFG_FLASH0_BASE CFG_CS1_BASE # define CFG_FLASH0_BASE CFG_CS1_BASE
# define CFG_FLASH1_BASE CFG_CS0_BASE # define CFG_FLASH1_BASE CFG_CS0_BASE
# define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x60000)
# define CFG_ENV_SECT_SIZE 0x20000
#endif #endif
/* M54455EVB has one non CFI flash, defined CFG_FLASH_CFI will cause the system /* M54455EVB has one non CFI flash, defined CFG_FLASH_CFI will cause the system
@ -328,9 +332,9 @@
* NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support. * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support.
*/ */
#ifdef CFG_ATMEL_BOOT #ifdef CFG_ATMEL_BOOT
# define CONFIG_JFFS2_DEV "nor0" # define CONFIG_JFFS2_DEV "nor1"
# define CONFIG_JFFS2_PART_SIZE 0x01000000 # define CONFIG_JFFS2_PART_SIZE 0x01000000
# define CONFIG_JFFS2_PART_OFFSET CFG_FLASH1_BASE # define CONFIG_JFFS2_PART_OFFSET (CFG_FLASH1_BASE + 0x500000)
#else #else
# define CONFIG_JFFS2_DEV "nor0" # define CONFIG_JFFS2_DEV "nor0"
# define CONFIG_JFFS2_PART_SIZE (0x01000000 - 0x500000) # define CONFIG_JFFS2_PART_SIZE (0x01000000 - 0x500000)
@ -356,20 +360,20 @@
#ifdef CFG_ATMEL_BOOT #ifdef CFG_ATMEL_BOOT
/* Atmel Flash */ /* Atmel Flash */
#define CFG_CS0_BASE 0 #define CFG_CS0_BASE 0x04000000
#define CFG_CS0_MASK 0x00070001 #define CFG_CS0_MASK 0x00070001
#define CFG_CS0_CTRL 0x00001140 #define CFG_CS0_CTRL 0x00001140
/* Intel Flash */ /* Intel Flash */
#define CFG_CS1_BASE 0x04000000 #define CFG_CS1_BASE 0x00000000
#define CFG_CS1_MASK 0x01FF0001 #define CFG_CS1_MASK 0x01FF0001
#define CFG_CS1_CTRL 0x003F3D60 #define CFG_CS1_CTRL 0x00000D60
#define CFG_ATMEL_BASE CFG_CS0_BASE #define CFG_ATMEL_BASE CFG_CS0_BASE
#else #else
/* Intel Flash */ /* Intel Flash */
#define CFG_CS0_BASE 0 #define CFG_CS0_BASE 0x00000000
#define CFG_CS0_MASK 0x01FF0001 #define CFG_CS0_MASK 0x01FF0001
#define CFG_CS0_CTRL 0x003F3D60 #define CFG_CS0_CTRL 0x00000D60
/* Atmel Flash */ /* Atmel Flash */
#define CFG_CS1_BASE 0x04000000 #define CFG_CS1_BASE 0x04000000
#define CFG_CS1_MASK 0x00070001 #define CFG_CS1_MASK 0x00070001
@ -388,4 +392,4 @@
#define CFG_CS3_MASK 0x00070001 #define CFG_CS3_MASK 0x00070001
#define CFG_CS3_CTRL 0x00000020 #define CFG_CS3_CTRL 0x00000020
#endif /* _JAMICA54455_H */ #endif /* _M54455EVB_H */

1
include/configs/MPC8541CDS.h
View File

@ -316,6 +316,7 @@ extern unsigned long get_clock_freq(void);
#define OF_SOC "soc8541@e0000000" #define OF_SOC "soc8541@e0000000"
#define OF_TBCLK (bd->bi_busfreq / 8) #define OF_TBCLK (bd->bi_busfreq / 8)
#define OF_STDOUT_PATH "/soc8541@e0000000/serial@4600" #define OF_STDOUT_PATH "/soc8541@e0000000/serial@4600"
#define OF_PCI "pci@e0008000"
/* /*
* I2C * I2C

1
include/configs/MPC8548CDS.h
View File

@ -340,6 +340,7 @@ extern unsigned long get_clock_freq(void);
#define OF_SOC "soc8548@e0000000" #define OF_SOC "soc8548@e0000000"
#define OF_TBCLK (bd->bi_busfreq / 8) #define OF_TBCLK (bd->bi_busfreq / 8)
#define OF_STDOUT_PATH "/soc8548@e0000000/serial@4600" #define OF_STDOUT_PATH "/soc8548@e0000000/serial@4600"
#define OF_PCI "pci@e0008000"
/* /*
* I2C * I2C

1
include/configs/MPC8555CDS.h
View File

@ -316,6 +316,7 @@ extern unsigned long get_clock_freq(void);
#define OF_SOC "soc8555@e0000000" #define OF_SOC "soc8555@e0000000"
#define OF_TBCLK (bd->bi_busfreq / 8) #define OF_TBCLK (bd->bi_busfreq / 8)
#define OF_STDOUT_PATH "/soc8555@e0000000/serial@4600" #define OF_STDOUT_PATH "/soc8555@e0000000/serial@4600"
#define OF_PCI "pci@e0008000"
/* /*
* I2C * I2C

2
include/configs/MPC8568MDS.h
View File

@ -297,7 +297,7 @@ extern unsigned long get_clock_freq(void);
#define OF_SOC "soc8568@e0000000" #define OF_SOC "soc8568@e0000000"
#define OF_QE "qe@e0080000" #define OF_QE "qe@e0080000"
#define OF_TBCLK (bd->bi_busfreq / 8) #define OF_TBCLK (bd->bi_busfreq / 8)
#define OF_STDOUT_PATH "/soc8568@e0000000/serial@4600" #define OF_STDOUT_PATH "/soc8568@e0000000/serial@4500"
/* /*
* I2C * I2C

11
include/configs/atstk1002.h
View File

@ -114,15 +114,10 @@
#define CONFIG_AUTOBOOT_STOP_STR " " #define CONFIG_AUTOBOOT_STOP_STR " "
/* /*
* These are "locally administered ethernet addresses" generated by * After booting the board for the first time, new ethernet addresses
* ./tools/gen_eth_addr * should be generated and assigned to the environment variables
* * "ethaddr" and "eth1addr". This is normally done during production.
* After booting the board for the first time, new addresses should be
* generated and assigned to the environment variables "ethaddr" and
* "eth1addr".
*/ */
#define CONFIG_ETHADDR 6a:87:71:14:cd:cb
#define CONFIG_ETH1ADDR ca:f8:15:e6:3e:e6
#define CONFIG_OVERWRITE_ETHADDR_ONCE 1 #define CONFIG_OVERWRITE_ETHADDR_ONCE 1
#define CONFIG_NET_MULTI 1 #define CONFIG_NET_MULTI 1

3
lib_m68k/m68k_linux.c
View File

@ -26,6 +26,7 @@
#include <image.h> #include <image.h>
#include <zlib.h> #include <zlib.h>
#include <bzlib.h> #include <bzlib.h>
#include <watchdog.h>
#include <environment.h> #include <environment.h>
#include <asm/byteorder.h> #include <asm/byteorder.h>
@ -36,6 +37,8 @@ DECLARE_GLOBAL_DATA_PTR;
#define LINUX_MAX_ENVS 256 #define LINUX_MAX_ENVS 256
#define LINUX_MAX_ARGS 256 #define LINUX_MAX_ARGS 256
#define CHUNKSZ (64 * 1024)
#ifdef CONFIG_SHOW_BOOT_PROGRESS #ifdef CONFIG_SHOW_BOOT_PROGRESS
# include <status_led.h> # include <status_led.h>
# define SHOW_BOOT_PROGRESS(arg) show_boot_progress(arg) # define SHOW_BOOT_PROGRESS(arg) show_boot_progress(arg)

25
mips_config.mk
View File

@ -22,3 +22,28 @@
# #
PLATFORM_CPPFLAGS += -DCONFIG_MIPS -D__MIPS__ PLATFORM_CPPFLAGS += -DCONFIG_MIPS -D__MIPS__
#
# From Linux arch/mips/Makefile
#
# GCC uses -G 0 -mabicalls -fpic as default. We don't want PIC in the kernel
# code since it only slows down the whole thing. At some point we might make
# use of global pointer optimizations but their use of $28 conflicts with
# the current pointer optimization.
#
# The DECStation requires an ECOFF kernel for remote booting, other MIPS
# machines may also. Since BFD is incredibly buggy with respect to
# crossformat linking we rely on the elf2ecoff tool for format conversion.
#
# cflags-y += -G 0 -mno-abicalls -fno-pic -pipe
# cflags-y += -msoft-float
# LDFLAGS_vmlinux += -G 0 -static -n -nostdlib
# MODFLAGS += -mlong-calls
#
#
# Meanwhile, U-Boot rely on PIC. We add proper switches explicitly.
#
PLATFORM_CPPFLAGS += -G 0 -mabicalls -fpic -pipe
PLATFORM_CPPFLAGS += -msoft-float
PLATFORM_LDFLAGS += -G 0 -static -n -nostdlib

11
net/bootp.c
View File

@ -850,9 +850,9 @@ static void DhcpSendRequestPkt(Bootp_t *bp_offer)
bp->bp_hlen = HWL_ETHER; bp->bp_hlen = HWL_ETHER;
bp->bp_hops = 0; bp->bp_hops = 0;
bp->bp_secs = htons(get_timer(0) / CFG_HZ); bp->bp_secs = htons(get_timer(0) / CFG_HZ);
NetCopyIP(&bp->bp_ciaddr, &bp_offer->bp_ciaddr); /* both in network byte order */ /* Do not set the client IP, your IP, or server IP yet, since it hasn't been ACK'ed by
NetCopyIP(&bp->bp_yiaddr, &bp_offer->bp_yiaddr); * the server yet */
NetCopyIP(&bp->bp_siaddr, &bp_offer->bp_siaddr);
/* /*
* RFC3046 requires Relay Agents to discard packets with * RFC3046 requires Relay Agents to discard packets with
* nonzero and offered giaddr * nonzero and offered giaddr
@ -870,7 +870,9 @@ static void DhcpSendRequestPkt(Bootp_t *bp_offer)
/* /*
* Copy options from OFFER packet if present * Copy options from OFFER packet if present
*/ */
NetCopyIP(&OfferedIP, &bp->bp_yiaddr);
/* Copy offered IP into the parameters request list */
NetCopyIP(&OfferedIP, &bp_offer->bp_yiaddr);
extlen = DhcpExtended((u8 *)bp->bp_vend, DHCP_REQUEST, NetDHCPServerIP, OfferedIP); extlen = DhcpExtended((u8 *)bp->bp_vend, DHCP_REQUEST, NetDHCPServerIP, OfferedIP);
pktlen = BOOTP_SIZE - sizeof(bp->bp_vend) + extlen; pktlen = BOOTP_SIZE - sizeof(bp->bp_vend) + extlen;
@ -980,3 +982,4 @@ void DhcpRequest(void)
#endif #endif
#endif #endif