From e5b29d870b0a7711affe640aa506fda633f0ef59 Mon Sep 17 00:00:00 2001 From: David Wu Date: Wed, 2 Jan 2019 21:02:35 +0800 Subject: [PATCH] ARM: dts: rk322x: Correct the uart2 default pin configuration To match the iomux setting of uart2 at SPL, correct the uart2 default pin configuration, if not changed, the evb-rk3229 can't output the log message. Signed-off-by: David Wu Reviewed-by: Kever Yang Reviewed-by: Philipp Tomsich --- arch/arm/dts/rk322x.dtsi | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/arch/arm/dts/rk322x.dtsi b/arch/arm/dts/rk322x.dtsi index be026b0e07..4a8be5dabb 100644 --- a/arch/arm/dts/rk322x.dtsi +++ b/arch/arm/dts/rk322x.dtsi @@ -206,7 +206,7 @@ clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; clock-names = "baudclk", "apb_pclk"; pinctrl-names = "default"; - pinctrl-0 = <&uart2_xfer>; + pinctrl-0 = <&uart21_xfer>; reg-shift = <2>; reg-io-width = <4>; status = "disabled"; @@ -748,7 +748,7 @@ uart2 { uart2_xfer: uart2-xfer { - rockchip,pins = <1 RK_PC2 RK_FUNC_2 &pcfg_pull_none>, + rockchip,pins = <1 RK_PC2 RK_FUNC_2 &pcfg_pull_up>, <1 RK_PC3 RK_FUNC_2 &pcfg_pull_none>; }; @@ -760,6 +760,13 @@ rockchip,pins = <0 RK_PD0 RK_FUNC_1 &pcfg_pull_none>; }; }; + + uart2-1 { + uart21_xfer: uart21-xfer { + rockchip,pins = <1 10 RK_FUNC_2 &pcfg_pull_up>, + <1 9 RK_FUNC_2 &pcfg_pull_none>; + }; + }; }; dmc: dmc@11200000 {