From a1f2779f5188280b1f131138c649354ec67ad12e Mon Sep 17 00:00:00 2001 From: Stefan Agner Date: Thu, 6 Dec 2018 14:55:03 +0100 Subject: [PATCH 01/17] board: toradex: colibri_vf: unset NFS and LOADS/B Safe some space by not selecting CMD_NFS and CMD_LOADS/B. Signed-off-by: Stefan Agner Reviewed-by: Lukasz Majewski --- configs/colibri_vf_defconfig | 3 +++ 1 file changed, 3 insertions(+) diff --git a/configs/colibri_vf_defconfig b/configs/colibri_vf_defconfig index fb0578868d..4192501257 100644 --- a/configs/colibri_vf_defconfig +++ b/configs/colibri_vf_defconfig @@ -23,11 +23,14 @@ CONFIG_CMD_MEMTEST=y CONFIG_CMD_DFU=y CONFIG_CMD_FUSE=y CONFIG_CMD_GPIO=y +# CONFIG_CMD_LOADB is not set +# CONFIG_CMD_LOADS is not set CONFIG_CMD_MMC=y CONFIG_CMD_USB=y CONFIG_CMD_USB_MASS_STORAGE=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_DHCP=y +# CONFIG_CMD_NFS is not set CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_BMP=y From a95d444055134fd8f0e1f2bd4c11222170fe6dc5 Mon Sep 17 00:00:00 2001 From: Stefan Agner Date: Fri, 14 Dec 2018 15:26:00 +0100 Subject: [PATCH 02/17] ARM: vf610: ddrmc: program Dummy DDRBYTE1/2 The Vybrid reference manual VFXXXRM Rev. 0 10/2016 states in chapter 5.2.6.1 DUMMY PADS (DDR/QuadSPI) that those pads need to be programed for correct operation of DDR. Assume the default DDR pin configuration which seems to work well on a Colibri VF50. Signed-off-by: Stefan Agner --- arch/arm/include/asm/arch-vf610/iomux-vf610.h | 2 ++ arch/arm/mach-imx/ddrmc-vf610.c | 2 ++ 2 files changed, 4 insertions(+) diff --git a/arch/arm/include/asm/arch-vf610/iomux-vf610.h b/arch/arm/include/asm/arch-vf610/iomux-vf610.h index c0eeaa7e7d..01bc2998b8 100644 --- a/arch/arm/include/asm/arch-vf610/iomux-vf610.h +++ b/arch/arm/include/asm/arch-vf610/iomux-vf610.h @@ -244,6 +244,8 @@ enum { VF610_PAD_DDR_WE__DDR_WE_B = IOMUX_PAD(0x02d0, 0x02d0, 0, __NA_, 0, VF610_DDR_PAD_CTRL), VF610_PAD_DDR_ODT1__DDR_ODT_0 = IOMUX_PAD(0x02d4, 0x02d4, 0, __NA_, 0, VF610_DDR_PAD_CTRL), VF610_PAD_DDR_ODT0__DDR_ODT_1 = IOMUX_PAD(0x02d8, 0x02d8, 0, __NA_, 0, VF610_DDR_PAD_CTRL), + VF610_PAD_DDR_DDRBYTE1__DDR_DDRBYTE1 = IOMUX_PAD(0x02dc, 0x02dc, 0, __NA_, 0, VF610_DDR_PAD_CTRL), + VF610_PAD_DDR_DDRBYTE2__DDR_DDRBYTE2 = IOMUX_PAD(0x02e0, 0x02e0, 0, __NA_, 0, VF610_DDR_PAD_CTRL), }; #endif /* __IOMUX_VF610_H__ */ diff --git a/arch/arm/mach-imx/ddrmc-vf610.c b/arch/arm/mach-imx/ddrmc-vf610.c index 3d7da1c25e..7cc8f5d2c0 100644 --- a/arch/arm/mach-imx/ddrmc-vf610.c +++ b/arch/arm/mach-imx/ddrmc-vf610.c @@ -61,6 +61,8 @@ void ddrmc_setup_iomux(const iomux_v3_cfg_t *pads, int pads_count) VF610_PAD_DDR_WE__DDR_WE_B, VF610_PAD_DDR_ODT1__DDR_ODT_0, VF610_PAD_DDR_ODT0__DDR_ODT_1, + VF610_PAD_DDR_DDRBYTE1__DDR_DDRBYTE1, + VF610_PAD_DDR_DDRBYTE2__DDR_DDRBYTE2, VF610_PAD_DDR_RESETB, }; From fb41ce0db0284e0455b062c92f8d07ad5487851c Mon Sep 17 00:00:00 2001 From: Stefan Agner Date: Tue, 4 Dec 2018 11:10:18 +0100 Subject: [PATCH 03/17] toradex: colibri_vf: fix memory initialization Commit 3f353ceccbbb ("vf610: refactor DDRMC code") changed on-die termination (ODT) values from 120 Ohm to 60 Ohm and enabled a static read/write leveling which has not been tested with this board. This commit reverts both changes and makes sure that memory gets initialized as it has been done before the mentioned commit. Fixes: 3f353ceccbbb ("vf610: refactor DDRMC code") Signed-off-by: Stefan Agner Acked-by: Max Krummenacher --- board/toradex/colibri_vf/colibri_vf.c | 10 +--------- 1 file changed, 1 insertion(+), 9 deletions(-) diff --git a/board/toradex/colibri_vf/colibri_vf.c b/board/toradex/colibri_vf/colibri_vf.c index 4db1757469..19cf748c5d 100644 --- a/board/toradex/colibri_vf/colibri_vf.c +++ b/board/toradex/colibri_vf/colibri_vf.c @@ -42,14 +42,6 @@ DECLARE_GLOBAL_DATA_PTR; #define USB_CDET_GPIO 102 static struct ddrmc_cr_setting colibri_vf_cr_settings[] = { - /* levelling */ - { DDRMC_CR97_WRLVL_EN, 97 }, - { DDRMC_CR98_WRLVL_DL_0(0), 98 }, - { DDRMC_CR99_WRLVL_DL_1(0), 99 }, - { DDRMC_CR102_RDLVL_REG_EN | DDRMC_CR102_RDLVL_GT_REGEN, 102 }, - { DDRMC_CR105_RDLVL_DL_0(0), 105 }, - { DDRMC_CR106_RDLVL_GTDL_0(4), 106 }, - { DDRMC_CR110_RDLVL_DL_1(0) | DDRMC_CR110_RDLVL_GTDL_1(4), 110 }, /* AXI */ { DDRMC_CR117_AXI0_W_PRI(0) | DDRMC_CR117_AXI0_R_PRI(0), 117 }, { DDRMC_CR118_AXI1_W_PRI(1) | DDRMC_CR118_AXI1_R_PRI(1), 118 }, @@ -88,7 +80,7 @@ static struct ddrmc_cr_setting colibri_vf_cr_settings[] = { DDRMC_CR154_PAD_ZQ_MODE(1) | DDRMC_CR154_DDR_SEL_PAD_CONTR(3) | DDRMC_CR154_PAD_ZQ_HW_FOR(1), 154 }, - { DDRMC_CR155_PAD_ODT_BYTE1(1) | DDRMC_CR155_PAD_ODT_BYTE0(1), 155 }, + { DDRMC_CR155_PAD_ODT_BYTE1(2) | DDRMC_CR155_PAD_ODT_BYTE0(2), 155 }, { DDRMC_CR158_TWR(6), 158 }, { DDRMC_CR161_ODT_EN(1) | DDRMC_CR161_TODTH_RD(2) | DDRMC_CR161_TODTH_WR(2), 161 }, From b77e368fa27631f13c06acdb0020fb64b59d4411 Mon Sep 17 00:00:00 2001 From: Stefan Agner Date: Tue, 4 Dec 2018 11:10:19 +0100 Subject: [PATCH 04/17] ARM: vf610: ddrmc: fix CR138 preprocessor define According to the data sheet bits 10-8 are PHYDRAM_CK_EN. Fix mask to allow setting PHYDRAM_CK_EN correctly. Signed-off-by: Stefan Agner Acked-by: Marcel Ziswiler Reviewed-by: Lukasz Majewski --- arch/arm/include/asm/arch-vf610/imx-regs.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/include/asm/arch-vf610/imx-regs.h b/arch/arm/include/asm/arch-vf610/imx-regs.h index 08ba8e94f8..b7374bfb8f 100644 --- a/arch/arm/include/asm/arch-vf610/imx-regs.h +++ b/arch/arm/include/asm/arch-vf610/imx-regs.h @@ -239,7 +239,7 @@ #define DDRMC_CR132_RDLAT_ADJ(v) ((v) & 0x3f) #define DDRMC_CR137_PHYCTL_DL(v) (((v) & 0xf) << 16) #define DDRMC_CR138_PHY_WRLV_MXDL(v) (((v) & 0xffff) << 16) -#define DDRMC_CR138_PHYDRAM_CK_EN(v) (((v) & 0x8) << 8) +#define DDRMC_CR138_PHYDRAM_CK_EN(v) (((v) & 0x7) << 8) #define DDRMC_CR139_PHY_WRLV_RESPLAT(v) (((v) & 0xff) << 24) #define DDRMC_CR139_PHY_WRLV_LOAD(v) (((v) & 0xff) << 16) #define DDRMC_CR139_PHY_WRLV_DLL(v) (((v) & 0xff) << 8) From 52c2c97e7c5b3ba326bae53a7940e27878efd405 Mon Sep 17 00:00:00 2001 From: Stefan Agner Date: Tue, 4 Dec 2018 11:10:20 +0100 Subject: [PATCH 05/17] ARM: vf610: ddrmc: fix initialization completion detection The CR80 register has multiple interrupt bits, the code is supposed to check bit 8 but instead uses a logical and. In most cases this probably did not affect real operations since at that stage typically none of the other bits are set. Signed-off-by: Stefan Agner Acked-by: Marcel Ziswiler --- arch/arm/include/asm/arch-vf610/imx-regs.h | 3 ++- arch/arm/mach-imx/ddrmc-vf610.c | 3 ++- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/arm/include/asm/arch-vf610/imx-regs.h b/arch/arm/include/asm/arch-vf610/imx-regs.h index b7374bfb8f..f71fbf4e73 100644 --- a/arch/arm/include/asm/arch-vf610/imx-regs.h +++ b/arch/arm/include/asm/arch-vf610/imx-regs.h @@ -200,7 +200,8 @@ #define DDRMC_CR78_Q_FULLNESS(v) (((v) & 0x7) << 24) #define DDRMC_CR78_BUR_ON_FLY_BIT(v) ((v) & 0xf) #define DDRMC_CR79_CTLUPD_AREF(v) (((v) & 0x1) << 24) -#define DDRMC_CR82_INT_MASK 0x10000000 +#define DDRMC_CR80_MC_INIT_COMPLETE (1 << 8) +#define DDRMC_CR82_INT_MASK (1 << 28) #define DDRMC_CR87_ODT_WR_MAPCS0(v) ((v) << 24) #define DDRMC_CR87_ODT_RD_MAPCS0(v) ((v) << 16) #define DDRMC_CR88_TODTL_CMD(v) (((v) & 0x1f) << 16) diff --git a/arch/arm/mach-imx/ddrmc-vf610.c b/arch/arm/mach-imx/ddrmc-vf610.c index 7cc8f5d2c0..9739738a08 100644 --- a/arch/arm/mach-imx/ddrmc-vf610.c +++ b/arch/arm/mach-imx/ddrmc-vf610.c @@ -233,6 +233,7 @@ void ddrmc_ctrl_init_ddr3(struct ddr3_jedec_timings const *timings, /* all inits done, start the DDR controller */ writel(DDRMC_CR00_DRAM_CLASS_DDR3 | DDRMC_CR00_START, &ddrmr->cr[0]); - while (!(readl(&ddrmr->cr[80]) && 0x100)) + while (!(readl(&ddrmr->cr[80]) & DDRMC_CR80_MC_INIT_COMPLETE)) udelay(10); + writel(DDRMC_CR80_MC_INIT_COMPLETE, &ddrmr->cr[81]); } From 81653478ebcce72de0daac725f5756872133cfbc Mon Sep 17 00:00:00 2001 From: Stefan Agner Date: Tue, 4 Dec 2018 11:10:21 +0100 Subject: [PATCH 06/17] ARM: vf610: ddrmc: do not write CR79 by default The current value CTLUPD_AREF(0) is the reset value of the register, so there is no need to write a value. If needed, the register can be written using board specific CR settings. Signed-off-by: Stefan Agner Acked-by: Marcel Ziswiler Reviewed-by: Lukasz Majewski --- arch/arm/mach-imx/ddrmc-vf610.c | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm/mach-imx/ddrmc-vf610.c b/arch/arm/mach-imx/ddrmc-vf610.c index 9739738a08..fa948f7812 100644 --- a/arch/arm/mach-imx/ddrmc-vf610.c +++ b/arch/arm/mach-imx/ddrmc-vf610.c @@ -190,7 +190,6 @@ void ddrmc_ctrl_init_ddr3(struct ddr3_jedec_timings const *timings, DDRMC_CR77_SWAP_EN, &ddrmr->cr[77]); writel(DDRMC_CR78_Q_FULLNESS(timings->q_fullness) | DDRMC_CR78_BUR_ON_FLY_BIT(12), &ddrmr->cr[78]); - writel(DDRMC_CR79_CTLUPD_AREF(0), &ddrmr->cr[79]); writel(DDRMC_CR82_INT_MASK, &ddrmr->cr[82]); From bf413781cfbbc3df5e154b1c00e231bc2d600550 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Fri, 7 Dec 2018 02:36:38 +0100 Subject: [PATCH 07/17] arm: mx5: Enable WDT and bootcounter on M53Menlo Enable watchdog and bootcounter support on the M53Menlo board. Signed-off-by: Marek Vasut Cc: Stefano Babic --- configs/m53menlo_defconfig | 8 ++++++++ include/configs/m53menlo.h | 3 +++ 2 files changed, 11 insertions(+) diff --git a/configs/m53menlo_defconfig b/configs/m53menlo_defconfig index dd7aed324f..5555e05030 100644 --- a/configs/m53menlo_defconfig +++ b/configs/m53menlo_defconfig @@ -20,6 +20,7 @@ CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_VERSION_VARIABLE=y CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_NAND_SUPPORT=y +CONFIG_SPL_WATCHDOG_SUPPORT=y CONFIG_HUSH_PARSER=y CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y @@ -33,6 +34,7 @@ CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_BMP=y +CONFIG_CMD_BOOTCOUNT=y CONFIG_CMD_DATE=y CONFIG_CMD_BTRFS=y CONFIG_CMD_EXT4=y @@ -44,6 +46,11 @@ CONFIG_MTDIDS_DEFAULT="nand0=mxc_nand" CONFIG_MTDPARTS_DEFAULT="mtdparts=mxc_nand:1m(u-boot),512k(env1),512k(env2),-(ubi)" CONFIG_CMD_UBI=y CONFIG_ENV_IS_IN_NAND=y +CONFIG_BOOTCOUNT_LIMIT=y +CONFIG_BOOTCOUNT_BOOTLIMIT=3 +CONFIG_SYS_BOOTCOUNT_SINGLEWORD=y +CONFIG_SYS_BOOTCOUNT_ADDR=0x53FA401C +CONFIG_SYS_BOOTCOUNT_MAGIC=0x0B01C041 CONFIG_FSL_ESDHC=y CONFIG_NAND=y CONFIG_NAND_MXC=y @@ -58,5 +65,6 @@ CONFIG_USB_ETHER_MCS7830=y CONFIG_USB_ETHER_SMSC95XX=y CONFIG_VIDEO=y # CONFIG_VIDEO_SW_CURSOR is not set +CONFIG_IMX_WATCHDOG=y CONFIG_FAT_WRITE=y CONFIG_OF_LIBFDT=y diff --git a/include/configs/m53menlo.h b/include/configs/m53menlo.h index 3fca28da6b..0e03bb31a7 100644 --- a/include/configs/m53menlo.h +++ b/include/configs/m53menlo.h @@ -157,6 +157,9 @@ /* IIM Fuses */ #define CONFIG_FSL_IIM +/* Watchdog */ +#define CONFIG_WATCHDOG_TIMEOUT_MSECS 8000 + /* * Boot Linux */ From e3bc7c668f424848c18acb664ef8b077b553697b Mon Sep 17 00:00:00 2001 From: Chris Spencer Date: Thu, 20 Dec 2018 09:25:24 +0000 Subject: [PATCH 08/17] imx: Add Makefile dependency for mkimage_fit_atf.sh The mkimage_fit_atf.sh SPL FIT generator script requires u-boot-nodtb.bin, but this was not enforced by the Makefile. This could cause the generator script to be executed before u-boot-nodtb.bin has been created. Signed-off-by: Chris Spencer Cc: NXP i.MX U-Boot Team --- Makefile | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Makefile b/Makefile index eeb299fc38..47589e47ac 100644 --- a/Makefile +++ b/Makefile @@ -1133,6 +1133,9 @@ U_BOOT_ITS = $(subst ",,$(CONFIG_SPL_FIT_SOURCE)) else ifneq ($(CONFIG_SPL_FIT_GENERATOR),"") U_BOOT_ITS := u-boot.its +ifeq ($(CONFIG_SPL_FIT_GENERATOR),"arch/arm/mach-imx/mkimage_fit_atf.sh") +U_BOOT_ITS_DEPS += u-boot-nodtb.bin +endif ifeq ($(CONFIG_SPL_FIT_GENERATOR),"arch/arm/mach-rockchip/make_fit_atf.py") U_BOOT_ITS_DEPS += u-boot endif From b82c7c32efcba76164c966733002c7c8528b005d Mon Sep 17 00:00:00 2001 From: Soeren Moch Date: Sat, 5 Jan 2019 09:31:17 +0100 Subject: [PATCH 09/17] board: tbs2910: Add u-boot.imx size limit check Check the size of the generated u-boot.imx file. Report an error if it would be too big and overwrite the u-boot environment. Signed-off-by: Soeren Moch --- include/configs/tbs2910.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/configs/tbs2910.h b/include/configs/tbs2910.h index a60223c623..2d4b9c9bfe 100644 --- a/include/configs/tbs2910.h +++ b/include/configs/tbs2910.h @@ -122,6 +122,8 @@ #define CONFIG_ENV_OFFSET (384 * 1024) #define CONFIG_ENV_OVERWRITE +#define CONFIG_BOARD_SIZE_LIMIT 392192 /* (CONFIG_ENV_OFFSET - 1024) */ + #define CONFIG_EXTRA_ENV_SETTINGS \ "bootargs_mmc1=console=ttymxc0,115200 di0_primary console=tty1\0" \ "bootargs_mmc2=video=mxcfb0:dev=hdmi,1920x1080M@60 " \ From 72bc93e1ef20cf0da31155ad164817799fe5f01b Mon Sep 17 00:00:00 2001 From: Soeren Moch Date: Sat, 5 Jan 2019 09:31:18 +0100 Subject: [PATCH 10/17] board: tbs2910: Remove FIT support in defconfig to reduce u-boot size The current defconfig build generates a u-boot.imx file that is too large for the available space on a eMMC/SD card. Installing this file overwrites the u-boot environment. So disable the unused FIT support to reduce the size of the u-boot binary. Signed-off-by: Soeren Moch --- configs/tbs2910_defconfig | 1 - 1 file changed, 1 deletion(-) diff --git a/configs/tbs2910_defconfig b/configs/tbs2910_defconfig index 55cd9bd998..fc15dcf013 100644 --- a/configs/tbs2910_defconfig +++ b/configs/tbs2910_defconfig @@ -5,7 +5,6 @@ CONFIG_SYS_TEXT_BASE=0x17800000 CONFIG_TARGET_TBS2910=y CONFIG_CMD_HDMIDETECT=y CONFIG_NR_DRAM_BANKS=1 -CONFIG_FIT=y CONFIG_BOOTDELAY=3 CONFIG_PRE_CONSOLE_BUFFER=y CONFIG_PRE_CON_BUF_ADDR=0x7c000000 From d17b0bedbfcd24dea36eb66852e6f8b2d334f729 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Sat, 15 Dec 2018 12:07:02 +0000 Subject: [PATCH 11/17] MAINTAINERS: update NXP i.MX mail list address Update NXP i.MX mail list address Signed-off-by: Peng Fan Reviewed-by: Bin Meng --- MAINTAINERS | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/MAINTAINERS b/MAINTAINERS index ae825014bd..f86fdf9c33 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -123,7 +123,7 @@ F: drivers/spi/bcmstb_spi.c ARM FREESCALE IMX M: Stefano Babic M: Fabio Estevam -R: NXP Linux Team +R: NXP i.MX U-Boot Team S: Maintained T: git git://git.denx.de/u-boot-imx.git F: arch/arm/cpu/arm1136/mx*/ From 224f745247045262f9c4ca9e379be1002204e4ea Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Sat, 15 Dec 2018 12:19:46 +0000 Subject: [PATCH 12/17] clk: imx8: fix build warning MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit When build clk driver in spl, met the warning: " drivers/clk/imx/clk-imx8.c:21:25: warning: ‘imx8_clk_names’ defined but not used [-Wunused-variable] static struct imx8_clks imx8_clk_names[] = { ^~~~~~~~~~~~~~ " Fix with wrapping the array with CONFIG_CMD_CLK. Signed-off-by: Peng Fan --- drivers/clk/imx/clk-imx8.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/clk/imx/clk-imx8.c b/drivers/clk/imx/clk-imx8.c index fcb8090d35..d03fcc2fdd 100644 --- a/drivers/clk/imx/clk-imx8.c +++ b/drivers/clk/imx/clk-imx8.c @@ -18,6 +18,7 @@ struct imx8_clks { const char *name; }; +#if CONFIG_IS_ENABLED(CMD_CLK) static struct imx8_clks imx8_clk_names[] = { { IMX8QXP_A35_DIV, "A35_DIV" }, { IMX8QXP_I2C0_CLK, "I2C0" }, @@ -39,6 +40,7 @@ static struct imx8_clks imx8_clk_names[] = { { IMX8QXP_ENET1_REF_DIV, "ENET1_REF" }, { IMX8QXP_ENET1_PTP_CLK, "ENET1_PTP" }, }; +#endif static ulong imx8_clk_get_rate(struct clk *clk) { From ecab65e4cdec0ee408ca1ac9d0b06d2793fdae91 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Sat, 15 Dec 2018 12:19:49 +0000 Subject: [PATCH 13/17] misc: imx: scu: avoid write null pointer When boot_dev is true, fill boot device. However the original logic is when boot_dev is false, fill boot device, this will trigger data abort. Also fix sc_misc_get_control when using pointer val. Signed-off-by: Peng Fan --- drivers/misc/imx8/scu_api.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/misc/imx8/scu_api.c b/drivers/misc/imx8/scu_api.c index 65080d7544..d9c4d5d784 100644 --- a/drivers/misc/imx8/scu_api.c +++ b/drivers/misc/imx8/scu_api.c @@ -169,7 +169,7 @@ int sc_misc_get_control(sc_ipc_t ipc, sc_rsrc_t resource, sc_ctrl_t ctrl, printf("%s: ctrl:%d resource:%d: res:%d\n", __func__, ctrl, resource, RPC_R8(&msg)); - if (!val) + if (val) *val = RPC_U32(&msg, 0U); return ret; @@ -194,7 +194,7 @@ void sc_misc_get_boot_dev(sc_ipc_t ipc, sc_rsrc_t *boot_dev) if (ret) printf("%s: res:%d\n", __func__, RPC_R8(&msg)); - if (!boot_dev) + if (boot_dev) *boot_dev = RPC_U16(&msg, 0U); } From 026381fc5a06cdc3e41a6bae83486be6cbaae0a9 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Sat, 15 Dec 2018 12:19:52 +0000 Subject: [PATCH 14/17] misc: imx8: scu: use platdata instead of priv data priv data has not been allocated when doing bind, so it is wrong to use dev_get_priv in bind call back. Let's switch to use platdata in the driver to fix the issue. Signed-off-by: Peng Fan Reviewed-by: Simon Glass --- drivers/misc/imx8/scu.c | 26 +++++++++++++------------- 1 file changed, 13 insertions(+), 13 deletions(-) diff --git a/drivers/misc/imx8/scu.c b/drivers/misc/imx8/scu.c index b824ac79e6..15101b3e5f 100644 --- a/drivers/misc/imx8/scu.c +++ b/drivers/misc/imx8/scu.c @@ -158,7 +158,7 @@ static int sc_ipc_write(struct mu_type *base, void *data) static int imx8_scu_call(struct udevice *dev, int no_resp, void *tx_msg, int tx_size, void *rx_msg, int rx_size) { - struct imx8_scu *priv = dev_get_priv(dev); + struct imx8_scu *plat = dev_get_platdata(dev); sc_err_t result; int ret; @@ -166,11 +166,11 @@ static int imx8_scu_call(struct udevice *dev, int no_resp, void *tx_msg, if (rx_msg && tx_msg != rx_msg) printf("tx_msg %p, rx_msg %p\n", tx_msg, rx_msg); - ret = sc_ipc_write(priv->base, tx_msg); + ret = sc_ipc_write(plat->base, tx_msg); if (ret) return ret; if (!no_resp) { - ret = sc_ipc_read(priv->base, rx_msg); + ret = sc_ipc_read(plat->base, rx_msg); if (ret) return ret; } @@ -182,24 +182,24 @@ static int imx8_scu_call(struct udevice *dev, int no_resp, void *tx_msg, static int imx8_scu_probe(struct udevice *dev) { - struct imx8_scu *priv = dev_get_priv(dev); + struct imx8_scu *plat = dev_get_platdata(dev); fdt_addr_t addr; - debug("%s(dev=%p) (priv=%p)\n", __func__, dev, priv); + debug("%s(dev=%p) (plat=%p)\n", __func__, dev, plat); addr = devfdt_get_addr(dev); if (addr == FDT_ADDR_T_NONE) return -EINVAL; - priv->base = (struct mu_type *)addr; + plat->base = (struct mu_type *)addr; /* U-Boot not enable interrupts, so need to enable RX interrupts */ - mu_hal_init(priv->base); + mu_hal_init(plat->base); gd->arch.scu_dev = dev; - device_probe(priv->clk); - device_probe(priv->pinclk); + device_probe(plat->clk); + device_probe(plat->pinclk); return 0; } @@ -211,7 +211,7 @@ static int imx8_scu_remove(struct udevice *dev) static int imx8_scu_bind(struct udevice *dev) { - struct imx8_scu *priv = dev_get_priv(dev); + struct imx8_scu *plat = dev_get_platdata(dev); int ret; struct udevice *child; int node; @@ -227,7 +227,7 @@ static int imx8_scu_bind(struct udevice *dev) if (ret) return ret; - priv->clk = child; + plat->clk = child; node = fdt_node_offset_by_compatible(gd->fdt_blob, -1, "fsl,imx8qxp-iomuxc"); @@ -238,7 +238,7 @@ static int imx8_scu_bind(struct udevice *dev) if (ret) return ret; - priv->pinclk = child; + plat->pinclk = child; return 0; } @@ -261,6 +261,6 @@ U_BOOT_DRIVER(imx8_scu) = { .bind = imx8_scu_bind, .remove = imx8_scu_remove, .ops = &imx8_scu_ops, - .priv_auto_alloc_size = sizeof(struct imx8_scu), + .platdata_auto_alloc_size = sizeof(struct imx8_scu), .flags = DM_FLAG_PRE_RELOC, }; From da72574b217d9a7c91371209ba47c2b69502c313 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Sat, 15 Dec 2018 12:19:55 +0000 Subject: [PATCH 15/17] imx8: cpu: correct info The CPU banner printed is as following: CPU: CPU: Freescale i.MX8QXP RevB A35 at 147228 MHz 1. Drop the CPU: 2. Change vendor from Freescale to NXP Signed-off-by: Peng Fan --- arch/arm/mach-imx/imx8/cpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-imx/imx8/cpu.c b/arch/arm/mach-imx/imx8/cpu.c index f093f34ca5..7599afe720 100644 --- a/arch/arm/mach-imx/imx8/cpu.c +++ b/arch/arm/mach-imx/imx8/cpu.c @@ -573,7 +573,7 @@ int cpu_imx_get_desc(struct udevice *dev, char *buf, int size) if (size < 100) return -ENOSPC; - snprintf(buf, size, "CPU: Freescale i.MX8%s Rev%s %s at %u MHz\n", + snprintf(buf, size, "NXP i.MX8%s Rev%s %s at %u MHz\n", plat->type, plat->rev, plat->name, plat->freq_mhz); return 0; From f7e475db4011d18b4ae974154eb022c3af6a4d16 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Sat, 15 Dec 2018 12:19:58 +0000 Subject: [PATCH 16/17] tools: imx8image: set dcd_skip to true To B0[+] chips, dcd_skip needs to be true. For A0 chip, it needs to be false, however A0 chip is no longer being supported anymore. Considering we are moving code from imx-mkimage to uboot mkimage, to make sure we not introduce some surprise, we still keep dcd_skip code there. Signed-off-by: Peng Fan --- tools/imx8image.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/imx8image.c b/tools/imx8image.c index 6e8ac464e7..0d856b9d94 100644 --- a/tools/imx8image.c +++ b/tools/imx8image.c @@ -968,7 +968,7 @@ int imx8image_copy_image(int outfd, struct image_tool_params *mparams) fprintf(stdout, "CONTAINER SW VERSION:\t0x%04x\n", sw_version); build_container(soc, sector_size, emmc_fastboot, - img_sp, false, fuse_version, sw_version, outfd); + img_sp, true, fuse_version, sw_version, outfd); return 0; } From d4a0c098925d4594355506a12ae0dbbe6eed00f2 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Fri, 28 Dec 2018 16:43:01 -0200 Subject: [PATCH 17/17] imx8m: clock: Fix oscillator values OSC_27M_CLK should return 27MHz and OSC_32K_CLK should return 32768Hz to reflect the reality. This also keeps the values in sync with the Linux clock tree. Signed-off-by: Fabio Estevam --- arch/arm/mach-imx/imx8m/clock.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-imx/imx8m/clock.c b/arch/arm/mach-imx/imx8m/clock.c index 3766d988ba..289b9417aa 100644 --- a/arch/arm/mach-imx/imx8m/clock.c +++ b/arch/arm/mach-imx/imx8m/clock.c @@ -250,9 +250,9 @@ static u32 get_root_src_clk(enum clk_root_src root_src) case OSC_25M_CLK: return 25000000; case OSC_27M_CLK: - return 25000000; + return 27000000; case OSC_32K_CLK: - return 32000; + return 32768; case ARM_PLL_CLK: return decode_frac_pll(root_src); case SYSTEM_PLL1_800M_CLK: