leandrof/u-boot
1
0
Fork 1
Code Issues Pull Requests Packages Projects Releases Wiki Activity

ARM: DRA7: Add ABB setup for all domains

Browse Source 
ABB should be initialized for all required domains voltage domain
for DRA7: IVA, GPU, EVE in addition to the existing MPU domain. If
we do not do this, kernel configuring just the frequency using the
default boot loader configured voltage can fail on many corner lot
units and has been hard to debug. This specifically is a concern with
DRA7 generation of SoCs since other than VDD_MPU, all other domains
are only permitted to setup the voltages to required OPP only at boot.

Reported-by: Richard Woodruff <r-woodruff2@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
This commit is contained in:
Nishanth Menon
2016-04-21 14:34:25 -05:00
committed by Tom Rini
parent a818097a33
commit e52e334e5c
6 changed files with 55 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

24
arch/arm/cpu/armv7/omap-common/clocks-common.c
View File

@@ -596,10 +596,34 @@ void scale_vcores(struct vcores_data const *vcores)
debug("gpu: %d\n", vcores->gpu.value);
do_scale_vcore(vcores->gpu.addr, vcores->gpu.value, vcores->gpu.pmic);
/* Configure GPU ABB LDO after scale */
abb_setup(vcores->gpu.efuse.reg,
(*ctrl)->control_wkup_ldovbb_gpu_voltage_ctrl,
(*prcm)->prm_abbldo_gpu_setup,
(*prcm)->prm_abbldo_gpu_ctrl,
(*prcm)->prm_irqstatus_mpu,
vcores->gpu.abb_tx_done_mask,
OMAP_ABB_FAST_OPP);
debug("eve: %d\n", vcores->eve.value);
do_scale_vcore(vcores->eve.addr, vcores->eve.value, vcores->eve.pmic);
/* Configure EVE ABB LDO after scale */
abb_setup(vcores->eve.efuse.reg,
(*ctrl)->control_wkup_ldovbb_eve_voltage_ctrl,
(*prcm)->prm_abbldo_eve_setup,
(*prcm)->prm_abbldo_eve_ctrl,
(*prcm)->prm_irqstatus_mpu,
vcores->eve.abb_tx_done_mask,
OMAP_ABB_FAST_OPP);
debug("iva: %d\n", vcores->iva.value);
do_scale_vcore(vcores->iva.addr, vcores->iva.value, vcores->iva.pmic);
/* Configure IVA ABB LDO after scale */
abb_setup(vcores->iva.efuse.reg,
(*ctrl)->control_wkup_ldovbb_iva_voltage_ctrl,
(*prcm)->prm_abbldo_iva_setup,
(*prcm)->prm_abbldo_iva_ctrl,
(*prcm)->prm_irqstatus_mpu,
vcores->iva.abb_tx_done_mask,
OMAP_ABB_FAST_OPP);
/* Might need udelay(1000) here if debug is enabled to see all prints */
#else
u32 val;

6
arch/arm/cpu/armv7/omap5/hw_data.c
View File

@@ -377,12 +377,14 @@ struct vcores_data dra752_volts = {
.eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.eve.addr = TPS659038_REG_ADDR_SMPS45,
.eve.pmic = &tps659038,
.eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
.gpu.value = VDD_GPU_DRA752,
.gpu.efuse.reg = STD_FUSE_OPP_VMIN_GPU_NOM,
.gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.gpu.addr = TPS659038_REG_ADDR_SMPS6,
.gpu.pmic = &tps659038,
.gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
.core.value = VDD_CORE_DRA752,
.core.efuse.reg = STD_FUSE_OPP_VMIN_CORE_NOM,
@@ -395,6 +397,7 @@ struct vcores_data dra752_volts = {
.iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.iva.addr = TPS659038_REG_ADDR_SMPS8,
.iva.pmic = &tps659038,
.iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK,
};
struct vcores_data dra722_volts = {
@@ -420,18 +423,21 @@ struct vcores_data dra722_volts = {
.gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.gpu.addr = TPS65917_REG_ADDR_SMPS3,
.gpu.pmic = &tps659038,
.gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
.eve.value = VDD_EVE_DRA72x,
.eve.efuse.reg = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
.eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.eve.addr = TPS65917_REG_ADDR_SMPS3,
.eve.pmic = &tps659038,
.eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
.iva.value = VDD_IVA_DRA72x,
.iva.efuse.reg = STD_FUSE_OPP_VMIN_IVA_NOM,
.iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.iva.addr = TPS65917_REG_ADDR_SMPS3,
.iva.pmic = &tps659038,
.iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK,
};
/*

10
arch/arm/cpu/armv7/omap5/prcm-regs.c
View File

@@ -446,6 +446,9 @@ struct omap_sys_ctrl_regs const dra7xx_ctrl = {
.control_emif1_sdram_config_ext = 0x4AE0C144,
.control_emif2_sdram_config_ext = 0x4AE0C148,
.control_wkup_ldovbb_mpu_voltage_ctrl = 0x4AE0C158,
.control_wkup_ldovbb_iva_voltage_ctrl = 0x4A002470,
.control_wkup_ldovbb_eve_voltage_ctrl = 0x4A00246C,
.control_wkup_ldovbb_gpu_voltage_ctrl = 0x4AE0C154,
.control_std_fuse_die_id_0 = 0x4AE0C200,
.control_std_fuse_die_id_1 = 0x4AE0C208,
.control_std_fuse_die_id_2 = 0x4AE0C20C,
@@ -831,6 +834,7 @@ struct prcm_regs const dra7xx_prcm = {
.cm_ipu_i2c5_clkctrl = 0x4a005578,
/* prm irqstatus regs */
.prm_irqstatus_mpu = 0x4ae06010,
.prm_irqstatus_mpu_2 = 0x4ae06014,
/* cm2.ckgen */
@@ -999,6 +1003,12 @@ struct prcm_regs const dra7xx_prcm = {
.prm_abbldo_mpu_setup = 0x4AE07DDC,
.prm_abbldo_mpu_ctrl = 0x4AE07DE0,
.prm_abbldo_iva_setup = 0x4AE07E34,
.prm_abbldo_iva_ctrl = 0x4AE07E24,
.prm_abbldo_eve_setup = 0x4AE07E30,
.prm_abbldo_eve_ctrl = 0x4AE07E20,
.prm_abbldo_gpu_setup = 0x4AE07DE4,
.prm_abbldo_gpu_ctrl = 0x4AE07DE8,
/*l3main1 edma*/
.cm_l3main1_tptc1_clkctrl = 0x4a008778,