Merge https://source.denx.de/u-boot/custodians/u-boot-marvell

- mrvl_uart.sh: Remove script (Pali)
- Fix Espressobin build for configs where ENV is not in SPI (Rogier)
- mvebu: a37xx: Add support for reading OTP (Pali)
- mvebu: uDPU: Ethernet fixes and misc DT and defconfig changes (Robert)
- mvebu: Add support for reading LD0 and LD1 eFuse (Pali)
- kwboot: Replace fstat()+st_size by lseek()+SEEK_END (Pali)
- mvebu: turris_omnia: Enable CONFIG_CMD_FUSE (Pali)
- arm: Add CONFIG_SPL_SYS_NO_VECTOR_TABLE used on 32bit MVEBU (Pali)
- mvebu: a37xx: Add support for writing Security OTP values (Pali)
- mvebu: turris: Misc enhancements and cleanups / fixes (Pali)
- Sheevaplug : Use Marvell uclass mvgbe and PHY driver for Ethernet (Tony)

arch/arm/Kconfig

@@ -58,6 +58,10 @@ config SYS_INIT_SP_BSS_OFFSET
 	  that the early malloc region, global data (gd), and early stack usage
 	  do not overlap any appended DTB.
 
+config SPL_SYS_NO_VECTOR_TABLE
+	depends on SPL
+	bool
+
 config LINUX_KERNEL_IMAGE_HEADER
 	depends on ARM64
 	bool

arch/arm/cpu/armv7/start.S

@@ -97,12 +97,10 @@ switch_to_hypervisor_ret:
 	orr	r0, r0, #0xc0		@ disable FIQ and IRQ
 	msr	cpsr,r0
 
+#if !CONFIG_IS_ENABLED(SYS_NO_VECTOR_TABLE)
 /*
  * Setup vector:
- * (OMAP4 spl TEXT_BASE is not 32 byte aligned.
- * Continue to use ROM code vector only in OMAP4 spl)
  */
-#if !(defined(CONFIG_OMAP44XX) && defined(CONFIG_SPL_BUILD))
 	/* Set V=0 in CP15 SCTLR register - for VBAR to point to vector */
 	mrc	p15, 0, r0, c1, c0, 0	@ Read CP15 SCTLR Register
 	bic	r0, #CR_V		@ V = 0

arch/arm/dts/armada-3720-uDPU-u-boot.dtsi

@@ -31,3 +31,27 @@
 &sdhci0 {
 	u-boot,dm-pre-reloc;
 };
+
+&pinctrl_sb {
+	sfp_pin: sfp-pin {
+		groups = "pcie1_clkreq";
+		function = "gpio";
+	};
+};
+
+&eth0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&sfp_pin>;
+
+	fixed-link {
+		speed = <1000>;
+		full-duplex;
+	};
+};
+
+&eth1 {
+	fixed-link {
+		speed = <1000>;
+		full-duplex;
+	};
+};

arch/arm/dts/armada-3720-uDPU.dts

@@ -99,7 +99,7 @@
 	pinctrl-names = "default";
 	pinctrl-0 = <&spi_quad_pins>;
 
-	m25p80@0 {
+	spi-flash@0 {
 		compatible = "jedec,spi-nor";
 		reg = <0>;
 		spi-max-frequency = <54000000>;
@@ -108,10 +108,15 @@
 			compatible = "fixed-partitions";
 			#address-cells = <1>;
 			#size-cells = <1>;
-			/* only bootloader is located on the SPI */
+
 			partition@0 {
-				label = "uboot";
+				label = "firmware";
-				reg = <0 0x400000>;
+				reg = <0x0 0x180000>;
+			};
+
+			partition@180000 {
+				label = "u-boot-env";
+				reg = <0x180000 0x10000>;
 			};
 		};
 	};
@@ -148,15 +153,15 @@
 	scl-gpios = <&gpionb 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 	sda-gpios = <&gpionb 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 
-	lm75@48 {
+	nct375@48 {
 		status = "okay";
-		compatible = "lm75";
+		compatible = "ti,tmp75c";
 		reg = <0x48>;
 	};
 
-	lm75@49 {
+	nct375@49 {
 		status = "okay";
-		compatible = "lm75";
+		compatible = "ti,tmp75c";
 		reg = <0x49>;
 	};
 };

arch/arm/dts/armada-385-turris-omnia-u-boot.dtsi

@@ -29,7 +29,7 @@
 			u-boot,dm-pre-reloc;
 
 			/* ATSHA204A at address 0x64 */
-			atsha204a@64 {
+			crypto@64 {
 				u-boot,dm-pre-reloc;
 				compatible = "atmel,atsha204a";
 				reg = <0x64>;
@@ -38,6 +38,7 @@
 	};
 };
 
+#ifdef CONFIG_ENV_IS_IN_SPI_FLASH
 &spi0 {
 	u-boot,dm-pre-reloc;
 
@@ -56,6 +57,7 @@
 		};
 	};
 };
+#endif
 
 &uart0 {
 	u-boot,dm-pre-reloc;

arch/arm/lib/vectors.S

@@ -24,6 +24,7 @@
 #else
 	b	reset
 #endif
+#if !CONFIG_IS_ENABLED(SYS_NO_VECTOR_TABLE)
 	ldr	pc, _undefined_instruction
 	ldr	pc, _software_interrupt
 	ldr	pc, _prefetch_abort
@@ -31,6 +32,7 @@
 	ldr	pc, _not_used
 	ldr	pc, _irq
 	ldr	pc, _fiq
+#endif
 	.endm
 
 
@@ -87,6 +89,7 @@ _start:
 	ARM_VECTORS
 #endif /* !defined(CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK) */
 
+#if !CONFIG_IS_ENABLED(SYS_NO_VECTOR_TABLE)
 /*
  *************************************************************************
  *
@@ -118,6 +121,7 @@ _irq:			.word irq
 _fiq:			.word fiq
 
 	.balignl 16,0xdeadbeef
+#endif
 
 /*
  *************************************************************************
@@ -131,6 +135,7 @@ _fiq:			.word fiq
 
 #ifdef CONFIG_SPL_BUILD
 
+#if !CONFIG_IS_ENABLED(SYS_NO_VECTOR_TABLE)
 	.align	5
 undefined_instruction:
 software_interrupt:
@@ -141,6 +146,7 @@ irq:
 fiq:
 1:
 	b	1b			/* hang and never return */
+#endif
 
 #else	/* !CONFIG_SPL_BUILD */
 

arch/arm/mach-mvebu/Kconfig

@@ -15,6 +15,7 @@ config ARMADA_32BIT
 	select SPL_SIMPLE_BUS if SPL
 	select SUPPORT_SPL
 	select TRANSLATION_OFFSET
+	select SPL_SYS_NO_VECTOR_TABLE if SPL
 
 config ARMADA_64BIT
 	bool
@@ -44,6 +45,7 @@ config ARMADA_XP
 config ARMADA_3700
 	bool
 	select ARM64
+	select HAVE_MVEBU_EFUSE
 
 # Armada 7K and 8K are very similar - use only one Kconfig symbol for both
 config ARMADA_8K

arch/arm/mach-mvebu/Makefile

@@ -27,7 +27,10 @@ obj-$(CONFIG_ARMADA_375) += ../../../drivers/ddr/marvell/axp/xor.o
 obj-$(CONFIG_ARMADA_38X) += ../../../drivers/ddr/marvell/a38x/xor.o
 obj-$(CONFIG_ARMADA_XP) += ../../../drivers/ddr/marvell/axp/xor.o
 obj-$(CONFIG_ARMADA_MSYS) += ../../../drivers/ddr/marvell/axp/xor.o
+
+ifdef CONFIG_ARMADA_38X
 obj-$(CONFIG_MVEBU_EFUSE) += efuse.o
+endif
 
 extra-y += kwbimage.cfg
 

arch/arm/mach-mvebu/armada3700/Makefile

@@ -2,4 +2,5 @@
 #
 # Copyright (C) 2016 Stefan Roese <sr@denx.de>
 
-obj-y = cpu.o
+obj-y = cpu.o mbox.o
+obj-$(CONFIG_MVEBU_EFUSE) += efuse.o

arch/arm/mach-mvebu/armada3700/efuse.c

@@ -0,0 +1,217 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) 2017 Marvell International Ltd.
+ * (C) 2021 Pali Rohár <pali@kernel.org>
+ */
+
+#include <config.h>
+#include <common.h>
+#include <asm/io.h>
+#include <linux/delay.h>
+#include <mach/mbox.h>
+#include <mach/soc.h>
+
+#define OTP_NB_REG_BASE		((void __iomem *)MVEBU_REGISTER(0x12600))
+#define OTP_SB_REG_BASE		((void __iomem *)MVEBU_REGISTER(0x1A200))
+
+#define OTP_CONTROL_OFF		0x00
+#define   OTP_MODE_BIT		BIT(15)
+#define   OTP_RPTR_RST_BIT	BIT(14)
+#define   OTP_POR_B_BIT		BIT(13)
+#define   OTP_PRDT_BIT		BIT(3)
+#define OTP_READ_PORT_OFF	0x04
+#define OTP_READ_POINTER_OFF	0x08
+#define   OTP_PTR_INC_BIT	BIT(8)
+
+static void otp_read_parallel(void __iomem *base, u32 *data, u32 count)
+{
+	u32 regval;
+
+	/* 1. Clear OTP_MODE_NB to parallel mode */
+	regval = readl(base + OTP_CONTROL_OFF);
+	regval &= ~OTP_MODE_BIT;
+	writel(regval, base + OTP_CONTROL_OFF);
+
+	/* 2. Set OTP_POR_B_NB enter normal operation */
+	regval = readl(base + OTP_CONTROL_OFF);
+	regval |= OTP_POR_B_BIT;
+	writel(regval, base + OTP_CONTROL_OFF);
+
+	/* 3. Set OTP_PTR_INC_NB to auto-increment pointer after each read */
+	regval = readl(base + OTP_READ_POINTER_OFF);
+	regval |= OTP_PTR_INC_BIT;
+	writel(regval, base + OTP_READ_POINTER_OFF);
+
+	/* 4. Set OTP_RPTR_RST_NB, then clear the same field */
+	regval = readl(base + OTP_CONTROL_OFF);
+	regval |= OTP_RPTR_RST_BIT;
+	writel(regval, base + OTP_CONTROL_OFF);
+
+	regval = readl(base + OTP_CONTROL_OFF);
+	regval &= ~OTP_RPTR_RST_BIT;
+	writel(regval, base + OTP_CONTROL_OFF);
+
+	/* 5. Toggle OTP_PRDT_NB
+	 * a. Set OTP_PRDT_NB to 1.
+	 * b. Clear OTP_PRDT_NB to 0.
+	 * c. Wait for a minimum of 100 ns.
+	 * d. Set OTP_PRDT_NB to 1
+	 */
+	regval = readl(base + OTP_CONTROL_OFF);
+	regval |= OTP_PRDT_BIT;
+	writel(regval, base + OTP_CONTROL_OFF);
+
+	regval = readl(base + OTP_CONTROL_OFF);
+	regval &= ~OTP_PRDT_BIT;
+	writel(regval, base + OTP_CONTROL_OFF);
+
+	ndelay(100);
+
+	regval = readl(base + OTP_CONTROL_OFF);
+	regval |= OTP_PRDT_BIT;
+	writel(regval, base + OTP_CONTROL_OFF);
+
+	while (count-- > 0) {
+		/* 6. Read the content of OTP 32-bits at a time */
+		ndelay(100000);
+		*(data++) = readl(base + OTP_READ_PORT_OFF);
+	}
+}
+
+static int rwtm_otp_read(u8 row, u32 word, u32 *data)
+{
+	u32 out[3];
+	u32 in[2];
+	int res = -EINVAL;
+
+	if (word < 2) {
+		/*
+		 * MBOX_CMD_OTP_READ_32B command is supported by Marvell
+		 * fuse.bin firmware and also by new CZ.NIC wtmi firmware.
+		 * This command returns raw bits without ECC corrections.
+		 * It does not provide access to the lock bit.
+		 */
+		in[0] = row;
+		in[1] = word * 32;
+		res = mbox_do_cmd(MBOX_CMD_OTP_READ_32B, in, 2, out, 1);
+		if (!res)
+			*data = out[0];
+	} else if (word == 2) {
+		/*
+		 * MBOX_CMD_OTP_READ command is supported only by new CZ.NIC
+		 * wtmi firmware and provides access to all bits, including
+		 * lock bit without doing ECC corrections. For compatibility
+		 * with Marvell fuse.bin firmware, use this command only for
+		 * accessing lock bit.
+		 */
+		in[0] = row;
+		res = mbox_do_cmd(MBOX_CMD_OTP_READ, in, 1, out, 3);
+		if (!res)
+			*data = out[2];
+	}
+
+	return res;
+}
+
+static int rwtm_otp_write(u8 row, u32 word, u32 data)
+{
+	u32 in[4];
+	int res = -EINVAL;
+
+	if (word < 2) {
+		/*
+		 * MBOX_CMD_OTP_WRITE_32B command is supported by Marvell
+		 * fuse.bin firmware and also by new CZ.NIC wtmi firmware.
+		 * This command writes only selected bits to OTP and does
+		 * not calculate ECC bits. It does not allow to write the
+		 * lock bit.
+		 */
+		in[0] = row;
+		in[1] = word * 32;
+		in[2] = data;
+		res = mbox_do_cmd(MBOX_CMD_OTP_WRITE_32B, in, 3, NULL, 0);
+	} else if (word == 2 && !(data & ~0x1)) {
+		/*
+		 * MBOX_CMD_OTP_WRITE command is supported only by new CZ.NIC
+		 * wtmi firmware and allows to write any bit to OTP, including
+		 * the lock bit. It does not calculate or write ECC bits too.
+		 * For compatibility with Marvell fuse.bin firmware, use this
+		 * command only for writing the lock bit.
+		 */
+		in[0] = row;
+		in[1] = 0;
+		in[2] = 0;
+		in[3] = data;
+		res = mbox_do_cmd(MBOX_CMD_OTP_WRITE, in, 4, NULL, 0);
+	}
+
+	return res;
+}
+
+/*
+ * Banks 0-43 are used for accessing Security OTP (44 rows with 67 bits via 44 banks and words 0-2)
+ * Bank 44 is used for accessing North Bridge OTP (69 bits via words 0-2)
+ * Bank 45 is used for accessing South Bridge OTP (97 bits via words 0-3)
+ */
+
+#define RWTM_ROWS	44
+#define RWTM_MAX_BANK	(RWTM_ROWS - 1)
+#define RWTM_ROW_WORDS	3
+#define OTP_NB_BANK	RWTM_ROWS
+#define OTP_NB_WORDS	3
+#define OTP_SB_BANK	(RWTM_ROWS + 1)
+#define OTP_SB_WORDS	4
+
+int fuse_read(u32 bank, u32 word, u32 *val)
+{
+	if (bank <= RWTM_MAX_BANK) {
+		if (word >= RWTM_ROW_WORDS)
+			return -EINVAL;
+		return rwtm_otp_read(bank, word, val);
+	} else if (bank == OTP_NB_BANK) {
+		u32 data[OTP_NB_WORDS];
+		if (word >= OTP_NB_WORDS)
+			return -EINVAL;
+		otp_read_parallel(OTP_NB_REG_BASE, data, OTP_NB_WORDS);
+		*val = data[word];
+		return 0;
+	} else if (bank == OTP_SB_BANK) {
+		u32 data[OTP_SB_WORDS];
+		if (word >= OTP_SB_WORDS)
+			return -EINVAL;
+		otp_read_parallel(OTP_SB_REG_BASE, data, OTP_SB_WORDS);
+		*val = data[word];
+		return 0;
+	} else {
+		return -EINVAL;
+	}
+}
+
+int fuse_prog(u32 bank, u32 word, u32 val)
+{
+	if (bank <= RWTM_MAX_BANK) {
+		if (word >= RWTM_ROW_WORDS)
+			return -EINVAL;
+		return rwtm_otp_write(bank, word, val);
+	} else if (bank == OTP_NB_BANK) {
+		/* TODO: not implemented yet */
+		return -ENOSYS;
+	} else if (bank == OTP_SB_BANK) {
+		/* TODO: not implemented yet */
+		return -ENOSYS;
+	} else {
+		return -EINVAL;
+	}
+}
+
+int fuse_sense(u32 bank, u32 word, u32 *val)
+{
+	/* not supported */
+	return -ENOSYS;
+}
+
+int fuse_override(u32 bank, u32 word, u32 val)
+{
+	/* not supported */
+	return -ENOSYS;
+}

arch/arm/mach-mvebu/armada3700/mbox.c

@@ -0,0 +1,83 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Marek Behun <marek.behun@nic.cz>
+ * Copyright (C) 2021 Pali Rohár <pali@kernel.org>
+ */
+
+#include <common.h>
+#include <asm/arch/soc.h>
+#include <asm/io.h>
+#include <linux/bitops.h>
+#include <linux/delay.h>
+#include <mach/mbox.h>
+
+#define RWTM_BASE		(MVEBU_REGISTER(0xb0000))
+#define RWTM_CMD_PARAM(i)	(size_t)(RWTM_BASE + (i) * 4)
+#define RWTM_CMD		(RWTM_BASE + 0x40)
+#define RWTM_CMD_RETSTATUS	(RWTM_BASE + 0x80)
+#define RWTM_CMD_STATUS(i)	(size_t)(RWTM_BASE + 0x84 + (i) * 4)
+#define MAX_ARGS		16
+
+#define RWTM_HOST_INT_RESET	(RWTM_BASE + 0xc8)
+#define RWTM_HOST_INT_MASK	(RWTM_BASE + 0xcc)
+#define SP_CMD_COMPLETE		BIT(0)
+
+#define MBOX_STS_SUCCESS		(0x0 << 30)
+#define MBOX_STS_FAIL			(0x1 << 30)
+#define MBOX_STS_BADCMD			(0x2 << 30)
+#define MBOX_STS_LATER			(0x3 << 30)
+#define MBOX_STS_ERROR(s)		((s) & (3 << 30))
+#define MBOX_STS_VALUE(s)		(((s) >> 10) & 0xfffff)
+#define MBOX_STS_CMD(s)			((s) & 0x3ff)
+#define MBOX_STS_MARVELL_ERROR(s)	((s) == 0 ? 0         : \
+					 (s) == 2 ? ETIMEDOUT : \
+					 (s) == 3 ? EINVAL    : \
+					 (s) == 4 ? ENOSYS    : \
+					            EIO)
+
+int mbox_do_cmd(enum mbox_cmd cmd, u32 *in, int nin, u32 *out, int nout)
+{
+	const int tries = 50;
+	int i;
+	u32 status;
+
+	if (nin > MAX_ARGS || nout > MAX_ARGS)
+		return -EINVAL;
+
+	clrbits_le32(RWTM_HOST_INT_MASK, SP_CMD_COMPLETE);
+
+	for (i = 0; i < nin; i++)
+		writel(in[i], RWTM_CMD_PARAM(i));
+	for (; i < MAX_ARGS; i++)
+		writel(0x0, RWTM_CMD_PARAM(i));
+	writel(cmd, RWTM_CMD);
+
+	for (i = 0; i < tries; ++i) {
+		mdelay(10);
+		if (readl(RWTM_HOST_INT_RESET) & SP_CMD_COMPLETE)
+			break;
+	}
+
+	if (i == tries) {
+		/* if timed out, don't read status */
+		setbits_le32(RWTM_HOST_INT_RESET, SP_CMD_COMPLETE);
+		return -ETIMEDOUT;
+	}
+
+	for (i = 0; i < nout; ++i)
+		out[i] = readl(RWTM_CMD_STATUS(i));
+	status = readl(RWTM_CMD_RETSTATUS);
+
+	setbits_le32(RWTM_HOST_INT_RESET, SP_CMD_COMPLETE);
+
+	if (MBOX_STS_CMD(status) != cmd)
+		return -MBOX_STS_MARVELL_ERROR(status);
+	else if (MBOX_STS_ERROR(status) == MBOX_STS_FAIL)
+		return -(int)MBOX_STS_VALUE(status);
+	else if (MBOX_STS_ERROR(status) == MBOX_STS_BADCMD)
+		return -ENOSYS;
+	else if (MBOX_STS_ERROR(status) != MBOX_STS_SUCCESS)
+		return -EIO;
+	else
+		return MBOX_STS_VALUE(status);
+}

arch/arm/mach-mvebu/efuse.c

@@ -27,6 +27,7 @@
 
 enum {
 	MVEBU_EFUSE_CTRL_PROGRAM_ENABLE = (1 << 31),
+	MVEBU_EFUSE_LD1_SELECT          = (1 <<  6),
 };
 
 struct mvebu_hd_efuse {
@@ -39,8 +40,10 @@ struct mvebu_hd_efuse {
 #ifndef DRY_RUN
 static struct mvebu_hd_efuse *efuses =
 	(struct mvebu_hd_efuse *)(MBUS_EFUSE_BASE + 0xF9000);
+static u32 *ld_efuses = (void *)MBUS_EFUSE_BASE + 0xF8F00;
 #else
 static struct mvebu_hd_efuse efuses[EFUSE_LINE_MAX + 1];
+static u32 ld_efuses[EFUSE_LD_WORDS];
 #endif
 
 static int efuse_initialised;
@@ -169,6 +172,21 @@ int mvebu_read_efuse(int nr, struct efuse_val *val)
 	return 0;
 }
 
+void mvebu_read_ld_efuse(int ld1, u32 *line)
+{
+	int i;
+
+#ifndef DRY_RUN
+	if (ld1)
+		setbits_le32(MVEBU_EFUSE_CONTROL, MVEBU_EFUSE_LD1_SELECT);
+	else
+		clrbits_le32(MVEBU_EFUSE_CONTROL, MVEBU_EFUSE_LD1_SELECT);
+#endif
+
+	for (i = 0; i < EFUSE_LD_WORDS; i++)
+		line[i] = readl(ld_efuses + i);
+}
+
 int mvebu_write_efuse(int nr, struct efuse_val *val)
 {
 	return prog_efuse(nr, val, ~0, ~0);
@@ -199,8 +217,18 @@ static int valid_prog_words;
 int fuse_read(u32 bank, u32 word, u32 *val)
 {
 	struct efuse_val fuse_line;
+	u32 ld_line[EFUSE_LD_WORDS];
 	int res;
 
+	if ((bank == EFUSE_LD0_LINE || bank == EFUSE_LD1_LINE) && word < EFUSE_LD_WORDS) {
+		res = mvebu_efuse_init_hw();
+		if (res)
+			return res;
+		mvebu_read_ld_efuse(bank == EFUSE_LD1_LINE, ld_line);
+		*val = ld_line[word];
+		return 0;
+	}
+
 	if (bank < EFUSE_LINE_MIN || bank > EFUSE_LINE_MAX || word > 2)
 		return -EINVAL;
 

arch/arm/mach-mvebu/include/mach/efuse.h

@@ -53,8 +53,13 @@ enum efuse_line {
 
 	EFUSE_LINE_MIN = 0,
 	EFUSE_LINE_MAX = 63,
+
+	EFUSE_LD0_LINE = 64,
+	EFUSE_LD1_LINE = 65,
 };
 
+#define EFUSE_LD_WORDS 9
+
 #endif
 
 int mvebu_efuse_init_hw(void);

arch/arm/mach-mvebu/include/mach/mbox.h

@@ -0,0 +1,40 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2018 Marek Behun <marek.behun@nic.cz>
+ * Copyright (C) 2021 Pali Rohár <pali@kernel.org>
+ */
+
+#ifndef _MVEBU_MBOX_H
+#define _MVEBU_MBOX_H
+
+enum mbox_cmd {
+	MBOX_CMD_GET_RANDOM	= 1,
+	MBOX_CMD_BOARD_INFO,
+	MBOX_CMD_ECDSA_PUB_KEY,
+	MBOX_CMD_HASH,
+	MBOX_CMD_SIGN,
+	MBOX_CMD_VERIFY,
+
+	MBOX_CMD_OTP_READ,
+	MBOX_CMD_OTP_WRITE,
+
+	MBOX_CMD_REBOOT,
+
+	/* OTP read commands supported by Marvell fuse.bin firmware */
+	MBOX_CMD_OTP_READ_1B	= 257,
+	MBOX_CMD_OTP_READ_8B,
+	MBOX_CMD_OTP_READ_32B,
+	MBOX_CMD_OTP_READ_64B,
+	MBOX_CMD_OTP_READ_256B,
+
+	/* OTP write commands supported by Marvell fuse.bin firmware */
+	MBOX_CMD_OTP_WRITE_1B	= 513,
+	MBOX_CMD_OTP_WRITE_8B,
+	MBOX_CMD_OTP_WRITE_32B,
+	MBOX_CMD_OTP_WRITE_64B,
+	MBOX_CMD_OTP_WRITE_256B,
+};
+
+int mbox_do_cmd(enum mbox_cmd cmd, u32 *in, int nin, u32 *out, int nout);
+
+#endif

arch/arm/mach-omap2/Kconfig

@@ -32,6 +32,7 @@ config OMAP34XX
 config OMAP44XX
 	bool "OMAP44XX SoC"
 	select SPL_USE_TINY_PRINTF
+	select SPL_SYS_NO_VECTOR_TABLE if SPL
 	imply NAND_OMAP_ELM
 	imply NAND_OMAP_GPMC
 	imply SPL_DISPLAY_PRINT

board/CZ.NIC/turris_atsha_otp.c

@@ -0,0 +1,119 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2017 Marek Behun <marek.behun@nic.cz>
+ * Copyright (C) 2016 Tomas Hlavacek <tomas.hlavacek@nic.cz>
+ */
+
+#include <env.h>
+#include <net.h>
+#include <dm/uclass.h>
+#include <atsha204a-i2c.h>
+
+#include "turris_atsha_otp.h"
+
+#define TURRIS_ATSHA_OTP_VERSION	0
+#define TURRIS_ATSHA_OTP_SERIAL		1
+#define TURRIS_ATSHA_OTP_MAC0		3
+#define TURRIS_ATSHA_OTP_MAC1		4
+
+static struct udevice *get_atsha204a_dev(void)
+{
+	/* Cannot be static because BSS does not have to be ready at this early stage */
+	struct udevice *dev;
+
+	if (uclass_get_device_by_name(UCLASS_MISC, "crypto@64", &dev)) {
+		puts("Cannot find ATSHA204A on I2C bus!\n");
+		dev = NULL;
+	}
+
+	return dev;
+}
+
+static void increment_mac(u8 *mac)
+{
+	int i;
+
+	for (i = 5; i >= 3; i--) {
+		mac[i] += 1;
+		if (mac[i])
+			break;
+	}
+}
+
+static void set_mac_if_invalid(int i, u8 *mac)
+{
+	u8 oldmac[6];
+
+	if (is_valid_ethaddr(mac) &&
+	    !eth_env_get_enetaddr_by_index("eth", i, oldmac))
+		eth_env_set_enetaddr_by_index("eth", i, mac);
+}
+
+int turris_atsha_otp_init_mac_addresses(int first_idx)
+{
+	struct udevice *dev = get_atsha204a_dev();
+	u8 mac0[4], mac1[4], mac[6];
+	int ret;
+
+	if (!dev)
+		return -1;
+
+	ret = atsha204a_wakeup(dev);
+	if (ret)
+		return ret;
+
+	ret = atsha204a_read(dev, ATSHA204A_ZONE_OTP, false,
+			     TURRIS_ATSHA_OTP_MAC0, mac0);
+	if (ret)
+		return ret;
+
+	ret = atsha204a_read(dev, ATSHA204A_ZONE_OTP, false,
+			     TURRIS_ATSHA_OTP_MAC1, mac1);
+	if (ret)
+		return ret;
+
+	atsha204a_sleep(dev);
+
+	mac[0] = mac0[1];
+	mac[1] = mac0[2];
+	mac[2] = mac0[3];
+	mac[3] = mac1[1];
+	mac[4] = mac1[2];
+	mac[5] = mac1[3];
+
+	set_mac_if_invalid((first_idx + 0) % 3, mac);
+	increment_mac(mac);
+	set_mac_if_invalid((first_idx + 1) % 3, mac);
+	increment_mac(mac);
+	set_mac_if_invalid((first_idx + 2) % 3, mac);
+
+	return 0;
+}
+
+int turris_atsha_otp_get_serial_number(u32 *version_num, u32 *serial_num)
+{
+	struct udevice *dev = get_atsha204a_dev();
+	int ret;
+
+	if (!dev)
+		return -1;
+
+	ret = atsha204a_wakeup(dev);
+	if (ret)
+		return ret;
+
+	ret = atsha204a_read(dev, ATSHA204A_ZONE_OTP, false,
+			     TURRIS_ATSHA_OTP_VERSION,
+			     (u8 *)version_num);
+	if (ret)
+		return ret;
+
+	ret = atsha204a_read(dev, ATSHA204A_ZONE_OTP, false,
+			     TURRIS_ATSHA_OTP_SERIAL,
+			     (u8 *)serial_num);
+	if (ret)
+		return ret;
+
+	atsha204a_sleep(dev);
+	return 0;
+}

board/CZ.NIC/turris_atsha_otp.h

@@ -0,0 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+#ifndef TURRIS_ATSHA_OTP_H
+#define TURRIS_ATSHA_OTP_H
+
+int turris_atsha_otp_init_mac_addresses(int first_idx);
+int turris_atsha_otp_get_serial_number(u32 *version_num, u32 *serial_num);
+
+#endif

board/CZ.NIC/turris_mox/mox_sp.c

@@ -8,74 +8,7 @@
 #include <asm/io.h>
 #include <linux/bitops.h>
 #include <linux/delay.h>
-
+#include <mach/mbox.h>
-#define RWTM_BASE		(MVEBU_REGISTER(0xb0000))
-#define RWTM_CMD_PARAM(i)	(size_t)(RWTM_BASE + (i) * 4)
-#define RWTM_CMD		(RWTM_BASE + 0x40)
-#define RWTM_CMD_RETSTATUS	(RWTM_BASE + 0x80)
-#define RWTM_CMD_STATUS(i)	(size_t)(RWTM_BASE + 0x84 + (i) * 4)
-
-#define RWTM_HOST_INT_RESET	(RWTM_BASE + 0xc8)
-#define RWTM_HOST_INT_MASK	(RWTM_BASE + 0xcc)
-#define SP_CMD_COMPLETE		BIT(0)
-
-#define MBOX_STS_SUCCESS		(0x0 << 30)
-#define MBOX_STS_FAIL			(0x1 << 30)
-#define MBOX_STS_BADCMD			(0x2 << 30)
-#define MBOX_STS_LATER			(0x3 << 30)
-#define MBOX_STS_ERROR(s)		((s) & (3 << 30))
-#define MBOX_STS_VALUE(s)		(((s) >> 10) & 0xfffff)
-#define MBOX_STS_CMD(s)			((s) & 0x3ff)
-
-enum mbox_cmd {
-	MBOX_CMD_GET_RANDOM	= 1,
-	MBOX_CMD_BOARD_INFO,
-	MBOX_CMD_ECDSA_PUB_KEY,
-	MBOX_CMD_HASH,
-	MBOX_CMD_SIGN,
-	MBOX_CMD_VERIFY,
-
-	MBOX_CMD_OTP_READ,
-	MBOX_CMD_OTP_WRITE
-};
-
-static int mbox_do_cmd(enum mbox_cmd cmd, u32 *out, int nout)
-{
-	const int tries = 50;
-	int i;
-	u32 status;
-
-	clrbits_le32(RWTM_HOST_INT_MASK, SP_CMD_COMPLETE);
-
-	writel(cmd, RWTM_CMD);
-
-	for (i = 0; i < tries; ++i) {
-		mdelay(10);
-		if (readl(RWTM_HOST_INT_RESET) & SP_CMD_COMPLETE)
-			break;
-	}
-
-	if (i == tries) {
-		/* if timed out, don't read status */
-		setbits_le32(RWTM_HOST_INT_RESET, SP_CMD_COMPLETE);
-		return -ETIMEDOUT;
-	}
-
-	for (i = 0; i < nout; ++i)
-		out[i] = readl(RWTM_CMD_STATUS(i));
-	status = readl(RWTM_CMD_RETSTATUS);
-
-	setbits_le32(RWTM_HOST_INT_RESET, SP_CMD_COMPLETE);
-
-	if (MBOX_STS_CMD(status) != cmd)
-		return -EIO;
-	else if (MBOX_STS_ERROR(status) == MBOX_STS_FAIL)
-		return -(int)MBOX_STS_VALUE(status);
-	else if (MBOX_STS_ERROR(status) != MBOX_STS_SUCCESS)
-		return -EIO;
-	else
-		return MBOX_STS_VALUE(status);
-}
 
 const char *mox_sp_get_ecdsa_public_key(void)
 {
@@ -86,7 +19,7 @@ const char *mox_sp_get_ecdsa_public_key(void)
 	if (public_key[0])
 		return public_key;
 
-	res = mbox_do_cmd(MBOX_CMD_ECDSA_PUB_KEY, out, 16);
+	res = mbox_do_cmd(MBOX_CMD_ECDSA_PUB_KEY, NULL, 0, out, 16);
 	if (res < 0)
 		return NULL;
 
@@ -114,7 +47,7 @@ int mbox_sp_get_board_info(u64 *sn, u8 *mac1, u8 *mac2, int *bv, int *ram)
 	u32 out[8];
 	int res;
 
-	res = mbox_do_cmd(MBOX_CMD_BOARD_INFO, out, 8);
+	res = mbox_do_cmd(MBOX_CMD_BOARD_INFO, NULL, 0, out, 8);
 	if (res < 0)
 		return res;
 

board/CZ.NIC/turris_omnia/Makefile

@@ -2,4 +2,4 @@
 #
 # Copyright (C) 2017 Marek Behun <marek.behun@nic.cz>
 
-obj-y	:= turris_omnia.o
+obj-y	:= turris_omnia.o ../turris_atsha_otp.o

board/CZ.NIC/turris_omnia/turris_omnia.c

@@ -14,8 +14,6 @@
 #include <log.h>
 #include <miiphy.h>
 #include <mtd.h>
-#include <net.h>
-#include <netdev.h>
 #include <asm/global_data.h>
 #include <asm/io.h>
 #include <asm/arch/cpu.h>
@@ -25,10 +23,10 @@
 #include <time.h>
 #include <linux/bitops.h>
 #include <u-boot/crc.h>
-# include <atsha204a-i2c.h>
 
 #include "../drivers/ddr/marvell/a38x/ddr3_init.h"
 #include <../serdes/a38x/high_speed_env_spec.h>
+#include "../turris_atsha_otp.h"
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -71,11 +69,6 @@ enum status_word_bits {
 	MSATA_IND_STSBIT	= 0x0020,
 };
 
-#define OMNIA_ATSHA204_OTP_VERSION	0
-#define OMNIA_ATSHA204_OTP_SERIAL	1
-#define OMNIA_ATSHA204_OTP_MAC0		3
-#define OMNIA_ATSHA204_OTP_MAC1		4
-
 /*
  * Those values and defines are taken from the Marvell U-Boot version
  * "u-boot-2013.01-2014_T3.0"
@@ -594,49 +587,12 @@ int board_late_init(void)
 	return 0;
 }
 
-static struct udevice *get_atsha204a_dev(void)
-{
-	static struct udevice *dev;
-
-	if (dev)
-		return dev;
-
-	if (uclass_get_device_by_name(UCLASS_MISC, "atsha204a@64", &dev)) {
-		puts("Cannot find ATSHA204A on I2C bus!\n");
-		dev = NULL;
-	}
-
-	return dev;
-}
-
 int show_board_info(void)
 {
 	u32 version_num, serial_num;
-	int err = 1;
+	int err;
 
-	struct udevice *dev = get_atsha204a_dev();
+	err = turris_atsha_otp_get_serial_number(&version_num, &serial_num);
-
-	if (dev) {
-		err = atsha204a_wakeup(dev);
-		if (err)
-			goto out;
-
-		err = atsha204a_read(dev, ATSHA204A_ZONE_OTP, false,
-				     OMNIA_ATSHA204_OTP_VERSION,
-				     (u8 *)&version_num);
-		if (err)
-			goto out;
-
-		err = atsha204a_read(dev, ATSHA204A_ZONE_OTP, false,
-				     OMNIA_ATSHA204_OTP_SERIAL,
-				     (u8 *)&serial_num);
-		if (err)
-			goto out;
-
-		atsha204a_sleep(dev);
-	}
-
-out:
 	printf("Model: Turris Omnia\n");
 	printf("  RAM size: %i MiB\n", omnia_get_ram_size_gb() * 1024);
 	if (err)
@@ -648,65 +604,9 @@ out:
 	return 0;
 }
 
-static void increment_mac(u8 *mac)
-{
-	int i;
-
-	for (i = 5; i >= 3; i--) {
-		mac[i] += 1;
-		if (mac[i])
-			break;
-	}
-}
-
-static void set_mac_if_invalid(int i, u8 *mac)
-{
-	u8 oldmac[6];
-
-	if (is_valid_ethaddr(mac) &&
-	    !eth_env_get_enetaddr_by_index("eth", i, oldmac))
-		eth_env_set_enetaddr_by_index("eth", i, mac);
-}
-
 int misc_init_r(void)
 {
-	int err;
+	turris_atsha_otp_init_mac_addresses(1);
-	struct udevice *dev = get_atsha204a_dev();
-	u8 mac0[4], mac1[4], mac[6];
-
-	if (!dev)
-		goto out;
-
-	err = atsha204a_wakeup(dev);
-	if (err)
-		goto out;
-
-	err = atsha204a_read(dev, ATSHA204A_ZONE_OTP, false,
-			     OMNIA_ATSHA204_OTP_MAC0, mac0);
-	if (err)
-		goto out;
-
-	err = atsha204a_read(dev, ATSHA204A_ZONE_OTP, false,
-			     OMNIA_ATSHA204_OTP_MAC1, mac1);
-	if (err)
-		goto out;
-
-	atsha204a_sleep(dev);
-
-	mac[0] = mac0[1];
-	mac[1] = mac0[2];
-	mac[2] = mac0[3];
-	mac[3] = mac1[1];
-	mac[4] = mac1[2];
-	mac[5] = mac1[3];
-
-	set_mac_if_invalid(1, mac);
-	increment_mac(mac);
-	set_mac_if_invalid(2, mac);
-	increment_mac(mac);
-	set_mac_if_invalid(0, mac);
-
-out:
 	return 0;
 }
 

board/Marvell/mvebu_armada-37xx/board.c

@@ -328,9 +328,10 @@ int board_network_enable(struct mii_dev *bus)
 	return 0;
 }
 
-#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_ENV_IS_IN_SPI_FLASH)
+#ifdef CONFIG_OF_BOARD_SETUP
 int ft_board_setup(void *blob, struct bd_info *bd)
 {
+#ifdef CONFIG_ENV_IS_IN_SPI_FLASH
 	int ret;
 	int spi_off;
 	int parts_off;
@@ -424,6 +425,7 @@ int ft_board_setup(void *blob, struct bd_info *bd)
 		return 0;
 	}
 
+#endif
 	return 0;
 }
 #endif

board/Marvell/sheevaplug/sheevaplug.c

@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
- * Copyright (C) 2021  Tony Dinh <mibodhi@gmail.com>
+ * Copyright (C) 2021-2022  Tony Dinh <mibodhi@gmail.com>
  * (C) Copyright 2009
  * Marvell Semiconductor <www.marvell.com>
  * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
@@ -8,17 +8,21 @@
 
 #include <common.h>
 #include <init.h>
-#include <miiphy.h>
+#include <netdev.h>
-#include <net.h>
 #include <asm/global_data.h>
 #include <asm/mach-types.h>
 #include <asm/arch/cpu.h>
 #include <asm/arch/soc.h>
 #include <asm/arch/mpp.h>
-#include "sheevaplug.h"
+#include <linux/bitops.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
+#define SHEEVAPLUG_OE_LOW		(~(0))
+#define SHEEVAPLUG_OE_HIGH		(~(0))
+#define SHEEVAPLUG_OE_VAL_LOW		BIT(29)       /* USB_PWEN low */
+#define SHEEVAPLUG_OE_VAL_HIGH		BIT(17)       /* LED pin high */
+
 int board_early_init_f(void)
 {
 	/*
@@ -88,6 +92,11 @@ int board_early_init_f(void)
 	return 0;
 }
 
+int board_eth_init(struct bd_info *bis)
+{
+	return cpu_eth_init(bis);
+}
+
 int board_init(void)
 {
 	/*
@@ -95,72 +104,8 @@ int board_init(void)
 	 */
 	gd->bd->bi_arch_number = MACH_TYPE_SHEEVAPLUG;
 
-	/* adress of boot parameters */
+	/* address of boot parameters */
 	gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
 
 	return 0;
 }
-
-static int fdt_get_phy_addr(const char *path)
-{
-	const void *fdt = gd->fdt_blob;
-	const u32 *reg;
-	const u32 *val;
-	int node, phandle, addr;
-
-	/* Find the node by its full path */
-	node = fdt_path_offset(fdt, path);
-	if (node >= 0) {
-		/* Look up phy-handle */
-		val = fdt_getprop(fdt, node, "phy-handle", NULL);
-		if (val) {
-			phandle = fdt32_to_cpu(*val);
-			if (!phandle)
-				return -1;
-			/* Follow it to its node */
-			node = fdt_node_offset_by_phandle(fdt, phandle);
-			if (node) {
-				/* Look up reg */
-				reg = fdt_getprop(fdt, node, "reg", NULL);
-				if (reg) {
-					addr = fdt32_to_cpu(*reg);
-					return addr;
-				}
-			}
-		}
-	}
-	return -1;
-}
-
-#ifdef CONFIG_RESET_PHY_R
-/* Configure and enable MV88E1116 PHY */
-void reset_phy(void)
-{
-	u16 reg;
-	int phyaddr;
-	char *name = "ethernet-controller@72000";
-	char *eth0_path = "/ocp@f1000000/ethernet-controller@72000/ethernet0-port@0";
-
-	if (miiphy_set_current_dev(name))
-		return;
-
-	phyaddr = fdt_get_phy_addr(eth0_path);
-	if (phyaddr < 0)
-		return;
-
-	/*
-	 * Enable RGMII delay on Tx and Rx for CPU port
-	 * Ref: sec 4.7.2 of chip datasheet
-	 */
-	miiphy_write(name, phyaddr, MV88E1116_PGADR_REG, 2);
-	miiphy_read(name, phyaddr, MV88E1116_MAC_CTRL_REG, &reg);
-	reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
-	miiphy_write(name, phyaddr, MV88E1116_MAC_CTRL_REG, reg);
-	miiphy_write(name, phyaddr, MV88E1116_PGADR_REG, 0);
-
-	/* reset the phy */
-	miiphy_reset(name, phyaddr);
-
-	printf("88E1116 Initialized on %s\n", name);
-}
-#endif /* CONFIG_RESET_PHY_R */

board/Marvell/sheevaplug/sheevaplug.h

@@ -1,24 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2009
- * Marvell Semiconductor <www.marvell.com>
- * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
- */
-
-#ifndef __SHEEVAPLUG_H
-#define __SHEEVAPLUG_H
-
-#define SHEEVAPLUG_OE_LOW		(~(0))
-#define SHEEVAPLUG_OE_HIGH		(~(0))
-#define SHEEVAPLUG_OE_VAL_LOW		(1 << 29)	/* USB_PWEN low */
-#define SHEEVAPLUG_OE_VAL_HIGH		(1 << 17)	/* LED pin high */
-
-/* PHY related */
-#define MV88E1116_LED_FCTRL_REG		10
-#define MV88E1116_CPRSP_CR3_REG		21
-#define MV88E1116_MAC_CTRL_REG		21
-#define MV88E1116_PGADR_REG		22
-#define MV88E1116_RGMII_TXTM_CTRL	(1 << 4)
-#define MV88E1116_RGMII_RXTM_CTRL	(1 << 5)
-
-#endif /* __SHEEVAPLUG_H */

configs/mvebu_db-88f3720_defconfig

@@ -4,6 +4,7 @@ CONFIG_ARCH_MVEBU=y
 CONFIG_SYS_TEXT_BASE=0x00000000
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_TARGET_MVEBU_ARMADA_37XX=y
+CONFIG_MVEBU_EFUSE=y
 CONFIG_ENV_SIZE=0x10000
 CONFIG_ENV_OFFSET=0x3f0000
 CONFIG_ENV_SECT_SIZE=0x10000
@@ -23,6 +24,7 @@ CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_ARCH_EARLY_INIT_R=y
 CONFIG_BOARD_EARLY_INIT_F=y
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_FUSE=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y

configs/mvebu_espressobin-88f3720_defconfig

@@ -4,6 +4,7 @@ CONFIG_ARCH_MVEBU=y
 CONFIG_SYS_TEXT_BASE=0x00000000
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_TARGET_MVEBU_ARMADA_37XX=y
+CONFIG_MVEBU_EFUSE=y
 CONFIG_ENV_SIZE=0x10000
 CONFIG_ENV_OFFSET=0x3F0000
 CONFIG_ENV_SECT_SIZE=0x10000
@@ -25,6 +26,7 @@ CONFIG_ARCH_EARLY_INIT_R=y
 CONFIG_BOARD_EARLY_INIT_F=y
 CONFIG_BOARD_LATE_INIT=y
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_FUSE=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_GPT=y
 CONFIG_CMD_I2C=y

configs/sheevaplug_defconfig

@@ -21,7 +21,6 @@ CONFIG_USE_BOOTCOMMAND=y
 CONFIG_BOOTCOMMAND="${x_bootcmd_kernel}; setenv bootargs ${x_bootargs} ${x_bootargs_root}; bootm 0x6400000;"
 CONFIG_USE_PREBOOT=y
 # CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_RESET_PHY_R=y
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_FLASH is not set
@@ -29,13 +28,13 @@ CONFIG_CMD_MMC=y
 CONFIG_CMD_NAND=y
 CONFIG_CMD_SATA=y
 CONFIG_CMD_USB=y
-# CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_EXT2=y
 CONFIG_CMD_EXT4=y
 CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_CMD_JFFS2=y
 CONFIG_CMD_MTDPARTS=y
 CONFIG_MTDIDS_DEFAULT="nand0=orion_nand"
@@ -54,6 +53,7 @@ CONFIG_SYS_SATA_MAX_DEVICE=2
 CONFIG_MVEBU_MMC=y
 CONFIG_MTD=y
 CONFIG_MTD_RAW_NAND=y
+CONFIG_PHY_MARVELL=y
 CONFIG_DM_ETH=y
 CONFIG_MVGBE=y
 CONFIG_MII=y

configs/turris_mox_defconfig

@@ -4,6 +4,7 @@ CONFIG_ARCH_MVEBU=y
 CONFIG_SYS_TEXT_BASE=0x00000000
 CONFIG_NR_DRAM_BANKS=2
 CONFIG_TARGET_TURRIS_MOX=y
+CONFIG_MVEBU_EFUSE=y
 CONFIG_ENV_SIZE=0x10000
 CONFIG_ENV_OFFSET=0x180000
 CONFIG_ENV_SECT_SIZE=0x10000
@@ -30,6 +31,7 @@ CONFIG_MISC_INIT_R=y
 CONFIG_CMD_SHA1SUM=y
 CONFIG_CMD_CLK=y
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_FUSE=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_GPT=y
 CONFIG_CMD_I2C=y

configs/turris_omnia_defconfig

@@ -9,6 +9,7 @@ CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_NR_DRAM_BANKS=2
 CONFIG_TARGET_TURRIS_OMNIA=y
 CONFIG_DDR_RESET_ON_TRAINING_FAILURE=y
+CONFIG_MVEBU_EFUSE=y
 CONFIG_ENV_SIZE=0x10000
 CONFIG_ENV_OFFSET=0xF0000
 CONFIG_ENV_SECT_SIZE=0x10000
@@ -41,6 +42,7 @@ CONFIG_CMD_MEMTEST=y
 CONFIG_SYS_ALT_MEMTEST=y
 CONFIG_CMD_SHA1SUM=y
 CONFIG_CMD_LZMADEC=y
+CONFIG_CMD_FUSE=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_GPT=y
 CONFIG_CMD_I2C=y

configs/uDPU_defconfig

@@ -3,6 +3,7 @@ CONFIG_ARCH_CPU_INIT=y
 CONFIG_ARCH_MVEBU=y
 CONFIG_SYS_TEXT_BASE=0x00000000
 CONFIG_TARGET_MVEBU_ARMADA_37XX=y
+CONFIG_MVEBU_EFUSE=y
 CONFIG_ENV_SIZE=0x10000
 CONFIG_ENV_OFFSET=0x180000
 CONFIG_ENV_SECT_SIZE=0x10000
@@ -15,9 +16,8 @@ CONFIG_AHCI=y
 CONFIG_DISTRO_DEFAULTS=y
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_FIT=y
-CONFIG_SPI_BOOT=y
+CONFIG_FIT_VERBOSE=y
 CONFIG_USE_PREBOOT=y
-CONFIG_SYS_CONSOLE_INFO_QUIET=y
 # CONFIG_DISPLAY_CPUINFO is not set
 # CONFIG_DISPLAY_BOARDINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
@@ -28,9 +28,11 @@ CONFIG_SYS_PROMPT="uDPU>> "
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_XIMG is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_FUSE=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
+CONFIG_CMD_MTD=y
 CONFIG_CMD_PCI=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_USB=y
@@ -40,9 +42,6 @@ CONFIG_CMD_CACHE=y
 CONFIG_CMD_TIME=y
 CONFIG_CMD_MVEBU_BUBT=y
 CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_MTDPARTS=y
-CONFIG_MTDIDS_DEFAULT="nor0=spi0"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=spi0:4m(uboot),-(rootfs)"
 CONFIG_MAC_PARTITION=y
 CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_IS_IN_SPI_FLASH=y
@@ -57,12 +56,13 @@ CONFIG_DM_I2C=y
 CONFIG_DM_I2C_GPIO=y
 CONFIG_SYS_I2C_MV=y
 CONFIG_MISC=y
+CONFIG_MMC_HS200_SUPPORT=y
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_SDMA=y
 CONFIG_MMC_SDHCI_XENON=y
 CONFIG_MTD=y
 CONFIG_DM_MTD=y
-CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_SFDP_SUPPORT=y
 CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_SPI_FLASH_STMICRO=y

drivers/net/mvneta.c

@@ -286,6 +286,7 @@ struct mvneta_port {
 	struct phy_device *phydev;
 #if CONFIG_IS_ENABLED(DM_GPIO)
 	struct gpio_desc phy_reset_gpio;
+	struct gpio_desc sfp_tx_disable_gpio;
 #endif
 	struct mii_dev *bus;
 };
@@ -1693,6 +1694,9 @@ static int mvneta_probe(struct udevice *dev)
 {
 	struct eth_pdata *pdata = dev_get_plat(dev);
 	struct mvneta_port *pp = dev_get_priv(dev);
+#if CONFIG_IS_ENABLED(DM_GPIO)
+	struct ofnode_phandle_args sfp_args;
+#endif
 	void *blob = (void *)gd->fdt_blob;
 	int node = dev_of_offset(dev);
 	struct mii_dev *bus;
@@ -1767,6 +1771,11 @@ static int mvneta_probe(struct udevice *dev)
 		return ret;
 
 #if CONFIG_IS_ENABLED(DM_GPIO)
+	ret = dev_read_phandle_with_args(dev, "sfp", NULL, 0, 0, &sfp_args);
+	if (!ret && ofnode_is_enabled(sfp_args.node))
+		gpio_request_by_name_nodev(sfp_args.node, "tx-disable-gpio", 0,
+					   &pp->sfp_tx_disable_gpio, GPIOD_IS_OUT);
+
 	gpio_request_by_name(dev, "phy-reset-gpios", 0,
 			     &pp->phy_reset_gpio, GPIOD_IS_OUT);
 
@@ -1775,6 +1784,9 @@ static int mvneta_probe(struct udevice *dev)
 		mdelay(10);
 		dm_gpio_set_value(&pp->phy_reset_gpio, 0);
 	}
+
+	if (dm_gpio_is_valid(&pp->sfp_tx_disable_gpio))
+		dm_gpio_set_value(&pp->sfp_tx_disable_gpio, 0);
 #endif
 
 	return board_network_enable(bus);

include/configs/sheevaplug.h

@@ -1,5 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0+ */
 /*
+ * (C) Copyright 2022 Tony Dinh <mibodhi@gmail.com>
  * (C) Copyright 2009-2014
  * Gerald Kerma <dreagle@doukki.net>
  * Marvell Semiconductor <www.marvell.com>
@@ -14,17 +15,8 @@
 /*
  *  Environment variables configurations
  */
-/*
- * max 4k env size is enough, but in case of nand
- * it has to be rounded to sector size
- */
-
-/*
- * Default environment variables
- */
-
 #define CONFIG_EXTRA_ENV_SETTINGS	"x_bootargs=console"	\
-	"=ttyS0,115200 mtdparts="CONFIG_MTDPARTS_DEFAULT	\
+	"=ttyS0,115200 mtdparts=" CONFIG_MTDPARTS_DEFAULT	\
 	"x_bootcmd_kernel=nand read 0x6400000 0x100000 0x400000\0" \
 	"x_bootcmd_usb=usb start\0" \
 	"x_bootargs_root=root=/dev/mtdblock3 rw rootfstype=jffs2\0"
@@ -32,16 +24,13 @@
 /*
  * Ethernet Driver configuration
  */
-#ifdef CONFIG_CMD_NET
 #define CONFIG_MVGBE_PORTS	{1, 0}	/* enable port 0 only */
 #define CONFIG_PHY_BASE_ADR	0
-#endif /* CONFIG_CMD_NET */
 
 /*
- * SATA driver configuration
+ * Support large disk for SATA and USB
  */
-#ifdef CONFIG_SATA
+#define CONFIG_SYS_64BIT_LBA
 #define CONFIG_LBA48
-#endif /* CONFIG_SATA */
 
 #endif /* _CONFIG_SHEEVAPLUG_H */

tools/kwboot.c

@@ -1591,8 +1591,8 @@ static void *
 kwboot_read_image(const char *path, size_t *size, size_t reserve)
 {
 	int rc, fd;
-	struct stat st;
 	void *img;
+	off_t len;
 	off_t tot;
 
 	rc = -1;
@@ -1602,31 +1602,34 @@ kwboot_read_image(const char *path, size_t *size, size_t reserve)
 	if (fd < 0)
 		goto out;
 
-	rc = fstat(fd, &st);
+	len = lseek(fd, 0, SEEK_END);
-	if (rc)
+	if (len == (off_t)-1)
 		goto out;
 
-	img = malloc(st.st_size + reserve);
+	if (lseek(fd, 0, SEEK_SET) == (off_t)-1)
+		goto out;
+
+	img = malloc(len + reserve);
 	if (!img)
 		goto out;
 
 	tot = 0;
-	while (tot < st.st_size) {
+	while (tot < len) {
-		ssize_t rd = read(fd, img + tot, st.st_size - tot);
+		ssize_t rd = read(fd, img + tot, len - tot);
 
 		if (rd < 0)
 			goto out;
 
 		tot += rd;
 
-		if (!rd && tot < st.st_size) {
+		if (!rd && tot < len) {
 			errno = EIO;
 			goto out;
 		}
 	}
 
 	rc = 0;
-	*size = st.st_size;
+	*size = len;
 out:
 	if (rc && img) {
 		free(img);

tools/mrvl_uart.sh

@@ -1,119 +0,0 @@
-#!/bin/bash
-# SPDX-License-Identifier: GPL-2.0
-#
-######################################################
-# Copyright (C) 2016 Marvell International Ltd.
-#
-# https://spdx.org/licenses
-#
-# Author: Konstantin Porotchkin kostap@marvell.com
-#
-# Version 0.3
-#
-# UART recovery downloader for Armada SoCs
-#
-######################################################
-
-port=$1
-file=$2
-speed=$3
-
-pattern_repeat=1500
-default_baudrate=115200
-tmpfile=/tmp/xmodem.pattern
-tools=( dd stty sx minicom )
-
-case "$3" in
-    2)
-        fast_baudrate=230400
-        prefix="\xF2"
-        ;;
-    4)
-        fast_baudrate=460800
-        prefix="\xF4"
-        ;;
-    8)
-    	fast_baudrate=921600
-        prefix="\xF8"
-        ;;
-    *)
-    	fast_baudrate=$default_baudrate
-        prefix="\xBB"
-esac
-
-if [[ -z "$port" || -z "$file" ]]
-then
-    echo -e "\nMarvell recovery image downloader for Armada SoC family."
-    echo -e "Command syntax:"
-    echo -e "\t$(basename $0) <port> <file> [2|4|8]"
-    echo -e "\tport  - serial port the target board is connected to"
-    echo -e "\tfile  - recovery boot image for target download"
-    echo -e "\t2|4|8 - times to increase the default serial port speed by"
-    echo -e "For example - load the image over ttyUSB0 @ 460800 baud:"
-    echo -e "$(basename $0) /dev/ttyUSB0 /tmp/flash-image.bin 4\n"
-    echo -e "=====WARNING====="
-    echo -e "- The speed-up option is not available in SoC families prior to A8K+"
-    echo -e "- This utility is not compatible with Armada 37xx SoC family\n"
-fi
-
-# Sanity checks
-if [ -c "$port" ]
-then
-   echo -e "Using device connected on serial port \"$port\""
-else
-   echo "Wrong serial port name!"
-   exit 1
-fi
-
-if [ -f "$file" ]
-then
-   echo -e "Loading flash image file \"$file\""
-else
-   echo "File $file does not exist!"
-   exit 1
-fi
-
-# Verify required tools installation
-for tool in ${tools[@]}
-do
-    toolname=`which $tool`
-    if [ -z "$toolname" ]
-    then
-        echo -e "Missing installation of \"$tool\" --> Exiting"
-        exit 1
-    fi
-done
-
-
-echo -e "Recovery will run at $fast_baudrate baud"
-echo -e "========================================"
-
-if [ -f "$tmpfile" ]
-then
-    rm -f $tmpfile
-fi
-
-# Send the escape sequence to target board using default debug port speed
-stty -F $port raw ignbrk time 5 $default_baudrate
-counter=0
-while [ $counter -lt $pattern_repeat ]; do
-    echo -n -e "$prefix\x11\x22\x33\x44\x55\x66\x77" >> $tmpfile
-    let counter=counter+1
-done
-
-echo -en "Press the \"Reset\" button on the target board and "
-echo -en "the \"Enter\" key on the host keyboard simultaneously"
-read
-dd if=$tmpfile of=$port &>/dev/null
-
-# Speed up the binary image transfer
-stty -F $port raw ignbrk time 5 $fast_baudrate
-sx -vv $file > $port < $port
-#sx-at91 $port $file
-
-# Return the port to the default speed
-stty -F $port raw ignbrk time 5 $default_baudrate
-
-# Optional - fire up Minicom
-minicom -D $port -b $default_baudrate
-