exynos: i2c: Fix i2c driver to handle NACKs properly
The Exynos5 i2c driver does not handle NACKs properly. This change: - fixes the NACK processing problem (do not continue transaction if address cycle was NACKed) - eliminates a fair amount of duplicate code Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-by: Simon Glass <sjg@google.com> Signed-off-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com>
This commit is contained in:
Naveen Krishna Ch
Heiko Schocher
parent
83d271b5ff
commit
e4e2402071
@ -43,7 +43,7 @@
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#define I2C_START_STOP 0x20 /* START / STOP */
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#define I2C_TXRX_ENA 0x10 /* I2C Tx/Rx enable */
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#define I2C_TIMEOUT 1 /* 1 second */
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#define I2C_TIMEOUT_MS 1000 /* 1 second */
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/*
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@ -84,22 +84,26 @@ static void SetI2CSCL(int x)
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}
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#endif
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/*
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* Wait til the byte transfer is completed.
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*
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* @param i2c- pointer to the appropriate i2c register bank.
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* @return I2C_OK, if transmission was ACKED
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* I2C_NACK, if transmission was NACKED
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* I2C_NOK_TIMEOUT, if transaction did not complete in I2C_TIMEOUT_MS
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*/
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static int WaitForXfer(struct s3c24x0_i2c *i2c)
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{
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int i;
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ulong start_time = get_timer(0);
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i = I2C_TIMEOUT * 10000;
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while (!(readl(&i2c->iiccon) & I2CCON_IRPND) && (i > 0)) {
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udelay(100);
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i--;
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}
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do {
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if (readl(&i2c->iiccon) & I2CCON_IRPND)
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return (readl(&i2c->iicstat) & I2CSTAT_NACK) ?
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I2C_NACK : I2C_OK;
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} while (get_timer(start_time) < I2C_TIMEOUT_MS);
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return (readl(&i2c->iiccon) & I2CCON_IRPND) ? I2C_OK : I2C_NOK_TOUT;
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}
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static int IsACK(struct s3c24x0_i2c *i2c)
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{
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return !(readl(&i2c->iicstat) & I2CSTAT_NACK);
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return I2C_NOK_TOUT;
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}
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static void ReadWriteByte(struct s3c24x0_i2c *i2c)
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@ -180,21 +184,27 @@ unsigned int i2c_get_bus_num(void)
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void i2c_init(int speed, int slaveadd)
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{
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int i;
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struct s3c24x0_i2c *i2c;
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#if !(defined CONFIG_EXYNOS4 || defined CONFIG_EXYNOS5)
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struct s3c24x0_gpio *gpio = s3c24x0_get_base_gpio();
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#endif
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int i;
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ulong start_time = get_timer(0);
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/* By default i2c channel 0 is the current bus */
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g_current_bus = 0;
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i2c = get_base_i2c();
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/* wait for some time to give previous transfer a chance to finish */
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i = I2C_TIMEOUT * 1000;
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while ((readl(&i2c->iicstat) & I2CSTAT_BSY) && (i > 0)) {
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udelay(1000);
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i--;
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/*
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* In case the previous transfer is still going, wait to give it a
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* chance to finish.
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*/
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while (readl(&i2c->iicstat) & I2CSTAT_BSY) {
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if (get_timer(start_time) > I2C_TIMEOUT_MS) {
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printf("%s: I2C bus busy for %p\n", __func__,
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&i2c->iicstat);
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return;
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}
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}
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#if !(defined CONFIG_EXYNOS4 || defined CONFIG_EXYNOS5)
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@ -260,7 +270,8 @@ static int i2c_transfer(struct s3c24x0_i2c *i2c,
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unsigned char data[],
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unsigned short data_len)
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{
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int i, result;
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int i = 0, result;
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ulong start_time = get_timer(0);
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if (data == 0 || data_len == 0) {
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/*Don't support data transfer of no length or to address 0 */
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@ -268,128 +279,78 @@ static int i2c_transfer(struct s3c24x0_i2c *i2c,
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return I2C_NOK;
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}
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/* Check I2C bus idle */
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i = I2C_TIMEOUT * 1000;
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while ((readl(&i2c->iicstat) & I2CSTAT_BSY) && (i > 0)) {
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udelay(1000);
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i--;
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while (readl(&i2c->iicstat) & I2CSTAT_BSY) {
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if (get_timer(start_time) > I2C_TIMEOUT_MS)
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return I2C_NOK_TOUT;
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}
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if (readl(&i2c->iicstat) & I2CSTAT_BSY)
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return I2C_NOK_TOUT;
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writel(readl(&i2c->iiccon) | I2CCON_ACKGEN, &i2c->iiccon);
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result = I2C_OK;
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/* Get the slave chip address going */
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writel(chip, &i2c->iicds);
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if ((cmd_type == I2C_WRITE) || (addr && addr_len))
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writel(I2C_MODE_MT | I2C_TXRX_ENA | I2C_START_STOP,
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&i2c->iicstat);
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else
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writel(I2C_MODE_MR | I2C_TXRX_ENA | I2C_START_STOP,
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&i2c->iicstat);
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/* Wait for chip address to transmit. */
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result = WaitForXfer(i2c);
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if (result != I2C_OK)
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goto bailout;
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/* If register address needs to be transmitted - do it now. */
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if (addr && addr_len) {
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while ((i < addr_len) && (result == I2C_OK)) {
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writel(addr[i++], &i2c->iicds);
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ReadWriteByte(i2c);
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result = WaitForXfer(i2c);
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}
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i = 0;
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if (result != I2C_OK)
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goto bailout;
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}
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switch (cmd_type) {
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case I2C_WRITE:
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if (addr && addr_len) {
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writel(chip, &i2c->iicds);
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/* send START */
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writel(I2C_MODE_MT | I2C_TXRX_ENA | I2C_START_STOP,
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&i2c->iicstat);
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i = 0;
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while ((i < addr_len) && (result == I2C_OK)) {
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result = WaitForXfer(i2c);
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writel(addr[i], &i2c->iicds);
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ReadWriteByte(i2c);
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i++;
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}
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i = 0;
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while ((i < data_len) && (result == I2C_OK)) {
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result = WaitForXfer(i2c);
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writel(data[i], &i2c->iicds);
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ReadWriteByte(i2c);
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i++;
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}
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} else {
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writel(chip, &i2c->iicds);
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/* send START */
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writel(I2C_MODE_MT | I2C_TXRX_ENA | I2C_START_STOP,
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&i2c->iicstat);
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i = 0;
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while ((i < data_len) && (result == I2C_OK)) {
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result = WaitForXfer(i2c);
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writel(data[i], &i2c->iicds);
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ReadWriteByte(i2c);
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i++;
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}
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}
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if (result == I2C_OK)
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while ((i < data_len) && (result == I2C_OK)) {
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writel(data[i++], &i2c->iicds);
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ReadWriteByte(i2c);
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result = WaitForXfer(i2c);
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/* send STOP */
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writel(I2C_MODE_MT | I2C_TXRX_ENA, &i2c->iicstat);
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ReadWriteByte(i2c);
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}
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break;
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case I2C_READ:
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if (addr && addr_len) {
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/*
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* Register address has been sent, now send slave chip
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* address again to start the actual read transaction.
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*/
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writel(chip, &i2c->iicds);
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/* send START */
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writel(I2C_MODE_MT | I2C_TXRX_ENA | I2C_START_STOP,
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&i2c->iicstat);
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result = WaitForXfer(i2c);
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if (IsACK(i2c)) {
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i = 0;
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while ((i < addr_len) && (result == I2C_OK)) {
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writel(addr[i], &i2c->iicds);
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ReadWriteByte(i2c);
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result = WaitForXfer(i2c);
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i++;
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}
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writel(chip, &i2c->iicds);
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/* resend START */
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writel(I2C_MODE_MR | I2C_TXRX_ENA |
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I2C_START_STOP, &i2c->iicstat);
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ReadWriteByte(i2c);
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result = WaitForXfer(i2c);
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i = 0;
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while ((i < data_len) && (result == I2C_OK)) {
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/* disable ACK for final READ */
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if (i == data_len - 1)
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writel(readl(&i2c->iiccon)
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& ~I2CCON_ACKGEN,
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&i2c->iiccon);
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ReadWriteByte(i2c);
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result = WaitForXfer(i2c);
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data[i] = readl(&i2c->iicds);
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i++;
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}
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} else {
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result = I2C_NACK;
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}
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} else {
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writel(chip, &i2c->iicds);
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/* send START */
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/* Generate a re-START. */
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writel(I2C_MODE_MR | I2C_TXRX_ENA | I2C_START_STOP,
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&i2c->iicstat);
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ReadWriteByte(i2c);
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result = WaitForXfer(i2c);
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if (IsACK(i2c)) {
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i = 0;
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while ((i < data_len) && (result == I2C_OK)) {
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/* disable ACK for final READ */
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if (i == data_len - 1)
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writel(readl(&i2c->iiccon) &
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~I2CCON_ACKGEN,
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&i2c->iiccon);
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ReadWriteByte(i2c);
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result = WaitForXfer(i2c);
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data[i] = readl(&i2c->iicds);
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i++;
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}
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} else {
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result = I2C_NACK;
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}
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if (result != I2C_OK)
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goto bailout;
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}
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/* send STOP */
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writel(I2C_MODE_MR | I2C_TXRX_ENA, &i2c->iicstat);
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ReadWriteByte(i2c);
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while ((i < data_len) && (result == I2C_OK)) {
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/* disable ACK for final READ */
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if (i == data_len - 1)
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writel(readl(&i2c->iiccon)
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& ~I2CCON_ACKGEN,
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&i2c->iiccon);
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ReadWriteByte(i2c);
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result = WaitForXfer(i2c);
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data[i++] = readl(&i2c->iicds);
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}
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if (result == I2C_NACK)
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result = I2C_OK; /* Normal terminated read. */
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break;
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default:
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@ -398,6 +359,11 @@ static int i2c_transfer(struct s3c24x0_i2c *i2c,
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break;
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}
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bailout:
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/* Send STOP. */
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writel(I2C_MODE_MR | I2C_TXRX_ENA, &i2c->iicstat);
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ReadWriteByte(i2c);
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return result;
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}
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