net: sun8i-emac: support R40 GMAC
Add support for the GMAC found in the Allwinner R40/V40 SoC. The R40 GMAC interface is not controlled by the syscon register but has a separate configuration register in the CCU. The clock gate and reset bits are in a different register compared to the other SoCs supported by this driver. The driver uses the -gmac suffix for the R40 because the R40 also has a different 100 MBit MAC (EMAC). Signed-off-by: Lothar Felten <lothar.felten@gmail.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@openedev.com>
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@ -67,6 +67,7 @@
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/* IO mux settings */
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#define SUN8I_IOMUX_H3 2
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#define SUN8I_IOMUX_R40 5
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#define SUN8I_IOMUX 4
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/* H3/A64 EMAC Register's offset */
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@ -97,6 +98,7 @@ enum emac_variant {
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A83T_EMAC = 1,
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H3_EMAC,
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A64_EMAC,
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R40_GMAC,
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};
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struct emac_dma_desc {
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@ -278,6 +280,9 @@ static int sun8i_emac_set_syscon(struct emac_eth_dev *priv)
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reg = readl(priv->sysctl_reg + 0x30);
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if (priv->variant == R40_GMAC)
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return 0;
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if (priv->variant == H3_EMAC) {
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ret = sun8i_emac_set_syscon_ephy(priv, ®);
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if (ret)
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@ -495,6 +500,8 @@ static int parse_phy_pins(struct udevice *dev)
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if (priv->variant == H3_EMAC)
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sunxi_gpio_set_cfgpin(pin, SUN8I_IOMUX_H3);
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else if (priv->variant == R40_GMAC)
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sunxi_gpio_set_cfgpin(pin, SUN8I_IOMUX_R40);
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else
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sunxi_gpio_set_cfgpin(pin, SUN8I_IOMUX);
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@ -634,11 +641,26 @@ static void sun8i_emac_board_setup(struct emac_eth_dev *priv)
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}
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}
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/* Set clock gating for emac */
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setbits_le32(&ccm->ahb_gate0, BIT(AHB_GATE_OFFSET_GMAC));
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if (priv->variant == R40_GMAC) {
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/* Set clock gating for emac */
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setbits_le32(&ccm->ahb_reset1_cfg, BIT(AHB_RESET_OFFSET_GMAC));
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/* De-assert EMAC */
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setbits_le32(&ccm->ahb_reset0_cfg, BIT(AHB_RESET_OFFSET_GMAC));
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/* De-assert EMAC */
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setbits_le32(&ccm->ahb_gate1, BIT(AHB_GATE_OFFSET_GMAC));
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/* Select RGMII for R40 */
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setbits_le32(&ccm->gmac_clk_cfg,
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CCM_GMAC_CTRL_TX_CLK_SRC_INT_RGMII |
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CCM_GMAC_CTRL_GPIT_RGMII);
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setbits_le32(&ccm->gmac_clk_cfg,
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CCM_GMAC_CTRL_TX_CLK_DELAY(CONFIG_GMAC_TX_DELAY));
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} else {
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/* Set clock gating for emac */
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setbits_le32(&ccm->ahb_gate0, BIT(AHB_GATE_OFFSET_GMAC));
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/* De-assert EMAC */
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setbits_le32(&ccm->ahb_reset0_cfg, BIT(AHB_RESET_OFFSET_GMAC));
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}
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}
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#if defined(CONFIG_DM_GPIO)
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@ -805,22 +827,32 @@ static int sun8i_emac_eth_ofdata_to_platdata(struct udevice *dev)
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return -EINVAL;
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}
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offset = fdtdec_lookup_phandle(gd->fdt_blob, node, "syscon");
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if (offset < 0) {
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debug("%s: cannot find syscon node\n", __func__);
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priv->variant = dev_get_driver_data(dev);
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if (!priv->variant) {
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printf("%s: Missing variant\n", __func__);
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return -EINVAL;
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}
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reg = fdt_getprop(gd->fdt_blob, offset, "reg", NULL);
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if (!reg) {
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debug("%s: cannot find reg property in syscon node\n",
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__func__);
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return -EINVAL;
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}
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priv->sysctl_reg = fdt_translate_address((void *)gd->fdt_blob,
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offset, reg);
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if (priv->sysctl_reg == FDT_ADDR_T_NONE) {
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debug("%s: Cannot find syscon base address\n", __func__);
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return -EINVAL;
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if (priv->variant != R40_GMAC) {
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offset = fdtdec_lookup_phandle(gd->fdt_blob, node, "syscon");
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if (offset < 0) {
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debug("%s: cannot find syscon node\n", __func__);
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return -EINVAL;
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}
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reg = fdt_getprop(gd->fdt_blob, offset, "reg", NULL);
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if (!reg) {
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debug("%s: cannot find reg property in syscon node\n",
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__func__);
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return -EINVAL;
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}
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priv->sysctl_reg = fdt_translate_address((void *)gd->fdt_blob,
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offset, reg);
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if (priv->sysctl_reg == FDT_ADDR_T_NONE) {
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debug("%s: Cannot find syscon base address\n",
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__func__);
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return -EINVAL;
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}
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}
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pdata->phy_interface = -1;
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@ -845,13 +877,6 @@ static int sun8i_emac_eth_ofdata_to_platdata(struct udevice *dev)
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return -EINVAL;
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}
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priv->variant = dev_get_driver_data(dev);
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if (!priv->variant) {
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printf("%s: Missing variant\n", __func__);
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return -EINVAL;
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}
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if (priv->variant == H3_EMAC) {
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int parent = fdt_parent_offset(gd->fdt_blob, offset);
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@ -892,6 +917,8 @@ static const struct udevice_id sun8i_emac_eth_ids[] = {
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.data = (uintptr_t)A64_EMAC },
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{.compatible = "allwinner,sun8i-a83t-emac",
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.data = (uintptr_t)A83T_EMAC },
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{.compatible = "allwinner,sun8i-r40-gmac",
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.data = (uintptr_t)R40_GMAC },
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{ }
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};
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